MOS Transistor

Theory

Slides adapted from:

N. Weste, D. Harris, CMOS VLSI Design,

© Addison-Wesley, 3/e, 2004

Outline

ƒ The Big Picture

ƒ MOS Structure
ƒ Ideal I-V Charcteristics
ƒ MOS Capacitance Models
ƒ Non ideal I-V Effects
ƒ Pass transistor circuits
ƒ Tristate Inverter
ƒ Switch level RC Delay Models
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The Big Picture

ƒ So far, we have treated transistors as ideal switches

ƒ An ON transistor passes a finite amount of current
ƒ Depends on terminal voltages
ƒ Derive current-voltage (I-V) relationships
ƒ Transistor gate, source, drain all have capacitance
ƒ I = C (∆V/∆t) Æ ∆t = (C/I) ∆V
ƒ Capacitance and current determine speed

MOS Transistor Symbol

2
 MOS Structure

ƒ Gate and body form

MOS capacitor
ƒ Operating modes
ƒ Accumulation
ƒ Depletion
ƒ Inversion

nMOS Transistor Terminal Voltages

Vg
ƒ Mode of operation depends on Vg, Vd, Vs
+ +
ƒ Vgs = Vg – Vs Vgs Vgd
- -
ƒ Vgd = Vg – Vd Vs Vd
-
Vds +
ƒ Vds = Vd – Vs = Vgs - Vgd
ƒ Source and drain are symmetric diffusion terminals
ƒ By convention, source is terminal at lower voltage
ƒ Hence Vds ≥ 0
ƒ nMOS body is grounded. First assume source is 0 too.
ƒ Three regions of operation
ƒ Cutoff
ƒ Linear
6
ƒ Saturation

3
 nMOS in cutoff operation mode

ƒ No channel
ƒ Ids = 0

nMOS in linear operation mode

ƒ Channel forms
ƒ Current flows from D to S
ƒ e- from S to D
ƒ Ids increases with Vds
ƒ Similar to linear
resistor

4
 nMOS in Saturation operation mode

ƒ Channel pinches off

ƒ Ids independent of Vds
ƒ We say current saturates
ƒ Similar to current source

pMOS Transistor

10

5
 I-V Characteristics (nMOS)
ƒ In Linear region, Ids depends on
ƒ How much charge is in the channel?
ƒ How fast is the charge moving?

11

Channel Charge
ƒ MOS structure looks like parallel
plate capacitor while operating in
inversion:
ƒ Gate – oxide – channel
ƒ Qchannel = CV
ƒ C = Cg = εoxWL/tox = coxWL
ƒ V = Vgc – Vt = (Vgs – Vds/2) – Vt

cox = εox / tox

12

6
 Carrier velocity

ƒ Charge is carried by e-
ƒ Carrier velocity v proportional to lateral
E-field between source and drain
ƒ v = µE µ called mobility
ƒ E = Vds/L
ƒ Time for carrier to cross channel:
ƒ t=L/v

13

nMOS Linear I-V

ƒ Now we know
ƒ How much charge Qchannel is in the channel
ƒ How much time t each carrier takes to cross
Qchannel
I ds = =
t
W V − V − Vds V
= µCox  gs  ds
L 
t 2 
= β Vgs − Vt − ds Vds
V
W  2
β = µCox
L 14

7
 nMOS Saturation I-V

ƒ If Vgd < Vt, channel pinches off near drain

ƒ When Vds > Vdsat = Vgs – Vt
ƒ Now drain voltage no longer increases current

I ds = β Vgs − Vt − dsat Vdsat

V
 2
β
(V − Vt )
2
= gs
2
15

nMOS I-V Summary

ƒ first order transistor models


 0 Vgs < Vt cutoff


I ds =  β  Vgs − Vt − ds V V < V
V
 ds linear
2 ds dsat
  
 β
( )
2
 V gs − Vt Vds > Vdsat saturation
2
16

8
 I-V characteristics of nMOS Transistor

17

Example

ƒ 0.6 µm process from AMI Semiconductor

ƒ tox = 100 Å 2.5
Vgs = 5

ƒ m = 350 cm2/V*s 2

ƒ Vt = 0.7 V 1.5 Vgs = 4

Ids (mA)

ƒ Plot Ids vs. Vds 1

Vgs = 3
0.5
ƒ Vgs = 0, 1, 2, 3, 4, 5 Vgs = 2
Vgs = 1
0
ƒ Use W/L = 4/2 λ 0 1 2
Vds
3 4 5

W  3.9 • 8.85 ⋅ 10−14   W  W

β = µ Cox = ( 350 )  −8    = 120 µ A / V
2

L  100 ⋅ 10   L  L 18

9
 pMOS I-V Characteritics

ƒ All dopings and voltages are inverted for pMOS

ƒ Mobility µp is determined by holes
ƒ Typically 2-3x lower than that of electrons µn
ƒ 120 cm2/V*s in AMI 0.6 mm process
ƒ Thus pMOS must be wider to provide same
current
ƒ In this class, assume µn / µp = 2

19

pMOS I-V Summary

ƒ first order transistor models


 0 Vgs < Vt cutoff


I ds =  β  Vgs − Vt − ds V V < V
V
 ds linear
2 ds dsat
  
 β
(Vgs − Vt )
2
 Vds > Vdsat saturation
2
20

10
I-V characteristics of pMOS Transistor

21

Capacitances of a MOS Transistor

ƒ Any two conductors separated by an insulator
have capacitance
ƒ Gate to channel capacitor is very important
ƒ Creates channel charge necessary for
operation (intrinsic capacitance)
ƒ Source and drain have capacitance to body
(parasitic capacitance)
ƒ Across reverse-biased diodes
ƒ Called diffusion capacitance because it is
associated with source/drain diffusion 22

11
Gate Capacitance

ƒ When the transistor is off, the channel is not

inverted
Cg = Cgb = εoxWL/tox = CoxWL
ƒ Let’s call CoxWL = C0
ƒ When the transistor is on, the channel extends
from the source to the drain (if the transistor is
unsaturated, or to the pinchoff point otherwise)
Cg = Cgb + Cgs + Cgd
23

Gate Capacitance

In reality the gate overlaps source and

drain. Thus, the gate capacitance should
include not only the intrinsic capacitance
but also parasitic overlap capacitances:
Cgs(overlap) = Cox W LD
Cgs(overlap) = Cox W LD 24

12
 Detailed Gate Capacitance
Capacitance Cutoff Linear Saturation
Cgb (total) C0 0 0
Cgd (total) CoxWLD C0/2 + CoxWLD CoxWLD
Cgs (total) CoxWLD C0/2 + CoxWLD 2/3 C0+ CoxWLD

Source: M-S Kang, Y. Leblebici,

CMOS Digital ICs, 3/e,
2003, McGraw-Hill 25

Diffusion Capacitance
ƒ Csb, Cdb
ƒ Undesired capacitance (parasitic)
ƒ Due to the reverse biased p-n
junctions between source diffusion
and body and drain diffusion and body
ƒ Capacitance depends on area and
perimeter
ƒ Use small diffusion nodes
ƒ Comparable to Cg for
contacted diffusion
ƒ ½ Cg for uncontacted
ƒ Varies with process
26

13
Lumped representation of the
MOSFET capacitances

27

Non-ideal I-V effects

ƒ The saturation current increases less than quadratically with

increasing Vgs
ƒ Velocity saturation
ƒ Mobility degradation
ƒ Channel length modulation
ƒ Body Effect
ƒ Leakage currents
ƒ Sub-threshold conduction
ƒ Junction leakage
ƒ Tunneling
ƒ Temperature Dependence
ƒ Geometry Dependence
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 Velocity saturation and
mobility degradation
ƒ At strong lateral fields
resulting from high Vds,
drift velocity rolls off due
to carrier scattering and
eventually saturates

ƒ Strong vertical fields

resulting from large Vgs
cause the carriers to
scatter against the
surface and also reduce
the carrier mobility. This
effect is called mobility
degradation 29

Channel length modulation

ƒ The reverse biased p-n junction
between the drain and the body
forms a depletion region with length
L’ that increases with Vdb. The
depletion region effectively shorten
the channel length to: Leff = L – L’

ƒ Assuming the source voltage is

close to the body votage Vdb ~ Vsb.
Hence, increasing Vds decrease the
effective channel length.

ƒ Shorter channel length results in

higher current
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 Body Effect

ƒ The potential difference between source and

body Vsb affects (increases) the threshold
voltage
ƒ Threshold voltage depends on:
ƒ Vsb
ƒ Process
ƒ Doping
ƒ Temperature
31

Subthreshold Conduction
ƒ The ideal transistor I-V model assumes current only flows
from source to drain when Vgs > Vt.
ƒ In real transistors, current doesn’t abruptly cut off below
threshold, but rather drop off exponentially
ƒ This leakage current when the transistor is nominally OFF
depends on:
ƒ process (εox, tox)
ƒ doping levels (NA, or ND)
ƒ device geometry (W, L)
ƒ temperature (T)
ƒ ( Subthreshold voltage (Vt) )

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 Junction Leakage
ƒ The p-n junctions between diffusion and the substrate or
well for diodes.
ƒ The well-to-substrate is another diode
ƒ Substrate and well are tied to GND and VDD to ensure
these diodes remain reverse biased
ƒ But, reverse biased diodes still conduct a small amount of
current that depends on:
ƒ Doping levels
ƒ Area and perimeter of the diffusion region
ƒ The diode voltage

33

Tunneling

ƒ There is a finite probability that

carriers will tunnel though the
gate oxide. This result in gate
leakage current flowing into
the gate
ƒ The probability drops off
exponentially with tox
ƒ For oxides thinner than
15-20 Å, tunneling becomes a
factor
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17
 Temperature dependence

ƒ Transistor characteristics are

influenced by temperature
ƒ µ decreases with T
ƒ Vt decreases linearly with T
ƒ Ileakage increases with T
ƒ ON current decreases with T
OFF current increases with T
ƒ Thus, circuit performances are
worst at high temperature

35

Geometry Dependence

ƒ Layout designers draw transistors with Wdrawn, Ldrawn

ƒ Actual dimensions may differ from some factor XW and XL
ƒ The source and drain tend to diffuse laterally under the
gate by LD, producing a shorter effective channel
ƒ Similarly, diffusion of the bulk by WD decreases the
effective channel width
ƒ In process below 0.25 µm the effective length of the
transistor also depends significantly on the orientation of
the transistor

36

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 Impact of non-ideal I-V effects
ƒ Threshold is a significant fraction of the supply voltage
ƒ Leakage is increased causing gates to
ƒ consume power when idle
ƒ limits the amount of time that data is retained
ƒ Leakage increases with temperature
ƒ Velocity saturation and mobility degradation
result in less current than expected at high voltage
ƒ No point in trying to use high VDD to achieve fast
transistors
ƒ Transistors in series partition the voltage across each
transistor thus experience less velocity saturation
ƒ Tend to be a little faster than a single transistor
ƒ Two nMOS in series deliver more than half the
current of a single nMOS transistor of the same
width 37
ƒ Matching: same dimension and orientation

Pass Transistors

ƒ nMOS pass transistors pull no higher than VDD-Vtn

ƒ Called a degraded “1”
ƒ Approach degraded value slowly (low Ids)

ƒ pMOS pass transistors pull no lower than |Vtp|

ƒ Called a degraded “0”
ƒ Approach degraded value slowly (low Ids)

38

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Pass transistor Circuits

39

Transmission gate ON resistance

40

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Tri-state Inverter

If the output is tri-stated but A toggles,

charge from the internal nodes (= caps)
may disturb the floating output node

41

Effective resistance of a transistor

ƒ First-order transistor models have limited value

ƒ Not accurate enough for modern transistors
ƒ Too complicated for hand analysis
ƒ Simplification: treat transistor as resistor
ƒ Replace Ids(Vds, Vgs) with effective resistance R
ƒ Ids = Vds/R
ƒ R averaged across switching range of digital gate
ƒ Too inaccurate to predict current at any given time
ƒ But good enough to predict RC delay (propagation delay of a
logic gate)

42

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RC Values
ƒ Capacitance
ƒ C = Cg = Cs = Cd = 2 fF/µm of gate width
ƒ Values similar across many processes
ƒ Resistance
ƒ R ≈ 6 KΩ*µm in 0.6um process
ƒ Improves with shorter channel lengths
ƒ Unit transistors
ƒ May refer to minimum contacted device (4/2 λ)
ƒ or maybe 1 µm wide device
ƒ Doesn’t matter as long as you are consistent
43

RC Delay Models

ƒ Use equivalent circuits for MOS transistors

ƒ ideal switch + capacitance and ON resistance
ƒ unit nMOS has resistance R, capacitance C
ƒ unit pMOS has resistance 2R, capacitance C
ƒ Capacitance proportional to width
ƒ Resistance inversely proportional to width

44

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Switch level RC models

45

Inverter Delay Estimate

ƒ Estimate the delay of a fanout-of-1 inverter

46
delay = 6RC

23
Resistance of a unit transmission gate
z The effective resistance of a transmission gate is the
parallel of the resistance of the two transistor
z Approximately R in both directions
z Transmission gates are commonly built using equal-sized
transistors
z Boosting the size of the pMOS only slightly improve the
effective resistance while significantly increasing the
capacitance

47

Summary
ƒ Models are only approximations to reality, not reality itself
ƒ Models cannot be perfectly accurate
ƒ Little value in using excessively complicated models, particularly
for hand calculations
ƒ To first order current is proportional to W/L
ƒ But, in modern transistors Leff is shorter than Ldrawn
ƒ Doubling the Ldrawn reduces current more than a factor of two
ƒ Two series transistors in a modern process deliver more than half
the current of a single transistor
ƒ Use Transmission gates in place of pass transistors
ƒ Transistor speed depends on the ratio of current to capacitance
ƒ Sources of capacitance (voltage dependents)
ƒ Gate capacitance
ƒ Diffusion capacitance
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