Design of Hamming Encoder (23,16

International Journal of All Research Education and Scientific Methods (IJARESM), ISSN: 2455-6211
Volume 9, Issue 6, June -2021, Impact Factor: 7.429, Available online at: www.ijaresm.com
Design of Hamming Encoder (23,16) For Emerging

Applications
Mr. K. Kumaraswamy1, E. Susmitha2, K. Himasri3, N. Rachana4, B. Ravivarma5
1
Associate Professor, Department of Electronics and Communication Engineering, Teegala Krishna Reddy Engineering
College, Hyderabad, Telangana, India
2,3,4,5
Student, Department of Electronics and Communication Engineering, Teegala Krishna Reddy Engineering College,
Hyderabad, Telangana, India
-----------------------------------------------------------------*****************----------------------------------------------------------
ABSTRACT
The use of error-correction codes (ECCs) with advanced correction capability is a common system-level strategy to
harden the memory against multiple bit upsets (MBUs). Therefore, the construction of ECCs with advanced error
correction and low redundancy has become an important problem, especially for adjacent ECCs. Existing codes for
mitigating MBUs mainly focus on the correction of up to 3-bit burst errors. As the technology scales and cell interval
distance decrease, the number of affected bits can easily extend to more than 3 bit. The previous methods are
therefore not enough to satisfy the reliability requirement of the applications in harsh environments. In this paper, a
technique to extend 3-bit burst error-correction (BEC) codes with quadruple adjacent error correction (QAEC) is
presented. First, the design rules are specified and then a searching algorithm is developed to find the codes that
comply with those rules. The H matrices of the 3-bit BEC with QAEC obtained are presented. They do not require
additional paritycheck bitscompared with a 3-bit BEC code. By applying the new algorithm to previous 3-bit BEC
codes, the performance of 3-bit BEC is also remarkably improved. Theencodingand decodingprocedure of the
proposed codes is illustrated with an example. Then, theencodersand decodersare implementedusinga65-nm library
and the results show that our codes have moderate total area and delay overhead to achieve the correction ability
extension.
INTRODUCTION
RELIABILITY is an important requirement for space applications [1]. Memories as the data storing components play a
significant role in the electronic systems. They are widely used in the system on a chip and application-specific integrated
circuits [2], [3]. In these applications, memories.
This makes memories suffer more space radiation than other components. Therefore, the sensitivity to radiation of
memories has become a critical issue to ensure the reliability of electronic systems
IJARESM Publication, India >>>> www.ijaresm.com Page 2597

In modern static random access memories (SRAMs), radiation-induced soft errors in the form of the single event upset
(SEU) and multiple bit upset (MBU) are two prominent single event effects [5]. As semiconductor technology develops
from the submicrometer technology to the ultradeep submicrometer (UDSM) technology, the size of memory cells is
smaller and more cells are included in the radius affected by a particle [6], [7] as shown in Fig.
When a particle from a cosmic ray hits the basic memory cell, it generates a radial distribution of electron–hole pairs along
the transport track [8]. These generated electron–hole pairs can cause soft errors by changing the values stored in the
memory cell leading to data corruption and system failure [9]. For the transistors with a large feature size, a radiation event
just affects one memory cell, which means that only the SEU occurs.
In this case, the use of single error-correction (SEC)double error-detection (DED) codes [10] is enough to protect the
memory from radiation effects.
Burst Error:
It means 2 or more errors are occurred in data. The term burst error means that two or more bits in the data unit have
changed from 0 to 1 or vice-versa. Note that burst error doesn’t necessary means that error occurs in consecutive bits.
The length of the burst error is measured from the first corrupted bit to the last corrupted bit. Some bits in between may not
be corrupted.
Burst errors are mostly likely to happen in serial transmission. The duration of the noise is normally longer than the
duration of a single bit, which means that the noise affects data; it affects a set of bits as shown in Fig. The number of bits
affected depends on the data rate and duration of noise.
Error Detecting Codes Basic approach used for error detection is the use of redundancy, where additional bits are added to
facilitate detection and correction of errors. Popular techniques are:
1) Simple Parity check
2) Two-dimensional Parity check
3) Checksum
4) Cyclic redundancy
Simple Parity Checking Or One-Dimension Parity Check:

The most common and least expensive mechanism for error- detection is the simple parity check. In this technique, a
redundant bit called parity bit, is appended to every data unit so that the number of 1s in the unit (including the parity
becomes even). Blocks of data from the source are subjected to a check bit or Parity bit generator form, where a parity of 1
is added to the block if it contains an odd number of 1’s (ON bits) and 0 is added if it contains an even number of 1’s. At
the receiving end the parity bit is computed from the received data bits and compared with the received parity bit, as shown
in Fig. This scheme makes the total number of 1’s even, that is why it is called even parity checking.
Checksum:
In checksum error detection scheme, the data is divided into k segments each of m bits. In the sender’s end the segments are
added using 1’s complement arithmetic to get the sum. The sum is complemented to get the checksum.
Cyclic Redundancy Checks (Crc):

This Cyclic Redundancy Check is the most powerful and easy to implement technique. Unlike checksum scheme, which is
based on addition, CRC is based on binary division.

In CRC, a sequence of redundant bits, called cyclic redundancy check bits, are appended to the end of data unit so that the
resulting data unit becomes exactly divisible by a second, predetermined binary number. At the destination, the incoming
data unit is divided by the same number. If at this step there is no remainder, the data unit is assumed to be correct and is
therefore accepted.
Binary Linear Block Code (Blbc):

This set of 2k code words is called a block code. For a block code to be useful there should be a one-to-one correspondence
between a message u and its code word v. A desirable structure for a block code to possess is the linearity. With this
structure, the encoding complexity will be greatly reduced.
METHODOLOGY
Fig 3: Flow of code design algorithm.

Fig 4: Flow of algorithm with column weight restriction and past procedure record.
SIMULATION AND RESULT
Synthesis Results:
The developed project is simulated and verified their functionality. Once the functional verification is done, the RTL model
is taken to the synthesis process using the Xilinx ISE tool. In synthesis process, the RTL model will be converted to the
gate level netlist mapped to a specific technology library. Here in this Spartan 3E family, many different devices were
available in the Xilinx ISE tool. In order to synthesis this design the device named as “XC3S500E” has been chosen and the
package as “FG320” with the device speed such as “-4”.

This design is synthesized and its results were analyzed as follows
Encoder Rtl Schematic:
Decoder Rtl Schematic:
Noise Mixer Rtl:

Technology Schematic:
CONCLUSION
A technique is introduced in this article to improve QAEC's 3-bit BEC codes. The codes suggested are inconsistent to the
same degree as the previous BEC three-bit codes[23]. A new column checks and capturing functional algorithm is
suggested to speed up the search process for goal matrices. A search framework is built to carry out the search process
automatically based on the proposed algorithm. The validity of the suggested algorithm is shown by the relevant 3-bit BEC
codes[23] and by the two Optimization Parameters, the codes are improved considerably. In order to find the solution for
QAEC the existing algorithm is then used. The entire search process is complete The best solutions are then provided in
this article for 16 data bits, and for 32 and 64 data bits the best solutions find within an acceptable measurement time. Using
the HDL to execute the encoder and decoder for the proposed codes, synthesised with a 65-nm library. Overhead and delay
relative to previous 3-bit BEC codes [23] was low. This indicates that programmers can easily use the planned 3-bit BEC
with QAEC codes to shield SRAM memories from radiation and minimize MBUs with up to four neighboring bits. Finally,
as previously noted, the suggested scheme could be broadened to 3-bit ECCs that can remedy another.
ACKNOWLEDGEMENT
Mr. K. Kumaraswamy, is currently working as an Associate Professor in the Department of Electronics and
Communication Engineering at Teegala Krishna Reddy Engineering College.
REFERENCES
[1] R. D. Schrimpf and D. M. Fleetwood, Radiation Effects and Soft Errors in Integrated Circuits and Electronic
Devices. Singapore: World Scientific, 2004.
[2] S. K. Vishvakarma, B. S. Reniwal, V. Sharma, C. B. Khuswah, and D. Dwivedi, “Nanoscale memory design for
efficient computation: Trends, challenges and opportunity,” in Proc. IEEE Int. Syst. Nanoelectron. Inf. Syst., Dec.
2015, pp. 29–34.

[3] S.-Y. Wu, C. Y. Lin, S. H. Yang, J. J. Liaw, and J. Y. Cheng, “Advancing foundry technology with scaling and
innovations,” in Proc. Int. Symp. VLSI-TSA, Apr. 2014, pp. 1–3.
[4] ITRS. International Technology Roadmap for Semiconductors (ITRS) Report, Semiconductor Industry Association.
Accessed: 2009. [Online]. Available: http://www.itrs.net
[5] Y. Bentoutou, “A real time EDAC system for applications onboard earth observation small satellites,” IEEE Trans.
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[6] E. Ibe, H. Taniguchi, Y. Yahagi, K.-I. Shimbo, and T. Toba, “Impact of scaling on neutron-induced soft error in
SRAMs from a 250 nm to a 22 nm design rule,” IEEE Trans. Electron Devices, vol. 57, no. 7, pp. 1527–1538, Jul.
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Proc. IEEE 57th Int. Midwest Symp Circuits Syst., Aug. 2014, pp. 655–658.

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International Journal of All Research Education and Scientific Methods (IJARESM), ISSN: 2455-6211

Design of Hamming Encoder (23,16) For Emerging

IJARESM Publication, India >>>> www.ijaresm.com Page 2597

Simple Parity Checking Or One-Dimension Parity Check:

Cyclic Redundancy Checks (Crc):

IJARESM Publication, India >>>> www.ijaresm.com Page 2598

Binary Linear Block Code (Blbc):

Fig 3: Flow of code design algorithm.

IJARESM Publication, India >>>> www.ijaresm.com Page 2599

SIMULATION AND RESULT

IJARESM Publication, India >>>> www.ijaresm.com Page 2600

This design is synthesized and its results were analyzed as follows

Encoder Rtl Schematic:

Decoder Rtl Schematic:

Noise Mixer Rtl:

IJARESM Publication, India >>>> www.ijaresm.com Page 2601

IJARESM Publication, India >>>> www.ijaresm.com Page 2602

IJARESM Publication, India >>>> www.ijaresm.com Page 2603

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