CSC429

COMPUTER ORGANIZATION
AND ARCHITECTURE

INSTRUCTION SET ARCHITECTURE

CHAPTER 6

FMH/UiTM 1
 Contents

• Instruction set architecture

• Instruction formats
• Byte ordering
• Zero addressing
• One addressing
• Two addressing
• Three addressing
• Addressing mode

FMH/UiTM 2
 Instruction Set Architecture
• The complete collection of instructions that are
understood by a CPU
• Serves as an interface between software and hardware
• An instruction is a binary code, which specifies a basic
operation (e.g. add, subtract, and, or) for the computer 
usually in assembly code:
• Operation Code:
• Define the operation type
• Operands:
• Operation source and destination

FMH/UiTM 3
Instruction Set Architecture

FMH/UiTM 4
 Instruction Set Architecture

• In machine code each instruction has a unique bit pattern

• For human consumption (well, programmers anyway) a
symbolic representation is used
• E.g. ADD, SUB, LOAD
• Operands can also be represented in this way
• ADD A,B

FMH/UiTM 5
 Instruction Formats

• Instruction sets are differentiated by the following:

• Number of bits per instruction
• Stack-based or register-based
• Number of explicit operands per instruction
• Operand location
• Types of operations
• Type and size of operands

FMH/UiTM 6
 Instruction Formats

• In designing an instruction set, consideration is given to:

• Instruction length
• Whether short, long or variable
• Number of operands
• Number of addressable registers
• Memory organization
• Whether byte or word addressable
• Addressing modes
• Choose any or all: direct, indirect or indexed

FMH/UiTM 7
 Instruction Formats
• Byte ordering, or endianness, is another major architectural
consideration
• If we have two-byte integer, the integer may be stored so that
the least significant byte is followed by the most significant
byte or vice versa
• In little endian machines, the least significant byte is followed by the
most significant byte
• The high byte goes to the high address, the low byte goes to the low
address
• In big endian machines store the most significant byte first (at lower
address)
• The low byte goes to the high address, the high byte goes to the low
address

FMH/UiTM 8
 Instruction Formats

• As an example, suppose we have the hexadecimal

number 12345678
• The big endian and small endian arrangements of the
bytes are shown below:

FMH/UiTM 9
 Instruction Formats
• Big endian
• Is more natural
• The sign of the number can be determined by looking at the
bytes at address offset 0
• Strings and integers are stored in the same order
• Little endian
• Makes it easier to place values on non-word boundaries
• Conversion from a 16-bit integer address to a 32-bit integer
address does not require any arithmetic

FMH/UiTM 10
 Instruction Formats
• The next consideration for architecture design concerns
how the CPU will store data
• We have three choices:
• A stack architecture
• An accumulator architecture
• A general purpose register architecture
• In choosing one over the other, the tradeoffs are
simplicity (and cost) of hardware design with execution
speed and ease of use

FMH/UiTM 11
 Instruction Formats
• In the stack architecture, instructions and operands are
implicitly taken from the stack
• A stack cannot be accessed randomly
• In an accumulator architecture, one operand of a binary is
implicitly in the accumulator
• One operand is in memory, creating lots of bus traffic
• In a general purpose register (GPR) architecture, registers can
be use instead of memory
• Faster than accumulator architecture
• Efficient implementation for compilers
• Results in longer instructions

FMH/UiTM 12
 Instruction Formats
• Most systems today are GPR system
• There are three types:
• Memory-memory where two or three operands may be in
memory
• Register-memory where at least one operand must be in a
register
• Load-store where no operands may be in memory
• The number of operands and the number of available
registers has a direct affect on instruction length

FMH/UiTM 13
 Instruction Formats
• Stack machines use one- and zero- operand instructions
• LOAD and STORE instructions require a single memory
address operand
• Other instructions use operands from the stack implicitly
• PUSH and POP operations involve only the stack’s top
element
• Binary instructions (e.g. ADD, MULT) use the top two
items on the stack

FMH/UiTM 14
 Instruction Formats
• Four common instruction formats:
(a) Zero-address instruction
(b) One-address instruction
(c) Two-address instruction
(d) Three-address instruction

FMH/UiTM 15
 Different Addressing
0 Address 1 Address 2 Address 3 Address
Stack Accumulator Register Register
(register-memory) (load-store)
Push A Load A Load R1, A Add R3, R1, R2
Push B Add B Add R1, B Mul R1, R2, R3
Add Store C Store C, R1
Pop C

FMH/UiTM 16
 3 address

• Operation, Result, Operand 1, Operand 2

• a=b+c
• Not common
• Needs very long words to hold everything
• Y = (A-B)/[C+(D*E)]
SUB X,A,B X <- A-B
MUL Z,D,E Z <- D*E
ADD Z,Z,C Z <- Z+C
DIV Y,X,Z Y <- X/Z

FMH/UiTM 17
 2 address
• One address doubles as operand and result
• a=a+b
• Reduces length of instruction
• Requires some extra work: temporary storage to hold some
result
• Y = (A-B)/[C+(D*E)]
MOVE Y,A Y <- A
SUB Y,B Y <-Y-B
MOVE X,D X <- D
MUL X,E X <- X*E
ADD X,C X <- X+C
DIV Y,X Y <-Y/X

FMH/UiTM 18
 1 address
• Implicit second address, usually a register (AC)
• Y = (A-B)/[C+(D*E)]
LOAD D AC <- D
MUL E AC <- AC*E
ADD C AC <- AC+C
STOR Y Y <- AC
LOAD A AC <- A
SUB B AC <- AC-B
DIV Y AC <- AC/Y
STOR Y Y <- AC

FMH/UiTM 19
 0 Address
• All addresses implicit and uses a stack
• Y = (A-B)/[C+(D*E)]
PUSH A
PUSH B
SUB
PUSH C
PUSH D
PUSH E
MUL
ADD
DIV
POP Y

FMH/UiTM 20
 Example 1
• Z = (X*Y) + (W*U)
Zero Address One Address Two Address Three Address
PUSH X LOAD X MUL X,Y MUL X,X,Y
PUSH Y MUL Y MUL W,U MUL Y,W,U
MUL STOR X ADD X,W ADD Z,X,Y
PUSH W LOAD W STOR Z,X
PUSH U MUL U
MUL STOR Y
ADD LOAD X
POP Z ADD Y
STOR Z

FMH/UiTM 21
 Example 2

(June 2019)
FMH/UiTM 22
 Solution Example 2
X = [(AB2) + (A-BC)] / D

One-Address Two-Address Three-Address

B2 LOAD B MOV X,B MUL X,B,B
MUL B MUL X,X
STOR X
AB2 LOAD A MUL X, A MUL X,X,A
MUL X
STOR X
BC LOAD B MOV Y,B MUL Y,B,C
MUL C MUL Y,C
STOR Y
A-BC LOAD A MOV Z,A SUB Z,A,Y
SUB Y SUB Z,Y
STOR Z
AB2 + (A-BC) LOAD X ADD X,Z ADD X,X,Z
ADD Z
STOR Y
X = [AB2 + (A-BC)]/D LOAD Y DIV X,D DIV X,X,D
DIV D
STOR X
FMH/UiTM 23
 Addressing Mode
• Way of specifying address
• Used in memory-memory or load/store instructions in register
ISA
• Can be categorized into:
• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement (Indexed)
• Stack

FMH/UiTM 24
 Addressing Mode
• Addressing modes specify where an operand is located
• They can specify a constant, a register, or a memory location
• The actual location of an operand is its effective address
• Certain addressing modes allow us to determine the address of
an operand dynamically
• The following notation is used:
• A = contents of an address field in the instruction
• R = contents of an address field in the instruction that refers to a
register
• EA = actual (effective) address of the location containing the
referenced operand
• (X) = contents of memory location X or register X

FMH/UiTM 25
 Addressing Mode
• Basic Addressing Modes

FMH/UiTM 26
 Addressing Mode: Immediate

• Operand is part of instruction

• Operand = A (address field)
• E.g. ADD 5 or ADD#5
• Add 5 to contents of accumulator
• 5 is operand
• No memory reference to fetch data
• Fast
• Limited range
FMH/UiTM 27
 Addressing Mode: Direct

• Address field contains address of operand

• Effective address = address field
• EA = A
• E.g: ADD A
• Add contents of cell A to accumulator
• Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations needed to work
out effective address
• Limited address space (length of address
field)

FMH/UiTM 28
 Addressing Mode: Indirect

• Memory cell pointed to by address field

• Contains the address of (pointer to) the
operand
• E.g. ADD (A)
• Add contents of cell pointed to by
contents of A to accumulator
• Large address space
• Multiple memory access to find operand
• Slower
• EA = (A)

FMH/UiTM 29
 Addressing Mode: Register

• Memory cell pointed to by address field

• Operand is held in register named in
address filed
• EA = R
• Limited number of registers
• Very small address field needed
• Shorter instructions
• Faster instruction fetch
• No memory access
• Very fast execution
• Very limited address space

FMH/UiTM 30
Addressing Mode: Register Indirect

• Operand is in memory cell pointed

to by content of register R
• Large address space (2n)
• One fewer memory access than
indirect addressing
• EA = (R)

FMH/UiTM 31
 Addressing Mode: Displacement
(Indexed)

• Address field hold two values

• A = base value
• R = register that holds
displacement
• Or vice versa
• EA = A + (R)

FMH/UiTM 32
 Addressing
• Immediate addressing is where the data is part of the
instruction
• Direct addressing is where the address of the data is given
in the instruction
• Register addressing is where the data is located in a
register
• Indirect addressing gives the address of the address of the
data in the instruction
• Register indirect addressing uses a register to store the
address of the address of the data

FMH/UiTM 33
 Addressing
• Indexed addressing uses a register (implicitly or explicitly)
as an offset, which is added to the address is the operand
to determine the effective address of the data
• Based addressing is similar except that a base register is
used instead of an index register
• The difference between these two is that an index
register holds an offset relative to the address given in
the instruction, a base register holds a base address
where the address field represents a displacement from
this base

FMH/UiTM 34
 Addressing

FMH/UiTM 35
 Addressing (Example 1)

• For the instruction shown below, what value is loaded

into accumulator for each addressing mode?

FMH/UiTM 36
 Addressing (Solution)

• These are the value loaded into the accumulator for each
addressing mode

FMH/UiTM 37
 Example 2

300
1300
8800
100
500
(June 2019)
FMH/UiTM 38
END OF CHAPTER 6

FMH/UiTM 39