Digital Logic Circuits 1 Introduction Digital Logic Circuits 2 Logic Gates

DIGITAL LOGIC CIRCUITS LOGIC GATES

Digital Computers

- Imply that the computer deals with digital information, i.e., it deals
Logic Gates with the information that is represented by binary digits
- Why BINARY ? instead of Decimal or other number system ?
Boolean Algebra
* Consider electronic signal
Map Specification
1 7
Combinational Circuits 6
5 signal
4
Flip-Flops 3 range
2
0 1
Sequential Circuits 0
binary octal
Memory Components
0 1 2 3 4 5 6 7 8 9
Integrated Circuits * Consider the calculation cost - Add 0 0 1 2 3 4 5 6 7 8 9
1 1 2 3 4 5 6 7 8 9 10
0 1 2 2 3 4 5 6 7 8 9 1011
3 3 4 5 6 7 8 9 101112
0 0 1 4 4 5 6 7 8 9 10111213
1 1 10 5 5 6 7 8 9 1011121314
6 6 7 8 9 101112131415
7 7 8 9 10111213141516
8 8 9 1011121314151617
9 9 101112131415161718

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Digital Logic Circuits 3 Logic Gates Digital Logic Circuits 4 Logic Gates

BASIC LOGIC BLOCK - GATE - COMBINATIONAL GATES

Name Symbol Function Truth Table
Binary Binary A X=A•B
A
0
B
0
X
0
Digital Digital AND X or 0 1 0
. Gate Output B X = AB 1 0 0
Input . 1 1 1
Signal . Signal A B X
A 0 0 0
OR X X=A+B 0 1 1
B 1 0 1
1 1 1
Types of Basic Logic Blocks A X
I A X X = A’ 0
1
1
0
- Combinational Logic Block A X
Buffer A X X=A 0 0
Logic Blocks whose output logic value 1 1
depends only on the input logic values A
0
B
0
X
1
A
NAND X X = (AB)’ 0
1
1
0
1
1
- Sequential Logic Block B 1 1 0
Logic Blocks whose output logic value A B X
A 0 0 1
depends on the input values and the NOR X X = (A + B)’ 0 1 0
B 1 0 0
state (stored information) of the blocks 1 1 0
A B X
A X=A⊕B
Functions of Gates can be described by XOR X or 0 0 0
Exclusive OR 0 1 1
B X = A’B + AB’ 1 0 1
1 1 0
- Truth Table A B X
A X = (A ⊕ B)’
- Boolean Function XNOR X or
0
0
0
1
1
0
Exclusive NOR
- Karnaugh Map or Equivalence B X = A’B’+ AB 1
1
0
1
0
1

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Digital Logic Circuits 5 Boolean Algebra Digital Logic Circuits 6 Boolean Algebra

BOOLEAN ALGEBRA LOGIC CIRCUIT DESIGN

Boolean Algebra x y z F
0 0 0 0
* Algebra with Binary(Boolean) Variable and Logic Operations Truth 0 0 1 1
* Boolean Algebra is useful in Analysis and Synthesis of Table 0 1 0 0
Digital Logic Circuits 0 1 1 0
1 0 0 1
- Input and Output signals can be 1 0 1 1
represented by Boolean Variables, and 1 1 0 1
- Function of the Digital Logic Circuits can be represented by 1 1 1 1
Logic Operations, i.e., Boolean Function(s)
- From a Boolean function, a logic diagram Boolean F = x + y’z
can be constructed using AND, OR, and I Function
Truth Table

* The most elementary specification of the function of a Digital Logic

Circuit is the Truth Table
x
F
- Table that describes the Output Values for all the combinations Logic y
of the Input Values, called MINTERMS Diagram
- n input variables ĺ 2n minterms z

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Digital Logic Circuits 7 Boolean Algebra Digital Logic Circuits 8 Boolean Algebra

BASIC IDENTITIES OF BOOLEAN ALGEBRA EQUIVALENT CIRCUITS

[1] x + 0 = x [2] x • 0 = 0
[3] x + 1 = 1 [4] x • 1 = x Many different logic diagrams are possible for a given Function
[5] x + x = x [6] x • x = x
[7] x + x’ = 1 [8] x • x’ = 0 F = ABC + ABC’ + A’C .......…… (1)
[9] x + y = y + x [10] xy = yx = AB(C + C’) + A’C [13] ..…. (2)
[11] x + (y + z) = (x + y) + z [12] x(yz) = (xy)z = AB • 1 + A’C [7]
[13] x(y + z) = xy +xz [14] x + yz = (x + y)(x + z) = AB + A’C [4] ...…. (3)
[15] (x + y)’ = x’y’ [16] (xy)’ = x’ + y’
[17] (x’)’ = x A
B
[15] and [16] : De Morgan’s Theorem (1) C
Usefulness of this Table F
- Simplification of the Boolean function
- Derivation of equivalent Boolean functions
to obtain logic diagrams utilizing different logic gates
-- Ordinarily ANDs, ORs, and Inverters (2) A
B
-- But a certain different form of Boolean function may be convenient
F
to obtain circuits with NANDs or NORs C
ĺ Applications of De Morgans Theorem

x’y’ = (x + y)’ x’+ y’= (xy)’

I, AND ĺ NOR I, OR ĺ NAND (3) A
B
F
C

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Digital Logic Circuits 9 Boolean Algebra Digital Logic Circuits 10 Map Simplification

COMPLEMENT OF FUNCTIONS SIMPLIFICATION

A Boolean function of a digital logic circuit is represented by only using
logical variables and AND, OR, and Invert operators. Truth Boolean
Table Function
ĺ Complement of a Boolean function
Unique Many different expressions exist
- Replace all the variables and subexpressions in the parentheses Simplification from Boolean function
appearing in the function expression with their respective complements
- Finding an equivalent expression that is least expensive to implement
A,B,...,Z,a,b,...,z Ÿ A’,B’,...,Z’,a’,b’,...,z’ - For a simple function, it is possible to obtain
(p + q) Ÿ (p + q)’ a simple expression for low cost implementation
- But, with complex functions, it is a very difficult task
- Replace all the operators with their respective
complementary operators Karnaugh Map (K-map) is a simple procedure for
simplifying Boolean expressions.
AND Ÿ OR
OR Ÿ AND Truth
Table
- Basically, extensive applications of the De Morgan’s theorem Simplified
Karnaugh Boolean
(x1 + x2 + ... + xn )’ Ÿ x1’x2’... xn’ Map Function
Boolean
(x1x2 ... xn)' Ÿ x1' + x2' +...+ xn' function

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Digital Logic Circuits 11 Map Simplification Digital Logic Circuits 12 Map Simplification

KARNAUGH MAP KARNAUGH MAP

x y z F
Karnaugh Map for an n-input digital logic circuit (n-variable sum-of-products 0 0 0 0 y
form of Boolean Function, or Truth Table) is 0 0 1 1 yz yz
- Rectangle divided into 2n cells 0 1 0 1 x 00 01 11 10 x 00 01 11 10
0 1 1 0 0 0 1 3 2 0 0 1 0 1
- Each cell is associated with a Minterm 1 0 0 1 x 1 4 5 7 6
- An output(function) value for each input value associated with a 1 0 1 0 1 1 0 0 0
1 1 0 0 z
mintern is written in the cell representing the minterm 1 1 1 0 F(x,y,z) = ¦ (1,2,4)
ĺ 1-cell, 0-cell
wx w
Each Minterm is identified by a decimal number whose binary representation u v w x F
uv 00 01 11 10
0 0 0 0 0
is identical to the binary interpretation of the input values of the minterm. 0 0 0 1 1 00 0 1 3 2 v
0 0 1 0 0
0 0 1 1 1 01 4 5 7 6
Karnaugh Map 0 1 0 0 0
x value 0 1 0 1 0 u 11 12 13 15 14
x Identification
0 1 1 0 1
x
0
F
1 0 0 of the cell 0 0 of F
0 1 1 1 0 10 8 9 11 10
1 0 1 1 1 1 1
1
0
0
0
0
0
1
1
1
x
F(x) =¦ (1) 1 0 1 0 0 wx
1 0 1 1 1 uv 00 01 11 10
1 1 0 0 0 00 0 1 1 0
1-cell 1 1 0 1 0
y 1 1 1 0 1
01 0 0 0 1
x
0
y
0
F
0
x 0 1 y0 1 1 1 1 1 0

0 1 1
0 0 1 x 11 0 0 0 1
0 0 1
1 0 1 1 2 3 10 1 1 1 0
1 1 1 1 1 0
F(x,y) = ¦ (1,2) F(u,v,w,x) = ¦ (1,3,6,8,9,11,14)
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Digital Logic Circuits 13 Map Simplification Digital Logic Circuits 14 Map Simplification

MAP SIMPLIFICATION - 2 ADJACENT CELLS - MAP SIMPLIFICATION - MORE THAN 2 CELLS -

wx u’v’ wx u’x’
Rule: xy’ +xy = x(y+y’) = x u’v’w’x’ + u’v’w’x + u’v’wx + u’v’wx’ w w
= u’v’w’(x’+x) + u’v’w(x+x’) uv uv
Adjacent cells 1 1 1 1
= u’v’w’ + u’v’w 1 1 1 1
= u’v’(w’+w) vw’ 1 1 1 1
- binary identifications are different in one bit v v
ĺ minterms associated with the adjacent = u’v’ 1 1 1 1
u u
cells have one variable complemented each other 1 1 1 1
uw x
x v’x
Cells (1,0) and (1,1) are adjacent
Minterms for (1,0) and (1,1) are
x • y’ --> x=1, y=0 u’v’w’x’+u’v’w’x+u’vw’x’+u’vw’x+uvw’x’+uvw’x+uv’w’x’+uv’w’x
x • y --> x=1, y=1 = u’v’w’(x’+x) + u’vw’(x’+x) + uvw’(x’+x) + uv’w’(x’+x)
= u’(v’+v)w’ + u(v’+v)w’
F = xy’+ xy can be reduced to F = x = (u’+u)w’ = w’
From the map y wx
w w V’
x 0 1 uv uv
0 0 0 2 adjacent cells xy’ and xy w’ 1 1 1 1 1 1
1 1 1 ĺ merge them to a larger cell x 1 1
v v
1 1
F(x,y) = ¦ (2,3) u u 1 1 1 1 u
1 1 1 1 1 1
= xy’+ xy x x
=x

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Digital Logic Circuits 15 Map Simplification Digital Logic Circuits 16 Map Simplification

MAP SIMPLIFICATION IMPLEMENTATION OF K-MAPS - Sum-of-Products Form -

wx
uv 00 01 11 10 w Logic function represented by a Karnaugh map
00 1 1 0 1 1 1 0 1 can be implemented in the form of I-AND-OR
01 0 0 0 0 0 0 0 0
v A cell or a collection of the adjacent 1-cells can
11 0 1 1 0 0 1 1 0 be realized by an AND gate, with some inversion of the input variables.
10 0 1 0 0 u
0 1 0 0 y
x x’
1 1 y
x’ z’
F(u,v,w,x) = ¦ (0,1,2,9,13,15) y’ x’
z’ x 1 Ÿ y
(0,1), (0,2), (0,4), (0,8) Merge (0,1) and (0,2) x z’ 1 1
Adjacent Cells of 1 --> u’v’w’ + u’v’x’ z y z’
Adjacent Cells of 0 z’ 1
Merge (1,9) F(x,y,z) = ¦ (0,2,6)
(1,0), (1,3), (1,5), (1,9) --> v’w’x
... Merge (9,13)
... --> uw’x x’
Adjacent Cells of 15 y’ x
Merge (13,15) z’
(15,7), (15,11), (15,13), (15,14) --> uvx x’ Ÿ z
y F F
z’ y
x
F = u’v’w’ + u’v’x’ + v’w’x + uw’x + uvx y z
But (9,13) is covered by (1,9) and (13,15) z’
I AND OR
F = u’v’w’ + u’v’x’ + v’w’x + uvx

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Digital Logic Circuits 17 Map Simplification Digital Logic Circuits 18 Map Simplification
IMPLEMENTATION OF K-MAPS
IMPLEMENTATION OF K-MAPS - Product-of-Sums Form - - Don’t-Care Conditions -
In some logic circuits, the output responses
Logic function represented by a Karnaugh map for some input conditions are don’t care
can be implemented in the form of I-OR-AND whether they are 1 or 0.
If we implement a Karnaugh map using 0-cells, In K-maps, don’t-care conditions are represented
the complement of F, i.e., F’, can be obtained. by d’s in the corresponding cells.
Thus, by complementing F’ using DeMorgan’s
theorem F can be obtained Don’t-care conditions are useful in minimizing
the logic functions using K-map.
F(x,y,z) = (0,2,6) y
F’ = xy’ + z - Can be considered either 1 or 0
1 0 0 1 z - Thus increases the chances of merging cells into the larger cells
x F = (xy’)z’ --> Reduce the number of variables in the product terms
0 0 0 1
= (x’ + y)z’ y x’
x z
y’ 1 d d 1
x d 1
x z yz’
y
F
z x
F
I OR AND y
z
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Digital Logic Circuits 19 Combinational Logic Circuits Digital Logic Circuits 20 Combinational Logic Circuits

COMBINATIONAL LOGIC CIRCUITS COMBINATIONAL LOGIC CIRCUITS

y y
Half Adder x y c s x
0 0 0 0 0 0 0 1 c
y
0 1 0 1 x 0 1 x 1 0
1 0 0 1 c = xy s = xy’ + x’y s Other Combinational Circuits
1 1 1 0 =x ⊕ y
Full Adder Multiplexer
y y
x y cn-1 cn s Encoder
0 0 0 0 0 0 0 0 1 Decoder
0 0 1 0 1 0 1 c 1 0 c
n-1
Parity Checker
n-1
0 1 0 0 1 x 1 1 x 0 1 Parity Generator
0 1 1 1 0 0 1 1 0 etc
1 0 0 0 1 cn s
1 0 1 1 0
1 1 0 1 0 cn = xy + xcn-1+ ycn-1
1 1 1 1 1 = xy + (x ⊕ y)cn-1
s = x’y’cn-1+x’yc’n-1+xy’c’n-1+xycn-1
= x ⊕ y ⊕ cn-1 = (x ⊕ y) ⊕ cn-1
x
y S
cn-1
cn

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Digital Logic Circuits 21 Combinational Logic Circuits Digital Logic Circuits 22 Combinational Logic Circuits

MULTIPLEXER ENCODER/DECODER

4-to-1 Multiplexer Octal-to-Binary Encoder

D1 A0
Select Output D2
S1 S0 Y D3 A1
0 0 I0 D4
0 1 I1 D5 A2
1 0 I2 D6
1 1 I3
D7

I0
2-to-4 Decoder
I1 D0
Y
I2 E A1 A0 D0 D1 D2 D3 D1
A0
0 0 0 0 1 1 1
I3 0 0 1 1 0 1 1 D2
0 1 0 1 1 0 1
0 1 1 1 1 1 0
1 d d 1 1 1 1 A1 D3
S0
S1 E

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Digital Logic Circuits 23 Flip Flops Digital Logic Circuits 24 Flip Flops

FLIP FLOPS CLOCKED FLIP FLOPS

Characteristics In a large digital system with many flip flops, operations of individual flip flops
- 2 stable states are required to be synchronized to a clock pulse. Otherwise,
- Memory capability the operations of the system may be unpredictable.
- Operation is specified by a Characteristic Table
R
1 0 0 1 Q

c
(clock)
S Q’
0 1 1 0
0-state 1-state
Clock pulse allows the flip flop to change state only
In order to be used in the computer circuits, state of the flip flop should when there is a clock pulse appearing at the c terminal.
have input terminals and output terminals so that it can be set to a certain
state, and its state can be read externally. We call above flip flop a Clocked RS Latch, and symbolically as
R S R Q(t+1)
Q 0 0 Q(t) S Q S Q
0 1 0 c c
1 0 1 R Q’
1 1 indeterminate R Q’
S Q’
(forbidden) operates when operates when
clock is high clock is low

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Digital Logic Circuits 25 Flip Flops Digital Logic Circuits 26 Flip Flops

RS-LATCH WITH PRESET AND CLEAR INPUTS D-LATCH

P(preset) D-Latch
Forbidden input values are forced not to occur
R Q by using an inverter between the inputs
c
(clock) D Q
S Q’ Q

clr(clear) E E Q’
(enable)
Q’ D Q
D(data)
S P Q S P Q
c c D Q(t+1)
R clr Q’ E Q’
R clr Q’ 0 0
1 1

S P Q S P Q
c c
R clr Q’ R clr Q’

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Digital Logic Circuits 27 Flip Flops Digital Logic Circuits 28 Flip Flops

EDGE-TRIGGERED FLIP FLOPS POSITIVE EDGE-TRIGGERED

D-Flip Flop
Characteristics D S1 Q1 S2 Q2 Q D Q
- State transition occurs at the rising edge or SR1 SR2
falling edge of the clock pulse C1 C2 D-FF
R1 Q1' R2 Q2' Q' C Q'
C
Latches
SR1 inactive
SR2 active

respond to the input only during these periods SR2 inactive SR2 inactive
SR1 active SR1 active
JK-Flip Flop
Edge-triggered Flip Flops (positive)

J S1 Q1 S2 Q2 Q J Q
SR1 SR2
C1 C2 C
K R1 Q1' Q' K Q'
R2 Q2'

respond to the input only at this time C

T-Flip Flop: JK-Flip Flop whose J and K inputs are tied together to make
T input. Toggles whenever there is a pulse on T input.
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Digital Logic Circuits 29 Flip Flops Digital Logic Circuits 30 Sequential Circuits

CLOCK PERIOD DESIGN EXAMPLE

Clock period determines how fast the digital circuit operates. Design Procedure:
How can we determine the clock period ? Specification Ÿ State Diagram Ÿ State Table Ÿ
Excitation Table Ÿ Karnaugh Map Ÿ Circuit Diagram
Usually, digital circuits are sequential circuits which has some flip flops Example: 2-bit Counter -> 2 FF's
x=0 current next
state input state FF inputs
00 A B x A B Ja Ka Jb Kb
FF FF ... FF x=1 x=1 0 0 0 0 0 0 d 0 d
0 0 1 0 1 0 d 1 d
C x=0 01 11 x=0 0 1 0 0 1 0 d d 0
0 1 1 1 0 1 d d 1
x=1 1 0 0 1 0 d 0 0 d
Combinational . x=1 1 0 1 1 1 d 0 1 d
.
. Logic . 10 1 1 0 1 1 d 0 d 0
. Circuit . x=0 1 1 1 0 0 d 1 d 1

B B B B
Combinational d d d d
FF Logic FF
1 x d d x 1 d x d 1 x
Circuit d d 1 1 d x A B
A A A d 1 J Q J Q
FF Setup Time A
FF Delay Combinational logic Delay FF Hold Time d d d d C C

td Ja Ka Jb Kb K Q' K Q'
ts,th clock
Ja = Bx Ka = Bx Jb = x Kb = x
clock period T = td + ts + th
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Digital Logic Circuits 31 Sequential Circuits Digital Logic Circuits 32 Sequential Circuits

SEQUENTIAL CIRCUITS - Registers SEQUENTIUAL CIRCUITS - Counters

A0 A1 A2 A3
Q Q Q Q
D C D C D C D C

Clock A0 A1 A2 A3
I0 I1 I2 I3
Shift Registers Q Q Q Q
Serial Serial J K J K J K J K
D Q D Q D Q D Q Output
Input C C C C Clock
Clock

Bidirectional Shift Register with Parallel Load Counter

Enable
A0 A1 A2 A3

Q Q Q Q Output
Carry
D C D C D C D C

4x1 4x1 4x1 4x1

MUX MUX MUX MUX

Clock S0S1 SeriaI I0 I1 I2 Serial I3

Input Input
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Digital Logic Circuits 33 Memory Components Digital Logic Circuits 34 Memory Components

MEMORY COMPONENTS READ ONLY MEMORY(ROM)

0 Characteristics
- Perform read operation only, write operation is not possible
Logical Organization - Information stored in a ROM is made permanent
during production, and cannot be changed
- Organization k address input lines
words
(byte, or n bytes)
m x n ROM
(m=2k)
N-1
Random Access Memory
n data output lines
- Each word has a unique address Information on the data output line depends only
- Access to a word requires the same time on the information on the address input lines.
independent of the location of the word --> Combinational Logic Circuit address Output
- Organization X0=A’B’ + B’C ABC X0 X1 X2 X3 X4
n data input lines
X1=A’B’C + A’BC’ 000 1 0 0 0 0
X2=BC + AB’C’
X3=A’BC’ + AB’
001 1 1 0 0 0
k address lines 010 0 1 0 1 0
2k Words X4=AB
Read (n bits/word) 011 0 0 1 0 0
X0=A’B’C’ + A’B’C + AB’C 100 0 0 1 1 0
Write X1=A’B’C + A’BC’ 101 1 0 0 1 0
X2=A’BC + AB’C’ + ABC 110 0 0 0 0 1
Canonical minterms X3=A’BC’ + AB’C’ + AB’C 111 0 0 1 0 1
n data output lines X4=ABC’ + ABC
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Digital Logic Circuits 35 Memory Components Digital Logic Circuits 36 Memory Components

TYPES OF ROM INTEGRATED CIRCUITS

ROM Classification by the Circuit Density

- Store information (function) during production
- Mask is used in the production process SSI - several (less than 10) independent gates
- Unalterable MSI - 10 to 200 gates; Perform elementary digital functions;
Decoder, adder, register, parity checker, etc
- Low cost for large quantity production --> used in the final products LSI - 200 to few thousand gates; Digital subsystem
Processor, memory, etc
PROM (Programmable ROM) VLSI - Thousands of gates; Digital system
- Store info electrically using PROM programmer at the user’s site Microprocessor, memory module
- Unalterable
- Higher cost than ROM -> used in the system development phase Classification by Technology
-> Can be used in small quantity system
TTL - Transistor-Transistor Logic
Bipolar transistors
EPROM (Erasable PROM) NAND
- Store info electrically using PROM programmer at the user’s site ECL - Emitter-coupled Logic
- Stored info is erasable (alterable) using UV light (electrically in Bipolar transistor
some devices) and rewriteable NOR
- Higher cost than PROM but reusable --> used in the system MOS - Metal-Oxide Semiconductor
development phase. Not used in the system production Unipolar transistor
due to erasability High density
CMOS - Complementary MOS
Low power consumption

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