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ABSTRACT
Most linear modern linear regulators use a PMOS architecture. This document covers the key
characteristics of a PMOS LDO and the theory behind these linear regulators.
Contents
1 Fundamentals ................................................................................................................ 1
2 Regulator Sequence ......................................................................................................... 4
List of Figures
1 Constant-Voltage Source ................................................................................................... 1
2 Output-Voltage Error vs Load Resistance ................................................................................ 2
3 Linear Relation Between RIN and RLOAD ................................................................................... 2
4 Basic Linear-Voltage Regulator ............................................................................................ 3
5 PMOS Enhancement FET .................................................................................................. 4
6 Regulation Sequence When RLOAD Drops ............................................................................. 5
7 Regulator Block Diagram ................................................................................................... 5
8 PMOS Input/Output Characteristic ........................................................................................ 6
List of Tables
Trademarks
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1 Fundamentals
A voltage regulator is a constant voltage source that adjusts its internal resistance to any occurring
changes of load resistance to provide a constant voltage at the regulator output.
The internal resistance of a constant voltage source (Figure 1) must be significantly smaller than the
external load resistor (RIN << RLOAD) to ensure a constant output voltage over a certain range of load
changes.
RIN
VIN RLOAD
SLVA068A – April 1999 – Revised August 2018 Fundamental Theory of PMOS Low-Dropout Voltage Regulators 1
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Fundamentals www.ti.com
40
30
20
10
0
1 10 100
RLOAD / RIN - Ratio
To minimize the error we need a circuit that senses any occurring load changes and, via some kind of
feedback, adjusts a variable internal resistor to keep a constant ratio of internal-resistance to load-
resistance, as described by Equation 4.
RIN RLOAD u k (4)
When the relationship described in Equation 4 is true, RIN then follows RLOAD in a linear relation, as given
by Equation 4. This circuit is shown in Figure 3.
RIN = k x RLOAD
VIN RLOAD
2 Fundamental Theory of PMOS Low-Dropout Voltage Regulators SLVA068A – April 1999 – Revised August 2018
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www.ti.com Fundamentals
A circuit that achieves this relationship through adjusting the a variable resistor is basically a linear-voltage
regulator, and is shown in Figure 4.
S D
VIN
PMOS
VGS Pass Element
G
R1
VOUT RLOAD
VERR
Error
Amplifier R2
VREF
In the linear-voltage regulator shown in Figure 4, we can identify the building blocks discussed in the
following sections.
SLVA068A – April 1999 – Revised August 2018 Fundamental Theory of PMOS Low-Dropout Voltage Regulators 3
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-ID (mA)
0V -3 V -10 V
S G D
4
-VGS
p p
3
p ± Channel
n - Substrate
2
a) Basic Structure
1
5 4 3 2 1 0 3 6 9 12
2 Regulator Sequence
This section describes the regulation sequence when RLOAD drops as illustrated in Figure 6. Figure 7
depicts how the regulation sequence described relates to the internal LDO blocks.
When the load resistance drops, the output voltage falls from VOUT1 to VOUT2, and the voltage across the
pass element rises from –VDS1 to –VDS2. VP (which is a scaled-down version of VOUT) falls significantly
below VREF causing the gate-source voltage to jump from –VGS1 to –VGS2.
The PMOS FET now conducts harder, increasing the output current from IOUT1 to IOUT2. The output voltage
and, by virtue of VP, the error voltage start to recover. The gate voltage increases gradually to –VGS3, thus
causing the increased output current IOUT3 to generate an output voltage VOUT. When this output voltage is
scaled down via R1 and R2, the result is a zero-error voltage VERR = 0.
The output characteristic illustrated in Figure 8 confirms the regulation sequence. When RLOAD drops, the
PMOS FET operating point jumps from P1 to P2 and then regulates to P3.
4 Fundamental Theory of PMOS Low-Dropout Voltage Regulators SLVA068A – April 1999 – Revised August 2018
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www.ti.com Regulator Sequence
RLOAD Drops
VOUT
VOUT1
VOUT2
0 t
-VDS
-VDS2
-VDS1
0 t
VERR
VREF
Vp
0 t
VERR
-VGS
-VGS3
-VGS2
-VGS1 Negative VGS
Turns The PMOS
On Harder
0 t
IOUT (ID)
IOUT3
IOUT2
IOUT1
0 t
Figure 6. Regulation Sequence When RLOAD Drops
-VDS
S D
VIN
PMOS
-VGS Pass Element
G
R1
VOUT RLOAD
VERR
Error
Amplifier R2
VREF
SLVA068A – April 1999 – Revised August 2018 Fundamental Theory of PMOS Low-Dropout Voltage Regulators 5
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Regulator Sequence www.ti.com
-ID
IOUT3 P3
-VGS3
-VGS
IOUT2
-VGS2
IOUT1 P2
-VGS1
P1
-VGS -VDS
-VGS3 -VGS1 -VDS1 -VDS2
-VGS2
For a given quiescent point PN where the output voltage is stabilized (that is, VOUT and VDS are constant),
we can define the internal resistance of the PMOS FET, and the load resistance in general terms as
described in Equation 6:
VDS
RINN
I OUTN
and
VOUTN
RLOAD
I OUTN
Solving both equations for IOUT yields:
VDS V
I OUTN
RINN R
Solving for RIN results in:
VDS
I OUTN RLOAD u
VOUT (6)
With k = VDS/VOUT, Equation 6 provides the linear relation required by a linear voltage regulator.
6 Fundamental Theory of PMOS Low-Dropout Voltage Regulators SLVA068A – April 1999 – Revised August 2018
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