ANALOG TO DIGITAL INTERFACING

ADC0804 Family:

The ADC0804 Family are ADC0803, ADC0804 and ADC0805 are

CMOS 8-bit successive-approximation analog to digital
converters. These devices are design to operate from common
microprocessor control buses, with tri-state output latches
driving the data bus, and are identical except for accuracy.
Pin Diagram of ADC0804 Family:

Fig. 14.120 shows the pin diagram of ADC0803, ADC0804 and

ADC0805. IN+ and IN- inputs allow application of differential
input voltage which has high common mode rejection and
eliminates offset due to the zero input analog voltage value.
The devices can operate with an external clock signal or, the on
chip clock generator can be used independently by adding an
external resistor and capacitor to set the time period.
Features of ADC0804 Family:

 8-bit successive approximation ADC

 Conversion time 100 μs

 Access time 135 ns.

 It has an on-chip clock generator.

 It does not require any zero adjustment.

 It operate’s on single 5V power supply.

 Output meet TTL Output meet TTL voltage level

specifications.
When the WR input goes low, the internal successive
approximation register (SAR) is reset. As long as both CS and
WR remain low, the analog to digital converter will remain in its
reset state. One to eight clock periods after CS or WR makes a
low-to-high transition, conversion starts. The INTR signal its
held high during conversion process. After conversion, INTR
goes low which is used as end of conversion signal. By making
CS and RD signals low, an output can be read through DB 0 to
DB7 data signals.
Analog Inputs of ADC0804 Family:

As mentioned earlier, there are two analog inputs to

ADC0803/0804/0805 : IN+ and IN-. These inputs are connected
to an internal operational amplifier and are differential inputs.
The differential input rejects the common mode noise and
eliminates offset at zero analog input voltage.

The Fig shows a few ways to use these differential inputs. The
Fig 14.121 (a) shows the one way to use single input that can
vary between 0V and +5V. Using another way variable voltage
can be applied to the Vin, (—) pin so that the zero reference for
Vin (+) can be adjusted, as shown in Fig.
Clock Signal:

The ADC0803/0804/0805 requires a clock source ranging 100

kHz to 1460 kHz for operation. The clock signal can be applied
external or it can be generated with an RC circuit, as shown in
the Fig. 14.122. When the RC circuit, shown in Fig. is used to
generate the clock, the clock frequency is given as

Note : To have a minimum conversion time clock frequency

should be kept nearer to 1460 kHz.
Typical Interface of ADC0804 Family:

Fig. 14.123 shows the interfacing of ADC 0803, ADC 0804 and
ADC 0805 with microprocessor system.
Interfacing the ADC 0803/0804/0805 to 8086
Microprocessor:
Fig. 14.133 shows the interfacing of ADC 0803/0804/0805 to
the 8086 microprocessor. Here, converted digital data is read
through data bus. The address is decoded using I/O mapped I/O
technique. As shown in the Fig.14.133, address for ADC is 8011
The Fig. 14.134 shows the timing diagram of ADC operation.
The conversion starts when CS and WR signals go low. The end
of conversion is indicated by INTR output of the ADC. The INTR
output goes low after conversion is over. Therefore, INTR signal
is polled through data bus by enabling a buffer to detect the
end of conversion. Once the conversion is over, the digital data
is read by activating I/O read command. This is illustrated in the
following procedure.
Interfacing ADC 0803/0804/0805 to 8086 using 8255:

Fig. 14.135 shows the interfacing of ADC 0803/0804/0805 to

8086 using 8255. Here, port A of 8255 is used to read digital
data from 8255. The start of conversion signal (WR and CS  =
low) generated using port B, PB0 pin. The end of conversion is
detected by polling INTR pin through PC0.

DAC0830 Digital to Analog Converter(DIGITAL TO

ANALOG INTERFACE)

The DAC0830 Digital to Analog Converter is an advanced CMOS

8-bit DAC designed to interface directly with the 8080, 8048,
8085, Z80, and other popular microprocessors. A deposited
silicon-chromium R-2R resistor ladder network divides . the
reference current and provides the circuit with excellent
temperature tracking characteristics (0.05% of Full Scale Range
maximum linearity error over temperature). The circuit uses
CMOS current switches and control logic to achieve low power
consumption and low output leakage current errors. Special
circuitry provides TTL logic input voltage level compatibility.
Double buffering feature allows this DAC to output a voltage
corresponding to one digital word while holding the next digital
word. This permits the simultaneous updating of any number of
DACs.
The DAC0830 Digital to Analog Converter series
(DAC0830/DAC0831/DAC0832) are the 8-bit members of a
family of microprocessor-compatible DACs. For applications
demanding higher resolution, the DAC1000 series (10-bits) and
the DAC1208 and DAC1230 (12-bits) are available alternatives.
Features:

 Double-buffered, single-buffered or flow-through digital

data inputs.
 Easy interchange and pin-compatible with 12-bit DAC1230
series.
 Direct interface to all popular microprocessors.
 Built-in facility for zero adjustment.
 Works with ± 10V reference voltage.
 Can be used in the voltage switching mode.
 Logic inputs which meet TTL voltage level specifications.
  Operates “STAND ALONE” (without up) if desired.
 Available in 20-pin small-outline or molded chip carrier
package.

Pin Diagrams:

Fig shows the pin diagram of DAC0830 Digital to Analog

Converter. The function of each pin is explained in Table 14.12.
Functional Block Diagram:

A most unique characteristic of this DAC is that the 8-bit digital

input byte in double-buffered, as shown in the Fig. 14.112. This
means that the data must transfer through two independently
controlled 8-bit latching registers before being applied to the R-
2R ladder network to change the analog output. The addition of
a second register allows two useful control features. First, any
DAC in a system can simultaneously hold the current DAC data
in one register (DAC register) and the next data word in the
second register (input register) to allow fast updating of the
DAC output on demand. Second, and probably more important,
double-buffering allows any number of DACs in a system to be
updated to their new analog output levels simultaneously via a
common strobe signal.
Double-Buffered Operation:

Updating the analog output of this DAC in a double-buffered

manner is basically a two step or double write operation. In a
microprocessor system two unique system addresses must be
decoded, one for the input latch controlled by the CS pin and a
second for the DAC latch which is controlled by the XFER line. If
more than one DAC is being driven, Fig. 14.113, the CS line of
each DAC would typically be decoded individually, but all of the
converters could share a common XFER address to allow
simultaneous updating of any number of DACs. The timing for
this operation is shown, Fig. 14.114.
It is important to note that the analog outputs that will change
after a simultaneous transfer are those from the DACs whose
input register had been modified prior to the XFER command.
The ILE pin is an active high chip select which can be decoded
from the address bus as a qualifier for the normal CS signal
generated during a write operation. This can be used to provide
a higher degree of decoding unique control signals for a
particular DAC, and thereby create a more efficient addressing
scheme.
Another useful application of the ILE pin of each DAC in a
multiple DAC system is to tie these inputs together and use this
as a control line that can effectively “freeze” the outputs of all
the DACs at their present value. Pulling this line low latches the
input register and prevents new data from being written to the
DAC. This can be particularly useful in multiprocessing systems
to allow a processor other than the one controlling the DACs to
take over control of the data bus and control lines. If this
second system were to use the same addresses as those
decoded for DAC control (but for a different purpose) the ILE
function would prevent the DACs from being erroneously
altered.
Analog Output:

In the case of the DAC0830 Digital to Analog Converter, the

output, IOUT1, is a current directly proportional to the product of
the applied referenced voltage and the digital input word. For
application versatility, a second output, Tarn, is provided as a
current directly proportional to the complement of the digital
input. Basically:

where the digital input is the decimal (base 10) equivalent of

the applied 8-bit binary word (0 to 255), VREF is the voltage at
pin 8 and 15 kΩ is the nominal value of the internal resistance,
R, of the R-2R ladder network.
Typical Connection:

Fig. 14.115 shows the typical connection to interface DAC0830

Digital to Analog Converter to a microprocessor. As shown in
the Fig. 14.115, microprocessor sends digital data to DAC
through the data bus. The DAC0830 gives the converted output
in current form and this output is converted into voltage form
by external op-amp.
Interfacing DAC 0830 with 8086:

The DAC0830 Digital to Analog Converter is connected to 8086

microprocessor, as shown in the Fig. 14.118. Here, I/O port
address is decoded using_ OR gate. The digital data is loaded
into DAC0830 when A0-A7 lines, WR and IO/M signals are low.
This gives us the address for DAC0830 as 00H and the data can
be loaded in the DAC0830 by OUT 00H,AL instruction, where AL
register contains the digital data to be sent to DAC0830. The IC
741, the operational amplifier is used to convert current output
of DAC0830 to voltage output. The voltage output of the
operational amplifier is used to drive the DC motor after
increasing the driving capacity. The driving capacity is increased
by using the darlington transistor.
Interfacing DAC0830 with 8086 Using 8255:
Fig. 14.119 (see on previous page) shows the interfacing of
DAC0830 to 8086 Microprocessor using 8255. Here, port A of
8255 is used to send data to the DAC0830 and the XFER signal is
generated by programming PB0 pin of 8255. The 8255 is
interfaced to 8086 system in I/O mapped I/O with address : PA
= 00H, PB = 02H, PC = 04H, PC= 06H.
Stepper Motor Interface:

A stepper motor is a digital motor. It can be driven by digital

signal. Fig. 15.18 shows the typical 2 phase Stepper Motor
Interface using 8255. Motor shown in the circuit has two
phases, with center-tap winding. The center taps of these
windings are connected to the 12V supply. Due to this, motor
can be excited by grounding four terminals of the two windings.
Motor can be rotated in steps by giving proper excitation
sequence to these windings. The lower nibble of port A of the
8255 is used to generate excitation signals in the proper
sequence.
The table 15.3 shows typical excitation sequence. The given
excitation sequence rotates the motor in clockwise direction.
To rotate motor in anticlockwise direction we have to excite
motor in a reverse sequence. The excitation sequence for
Stepper Motor Interface many change due to change in winding
connections. However, it is not desirable to excite both the
ends of the same winding simultaneously. This cancels the flux
and motor winding may damage. To avoid this, digital locking
system must be designed. Fig. 15.19 (c) shows a simple digital
locking system. Only one output is activated (made low) when
properly excited; otherwise output is disabled (made high).

The excitation sequence given in Table 15.3 is called full step

sequence. In which excitation ends of the phase are changed in
one step. The excitation sequence given in table 15.4 takes two
steps to change the excitation ends of the phase. Such a
sequence is called half step sequence and in each step the
motor is rotated by 0.9°.
We know that Stepper Motor Interface is stepped from one
position to the next by changing the currents through the fields
in the motor. The winding inductance opposes the change in
current and this puts limit on the stepping rate. For higher
stepping rates and more torque, it is necessary to use a higher
voltage source and current limiting resistors as shown in Fig.
15.20.
By adding series resistance, we decrease L/R time constant,
which allows the current to change more rapidly in the
windings. There is a power loss across series resistor, but
designer has to compromise between power and speed.

REFERENC E-2 : STEPPER MOTOR INTERFACING

Interfacing to Stepper Motor:
 A stepper motor is a device used to obtain an accurate
position control of rotating shafts.
 It employs rotation of its shafts in terms of steps, rather
than continuous rotation as in case of AC or DC motors.
 To rotate the shafts of the stepper motor, a sequence of
pulses is needed to be applied to the windings of the
stepper motor in a proper sequence.
 The number of pulses required for one complete rotation
of the shaft of the stepper motor are equal to its number
of internal teeth or its rotor.
 The stator teeth and the rotor teeth lock with each other
to fix a position of the shaft.
 With a pulse applied to the winding input the rotor rotates
by one teeth position or an angle x.
 The angle x=3600 /no. of rotor teeth
 After the rotation of the shaft through angle x, the rotor
locks itself with the next tooth in sequence on the internal
surface of stator.
 A typical stepper motor may have parameters like torque
3Kg-cm, operating voltage 12V, current rating 0.2A and a
step angle 1.80,
i.e. 200 steps/revolution (number of rotor teeth).
 The stepper motors are designed to work with digital
circuits.
 Binary level pulses of 0-5V are required at its winding
inputs to obtain the rotation of shafts.
 The sequence of pulses can be decided upon the required
motion of the shaft.
 The circuit for interfacing a winding Wn with an I/O port is

 Each of the windings of a stepper motor need this circuit

for its interfacing with output port
 A simple scheme for rotating the shaft of stepper motor is
called a wave scheme.
 In this scheme, the windings Wa,Wb,Wc and Wd are applied
with required voltage pulses, in a cyclic fashion.
 The count for rotating the shafts of stepper motor through
a specified angle may be calculated from number of rotor
teeth.
 The number of rotor teeth is equal to the count of one
rotation i.e.3600.
 Hence for any specified angle θ0 the count is calculated as

FIG:STEPPER MOTOR INTERFACING WITH 8255