Lab 4.

SIMULATION OF DIGITAL-ANALOG CONVERTERS

The lab intends to help students understand the behavioral basics of
R-2R network digital-analog converters, using both bipolar and CMOS IC
technologies.
THE LAB PURPOSE
A special written program simulates digital-analog converters
previously discussed at class, emphasizing several non-ideal parameters of
the implied circuits (Slew-Rate, setting time, etc.). Most parameters can be
modified in certain ranges, but there are also fixed value parameters (i.e.
transition times for input bits correspond to TTL family standard).
The students perform steps similar to designing, building and testing
of an experimental D/A circuit:
CHOOSING THE SCHEMATIC TYPE
Three types of schemes are available:
CMOS-technology converter, voltage output
Fig. 1 represents the internal structure of AD7520 A/D converter.
The basic structure shown is similar to a whole family of CMOS integrated
A/D converters, differing in the bit number, equivalent resistance or
additional provided features.
Fig. 2 shows the typical usage of that circuit (voltage output). The
equivalent resistance of the R-2R network is Rech = 10k, measured at Ref
pin to Io, Io and ground, all tied together. Both the reference voltage and
reference current and the output currents could have both signs (directions).
For correct polarization of the R-2R resistor network, Io and Io pins have to
be forced at zero voltage (virtual ground) by mechanisms external to the DA
converter chip (i.e. the virtual ground at inverting input for a negative feedback
OA stage). The speed performance is strongly limited by the operational
amplifier Slew Rate but also by the converter chip setting time.
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Data Conversion and Acquisition Systems - Lab Manual

BIT 1 (MSB)

V ref

BIT 2

BIT 3

Iref

BIT N (LSB)

2R

...
2R

2R

S-1

2R

S-2

2R

S-3

S-N

Rr

AD7520
Io

Io

Rr

Fig. 1 The internal basic structure of a CMOS technology DA converter IC

Rout
Iref

{A}
. . .

V ref

Io

D/A CMOS

(A D7520)

Io

V out

Fig. 2 The typical usage schematic for CMOS technology DA converter IC

Simulation of digital-analog converters

BIT1 ( MSB)

BIT2

BITN ( LSB)

Bipolar-technology converter, voltage output

Fig. 3 shows the internal structure of DAC08 digital to analogIo
converter IC. Once again, the basic structure is common for a whole D/AIo
bipolar DAC08
technology integrated converter family, differentiate by the bit
number, equivalent resistance
and additional
provided features.
S-1
S-2
S-N
The internal R-2R network equivalent resistance is Rech=1.2k, but the
Iref
value
is not measurable at external pins. The R-2R network polarization is
+
+
performed by IC internal mechanisms, Io and Io.... pins can have non-zero
voltages.
The reference voltage and current, as the output currents can be
only positive (all the
currents
enter2R the chip). The value2Rof the reference
R
2R
2R
current is imposed only by devices external to the converter chip (Vref and Rref).
The schematic shown by Fig. 4 uses the....
converter IC with voltage
R
R
R
output. A negative feedback OA output
stage
is not mandatory,
although it is
used. The setting time-V alim
of the converter IC is much smaller than for a CMOS
converter,
howeverbasic
the overall
performance
is strongly
limited IC
by the
Fig.
3 The internal
structurespeed
of a bipolar
technology
DA converter
Rout
OA Slew-Rate.

{A }

. . converter,
.
Iref
Bipolar-technology
current output
V ref The schematic shown in Fig. 5 corresponds to the typical usage of the
Io
+
Rref The output stage
D/A Bipo
DAC08 IC.
islarthis times a simple resistor (Rout)V out
to ground,
flown by output current Io(DA
. The
C08)voltage
Io at Io pin is the voltage drop across Rout,
obviously non-zero. The setting time of the converter IC is much smaller than
for a CMOS converter and is not any more limited by output stage.

Fig. 4CONFIGURING
The typical usage(DESIGNING)
schematic for aTHE
bipolar
technology DA converter
SCHEMATICS.
IC, voltage output.

D/A Converter
{A }
. .
Irefbooks.specify
The data
values for behavioral parameters of AD7520
V ref DAC08 ICs. However, the simulation program
V out
and
allows the user to set
Io
Rref
D/A
Bipo
lar
different values. That corresponds somehow to the reality, meaning the two
Rout
mentioned circuits are representative
for their technologies. Beside them,
(DA C08)
Io
there are many circuits available, with similar basic structures, but different
performances.

Fig. 5 The typical usage schematic for a bipolar technology DA converter

IC, current output.
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Data Conversion and Acquisition Systems - Lab Manual

The output stage
The Rout value is settable. For voltage output schematics, OA
parameters are settable also.
DEFINING THE INPUT QUANTITIES
(supply- and reference-voltages, clock frequency, binary input number)
Reference voltage supply
Could be set constant (zero frequency => digital-to-analog converter
behavior), or variable (digital gain controlled amplifier or multiplying stage).
Digital code generator
A binary counter (the same bit number as the DA converter itself) or
an astable circuit can be simulated. In the last case, two numbers need to be
specified: the low (minimum) and the high (maximum) values, which alternate
at each clock signal active slope. Specifying two identical values forces a
constant number at the DA converter input (digital gain controlled amplifier).
SCOPE-SCREEN LIKE ANALYSIS
The program allows visualizing signal shapes picked up at several
interesting points in the schematic. An 8-channel (3 analog, 5 logical, binary)
memory scope is simulated. The vertical and horizontal scaling is somehow
different compared to a real scope:
vertical scaling (analog signal amplification) is automatically set to fit the
symmetrical supply range.
horizontal scaling (time base) is set expressed in tact/division. The image
is scaled such a way that a division (1/10 of the screen length) to enclose the
specified number of tact periods (the tact period is specified at code generator),
regardless its actual value. The time period for a division and the time values
for the screen boundaries are posted on the up side of the screen.
The shown signals are:

Simulation of digital-analog converters

Analog signals:
Vref = the reference voltage (as defined).
Vout = output voltage.
V- = the voltage at the inverting input of the output stage OA. The signal is
missing in the schematic not using an OA. Normally, negative feedback forces
that voltage to equal the non-inverting input one (zero differential input
voltage). Due to the output voltage limitations (static: |Vout| < |Vali|, dynamic |d(Vout)/dt|<Slew Rate), the negative feedback doesnt work properly
sometimes, bringing V- at non-zero values.
Logical signals
are shown as logical values only (the actual amplitude of the carrier voltage is
not shown):
the clock signal of the code generator. Each active (rising) slope changes
the digital input value, in a manner corresponding to the chosen type.
the most significant 4 bits of the digital input. If a converter having
more than 4 bits was chosen, the less significant ones are not shown, but
their value does influence Vout and eventually V-. The propagation delay
times for the TTL family are shown by different delays for rising and falling
slopes. The hexadecimal digital input value is shown at each division begin.
SIMCNA PROGRAM PRESENTATION
SIMCNA program uses a tree command menu. The current branch
available commands are displayed in the lower left screen corner. Pressing
the appropriate letter or digit shown in the list launches a command.
Choosing a schematic correspondingly modifies the diagram at
screen bottom. The simulated signals are shown on the schematic.
The full menu includes the following commands:
A: Parameter display (the list of all considered parameters)
T: Schematic type

1: bipolar D/A, I output (current output)

2: bipolar D/A, U output (voltage output)
3: CMOS D/A, U output (voltage output)
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Data Conversion and Acquisition Systems - Lab Manual

C: Configure
C: D/A Converter
N: Bit number (4...12).
T: Setting time (1...10000ns)
L: Reference limit -Iref max. (1...10mA)
(bipolar DAC)
-Input stage Slew-Rate (1...100mA/s)
- Rref (0.1...100k)
L: Reference limit - Vref max. (1...15V)
(CMOS DAC)
S: Reference F: Frequency (0...10000kHz)
supply
O: Offset (-20...20V)
A: Amplitude (0...20V)
T: Signal type
S: Sinus
T: Triangle
D: Rectangle
G: Code
D: Clock period (0.01...1000s)
generator T: Code type
N: Counter
A: Astable - low val. (0...2n-1).
- high val.(0 ... 2n-1)
M: Output
stage

R: Output resistance (0.01...10000k)

S: OA Slew-Rate (0.1...100V/s)
T: Supply voltage (0.1...30V)

B: Time base 1: 1/10 tact/division

2: 1/3 tact/division
3: 1 tact/division
4: 3 tact/division
5: 10 tact/division
S: Simulate
E: Exit
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Simulation of digital-analog converters

The schematic parameters can be modified in the configuration
menu. The Parameters are grouped in four simulated objects: the reference
supply, the code generator, the D/A converter and the output stage. The
changing parameter widow shows the parameter meaning, the measuring
unit, the allowed range and the old value. An outside-range value is rejected.
To keep the old value, press Enter, without typing a value.
Once the schematic type or configuration menu is activated, the
subsequent simulation starts the time at zero and all the initial values are set
to zero also. Otherwise, successive simulation commands produce
successive time windows (the time-length depending on the chosen time
base), each starting at the endpoint of the previous one. However, displaying
the parameters or changing the time base, does not reset the start time value.
THE LAB FLOW
All the provided schematic types are analyzed, one by one. First, a
"reasonable" configuration is set, to generate a close-to-ideal output signal.
The parameters are then changed, one by one, analyzing the simulation
effect. Explain the mechanism leading to the observed effect. Show the
range for the modified parameter to keep acceptable errors (obviously, in
correlation to other parameter values).
Step by step, different configurations are set to emphasize on:
- output stage OA Slew Rate
- limiting Vout at supply voltage
- converter IC setting time
- reference stage AO Slew Rate (for bipolar technology converter IC)
- propagation time delays (different for low-to-high and high-to-low
transitions).
Set such configurations to simulate real circuits (A741, DAC 08,
AD7520). Find the input signal limit parameter values to keep the schematic
working properly.