USN

CAMBRIDGE INSTITUTE OF TECHNOLOGY

K.R. PURAM, BENGALURU-560036

Department of [(type in bold letters) (font 14)]

Program: B.E. M.Tech. Specialization: (unbold)

Third Internal Assessment - Odd Semester 2020-21

Sub. Name: Verilog HDL Sub. Code:18EC56/15EC53/17EC53 Semester: 5

Date: 06-01-2021 Time: 2 to 3.30PM Duration: 90 Minutes Max. Marks: 50

[Note: Answer any 2 full questions as indicated below]

Sl. QUESTIONS COs
RBT Marks
No. Levels
Describe regular timing control and named event timing control with CO4 L2 07M
a)
an example.
1. b) Write behavioral modeling for 4 bit counter program in Verilog. CO4 L2 08M

c) Illustrate initial statements and always statements with an example. CO4 L3 10M
OR
a) Explain while loop and forever loop with an example. CO4 L2 07M

2. b) Explain Function declaration and Function invocation with examples. CO4 L2 08M

c) Discuss Task declaration and Task invocation with examples CO4 L3 10M

With example explain assign and deassign keywords in procedural CO5 L2 07M
a)
continuous assignments.
3. With explain force and release keywords in procedural continuous CO5 L2 08M
b)
assignments.
c) Explain Value change dump file with neat block diagram CO5 L3 10M
OR
With neat diagram explain basic computer aided logic synthesis CO5 L2 07M
a)
process.
4. b) Discuss about the impact of logic synthesis CO5 L2 08M

c) Explain logic synthesis flow from RTL to gates with neat diagram CO5 L3 10M

Name & Signature Scrutinized by (Name & Signature)

of Course Instructors 1)

1) Girish H 2)
2) Mahendra B M HOD

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