IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO.
8, AUGUST 2007 1393
Realizable Reduction of RC Networks
Bernard N. Sheehan, Member, IEEE
Abstract—In this paper, we develop from various points of view
the TIme-Constant Equilibration Reduction (TICER) algorithm,
a circuit-reduction method that converts a given RC network into
a smaller RC network (one with fewer nodes and branches) by
eliminating nodes that have few neighbors and small nodal time
constants. Advantages of TICER include: great efficiency, intuitive
error control, preservation of sparsity, output in the form of an
RC network, and the ability to handle networks with many ports.
Index Terms—Interconnect modeling, model-order reduc-
tion (MOR), parasitic extraction, time-constant equilibration
reduction (TICER).
I. I NTRODUCTION
M ODEL-ORDER reduction (MOR) of electrical networks
describing interconnect in integrated circuits has been
an important area of research since the early 1990s. Krylov-
subspace methods like Padé Via Lanczos (PVL) and passive
reduced-order-interconnect macromodeling (PRIMA) have es-
pecially received a great deal of attention [4], [13]. While these
methods can be effective, they suffer notable disadvantages
that are seldom mentioned in the literature. For example, these
methods take in an RC or RLCM network but produce some-
thing quite different, a set of poles and zeros perhaps, or an ab-
stract system of ordinary differential equations (ODEs) that can
be recast as an electrical circuit only by constructing a nexus
of controlled current and voltage sources [14]. Furthermore,
some Krylov methods can experience numerical issues, making
the goal of a robust commercial implementation elusive.1 They
produce dense systems; sparsity—a highly desirable trait of
most real-life circuits—is lost. Short of undertaking periodic
post hoc error calculations as moments are added, these meth-
ods leave one guessing as to how many moments must be
matched. Moreover, the methods falter on networks with many
ports (see [5] and [26] for two efforts to fill this breach).
The balanced-truncation method (BTM) is the method pre-
ferred by control theorists [12], but this method is probably too
costly O(n3 ) for the large systems electrical engineers want to
reduce; see [15].
Logically, a third category of MOR techniques are what
we call elimination methods. Whereas Krylov-subspace tech-
niques might be likened to the conjugate-gradient algorithm for
Manuscript received January 6, 2006; revised June 7, 2006 and November 1,
2006. This paper was recommended by Associate Editor J. R. Phillips.
The author is with the Mentor Graphics Corporation, Wilsonville, OR
97070 USA.
Digital Object Identifier 10.1109/TCAD.2007.891374
1 For example, the pole-residue decomposition, which is the second phase
of the PRIMA algorithm, generally assumes that the system has only simple
distinct poles. Treatment of higher order poles (i.e., Jordan form) can be tricky
and is not well conditioned. Another robustness issue is that sometimes the
projected G matrix can be singular.
0278-0070/$25.00 © 2007 IEEE
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solving linear equations (both seek solutions within a Krylov
subspace), and loosely speaking, BTM might be classed as
the analog to singular value decomposition methods for least
squares problems (both work with singular values), the third
approach to reduction, reduction by elimination, might be re-
garded as the counterpart to solving systems of equations by
Gaussian elimination.
Krylov methods, BTM, and elimination methods each have
their pros and cons. For many networks, the Krylov approach
might achieve the most reduction. Yet, for some types of
networks—local networks with few elements and many ports,
say, or power distribution networks riddled with ports—Krylov
methods might be quite helpless to provide any reduction,
whereas elimination methods might still be effective for such
nets. BTM methods are the choice when global error bounds are
required. In short, just as an artist may choose different colors
for different visual effects, the computer-aided-design engineer
may prefer different reduction methods for different purposes.
No single reduction method surpasses all others in all respects.
In this competition of methods, elimination methods for
MOR do have important advantages: They are easy to imple-
ment (they do not require, for instance, sparse-matrix solvers or
eigensolvers, unlike PVL or PRIMA); they are highly efficient,
due to the near O(n) run time associated with local operations
on a sparse graph; they produce an output that takes the form
of an RC network whose topology echoes the original circuit’s
structure; they preserve sparsity; and they are capable of dealing
with networks with many ports.
This paper presents one approach to elimination MOR by de-
veloping in detail, with an accent on theory, the TIme-Constant
Equilibration Reduction (TICER) algorithm [20]. In Section II,
we summarize the history of elimination methods; next, to
throw light on different facets of the theory, we deduce the
TICER nodal-elimination algorithm by each of the four avenues
of attack: First, in Section III, we integrate the convolution
integral by parts; in Section IV-A, we do a series expansion
of the Schur complement; in Section IV-E, we substitute the
“quasi-dc approximation” (to be explained) into expressions for
current and charge; and finally, in Section IV-F, we perform
dc projection. We briefly interrupt this tour of alternate view-
points, in Section IV-B–D, to discuss implementation issues.
In Section VI, we present experimental results. In Section VII,
we compare TICER to a competing algorithm [3], and in
Section VIII, we look at the issue of error accumulation. Proofs
of a number of theorems are given in the Appendix.
II. H ISTORY OF N ODAL -E LIMINATION M ETHODS
Applied to circuit reduction, an early instance of nodal-
elimination methods is found in the mid-1980’s work of Harbor
1394 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 8, AUGUST 2007

and Drake [7], who worked out a frontal wave approach that
eliminated the internal nodes of a resistive mesh obtained
by finite-difference discretization of Laplace’s equation. The
same authors later extended their method to networks with
capacitance [8] by introducing special polynomial multiply and
divide operations

(a + bs)(c + ds) = ac + (ad + bc)s (1)

Fig. 1. Circuit before elimination of v3 .
(a + bs) a (bc − ad)
= + s (2)
(c + ds) c c2 III. E LIMINATION A PPLIED TO RC N ETWORKS
To introduce our method, let us work through an example of
and formally carrying out Gaussian elimination using this how a variable can be eliminated from a set of ODEs describing
special arithmetic. The authors casually remark that negative an RC network. We take as our example the circuit of Fig. 1.
capacitances crop up with this method. The nodal equations for this circuit are
In 1988, van Genderen and van der Meijs [24] outlined a
nodal-elimination method for RC networks which prescribes a c1 v̇1 + gd v1 + g13 (v1 − v3 ) = j(t)
formula identical to (27). They obtained the formula by forcing c2 v̇2 + g23 (v2 − v3 ) = 0
the new circuit to match the Elmore delays of the old. In this c3 v̇3 + g13 (v3 − v1 ) + g23 (v3 − v2 ) = 0. (3)
early work, the authors did not yet apprehend the need to
control error; instead, quite optimistically, they eliminated all
A. Convolution Integral
“superfluous” (nonport) nodes.
In 1990, Stark and Horowitz [23] presented a method for By analogy with variable elimination in algebra, we pick the
reducing resistive supply meshes that coincides with (45). third equation in (3) and solve it for v3 ; the solution takes the
A few years later, Vanoostende et al. [25] assembled various form of a convolution integral
heuristics for reducing extracted RC networks, again guided
mainly by the goal of preserving Elmore delays. With this
t
1 −(t−u)
τ3
paper, we first see an inchoate awareness of the need to limit v3 (t) = e [g13 v1 (u) + g23 v2 (u)] du (4)
c3
the elimination process to ensure accuracy: “We do not sys- −∞
tematically reduce all nodes,” the authors caution, “because
where
approximation of a long line requires a number of sections.”
In 1996, Elias and van der Meijs [3] carry this recognition c3
τ3 ≡ . (5)
to the next level by proposing a selective nodal-elimination g13 + g23
algorithm regulated by an explicit metric of the error incurred
Now, (4) is not a friendly expression to substitute into the
when a node is removed.
remaining two equations of (3). To make progress, we must
In 1999, unaware at the time of Elias and van der Meijs’s
simplify; we do this by integrating (4) by parts
work (EM), Sheehan introduced the TICER algorithm [20],
which used nodal time constants as a simple physically relevant g13 v1 (t) + g23 v2 (t)
metric for deciding which nodes should be eliminated from v3 (t) =
g13 + g23
an RC network. In Section VIII, we compare the EM and
t  
nodal time-constant metrics and argue that the latter is to be τ3 −(t−u) dv1 dv2
− e τ3 g13 + g23 du. (6)
preferred. c3 du dt
−∞
Subsequent to [20], a number of papers have attempted to
generalize the TICER algorithm in various ways: higher order We note that the second term can be bounded by
Y –∆ transformations [16], [18], nodal elimination in circuits  

t   
with inductance [1], [19], [21], and port consolidation [17].  τ3 dv dv 
 e−(t−u)/τ3 g13
1
+ g23
2
du
This paper undertakes to give a thorough exposition of the  c3 du dt
TICER algorithm with emphasis on its conceptual founda-  
−∞
 
t       
tions. The theory we present here goes beyond the previously  τ3   −(t−u)/τ3   dv1   dv2 


   e  g13   
+ g23   du
du  du 
published work in several significant respects: The derivation
c3
of the TICER algorithm by integration-by-parts of a convo- −∞
lution integral (Section III-A); the rigorous error bounds in
t
1
Theorems 1 and 3; the discovery of the relation of TICER to dc
e−(t−u)/τ3 (g13 + g23 )M du
g13 + g23
projection (Section IV-F); the detailed discussion (Section VII) −∞
comparing nodal time constants to the metric in [3]; and finally,
t
the error-accumulation arguments in Section VIII are all new.
M e−(t−u)/τ3 du
This paper treats only RC networks, leaving aside the issue −∞
of inductance. = M τ3 (7)

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SHEEHAN: REALIZABLE REDUCTION OF RC NETWORKS 1395

Fig. 2. Circuit after elimination of v3 .

provided
   
 dv1   dv2 
   
 dt 
M and  dt 
M. (8)

Fig. 3. Comparison of response of systems (11) (solid) and (12) (dashed).

In view of (7), it seems reasonable to substitute
and the system after elimination, with c12 omitted, becomes
g13 v1 (t) + g23 v2 (t)        
v3 (t) ≈ (9) 1 0 ẋ1 1 3 −1 x1 2.00 1
g13 + g23 =− + j(t)
0 1 ẋ2 2.01 −1 0 x2 2.01 0
 
into the first two equations of (3) whenever M τ3
ε, ε being a x1
y(t) = . (12)
suitably small number. Such a substitution would achieve our x2
purpose: It would reduce the original system of three ODEs
into a smaller system of two ODEs without increasing the order That this is a plausible replacement for (11) can be seen by
of the differential equations. It would also eliminate variable noting that the transfer function of (11) is
v3 —which is what we set out to do.
This is not the best we can do, however. If we integrate (4) (0.2916)(1.7059) 201.00
H(s) = · (13)
by parts a second time, we get (s + 0.2916)(s + 1.7059) (s + 201.00)
  whereas that of (12) is
g13 v1 + g23 v2 g13 v̇1 + g23 v̇2
v3 = − τ3 + τ32 v̈3 . (10)
g13 + g23 g13 + g23 (0.2984)(1.6987)
H̃(s) = . (14)
(s + 0.2984)(s + 1.6987)
We might be tempted to try a third integration by parts, but
we must stop here. A third integration would introduce second- System (13) “admits of reduction,” we might say, because one
order derivatives, which violates our goal of keeping the system of its poles, s = −201.00, is expendable. It never comes into
in the first order. play except at very high frequencies, where the response is
If we substitute (10)—ignoring the term with v̈3 —into the already highly attenuated due to other low-frequency poles. The
first and second equations of (3), we obtain the following rather practical equivalence of (11) and (12) is manifest in the Bode
interesting result. We discover that the final pair of ODEs can, plots in Fig. 3.
in fact, be interpreted as the nodal equations of a modified Let us summarize this introductory discussion. We have seen
circuit—the circuit in Fig. 2. how variables can be eliminated from ODEs by integrating a
One uncomfortable feature about our solution is that c12 is convolution integral by parts once or twice, then substituting
a negative capacitor; we will have more to say about these the result, with the “remainder” term omitted, back into the
negative capacitors later. other equations. If the original equations represent an RC
Perhaps a numerical example will be helpful. Let gd = g13 = network, we saw that the equations after elimination could also
g23 = 1 and c1 = c2 = 1, c3 = 0.01. Then, (3) becomes be translated back into the form of an RC network. Finally, we
saw how, by imposing the condition that the “remainder” term
       
1 0 0 ẋ1 2 0 −1 x1 1 be small, we obtain a natural criterion for deciding which nodes
 0 1 0  ẋ2  =  0 1 −1  x2  +  0 j(t) might be eliminated.
0 0 1 ẋ3 −100 −100 −200 x3 0
  B. Restatement in the Laplace Domain
x1
y(t) =[ 0 1 0 ]  x2  (11) The integration by parts calculations, which we just com-
x3 pleted, can be carried out more succinctly in the Laplace

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1396 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 8, AUGUST 2007

Some vector notation will simplify our presentation. Define

     
V1 g1N c1N
 V2   g2N   c 
V =    , c =  2N  (18)
 ...  , g =  ..   ..
. 
.
VN −1 gN −1,N cN −1,N

where Vi = L[vi (t)] is the Laplace transform of the ith nodal

voltage. Let diag(x) distribute the elements of vector x along
the diagonal of a matrix.
With this notation, the nodal equations for the circuit in Fig. 4
take the form
    
sC + G + diag(sc + g) −(sc + g) V J
Fig. 4. RC network before eliminating node N . =
−(sc + g)T sCN + GN VN JN
(19)
domain. Assuming no initial charges on capacitors, the Laplace
transform L[•] of the third equation in (3) is where

GN ≡ g1 = g1 + g2 + · · · + gN −1
(c3 s + g13 + g23 )V3 − g13 V1 − g23 V2 = 0. (15)
CN ≡ c1 = c1 + c2 + · · · + cN −1 (20)
Solving for V3 (s) = L[v3 (t)] and introducing the quantity τ3
defined in (5), we have and J ∈ RN −1 and JN are the Laplace transforms of incident
current sources.
1 g13 V1 + g23 V2
V3 = · . (16)
1 + τ3 s g13 + g23 A. Schur-Complement Method
An elegant way to eliminate VN from (19) is by a process
Now, if |τ3 s| 1, which is the s-domain counterpart of
known in mathematics as forming the Schur complement.
M τ3 1, it is reasonable to write
First, solve the second block of (19) for VN
1 (sc + g)T
≈ 1 − τ3 s. (17) VN = ·V +
1
· JN . (21)
1 + τ3 s sCN + GN sCN + GN
Putting this into (16), substituting the resulting expression for Next, insert this expression into the first block of (19) to get
V3 into the Laplace transforms of the other two equations in (3),
and interpreting the result as the system of equations describing [sC + G + diag(sc + g) − E] V = J + f (22)
a circuit, we obtain, again, the circuit of Fig. 2.
Expanding in powers of s is simpler than integrating by where
parts. In what follows, therefore, we will mostly work in the (cs + g)(cs + g)T (cs + g)
s-domain. E≡ , f≡ JN . (23)
sCN + GN sCN + GN
So far, we have made no approximation. In order to simplify
IV. T HEORY OF N ODAL E LIMINATION
(23), define the time constant of node N to be
Let us move at once to the general case and consider how to
eliminate a given nodal voltage variable from the set of ODEs τN ≡ CN /GN . (24)
describing an RC network.
We have encountered this quantity before, for (5) is the nodal
Fig. 4 depicts a general RC circuit with node N singled
time constant of node v3 in the circuit of Fig. 1.
out; N is the node we plan to eliminate. The diagram ex-
The quantity τN has an important dynamical interpretation
plicitly shows all resistors and capacitors joining N to the
which accounts in part for the central role it plays in our theory.
other nodes of the network, i.e., nodes with labels in the set
In fact, it can be shown that the response of N to a step voltage
S = {1, 2, . . . , N − 1}. The quantity giN = 1/RiN is the con-
applied at i ∈ S, all other terminals j = i, j ∈ S being held at
ductance, and ciN is the capacitance joining N to i,
ground, is given by
i ∈ S; in practice, many of these values will be zero. Matrices
G ∈ R(N −1)×(N −1) and C ∈ R(N −1)×(N −1) , represented by  
giN ciN giN
the large box in Fig. 4, stamp interconnections among pairs hiN (t) = + − e−t/τN . (25)
GN CN GN
of nodes in S. We do not need to know the detailed structure
of these matrices, since they do not participate directly in the For our purposes, the key observation is that node N responds
elimination process. Of course, the ground node is necessarily with a characteristic time constant τN that is independent of
in the set S, since ground cannot be eliminated. which neighbor or combination of neighbors switches; in other

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SHEEHAN: REALIZABLE REDUCTION OF RC NETWORKS 1397

words, τN does not depend on i. We may, therefore, speak of

the time constant of a node in a circuit. The smaller a node’s
time constant, the more rapidly it returns to “dc equilibrium”
after a change in any neighbor’s voltage.
Now, suppose |s|CN GN ; equivalently, |sτN | 1; in our
terminology, we shall then say that the eliminated node is a
quick node. In this case, we can approximate the ijth element
Eij = eT i Eej by

 
giN gjN sCN giN cjN + gjN ciN Fig. 5. Implementation of the quick-node elimination rules.
Eij ≈ 1− +s (26)
GN GN GN

this expression being obtained from E in (23) by expanding in

powers of s and retaining terms up to the first order. But, the
second term in the parentheses is negligible by the quick-node
assumption; hence

giN gjN giN cjN + gjN ciN

Eij ≈ +s . (27)
GN GN

There is a simple recipe for translating (27) into an equiva-

lent modified circuit. First, remove all resistors and capacitors
connecting other nodes to N . Then, insert new resistors and
capacitors between the former neighbors of N according to the
following two rules. If nodes i and j had been connected to
N through conductances giN and gjN , insert a conductance
giN gjN /GN from i to j; if node i had a capacitor ciN to N
and node j had a conductance gjN to N then insert capacitor
ciN gjN /GN between i and j. It is easy to verify that the
admittance matrix of the circuit thus modified has offdiagonal
elements which agree with (Y − E) when Eij is given by (27).
Actually, a detailed analysis of the TICER elimination
process—see (35) and (38) later in this paper—shows that
diagonal elements (CN s/GN )giN δij must also be added to
(27) to fully describe the impact of these TICER rules for
changing a circuit. Here, δij is the Kronecker delta function.
The following theorem states that the relative error incurred
by the TICER approximation is small whenever |sτN | 1.
Theorem 1: With the exact Schur correction E that results
from the elimination of node N given by (23), let E TICER be
defined by
gg T s(gcT + cg T ) CN
E TICER ≡ + +s diag(g).
GN GN GN
If |sτN |
ε, then
E − E TICER

E2 · ε {1 + (√mN + mN ε) (1 + ε)}
2 appended to Q, since neighbor RDegs and time constants may
(29)
where mN is the number of neighbors to which N connects
through nonzero conductances and/or capacitances.
Proof: See Appendix.
The quick-node rules justified by the preceeding Theorem are
summarized in Fig. 5. A parallel theory can be developed for
eliminating a slow node—a node whose time constant satisfies
|sτN |  1. See [20] for the treatment of this case, which is less
important in practice.
Fig. 6. TICER algorithm using a queue (see text for an alternative implemen-
tation using a heap).
B. TICER Algorithm
The algorithm for reducing an RC circuit by successively
finding quick nodes and eliminating them by the above pre-
scription is called TICER. See Fig. 6 for a description of the
algorithm based on a queue Q that keeps nodes in line for
consideration for elimination.
Refer to the pseudocode in Fig. 6. The outer loop pro-
gressively steps variable Deg from two to some user-supplied
MaxDeg. For a given pass of the outer loop, all nodes that are
not fixed (fixed nodes are nodes which the user has designated
to be left alone) and that have not been eliminated in previous
steps, are placed on queue Q. Nodes then are successively
popped from Q until the queue is empty. If the current node N
has an RDeg (number of incident resistors) less than or equal
to the value of Deg stipulated for that pass, it is considered
for elimination. Its time constant is calculated, and if τN is
(28) sufficiently small (as controlled by f max , the maximum oper-
ating frequency of interest, and ε, a small number enforcing
the requirement that |sτN | be much less than one), the node
is eliminated using the quick-node rules; otherwise, the node
is left as is. Whenever a node is eliminated, its neighbors are
change and so neighbor nodes ought to be reconsidered for
elimination.
It is easy to add in techniques to keep down the size of Q.
For example, whenever nodes are added to Q (lines 2 and 8),
one need only add those nodes to the queue whose RDegs are
less than or equal to the current Deg and whose time constants
satisfying 2πf max τN ≤ (. One still, of course, must verify that
these conditions (lines 5 and 7) hold when a node is popped
from the queue, since a node’s RDeg and τ may change during

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1398 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 8, AUGUST 2007

the time the node is on the queue. Another efficiency strategy argument based on the so-called quasi-dc approximation, i.e.,
is to avoid duplicates in the Q. An easy way to ensure this is
N −1
to associate a flag IsInQueue with each node. The flag is set 1 
vN (t) ≈ gjN vj (t). (30)
whenever a node is added to the queue and cleared whenever it GN j=1
is removed from the queue. Before a node is added to the queue,
one checks the value of IsInQueue; if the flag is set, one omits We will examine in a moment the validity of (30)—in essence,
adding the node to the queue (since it is already in the queue). it assumes that the exponential term in (25) dies away so rapidly
Leaf nodes—nodes of RDeg 1—require special processing. that its contribution can be neglected. For now, assume (30)
Such nodes are usually ports (connection points to gates or holds; then, the current flowing from node i to node N through
transistors) and are, therefore, fixed. Occasionally, however, giN equals
one might be asked to reduce a network and only the response
from the driver to a particular receiver or subset of receivers giN (vi (t) − vN (t))
is of interest. By not fixing the other receiver ports, one might  

N −1
1
get a little more reduction by trimming stubs going to receivers ≈ giN 1 · vi (t) − gjN vj (t)
that are not of interest. This trimming will not affect the Elmore GN j=1
delay to the receivers of interest and will have little impact on  
the overall circuit behavior provided that the pruned stubs are 
N −1 
N −1
1 1
small (as measured by the 2πf max τN ≤ ( criterion). = giN  gjN · vi (t) − gjN vj (t)
GN GN
When pruning, it is more conservative to defer examination j=1 j=1
of leaf nodes until the end. This postponement will prevent −1

N
giN gjN
stubs from being “eaten” up one node at a time starting at = (vi (t) − vj (t)) . (31)
the leaf, even though τN for the leaf would have exceeded the j=1
GN
threshold, if the internal nodes of the stub had been eliminated
first. For a fuller explanation of this point, see [22]. Similarly, under the quasi-dc assumption, the charge on a
capacitor ciN equals
C. Fill-in −1

N
ciN gjN
Because the amount of fill-in—the creation of new resistors qiN (t) ≈ [vi (t) − vj (t)] . (32)
j=1
GN
and capacitors when a node is eliminated—increases with the
degree of the node, it is advisable to preferentially eliminate Magically, if we interpret each term in (31) and (32) as a
lower degree nodes before higher degree ones, much like in conductance or capacitor between i and j, we obtain the very
minimum degree ordering during sparse LU factorization. A same elimination rules that we arrived at earlier by the Schur-
reasonable policy is to require the number of incident resistors complement method.
to be three-or-less or even two-or-less. One might restrict the As to the validity of the quasi-dc approximation, we have the
number of incident capacitors as well to control fill-in of the following result.
capacitance matrix. Theorem 2: The error between the true voltage at node
N and the quasi-dc approximation is less than or equal to
D. Use of Heap-to-Sequence Eliminations 2M τN , i.e.,
A more sophisticated implementation than the queue imple-  
 
N −1 
 gqN 
mentation of Fig. 6 is to keep the nodes on a heap ordered by vN (t) − vq (t)
2M τN (33)
the compound key (RDeg, τ ). Lower degree nodes are on top of  GN 
q=1
higher degree nodes, and for same-degree nodes, smaller time-
constant nodes are on top of larger time-constant nodes. Only where τN is the time constant of node N and M =
nodes with ω max τN < ε are kept on the heap. Again, one defers maxq |dvq /dt| is the maximum slew rate among neighbors.
elimination of leaf nodes until the end; after heap processing Proof: See Appendix.
has stopped. With the heap approach, nodes are successively
eliminated from the top of the heap until a node is reached, F. Relation to DC Projection
whose RDeg exceeds MaxDeg. A further refinement is to use
local fill-in instead of RDeg as the first field of the key. There is one further piece of theoretical scaffolding that we
The heap option is appealing but carries with it the burden want to construct. In this section, we show that TICER is almost
of updating heap positions of neighbors each time a node is equivalent to a projection method—it can be obtained by a
eliminated. certain orthogonal projection followed by a slight doctoring of
the projected C matrix.
To establish this result, we need explicit expressions for the
E. Quasi-DC Approximation
conductance matrix GTICER and capacitance matrix CTICER
Our derivation of the TICER algorithm from the Schur obtained when a node N is eliminated using TICER.
complement is mathematical in nature. An alternative way to Consider first the conductance matrix, GTICER . The rules
get the quick-node elimination rules is by a simple physical prescribed by TICER are: 1) remove all conductances between

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SHEEHAN: REALIZABLE REDUCTION OF RC NETWORKS 1399

N —the node being eliminated—and the rest of the circuit [I g/GN ]T [V1 · · · VN −1 ]T . Projection of the original
and 2) between each pair p and q of former neighbors, add a system (19) by P gives
conductance
gpN gqN Gdc_proj = P T Gorig P
ĝpq = . (34)   
GN G + diag{g} −g I
=[I g/GN ]
−g T GN g T /GN
Define U = {(p, q)|1
p, q
N − 1}. Applying these rules
gg T
1    = G + diag(g) − (40)
GTICER = G+ ĝpq (ep −eq ) eT
p −eq
T GN
2
(p,q)∈U
and
1  gpN gqN  T 
= G+ ep ep −ep eT
q −eq ep +eq eq
T T
2 GN Cdc_proj = P T Corig P
(p,q)∈U
  
  C + diag{c} −c I
1 gg T gg T =[I g/GN ]
= G+ diag(g)− − + diag(g) −cT CN g T /GN
2 GN GN
cg T gcT CN gg T
gg T = C + diag(c) − − + . (41)
= G+ diag(g)− . (35) GN GN GN GN
GN
We are ready to tie the strands of our argument. We see that
Here, the first term of the third line is obtained by
GTICER = Gdc_proj , but CTICER and Cdc_proj differ
 
 gpN gqN N−1
1 
N −1  
T
ep ep = gqN gpN ep eTp CN gg T
GN G ∆C ≡ Cdc_proj − CTICER = − diag(g) − .
(p,q)∈U p=1 N q=1 GN GN
(42)

N −1
= gpN ep eTp = diag(g) (36) In fact, we can give a circuit interpretation to ∆C. In (35),
p=1 we saw that diag(g) − gg T /GN comes about by adding a
conductance ĝpq = gpN gqN /GN between each pair of nodes
with an appeal being made to the definition of GN . The fourth p, q ∈ S. By the identical reasoning, ∆C would arise by adding
term is handled similarly. a negative capacitance
Next, consider the capacitance matrix CTICER . The quick-  
node rules for capacitance are: 1) remove all capacitances CN gpN gqN
between N and the rest of the circuit and 2) between each pair δĉpq = − (43)
GN GN
p and q of former neighbors, add a capacitance
between each pair p, q ∈ S. We recognize δĉpq to be none other
cpN gqN gpN cqN
ĉpq = + . (37) than the −sCN /GN term dropped from (26).
GN GN To summarize, the TICER algorithm is equivalent to carry-
Accordingly ing out a dc projection and then dropping the small negative
capacitances δĉpq .
1   
CTICER = C + ĉpq (ep − eq ) eT
p − eq
T
2 G. Redistribution of Current Sources
(p,q)∈U
 cpN gqN   So far, we have concentrated on the E matrix in (23). Let us
p − ep eq − eq ep +eq eq
ep eT T T T
= C+
GN briefly consider the vector f in (23) that also comes out of the
(p,q)∈U
Schur-complement process.
cg T gcT CN Theorem 3: The exact Schur correction to the right-hand side
= C + diag(c) − − + diag(g). (38) being
GN GN GN
We wish to relate these results to the matrices obtained by g + sc
f= JN (44)
projecting the original conductance and capacitance matrices GN + sCN
in (19) using the projection matrix
let
 
I g
P = T ∈ RN ×(N −1) . (39) f TICER = JN (45)
g /GN GN
The motivation for (39) is that it uses the quasi-dc approxi- be used to approximate the exact expression. If |sτN |
ε, then
mation to estimate the voltage vN (t) in terms of the voltages
at neighboring nodes; in other words, one can think of (39) f − f TICER 1
f 1 · ε(2 + ε). (46)
as coming from the approximation [V1 · · · VN −1 VN ]T ≈

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1400 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 8, AUGUST 2007

Proof: Again, the proof is given in the Appendix.

Not surprisingly, J + f TICER equals the expression we ob-
tain by projecting the right-hand side of (19) with the dc-
projection matrix (39)
   
J J g
PT = [I g/GN ] · =J+ JN . (47)
JN JN GN

Since the sum of the elements of vector g equals GN , we can

interpret (45) as a prescription for how current at node N should
be redistributed to the neighboring nodes such that current
is neither created nor destroyed. The idea of redistributing a
current source to neighboring nodes is exploited for power-
distribution analysis in [11].

Fig. 7. Distribution of nodal time constants.

V. D ESIRABLE P ROPERTIES OF TICER
In this section, we summarize various desirable properties
of TICER. TICER works with general network topologies; it
can handle resistor loops and floating capacitors and can reduce
nets subjected to crosstalk. When leaf nodes are fixed and the
net has no resistance to ground, TICER preserves exactly the
dc characteristics of the circuit—a consideration that might be
important when calculating operating points or load currents of
nonlinear devices. It also preserves total capacitance to ground,
under lax assumptions, and total capacitance between coupled
nets, ensuring that down-range timing tools that use total capac-
itance to look up driver models or to estimate crosstalk will get
the same answer from the reduced as from the original circuit.
By judiciously assigning fixed nodes, i.e., nodes that must not
be eliminated, TICER can preserve essential network topology.
Provided only low-degree nodes are eliminated, TICER will
maintain sparsity; standard Krylov methods, of course, do not
share this property. Under the same assumption, since TICER
performs only local modifications of the network graph, the
run-time is close to O(n) on a sparse graph, n being the number
of nodes in the circuit.
TICER is particularly suited to the needs of geometric ex-
traction tools. These tools are triggered to insert nodes wher-
ever geometry changes—at corners, vias, or spacing shifts, for
example; the granularity of extraction, therefore, can be quite ir-
regular, with many tiny parasitics and relatively few larger ones.
Guided by nodal time constants, TICER can systematically
pinpoint the smallest parasitics and eliminate them, thereby
compacting the netlist into a more uniformly fractured less-stiff
circuit, usually with little loss in accuracy.
Although TICER does not replicate exactly the first-order
moments of the admittance matrix (because it drops the small
negative δĉpq capacitors), it turns out that TICER does, in
fact, preserve Elmore delays through RC trees—provided one
eliminates only internal (nonleaf and nonfork) quick nodes and
provided the tree has no resistive path to ground. Historically,
as already noted, (27) was first deduced by requiring Elmore
delays to be invariant; see [24].
TICER produces an output in the form of a realizable RC
circuit. As already noted, PRIMA can only recast its output
as a circuit by employing dependent sources. Significantly,
TICER easily accommodates networks with a large number of
TABLE I
TICER REDUCTION STATISTICS BY NET SIZE
ports. Without appeal to special techniques, Krylov-projection
methods cannot effectively reduce such networks.
VI. E XPERIMENTAL R ESULTS
Next, we give a few examples to demonstrate TICER’s
performance.
Fig. 7 plots the distribution of nodal time constants before
reduction (curve near the main diagonal) and after reduction
(curve in the upper left) for a small IC design composed of
397 nets/5650 nodes. The original design had nodal time con-
stants spanning more than eight decades. Not only does TICER
reduces the number of nodes (to about 1500); it also compresses
the range of nodal time constants, eliminating most nodes with
time constants below 10−16 . The result is a significantly less
stiff system of differential equations.
For this same design, Table I gives average statistics for nets
in various node-count ranges. For example, referring to the ta-
ble, there were 42 nets in the design whose sizes were between
21 and 40 nodes. Of these 42 nets, the average reduction in node
count was 81%; the nets had an average of 4.59 ports (ports
were fixed and could not be eliminated); the average peak error
when original and reduced nets were simulated side by side was
4.89 mV when a 1-V 0.2-ps ramp was applied to one of the
ports.
Fig. 8 plots the response of the largest net in the design.
The waveforms for the net before and after reduction are
superimposed and are almost indistinguishable—differing by
a maximum of 0.0012 V. TICER reduced the net from 96 to
17 nodes.
TICER also works well with coupled nets. Consider a
20-section capacitively coupled RC ladder network represent-
ing two neighboring 1-cm lengths of metal four traces in

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SHEEHAN: REALIZABLE REDUCTION OF RC NETWORKS
Fig. 8. Response of a 96-node network. Dashed curves: TICER. Solid curves:
SPICE (the two sets of curves are virtually superimposed).
Fig. 9. Coupled RC lines. Dashed curves: TICER. Solid curve: SPICE (the
two sets of curves are again virtually superimposed).
0.18-µm technology. Fig. 9 compares the simulated wave-
forms of the 42-node original (solid) and 12-node reduced
(dashed) networks. Again, the results are almost indistinguish-
able. TICER is a viable reduction method when crosstalk is
important.
Although a thorough comparison is beyond the scope of
this paper, the reader may find it helpful to see at least one
comparison of TICER with PRIMA. The example we consider
here brings out some of the issues involved with a PRIMA-
like reducer. We alluded to some of these issues already in
the introduction. The example we choose is a daisy-chain
configuration—a regular RC ladder composed of 1000 equal
π sections, with 26 tap points (ports) placed evenly along
the line (including at the beginning and end of the line); the
network’s total resistance is 1 Ω and its total capacitance is 1 nF.
First, consider TICER. Fig. 10 shows the waveforms at ports
2, 10, and 26 when the input to the line is driven by a 0–1-V
saturating ramp with a rise time of 100 ps. The figure shows
both the waveforms obtained from the original unreduced cir-
cuit and those obtained from the TICER-reduced circuit with
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1401
Fig. 10. Daisy chain reduced by TICER. Simulated waveforms at ports 2, 10,
22, before (solid) and after (dashed) reduction.
f max = 250 MHz and ε = 1. The two sets of waveforms
overlap and cannot be readily distinguished by the eye. The
original circuit had 1001 capacitors and 1000 resistors; TICER
compressed this to 26 capacitors and 25 resistors.
Next, consider PRIMA. When modeling a multiport network
like this one with PRIMA, one has a number of options. One
can designate each port as a voltage port, a current port, or an
observation port. This distinction has to do with the way the cir-
cuit equations are formulated. The original PRIMA paper uses
only voltage ports and observation ports [13]; ENOR, another
Krylov-subspace method, uses current ports and observation
ports [19]; in practice, one can mix and choose, with some
caveats.2
PRIMA’s raw output is a system of first-order ODEs, which
are divorced of any direct interpretation as an RC circuit. This
may cause difficulties in practice. If one does not have access
to the inner working of a simulator and the simulator does not
support PRIMA-like macromodels, then one must first convert
PRIMA’s output to a standard format such as SPICE. A method
for doing this, by means of controlled sources, is described
in [14] (see also [9]); the PRIMA implementation we use for
this example employs a similar realization method—adapted,
however, to obviate the need for dynamic capacitances.
Keeping in mind these preliminary remarks, let us return to
the daisy-chain example and reduce it with PRIMA. We choose
to do this in a number of ways. We first designate the driver port
as a current port and all other (25) ports as observation ports;
this results in a singular G matrix, and the reducer aborts. To
avoid a singular G, we next set the driver port to a voltage port
and, again, set all the other tap points to observation ports. Not
knowing anything better, we instruct PRIMA to match three
moments; with this setup, the PRIMA algorithm gives us the
results of Fig. 11. Although the reduced circuit has only three
state variables, the SPICE circuit based on it has a total of
142 circuit elements, mostly controlled sources forming the
2 One such caveat is the following: each dc-connected subgraph of the circuit
that has no dc path to ground must have at least one voltage port attached to it,
or else the G matrix will be singular.
1402 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 8, AUGUST 2007
Fig. 11. Daisy chain reduced by PRIMA. Waveforms at ports 2,10, and 26,
before (solid) and after (dashed) reduction. One active port; three moments
matched.
input-to-state and state-to-output linkages. The agreement with
the unreduced network is not particularly good, and the reduced
circuit is not particularly small. No doubt by matching more
moments, we could improve on accuracy, but the point being
made here is that the PRIMA algorithm gives no a priori
guidance as to how many moments need to be matched. Indeed,
in [2], the authors suggest a post hoc error assessment to guide
the algorithm in choosing the number moments to match. The
situation here should be contrasted with TICER, which requests
as input an f max parameter. The reducer, of course, cannot
decide for the user how high a frequency he or she is interested
in, but once this parameter is set, TICER automatically carries
out the reduction so as to preserve the response up to that
frequency (more or less).
We run PRIMA a third time on the daisy-chain network
stipulating that all 26 ports of the network be active ports—one
is set to a voltage port and the rest are set to current ports. The
simulated waveforms of the reduced and unreduced networks
now agree almost perfectly; we omit showing the plots, as
they look essentially like Fig. 10. Unfortunately, the reduced
network generated by this port assignment has 26 state variables
(the same as the TICER network) and uses 1505 circuit ele-
ments in its SPICE realization. Moreover, the reduced network
tacitly has the following usage constraints: The voltage port
of the interconnect subcircuit must not be left floating (for
then the voltage at the port is indeterminate) and the current
ports must not be shorted (for then the current at these ports in
indeterminate). It is difficult to ensure that a user of the SPICE
model will adhere to these constraints.
The reader should not go away from this discussion with an
overly negative view of PRIMA. PRIMA and related Krylov
methods are among the most celebrated methods for model-
order reduction.
Not only PRIMA but also TICER can experience difficulty in
reducing a network with too many ports (fixed nodes). The dif-
ficulty, however, occurs for a different reason. The nature of the
difficulty can be seen by examining the performance of TICER
applied to a small 122-net-parasitic database. Statistics before
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TABLE II
TICER REDUCTION OF SMALL DESIGN WITH 122 NETS
TABLE III
DISTRIBUTION OF RELATIVE TIME CONSTANTS AFTER REDUCTION
and after reduction are summarized in Table II. The table gives
how many nodes are in the network (Nodes); of these, how
many are fixed (Fixed); of those that are not fixed, how many
have more than two incident resistor branches (RDeg > 2);
the table also gives total counts for capacitors to ground (Cg),
coupling capacitors, and resistors. TICER reduction was done
with parameters f max = 1 GHz and MaxDeg = 2.
As expected, no fixed nodes were eliminated during reduc-
tion. Also, very few nodes with RDeg > 2 were eliminated (not
surprising, given our setting MaxDeg = 2). After reduction, all
but 13 of the nodes left in the design are either fixed or high-
degree nodes (1296 + 2639 = 3935).
The distribution of nodal time constants after reduction is
detailed in Table III. Only one node has a time constant within
a decade of τ max ; all other uneliminated nodes have time
constants significantly less than this threshold τ max controlling
the elimination process (τ max = (/2πf max ).
This example is typical. Especially with designs rich in local
interconnect—local interconnect is characterized by relatively
many ports and very small parasitic values—TICER is impeded
from reducing further not because nodal time constants are too
large but because most of the unreduced nodes are either fixed
or of high degree. Fortunately, TICER can be made to reduce
such designs further by adding port merge to its repertoire of
available operations. See [17] for a discussion of this important
enhancement.
VII. C OMPARISON OF M ETRICS
In [3], Elias and van der Meijs propose a different metric
than nodal time constants for controlling the error during elimi-
nation. In this section, we compare the metric in [3] to that used
in TICER.
First, some notation. As before, N is the node to be removed,
and i and j are any two neighbors of N before the elimination.
Denote by
(0) (1) (2)
Yij (s) = Yij + Yij s + Yij s2 + · · · (48)
SHEEHAN: REALIZABLE REDUCTION OF RC NETWORKS 1403

the moment expansion of the branch admittance connecting i

to j before elimination [Yij is the (i, j)th element of the block
sC + G + diag(sc + g) in (19)]. Finally, let

(0) (1) (2)

Eij (s) = Eij + Eij s + Eij s2 + · · · (49)

be the moment expansion of E in (23); recall that Eij (s) is

subtracted from Yij (s) when node N is eliminated. In terms of
these quantities, Elias and van der Meijs propose the metric

max δij
ε (50)

1
i,j
N −1 Fig. 12. Two incident branches, both with capacitors.

where the moments of Eij (s) can be computed by equating powers

  giN gjN
 (2)  (0)
Eij = (54)
 s2 Eij  GN

δij ≡      . (51)
(1)     
 Yij − Eij + s Yij − Eij 
(0) (0) (1)
giN cjN ciN gjN CN
(1) (0)
Eij = + − Eij (55)
GN GN GN
The rationale here is that δij measures the magnitude of the first  
(2) ciN cjN CN (1)
term being dropped in (49), due to matching only 0th and first- Eij = − Eij (56)
GN GN
order moments, compared to the magnitude of the two terms
 
being retained in the expansion of Yij (s) − Eij (s). (k+1) CN (k)
Condition (50) involves an array of numbers, δij ; TICER’s Eij =− Eij , k > 2. (57)
GN
metric, |sCN /GN | < ε, involves one number. Computation of
the δij s requires information about neighbor node’s neighbors;
Accordingly, (52) becomes
TICER’s metric does not.
The extra computation of (50) would be worth it if (50)   
 2 ciN cjN CN (1) 
gave a truer measure of error; but this is not the case, as we s G − GN E ij 
δij
 N  . (58)
now show.  (0) (1) 
It will simplify the discussion to assume3 Eij + sEij 

 
 s2 E (2)  Now, for most extracted circuits, a pair of nodes—like i and N
 ij 
δij
 (0)  (52) or j and N —is connected either by a resistor (if the two nodes
 E + sE (1) 
ij ij are on the same net) or by a capacitor (if the two nodes are on
different nets or if one of the nodes is ground) but not by both.
i.e., we ignore contributions from resistors and capacitors that Suppose giN = 0; then, by what we have just said, it is usually
directly connect i to j before elimination of N . From the case that ciN = 0, and (58) simplifies to
  
 2 CN (1)  2 CN (1)  
(giN + sciN )(gjN + scjN ) s GN Eij  s GN Eij   CN 
  δij
 
   
(0) (1)   (1)  = s GN  < ε. (59)
(0) (1) (2)
= (GN + sCN ) Eij + Eij s + Eij s2 + · · · (53) Eij + sEij  sEij 

An identical argument works if cjN = 0. For this prevalent

3 In what follows, (59) is affected by this assumption, but (66) and (67) are situation, if TICER says a node can be eliminated, then so will
not. If the admittance branch from i to j is composed of a resistor and capacitor Elias and van der Meijs’ criterion, (50).
(0)
in parallel, then Yij
0, being equal to minus the conductance of the resistor, Consider the remaining possibility, where ciN = 0 and
and Yij
(1)

0, being minus the value of the capacitor. Also, from (54), we see cjN = 0. The circuit in Fig. 12 sheds light on what can happen
(0) (1) in this case. As usual, N is the node being considered for
thatEij  0. From (55), we see that Eij could have either sign, and this
is what prevents (52) from being true in all cases: It is necessarily true only if elimination. The time constant of N is
(1) (1)
Eij  0. The other possibility Eij < 0 represents the unlikely, or at least
undesirable, scenario of a negative capacitor being introduced by the Schur-
complement operation. TICER, of course, avoids this possibility by dropping
τN = 2C/(G + 2g) (60)
the term being subtracted in (55), its nodal time-constant criteria ensuring that
this neglected term is small—see (26). Elias and van der Meijs’ criteria, (50),
does not have such a safeguard against the cropping up of negative capacitances. and τN 1 holds whenever G  2C, independently of the
Negative capacitances have the potential to produce an unstable circuit. value of g. In what follows, assume G  2C.

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1404 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 8, AUGUST 2007

The quantities entering (51) are VIII. G LOBAL E RROR A NALYSIS

(0) Since TICER proceeds incrementally by eliminating a node
Yij = 0
at a time, it is natural to ask how errors accumulate during this
(1) process. We offer some theoretical results in this direction, but
Yij = 0 (61)
the analysis is somewhat technical, so the reader seeking only
(0) g2 general impressions may want to skip this section.
Eij = (62)
GN Our first result asks what happens when we eliminate a node,
(1) 2Cg 2C (0) the values of the capacitors and resistors incident to that node
Eij = − E (63) already having errors in them due to previous elimination steps.
GN GN ij
Theorem 4: Suppose as a result of prior circuit transforma-
(2) C2 2C (1) tions we have for node N , in place of (23), the expression
Eij = − E (64)
GN GN ij E + δE, where
where GN = G + 2g. Substituting into (51)
  δE2
k1 E2 (68)

 s2 C 2 1 − 4g(G+g) 
 2 
δij =    .
(G+2g)
 (65) k1 being some constant. Then, node N can be eliminated with
 g 2 + 2sgC G+2g
G+g
 an error bound

As g → 0, (65) approaches
(E + δE) − (E + δE)TICER
k2 (1 + k1 )E2 (69)
2
δij ≈ s2 C 2 / [g(g + 2sC)] → ∞. (66)
where (E + δE)TICER includes the error in (28) due to
In other words, we have a situation where τN can be small, and √
prior circuit transformations and k2 = ε{1 + ( mN + mN ε)
yet, δij can be arbitrarily large, becoming, in fact, infinite when (1 + ε)} is the constant given by Theorem 1.
g = 0. Proof: We have
The case when g = 0 is not farfetched. The topology in
Fig. 12 with g = 0 is precisely that encountered when analyzing
(E + δE) − (E + δE)TICER
k2 E + δE2
crosstalk—nodes p, N, q being on one net, and nodes i and 2
j being on two neighboring nets capacitively coupled to N .
k2 (E2 + δE2 )
Criterion (50) precludes eliminating node N ; TICER permits

k2 (1 + k1 )E2 . (70)
it (if G  2C). The reader will see that the elimination is
reasonable.
As a final observation about the δij metric, note that (51) The first inequality is simply an invocation of Theorem 1, and
focuses solely on the error occasioned by dropping the second- the second inequality follows from the triangle law for | • |2 . 
(2)
order moment Eij s2 in the expansion of (49). However, the re- If k1 and k2 are both much less than one, then k2 (1 + k1 ) =
(k)
lation Eij = −τN Eij
(k−1)
, for k > 2 [see (57)] implies that the k2 + k2 k1 ≈ k2 , and the error factor associated with eliminat-
(0) (1) ing a node N is essentially what it would be if the Rs and Cs
magnitude of the individual terms in Eij (s) = Eij + Eij s +
(2)
incident to N were exact.
Eij s2 + · · · grow with the degree of s when |sτN | > 1; We obtain a somewhat different, and in some ways stronger,
(2)
therefore, in this case, Eij s2 is not the primary source of error. result by introducing the notion of independent sets of nodes.
Conversely, when |sτN | 1 Definition 1: A set of nodes {N1 , N2 , . . . , NI } is said to be
(0) (1) (2) (3) (4) independent if the nodes share no neighbors.
Eij (s) = Eij + Eij s + Eij s2 + Eij s3 + Eij s4 + · · · The significance of this concept is as follows. Conceptually,
(0) (1) (2)   we can order the nodes of a circuit in any way. Assume that
= Eij + Eij s + Eij s2 1 − τN s + τN s − ···
2 2
the nodes are labeled in this order: First, put nodes that are not
(0) (1) (2) 1 neighbors of any node in the independent set; next, all neigh-
= Eij + Eij s + Eij s2 · (67)
1 + τN s bors of N1 , then neighbors of N2 , etc., and finally, the nodes
in the independent set itself, {N1 , N2 , . . . , NI }. If this node
and, in this regime, the total truncation error in the approxi- ordering is adopted, then, after the nodes in the independent set
(0) (1)
mation Eij (s) ≈ Eij + Eij s is essentially equal to the first have been eliminated, the error in the global admittance matrix
term omitted. In short, the apparent conceptual foundation of of the circuit will have the following error structure:
(50)—the idea that one can limit oneself to considering the error
(2)
incurred by dropping Eij s2 and not consider the error from the  [0] 
higher order moments that are ignored in (27)—is valid only
 [δE1 ] 
when TICER’s criterion |τN s| 1 holds.  
For all these reasons, we believe that nodal time constants δEGLOBAL = 

[δE2 ] 
 (71)
 ..
. 
serve as a better guide to the nodal-elimination process than the
criteria proposed in [3]. [δEI ]

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SHEEHAN: REALIZABLE REDUCTION OF RC NETWORKS
where [δEi ] is an mNi × mNi block containing the errors
incurred by eliminated Ni and mNi is the count of Ni ’s neigh-
bors. These errors do not overlap in the global error matrix.
Theorem 5: Suppose S = {N1 , N2 , . . . , NI } is an indepen-
dent set. Suppose, further, that the errors from eliminating the
nodes in S individually, from Theorem 1, satisfy δEi 2

ki Ei 2 , i = 1 . . . I. Then, the global error (71) due to suc-
cessively eliminating all the nodes in the independent set is
bounded by
δEGLOBAL 1
(mN k)∗ EGLOBAL 1
where (mN k)∗ ≡ max1
i
I mNi ki .
Proof: Given the structure of (71), we have
δEGLOBAL 1 = max δEi 1
i
since  • 1 is the largest column sum of the absolute values of
√ δEi 1 in
entries in the column. Let Nj be the node for which
(73) takes√on its maximum. Then, since A1
mA2 and
A2
nA1 for any m × n matrix A, we have
√ √
δEj 1
mNj δEj 2
mNj kj Ej 2
mNj kj Ej 1 .
(74)
Combining (73) and (74) and noting that Ei 1

EGLOBAL 1 gives our result.  many moments at only one or a few points. One observes with
Our analysis of independent sets suggests that one might
want to organize the elimination process as a series of passes
over the network and confine oneself to eliminating only in-
dependent sets of nodes on a given pass. Rarely would one
have to perform more than a half dozen such passes, say, and
a result similar to Theorem 4 will govern the error accumulated
from one pass to the next. Furthermore, since many of the
nodes eliminated in the early passes are likely to have very
small nodal time constants, the error from these early passes
is often quite negligible; refer again to Fig. 5, for example.
Eliminating the nodes with τN < 10−14 will incur a negligible
error compared to the error from eliminating nodes with τN ≈
10−12 . Therefore, not all of these passes contribute materially
to the global error.
IX. C ONCLUSION
An appealing way to characterize TICER is to describe it
as an effort to seek out the correct level of discretization of
an electrical network, given a frequency range over which the
network is to be valid and an ad hoc fragmentation of the
network such as what occurs during parasitic extraction.
This notion of the “proper level of discretization” has been
studied elsewhere in the context of how many sections of an
RC ladder are required to model a uniform transmission line.
Such investigations corroborate this paper. To see this, consider
a uniform RC line of length d, with parameters R and C per-
unit length; it has infinitely many admittance poles [6]
 2
nπ
sn = − √ n = 1, 2, 3, . . . .
d RC
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1405
By contrast, N -cascaded T-sections, each T having two “arms”
with resistance (dR/2N ) and a “stem” with capacitance
(dC/N ), has only N admittance poles [6]
s̃n = −(2/RC)(1 − cos nπ/N ) n = 1, 2, . . . N. (76)
Given these expressions, the condition
|(s̃n − sn )/sn |
0.05 (77)
(72) can be shown to be equivalent to
|sn τRC |
0.29 (78)
where τRC = (dR/2N )(dC/N ) is the time constant of each
(73) node in the ladder. In other words, those poles of uniform and
of discretetized RC lines agree closely that are in the frequency
range given by (78). We are thus taken back to a TICER-like
bound |sτN |
ε on each node of the ladder.
Significantly, the above argument illustrates how bounds on
local time constants (time constants at the individual nodes of
the ladder) can translate into bounds on the errors of global
properties (e.g., transmission-line poles).
By way of conclusion, following [10], we suggest that match-
ing a few moments at many distinct points in the circuit is
comparable (as far as model accuracy is concerned) to matching
PRIMA, for instance, that as more ports are added to a circuit,
fewer moments are usually needed per port to achieve a given
accuracy. The multinode-moment-matching methodology in
[10] positions this idea as a central theme. One might say that
TICER is a multinode-moment method par excellence, for it
matches only very low order moments (the zeroth and, nearly,
the first) but does so at every retained node in the circuit.
A PPENDIX
We supply the proofs of Theorems 1, 2, and 3. We begin with
the following Lemma.
Lemma 1: With g and c defined as in (18) and GN and CN
defined by (20), suppose |s|CN
εGN . Then
s2 ccT 2
mN ε2 gg T 2
where mN is the number of nodes directly connected to N .
Proof: Using the fact√that xy T 2 = x2 y2 and that
x2
x1 and x1
mx2 , where x ∈ Rm , and not-
ing that c1 = CN and g1 = GN , we have
s2 ccT 2 = sc22
sc21
= |s|2 CN
2

ε2 G2N
= ε2 g21
mN ε2 g22
= mN ε2 gg T 2
where, by ignoring nodes with no direct connection to N , we
(75)
have taken c, g ∈ RmN in our norm comparisions. 
1406 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 8, AUGUST 2007

Lemma 2: We have the relation Vk (s) being the Laplace transform of the voltage at node k,
T k = 1, . . . , N . Solving for VN (s), we get
√ gg
diag(g)2
mN
GN .
2 
N −1  
giN + sciN
VN (s) = Vi (s)
Proof: From the Cauchy–Schwartz inequality i=1
GN + sCN

GN = |1 · g1N + 1 · g2N + · · · + 1 · gN −1,N | 

N −1    
ciN giN ciN 1
  = + − Vi (s).

12 + 12 + · · · + 12 g1N 2 + g2 + · · · g2 CN GN CN 1 + τN s
2N N −1N i
√
= mN g2 Taking inverse transforms
√
which implies 1
mN g2 /GN . Also, trivially, |giN |
−1  

N
ciN giN ciN
g2 for any i. Hence vN (t) = vi (t) + −
i
CN GN CN
√ g22
diag(g)2 = max |giN |
g2
mN −1
t
i GN 
N
e−(t−x)/τN
× vi (x)dx.
√ gg  T
i −∞
τN
= mN .
GN
 Integrating by parts
Theorem 1: Let E = (cs + g)(cs + g)T /(sCN + GN ) 
and E TICER = [gg T + s(gcT + cT g) + sCN diag(g)]/GN . −1
  giN
N  
giN ciN
If |sτN |
ε, then E − E TICER 2
kE2 , where vN (t) =  vi (t) − − .
√ GN GN CN
k = ε{1 + ( mN + mN ε)(1 + ε)}. i
Proof: Writing 

t
dv
(x)dx .
i
(cs + g)(cs + g)T −s2 ccT × e(x−t)/τN
E TICER = ·(1+sτN )+sτ ·diag(g) dt
GN (1 + sτN ) −∞

we have Hence
E − E 2TICER
 
  giN   g 
t

= −EsτN + s2 ccT /GN + sτ · diag(g) 2    iN ciN M
vN (t)− vi (t)
 −  e(x−t)/τN dx
 G N  G N C N
i i

εE2 + s2 ccT 2 /GN + ε diag(g)2 −∞
√ 

εE2 + mN ε2 gg T 2 /GN + ε mN gg T /GN   giN 
ciN 

√ =  GN − CN  M τN

εE2 + (mN ε2 + ε mN ) i

(cs + g)(cs + g)T     

· · |1 + sτN |   giN    ciN 
GN (1 + sτN ) 2
   
√  GN  +  CN  M τN

εE2 + ε( mN + mN ε)E2 · (1 + ε). i i

=2M τN .

Next, we prove Theorem 2, which establishes error bounds
for the quasi-dc approximation. 
Theorem 2: The quasi-dc approximation is accurate to We conclude this appendix by proving Theorem 3.
within the following error bound: Theorem 3: Let
 
 
N −1  g + sc
 gqN  f= jN
vN (t) − vq (t)
2M τN GN + sCN
 GN 
q=1
and
where M = maxq |dvq /dt| and, as usual, τN = CN /GN .
g
Proof: The situation we are dealing with is that in Fig. 4. f TICER = jN .
Kirchhoff’s current law for node N takes the form GN


N −1 If |sτN |
ε, then
(giN + sciN ) (Vi (s) − VN (s)) = 0
i=1
f − f TICER 1
f 1 · ε(2 + ε).

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SHEEHAN: REALIZABLE REDUCTION OF RC NETWORKS
Proof: The proof is very much along the lines of our proof
of Theorem 1. We write
(g + sc) − sc
f TICER · (1 + sτN ) · jN .
GN (1 + sτN )
Hence, recalling that c1 = CN and g1 = GN , so that
|sτN |
ε ⇐⇒ sc1
εg1
we have
f − f TICER 1 =  − sτN f + sc · jN /GN 1

f 1 ε + sc1 · jN /GN

f 1 ε + εg1 · jN /GN

f 1 ε + εg + sc1 · jN /GN
extracted RC netlists,” in Proc. ACM/IEEE Int. Workshop Timing Issues
g + sc
= f 1 ε +
· jN
GN (1 + sτN )
|1 + sτN | [18] E. Schrik and N. van der Meijs, “Comparing two Y –∆ methodologies
1 for realizable model reduction,” in Proc. IEEE Annu. Workshop Circuits,

f 1 ε + εf 1 (1 + ε).
 1999, pp. 17–21.
ACKNOWLEDGMENT
The author would like to thank Dr. S. Sapatnekar for his help-
ful suggestions in the early preparation of this paper. He would
also like to thank the anonymous reviewers for their careful
reading of this paper and their suggestions for improvements.
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Bernard N. Sheehan (M’91) received the B.A. de-
gree (magna cum laude with distinction in major) in
physics from Carleton College, Northfield, MN, in
1978, and received the M.S. degree in electrical en-
gineering and the Ph.D. degree in computer science
from the University of Minnesota, Minneapolis, in
1984 and 2005, respectively.
From 1984 to 1990, he worked at the mainframe
division of Control Data Corporation, Arden Hills,
MN. In 1990, he cofounded Integrity Engineering,
where he pioneered signal integrity, transmission
line, and boundary-element software. Since 1994, he has been a Staff Engineer
with Mentor Graphics Corporation, Wilsonville, OR. His interests include
numerical techniques for large systems of equations, model-order-reduction
methods, signal integrity, and power-grid analysis.