Microprocessor programming & Interfacing

CS-430

Course Teacher : Sumayya Zafar

Class : BE EE

Lecture 10
8088/8086 Microprocessor I/O Interfacing

Fall Semester 2020 1

 Recap
• I/O Interface
• Memory Mapped I/O
• Isolated I/O
• I/O Data Transfer
• Basic I/O interface
• Handshaking
• I/O Port Addressing
• Methods of Parallel Data Transfer
• 8255 PPI
• Block diagram & Pin Functions
• Operating Modes
• Programming

Fall Semester 2020 2

 Programming 8255 PPI – Mode 0 Operation
Example:
Interface a switch and a LED with 8255 PPI. Write code to set the LED according to the value on the switch
(if switch = 0 , LED is OFF ; if switch = 1, LED is ON). Configure 8255 PPI to a fixed port address of 60H –
63H.
Solution:
Mode 0 Operation
60H = 0110 0000 ; 63H = 0110 0011
Port A Input ; Port B Output
Control Word ----- Command Byte A
7 6 5 4 3 2 1 0
1 0 0 1 X 0 0 x

Control Word = 90H

Fall Semester 2020 3

 Programming 8255 PPI – Mode 0 Operation
Code:
MOV AL , 90H 𝑫𝟕 − 𝑫𝟎

From 8088
OUT 63H , AL RESET
8255 PPI
𝑫𝟕 − 𝑫𝟎
HERE: IN AL , 60H 𝑹𝑫
𝑷𝑨𝟎
. Switch

AND AL , 01H .
RESET .
OUT 61H , AL 𝑾𝑹 𝑷𝑨𝟕
𝑹𝑫 𝑷𝑩𝟎 LED
JMP HERE 𝑨𝟏 − 𝑨𝟎 𝑾𝑹
.
.
𝑷𝑩𝟕
𝑨𝟏 𝑨𝟎 Selection ഥ𝟐
𝑨
𝑨𝟏 .
𝑷𝑪𝟎
0 0 Port A ഥ𝟑
𝑨 𝑨𝟎 .
ഥ𝟒 .
0 1 Port B 𝑨
𝑨𝟓 .
𝑪𝑬
1 0 Port C 𝑨𝟔
𝑷𝑪𝟕

1 1 Command Register ഥ𝟕
𝑨

Fall Semester 2020 4

 Programming 8255 PPI – Mode 0 Operation
Example:
Set bit 2 of Port C and Reset bit 5 of Port C

Control Word ----- Command Byte B

7 6 5 4 3 2 1 0
05H
0 X X X 0 1 0 1
7 6 5 4 3 2 1 0
0AH
0 X X X 1 0 1 0

Code:

MOV AL, 05H

OUT 63H , AL ; PC2 = 1
MOV AL, 0AH

OUT 63H , AL ; PC5 = 0

Fall Semester 2020 5
 Programming 8255 PPI – Mode 1 Operation
• Mode 1 Input Control Signals
• 𝑆𝑇𝐵 (Strobe) – is an input that loads the data into the port latch, which holds the information until it is
input to the microprocessor using the IN instruction.
• 𝐼𝐵𝐹 (Input Buffer Full) – is an output that indicates that the data has been loaded into the input latch.
• 𝐼𝑁𝑇𝑅 (Interrupt Request) – is an output that is used to interrupt the CPU when an input device is
requesting service.
𝐼𝑁𝑇𝑅 = 𝐼𝑁𝑇𝐸 . 𝐼𝐵𝐹

𝑰𝑵𝑻𝑬
𝑰𝑵𝑻𝑹
𝑰𝑩𝑭

• 𝐼𝑁𝑇𝐸 (Interrupt Enable) – neither input nor output. It is an internal bit programmed via specific bit
positions of port C.
𝑃𝐶4 (𝑓𝑜𝑟 𝑃𝑜𝑟𝑡 𝐴) , 𝑃𝐶2 (𝑓𝑜𝑟 𝑃𝑜𝑟𝑡 𝐵)

Fall Semester 2020 6

 Programming 8255 PPI – Mode 1 Operation
• Mode 1 Output Control Signals
• 𝑂𝐵𝐹 (Output Buffer Full) – is an output that goes low whenever data are output to port A or port B
latch. This signal turns off (logic 1) whenever the 𝐴𝐶𝐾 pulse returns from external device.
• 𝐴𝐶𝐾 (Acknowledge) – response from an external device, indicating that it has received the data from
8255. It also turns 𝑂𝐵𝐹 off.
• 𝐼𝑁𝑇𝑅 (Interrupt Request) – is an output used to interrupt the CPU when an output device has accepted
data transmitted by the CPU.

𝐼𝑁𝑇𝑅 = 𝐼𝑁𝑇𝐸 . 𝑂𝐵𝐹

𝑰𝑵𝑻𝑬
𝑰𝑵𝑻𝑹
𝑶𝑩𝑭

• 𝐼𝑁𝑇𝐸 (Interrupt Enable) - neither input nor output. It is an internal bit programmed via specific bit
positions of port C.
𝑃𝐶6 (𝑓𝑜𝑟 𝑃𝑜𝑟𝑡 𝐴) , 𝑃𝐶2 (𝑓𝑜𝑟 𝑃𝑜𝑟𝑡 𝐵)

Fall Semester 2020 7

 Programming 8255 PPI – Mode 1 Operation
Assume Address Range : 40H – 43H Control Word ----- Command Byte A
Port A – Mode 1 Input 7 6 5 4 3 2 1 0
B4H
Port B – Mode 1 Output 1 0 1 1 X 1 0 X
Port C – Control Signals 𝑫𝟕 − 𝑫𝟎

From 8088
RESET
8255 PPI
𝑫𝟕 − 𝑫𝟎
𝑷𝑨𝟎
𝑹𝑫 .
Input
. device
𝑾𝑹
RESET .
𝑷𝑨𝟕
𝑹𝑫 𝑷𝑩𝟎
𝑨𝟏 − 𝑨𝟎 𝑾𝑹
.
Output
. device
𝑷𝑩𝟕
ഥ𝟐
𝑨
𝑨𝟏 .
𝑷𝑪𝟎
ഥ𝟑
𝑨 𝑨𝟎 .
ഥ𝟒
𝑨 .
𝑨𝟓 .
𝑪𝑬 𝑷𝑪𝟕

𝑨𝟔
Fall Semester 2020 ഥ𝟕
𝑨 8
 Programming 8255 PPI – Mode 1 Operation
.DATA 76543210
BIT5 EQU 20H AL : x x 0 x x x x x
PORTC EQU 42H BIT5 : 0 0 1 0 0 0 0 0 8255 PPI
PORTA EQU 40H Ans : 0 0 0 0 0 0 0 0 ;
ZF = 1
.CODE Input
𝑷𝑨𝟕 − 𝑷𝑨𝟎
READ PROC NEAR device
IN AL , PORTC 76543210
TEST AL , BIT5 AL : x x 1 x x x x x
𝑰𝑵𝑻𝑬𝑨 𝑷𝑪𝟒 𝑺𝑻𝑩
BIT5 : 0 0 1 0 0 0 0 0
JZ READ Ans : 0 0 1 0 0 0 0 0 ; 𝑰𝑩𝑭
IN AL, PORTA ZF = 0 𝑷𝑪𝟓
RET
READ ENDP

𝑷𝑪𝟑 𝑰𝑵𝑻𝑹

Fall Semester 2020 9

 Programming 8255 PPI – Mode 1 Operation
.DATA
BIT1 EQU 02H 76543210
AL : x x x x x x 0 x
PORTC EQU 42H BIT1 : 0 0 0 0 0 0 1 0 8255 PPI
PORTB EQU 41H Ans : 0 0 0 0 0 0 0 0 ;
.CODE ZF = 1
𝑷𝑩𝟕 − 𝑷𝑩𝟎
Output
device
WRITE PROC NEAR
IN AL , PORTC
76543210 𝑨𝑪𝑲
TEST AL , BIT1 AL : x x x x x x 1 x
𝑰𝑵𝑻𝑬𝑩 𝑷𝑪𝟐

JZ WRITE BIT1 : 0 0 0 0 0 0 1 0
𝑷𝑪𝟏
𝑶𝑩𝑭
MOV AL , AH Ans : 0 0 0 0 0 0 1 0 ;
ZF = 0
OUT PORTB , AL
RET
WRITE ENDP 𝑷𝑪𝟎 𝑰𝑵𝑻𝑹

Fall Semester 2020 10

 Programming 8255 PPI – Mode 2 Operation
• All pins have same functions except 𝐼𝑁𝑇𝑅.

𝐼𝑁𝑇𝑅 = 𝐼𝑁𝑇𝐸1 . 𝑂𝐵𝐹 + 𝐼𝑁𝑇𝐸2 . 𝐼𝐵𝐹

𝑰𝑵𝑻𝑬𝟏

𝑶𝑩𝑭

𝑰𝑵𝑻𝑹
𝑰𝑵𝑻𝑬𝟐

𝑰𝑩𝑭

• For 𝐼𝑁𝑇𝐸 set/reset port C pins are:

𝑃𝐶6 𝑓𝑜𝑟 𝐼𝑁𝑇𝐸1 , 𝑃𝐶4 𝑓𝑜𝑟 𝐼𝑁𝑇𝐸2

Fall Semester 2020 11

 Programming 8255 PPI – Mode 2 Operation
Assume Address Range : 40H – 43H Control Word ----- Command Byte A
Port A – Mode 2 Input/Output 7 6 5 4 3 2 1 0
C4H
Port B – Mode 1 Output 1 1 0 X X 1 0 X
Port C – Control Signals 𝑫𝟕 − 𝑫𝟎

From 8088
RESET
8255 PPI
𝑫𝟕 − 𝑫𝟎
𝑷𝑨𝟎
𝑹𝑫 . Input/
. Output
device
𝑾𝑹
RESET .
𝑷𝑨𝟕
𝑹𝑫 𝑷𝑩𝟎
𝑨𝟏 − 𝑨𝟎 𝑾𝑹
.
Output
. device
𝑷𝑩𝟕
ഥ𝟐
𝑨
𝑨𝟏 .
𝑷𝑪𝟎
ഥ𝟑
𝑨 𝑨𝟎 .
ഥ𝟒
𝑨 .
𝑨𝟓 .
𝑪𝑬 𝑷𝑪𝟕

𝑨𝟔
Fall Semester 2020 ഥ𝟕
𝑨 12
 Programming 8255 PPI – Mode 2 Operation
.DATA 76543210 8255 PPI
BIT5 EQU 20H AL : x x 0 x x x x x Input/
BIT7 EQU 80H BIT5 : 0 0 1 0 0 0 0 0 Output
PORTC EQU 42H Ans : 0 0 0 0 0 0 0 0 ; 𝑷𝑨𝟕 − 𝑷𝑨𝟎 device
ZF = 1
PORTA EQU 40H
.CODE 76543210 𝑨𝑪𝑲
READ PROC NEAR AL : x x 1 x x x x x
𝑰𝑵𝑻𝑬𝟏 𝑷𝑪𝟔
IN AL , PORTC BIT5 : 0 0 1 0 0 0 0 0 𝑶𝑩𝑭
TEST AL , BIT5 Ans : 0 0 1 0 0 0 0 0 ; 𝑷𝑪𝟕
JZ READ ZF = 0
IN AL , PORTA
RET 𝑷𝑪𝟑

READ ENDP 76543210

AL : 0 x x x x x x x 𝑰𝑵𝑻𝑹
WRITE PROC NEAR
BIT7 : 1 0 0 0 0 0 0 0
IN AL , PORTC
Ans : 0 0 0 0 0 0 0 0 ;
TEST AL , BIT7 ZF = 1
JZ WRITE
MOV AL , AH 76543210
𝑷𝑪𝟓
OUT PORTA , AL AL : 1 x x x x x x x
𝑰𝑩𝑭

RET BIT7 : 1 0 0 0 0 0 0 0
𝑷𝑪𝟒 𝑺𝑻𝑩
WRITE ENDP Ans : 1 0 0 0 0 0 0 0 ;
ZF = 0 𝑰𝑵𝑻𝑬𝟐

Fall Semester 2020 13

 8254A Programable Interval Timer
• 8254A is an LSI peripheral designed to permit easy implementation of timer and counter functions in a
microprocessor systems.
• It contains three independent 16-bit counters and operate as down counters. Each counter is capable of
counting in binary and BCD.
• The maximum allowable input frequency to any counter is 10 MHz
• This device is useful wherever the microprocessor must control real-time events.
• Some examples of usage include real-time clock, an events counter, and for motor speed and direction
control.

Fall Semester 2020

 Block Diagram of 8254A PIT
• 8254 is available in 24-pin DIP:
• 8-bit bidirectional data bus 𝐷7 − 𝐷0
• Register select input 𝐴1 − 𝐴0 𝑨𝟏 𝑨𝟎 Function
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word

• Clock input for each of the three counters 𝐶𝐿𝐾0 , 𝐶𝐿𝐾1 and 𝐶𝐿𝐾2 .
• Gate input for each of the three counters 𝐺𝐴𝑇𝐸0 , 𝐺𝐴𝑇𝐸1 and𝐺𝐴𝑇𝐸2 .
• Out output for each of the three counters 𝑂𝑈𝑇0 , 𝑂𝑈𝑇1 and 𝑂𝑈𝑇2 .
• Read/write control 𝑅𝐷 , 𝑊𝑅
• Chip Select 𝐶𝑆
• VCC , GND
Fall Semester 2020
 Architecture of 8254A PIT
• Data bus buffer and read/write control logic
represent the microprocessor interface.
• Control word register contains three 8-bit
registers used to configure the operation of
counters 0 ,1 and 2.

Fall Semester 2020

 Control Word Format
𝐷7 𝐷6 𝐷5 𝐷4 𝐷3 𝐷2 𝐷1 𝐷0

𝑆𝐶1 𝑆𝐶0 𝑅𝑊/𝑊1 𝑅𝑊/𝑊0 𝑀2 𝑀1 𝑀0 𝐵𝐶𝐷

Definition of Control:
M - mode
SC – Select Counter
𝑆𝐶1 𝑆𝐶0 Function 𝑀2 𝑀1 𝑀0 Function

0 0 Select counter 0 0 0 0 Mode 0

0 1 Select counter 1 0 0 1 Mode 1

1 0 Select counter 2 X 1 0 Mode 2

1 1 Read back command X 1 1 Mode 3

RW – Read /write 1 0 0 Mode 4

𝑅𝑊/𝑊1 𝑅𝑊/𝑊0 Function 1 0 1 Mode 5
0 0 Counter Latch Command
BCD
0 1 Read/Write MSB only
0 Binary Counter 16-bits
1 0 Read/Write LSB only
1 Binary Coded Decimal (BCD)
1 1 Read/Write LSB first then
MSB
Fall Semester 2020
 Programming 8254 PIT
Assume Address Range : 40H – 43H Control Word
Programming Counter 0 7 6 5 4 3 2 1 0
36H
Mode 3 – Binary Counting 0 0 1 1 0 1 1 0
Initial Count – 45F0H (16-bits) 𝑫𝟕 − 𝑫𝟎

From 8088
Code: 𝑹𝑫 8254
𝑫𝟕 − 𝑫𝟎
MOV AL , 36H 𝑪𝑳𝑲𝟎
𝑾𝑹 𝑮𝒂𝒕𝒆𝟎
OUT 43H , AL ; Initialized C#0 𝑹𝑫 𝑶𝑼𝑻𝟎
MOV AL , 0F0H 𝑾𝑹
𝑪𝑳𝑲𝟏
OUT 40H , AL ; LSB of count is written 𝑨𝟏 − 𝑨𝟎 𝑮𝒂𝒕𝒆𝟏

MOV AL , 45H 𝑶𝑼𝑻𝟏

OUT 40H , AL ; MSB of count is written ഥ𝟐

𝑨
𝑨𝟏
ഥ𝟑
𝑨 𝑨𝟎
𝑪𝑳𝑲𝟐
ഥ𝟒
𝑨
𝑮𝒂𝒕𝒆𝟐
𝑨𝟓
𝑪𝑺 𝑶𝑼𝑻𝟐
𝑨𝟔
Fall Semester 2020 ഥ𝟕
𝑨 18
 Reading 8254 PIT
Reading Counter 0:
Code:
𝑫𝟕 − 𝑫𝟎

From 8088
IN AL , 40H 𝑹𝑫 8254
MOV DL , AL ; LSB of count in DL 𝑫𝟕 − 𝑫𝟎
𝑪𝑳𝑲𝟎

IN AL , 40H 𝑾𝑹 𝑮𝒂𝒕𝒆𝟎
𝑹𝑫 𝑶𝑼𝑻𝟎
MOV DH , AL ; MSB of count in DH 𝑾𝑹
𝑪𝑳𝑲𝟏

𝑨𝟏 − 𝑨𝟎 𝑮𝒂𝒕𝒆𝟏

𝑶𝑼𝑻𝟏

ഥ𝟐 𝑨𝟏
𝑨
ഥ𝟑
𝑨 𝑨𝟎
𝑪𝑳𝑲𝟐
ഥ𝟒
𝑨
𝑮𝒂𝒕𝒆𝟐
𝑨𝟓
𝑪𝑺 𝑶𝑼𝑻𝟐
𝑨𝟔
ഥ𝟕
𝑨

Fall Semester 2020

 Counter Latch Command
Assume Address Range : 40H – 43H Control Word
Read Counter 1 7 6 5 4 3 2 1 0
𝑆𝐶1 𝑆𝐶0 𝑅𝑊/𝑊1 𝑅𝑊/𝑊0 X X X X
Code: 0 1 0 0 X X X X
MOV AL , 40H 40H
OUT 43H , AL ; Writing Counter Latch Command
IN AL , 41H
MOV DL , AL ; LSB of count in DL
IN AL , 41H
MOV DH , AL ; MSB of count in DH

Fall Semester 2020 20

Read Back Command
Assume Address Range : 40H – 43H Control Word
Read Count of Counter 1 and 2 7 6 5 4 3 2 1 0

Code:
𝑆𝐶1 𝑆𝐶0 𝐶𝑂𝑈𝑁𝑇 𝑆𝑇𝐴𝑇𝑈𝑆 𝐶𝑁𝑇 2 𝐶𝑁𝑇 1 𝐶𝑁𝑇 0 0
MOV AL , 0DCH 1 1 0 1 1 1 0 0
OUT 43H , AL ; Read-Back Command written DCH
IN AL , 41H

From 8088
𝑫𝟕 − 𝑫𝟎

𝑹𝑫 8254
MOV DL , AL ; LSB of counter 1’s count in DL
𝑫𝟕 − 𝑫𝟎
𝑪𝑳𝑲𝟎
IN AL , 41H 𝑾𝑹 𝑮𝒂𝒕𝒆𝟎
MOV DH , AL ; MSB of counter 1’s count in DH 𝑹𝑫 𝑶𝑼𝑻𝟎

IN AL , 42H 𝑾𝑹
𝑪𝑳𝑲𝟏
MOV BL , AL ; LSB of counter 2’s count in BL 𝑨𝟏 − 𝑨𝟎 𝑮𝒂𝒕𝒆𝟏

IN AL , 42H 𝑶𝑼𝑻𝟏

MOV BH , AL ; MSB of counter 2’s count in BH ഥ𝟐

𝑨
𝑨𝟏
ഥ𝟑
𝑨 𝑨𝟎
𝑪𝑳𝑲𝟐
ഥ𝟒
𝑨
𝑮𝒂𝒕𝒆𝟐
𝑨𝟓
𝑪𝑺 𝑶𝑼𝑻𝟐

Fall Semester 2020 𝑨𝟔 21

ഥ𝟕
𝑨
Read Back Command
Assume Address Range : 40H – 43H Control Word
Read Status of Counter 0 ,1 and 2 7 6 5 4 3 2 1 0

Code:
𝑆𝐶1 𝑆𝐶0 𝐶𝑂𝑈𝑁𝑇 𝑆𝑇𝐴𝑇𝑈𝑆 𝐶𝑁𝑇 2 𝐶𝑁𝑇 1 𝐶𝑁𝑇 0 0

MOV AL , 0EEH 1 1 1 0 1 1 1 0
EEH
OUT 43H , AL ; Read-Back Command written

From 8088
𝑫𝟕 − 𝑫𝟎

IN AL , 40H 𝑹𝑫 8254
MOV DL , AL ; Status of Counter 0 in DL 𝑫𝟕 − 𝑫𝟎
𝑪𝑳𝑲𝟎
𝑾𝑹 𝑮𝒂𝒕𝒆𝟎
IN AL , 41H 𝑹𝑫 𝑶𝑼𝑻𝟎
MOV CL , AL ; Status of Counter 1 in CL 𝑾𝑹
𝑪𝑳𝑲𝟏
IN AL , 42H 𝑨𝟏 − 𝑨𝟎 𝑮𝒂𝒕𝒆𝟏

MOV BL , AL ; Status of Counter 2 in BL 𝑶𝑼𝑻𝟏

ഥ𝟐 𝑨𝟏
𝑨
ഥ𝟑
𝑨 𝑨𝟎
𝑪𝑳𝑲𝟐
ഥ𝟒
𝑨
𝑮𝒂𝒕𝒆𝟐
𝑨𝟓
𝑪𝑺 𝑶𝑼𝑻𝟐
𝑨𝟔
Fall Semester 2020 ഥ𝟕
𝑨 22
 Summary
• Programming 8255 PPI
• Mode 0
• Mode 1
• Mode 2
• 8254A Programable Interval Timer
• Block Diagram and Architecture of 8254
• Programming of 8254

Fall Semester 2020

 Questions?

Spring Semester 2020 24