Control of Series Parallel Conversion Systems Compress

CPSS Power Electronics Series
Xinbo Ruan · Wu Chen

Tianzhi Fang · Kai Zhuang
Tao Zhang · Hong Yan
Control of
Series-Parallel
Conversion Systems
Series editors
Wei Chen, Fuzhou University, Fuzhou, Fujian, China
Yongzheng Chen, Liaoning University of Technology, Jinzhou, Liaoning, China
Xiangning He, Zhejiang University, Hangzhou, Zhejiang, China
Yongdong Li, Tsinghua University, Beijing, China
Jingjun Liu, Xi’an Jiaotong University, Xi’an, Shaanxi, China
An Luo, Hunan University, Changsha, Hunan, China
Xikui Ma, Xi’an Jiaotong University, Xi’an, Shaanxi, China
Xinbo Ruan, Nanjing University of Aeronautics and Astronautics, Nanjing,
Jiangsu, China
Kuang Shen, Zhejiang University, Hangzhou, Zhejiang, China
Dianguo Xu, Harbin Institute of Technology, Harbin, Heilongjiang, China
Jianping Xu, Xinan Jiaotong University, Chengdu, Sichuan, China
Mark Dehong Xu, Zhejiang University, Hangzhou, Zhejiang, China
Xiaoming Zha, Wuhan University, Wuhan, Hubei, China
Bo Zhang, South China University of Technology, Guangzhou, Guangdong, China
Lei Zhang, China Power Supply Society, Tianjin, China
Xin Zhang, Hefei University of Technology, Hefei, Anhui, China
Zhengming Zhao, Tsinghua University, Beijing, China
Qionglin Zheng, Beijing Jiaotong University, Beijing, China
Luowei Zhou, Chongqing University, Chongqing, China
This series comprises advanced textbooks, research monographs, professional
books, and reference works covering different aspects of power electronics, such as
Variable Frequency Power Supply, DC Power Supply, Magnetic Technology, New
Energy Power Conversion, Electromagnetic Compatibility as well as Wireless
Power Transfer Technology and Equipment. The series features leading Chinese
scholars and researchers and publishes authored books as well as edited
compilations. It aims to provide critical reviews of important subjects in the field,
publish new discoveries and significant progress that has been made in develop-
ment of applications and the advancement of principles, theories and designs, and
report cutting-edge research and relevant technologies. The CPSS Power
Electronics series has an editorial board with members from the China Power
Supply Society and a consulting editor from Springer.
Readership: Research scientists in universities, research institutions and the

industry, graduate students, and senior undergraduates.
More information about this series at http://www.springer.com/series/15422

Xinbo Ruan Wu Chen Tianzhi Fang
• •
Kai Zhuang Tao Zhang

•
Hong Yan
Control of Series-Parallel
Conversion Systems
123
Xinbo Ruan Kai Zhuang
College of Automation Engineering SDAAC Automotive Air-Conditioning
Nanjing University of Aeronautics System Co., Ltd.
and Astronautics Shanghai, China
Nanjing, Jiangsu, China
Tao Zhang
Wu Chen Flextronics R&D (ShenZhen) Co., Ltd.
School of Electrical Engineering Shenzhen, Guangdong, China
Southeast University
Nanjing, Jiangsu, China Hong Yan
School of Mechanical and Electronic
Tianzhi Fang Engineering
College of Automation Engineering Bengbu University
Nanjing University of Aeronautics Bengbu, Anhui, China
and Astronautics
Nanjing, Jiangsu, China
ISSN 2520-8853 ISSN 2520-8861 (electronic)

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Preface
In the past three decades, power electronics technology has been rapidly developing
and has found wide applications in almost all kinds of fields of industrial and
agricultural production and daily life. Recently, the development and utilization of
renewable energy for addressing the traditional fossil energy shortage and envi-
ronmental pollution has been received more and more attention, which provides
new opportunities for power electronics technology. Power electronics technology
has been playing an increasingly important role in renewable energy generation,
flexible AC/DC transmission, smart grid, and electric vehicle.
At present, most of power electronics products are composed of various discrete
devices. Inspired by the success of the development of microelectronics technology,
the concept of power electronics system integration is emerging for the purpose of
reducing the manufacture cost and improving the reliability. Generally, the power
electronics system integration can be divided into three levels. The first one is
component-level integration including active devices integration and passive
components integration. The second one is module-level integration, in which a
variety of integrated active devices and/or passive components are integrated
together to form highly versatile standardized converter modules. The last one is
system-level integration, in which a number of converter modules are put together
to form different kinds of power conversion systems.
In the system-level integration, series–parallel power conversion system, in
which multiple standardized converter modules are connected in series or parallel at
the input and output sides, is one of the typical forms. Series–parallel power
conversion systems have the following advantages, including reduced design dif-
ficulties, ease of capacity expansion, redundancy, and improved reliability. Series–
parallel power conversion systems can be categorized into four possible architec-
tures on the basis of the connection forms, namely, input-parallel-output-parallel
(IPOP), input-parallel-output-series (IPOS), input-series-output-parallel (ISOP), and
input-series-output-series (ISOS), and each type of series–parallel power conver-
sion system has its own specific application areas. The IPOP system is suitable for
the applications with high output current, the IPOS is suitable for the applications
with low input voltage and high output voltage, the ISOP system is suitable for the
v
vi Preface
applications with high input voltage and high output current, and the ISOS system
is attractive for the applications with high input voltage and high output voltage.
This book focuses on the control techniques for the series–parallel power con-
version systems with DC–DC converters and DC–AC inverters as the basic mod-
ules, respectively, to achieve equilibrium among the constituent modules. The
detailed theoretical analysis with design examples and experimental validations are
presented.
This book includes nine chapters.
In Chap. 1, the classification and characteristics of the series–parallel power
conversion systems are presented, and the control strategies for the series–parallel
power conversion systems with DC–DC converters and DC–AC inverters as the
basic modules, respectively, are briefly reviewed.
Chapters 2–4 focus on the control strategies for the DC–DC series–parallel
power conversion systems.
In Chap. 2, the inherent relationship between the sharing of input voltages/
currents and the sharing of output voltages/currents among the constituent modules
in the four types of DC–DC series–parallel power conversion systems is analyzed
systematically from the view of power conservation, and the stability of various
possible control strategies is discussed. Based on the analysis, a general control
strategy is proposed for the DC–DC series–parallel power conversion systems,
which not only achieve equilibrium among the constituent modules, but also
decouples the output voltage control loop and the sharing control loop.
In Chap. 3, the small-signal model of ISOP system consisting of multiple
phase-shifted full-bridge converters is derived to prove the decoupling of the sys-
tem output voltage control loop and input voltage sharing (IVS) control loop, and
the parameters design of the two control loops is given. Furthermore, in order to
improve the system dynamic response and realize output current short-circuit
protection, the inner current loop is incorporated into the general control strategy,
and the parameters design of the IVS control loop is analyzed.
In Chap. 4, the wireless IVS control strategies for the input-series-connected
power conversion systems based on positive output voltage gradient method are
presented, which increases the output voltage of each module with the increase of
module input voltage. With this control strategy, there is no control interconnection
among the constituent modules leading to a truly modular design and high system
reliability.
Chapters 5–8 are dedicated to the control strategies for the DC–AC series–
parallel power conversion systems.
In Chap. 5, the inherent relationship between the input voltage/current sharing
(IVS/ICS) and output voltage/current sharing (OVS/OCS) of the four kinds of DC–
AC series–parallel power conversion systems is analyzed systematically, and the
control strategies to achieve IVS/ICS and OVS/OCS and the system stability are
discussed. A general control strategy for the four kinds of DC–AC series–parallel
power conversion system is proposed.
Preface vii
Chapters 6 and 7 present the implementation of the compound balanced control

strategies for the DC–AC ISOP system and DC–AC ISOS system, respectively,
which control the module input voltages to be equal for achieving IVS and control
the magnitudes or phases of modular output currents (for ISOP system) or output
voltages (for ISOS system) to be identical for achieving OCS/OVS.
In Chap. 8, the load current feed-forward scheme is incorporated for the inverter
module in the DC–AC IPOP system, and the load current feed-forward node is
intentionally located before the current-limiting unit, for not only making the output
voltage of the inverter independent of load current but also limiting the load current.
In Chap. 9, the control strategy with changeable weighted values of the IVS
loops and the IVS auxiliary circuit are presented for the input-series-connected
power conversion system for achieving IVS under extreme load conditions,
including light-load, no-load, and short-circuit current-limiting.
This book is essential and valuable reference for graduate students and aca-
demics majoring in power electronics and engineers engaged in developing DC–DC
converters, DC–AC inverters, series–parallel power conversion systems and power
electronics transformers. Senior undergraduate students majoring in electrical
engineering and automation engineering would also find this book useful.
Nanjing, China Xinbo Ruan

Nanjing, China Wu Chen
Nanjing, China Tianzhi Fang
Shanghai, China Kai Zhuang
Zhuhai, China Tao Zhang
Bengbu, China Hong Yan
Acknowledgements
This research monograph systematically summarizes the research work on the

control techniques for series–parallel power conversion systems since 2003.
The work in this book was partially supported by the Delta Power Electronics
Science and Education Development Foundation under Award DREO2006006. We
would like to express our sincere thanks to the Executive Committee of Delta
Power Electronics Science and Education Development Foundation.
It has been a great pleasure to work with the colleagues of Springer, Science
Press, China, and China Power Supply Society (CPSS). The support and help from
Mr. Wayne Hu (the Project Editor) are greatly appreciated.
June 2018
ix
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Development Trend of Power Electronics . . . . . . . . . . . . . . . . . . 1
1.2 Power Electronics System Integration . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 Component-Level Integration . . . . . . . . . . . . . . . . . . . . . . 5
1.2.2 Module-Level Integration . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.3 System-Level Integration . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 DC–DC Series–Parallel Power Conversion Systems . . . . . . . . . . . 7
1.3.1 IPOP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.2 IPOS System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.3 ISOP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.4 ISOS System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4 DC–AC Inverter Series–Parallel Power Conversion Systems . . . . . . . 15
1.4.1 DC–AC Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4.2 IPOP DC–AC Inverter System . . . . . . . . . . . . . . . . . . . . . 16
1.4.3 IPOS DC–AC Inverter System . . . . . . . . . . . . . . . . . . . . . 20
1.4.4 ISOP DC–AC Inverter System . . . . . . . . . . . . . . . . . . . . . 21
1.4.5 ISOS DC–AC Inverter System . . . . . . . . . . . . . . . . . . . . . 22
1.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2 A General Control Strategy for DC–DC Series–Parallel
Power Conversion Systems . . . . . . . . . . . . . . . . . . . . . . . . ........ 29
2.1 Possible Control Strategies for DC–DC Series–Parallel
Power Conversion Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.1.1 IPOP Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.1.2 IPOS Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.1.3 ISOP Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.1.4 ISOS Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
xi
xii Contents
2.2 Stability of the Control Strategies . . . . . . . . . . . . . . . . . . . . . . .. 34

2.2.1 Controlling at Input Side . . . . . . . . . . . . . . . . . . . . . . . .. 35
2.2.2 Controlling at Output Side . . . . . . . . . . . . . . . . . . . . . . .. 36
2.3 General Control Strategy for DC–DC Series–Parallel Power
Conversion Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 40
2.4 Modularization Architecture for DC–DC Series–Parallel Power
Conversion Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.5 Experimental Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3 Mathematical Model and Closed-Loop Parameters Design
for DC–DC ISOP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.1 Small-Signal Model of PSFB-Based ISOP System . . . . . . . . . . . . 56
3.1.1 Small-Signal Model of PSFB Converter . . . . . . . . . . . . . . 56
3.1.2 Small-Signal Model of the PSFB-Based ISOP System . . . . 61
3.2 Decoupling the Control Loops of the PSFB-Based
ISOP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.3 Closed-Loop Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.3.1 Output Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.3.2 IVS Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.4 Experimental Verification of the General Control Strategy . . . . . . 74
3.5 Three-Loop Control Strategy for ISOP System . . . . . . . . . . . . . . . 74
3.5.1 Positive Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.5.2 IVS Regulator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.6 Experimental Verification of the Three-Loop Control Strategy . . . 82
3.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4 Wireless IVS Control Strategies for Input-Series-Connected
Systems Based on Positive Output Voltage Gradient Method . . . . .. 85
4.1 Genesis of the Wireless IVS Control Strategies Based on Positive
Output Voltage Gradient Method . . . . . . . . . . . . . . . . . . . . . . . .. 86
4.2 Basic Features of the Input-Series-Connected Systems with
Wireless IVS Control Strategies . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.2.1 ISOP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.2.2 ISOS System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.3 System Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.4 Experimental Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.4.1 Experimental Results of ISOP System . . . . . . . . . . . . . . . . 97
4.4.2 Experimental Results of ISOS System . . . . . . . . . . . . . . . . 102
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Contents xiii
5 A General Control Strategy for DC–AC Series–Parallel Power

Conversion Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.1 Relationship Between Input Voltage/Current Sharing
and Output Voltage/Current Sharing . . . . . . . . . . . . . . . . . . . . . . 108
5.1.1 IPOP Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.1.2 IPOS Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.1.3 ISOP Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.1.4 ISOS Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.2 Stability of the Control Strategies for DC–AC Series–Parallel
Power Conversion Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.2.1 Compound Balanced Control Strategy . . . . . . . . . . . . . . . . 114
5.2.2 Output Voltage/Current Sharing (OVS/OCS) Control
Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.3 General Voltage/Current Sharing Control Strategy for DC–AC
Series–Parallel Power Conversion Systems . . . . . . . . . . . . . . . . . . 115
5.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6 Compound Balanced Control Strategy for DC–AC Input-Series
Output-Parallel Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.1 DC–AC Inverter Topology for the ISOP Systems . . . . . . . . . . . . . 122
6.2 Implementation of the Compound Balanced Control Strategy . . . . 124
6.3 Closed-Loops Design for DC–AC ISOP Systems . . . . . . . . . . . . . 127
6.3.1 Decoupling Relationship Between IVS Loop and Output
Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.3.2 Design of Control Loop of the First-Stage Full-Bridge
Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.3 Design of IVS Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.3.4 Design of Output Voltage Loop . . . . . . . . . . . . . . . . . . . . 137
6.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.5.1 Steady-State Experiment . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.5.2 Dynamic Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.5.3 Comparison of the Output Current Feedback and Output
Filter Inductor Current Feedback . . . . . . . . . . . . . . . . . . . 145
6.6 Distributed IVS/OCS Control Strategy . . . . . . . . . . . . . . . . . . . . . 148
6.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
7 Compound Balanced Control Strategy for DC–AC
Input-Series-Output-Series Systems . . . . . . . . . . . . . . . . . . . . . . . . . 153
7.1 Implementation of the Compound Balanced Control Strategy . . . . 154
7.2 Decoupling the Control Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
7.3 Design of the Control Loops for the DC–AC ISOS Systems . . . . . 161
xiv Contents
7.3.1 Design of the Output Voltage Loop . . . . . . . . . . . . . . . . . 161

7.3.2 Design of the Control Loop of the First-Stage Converter
and IVS Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
7.4 Simulation and Experimental Verification . . . . . . . . . . . . . . . . . . 163
7.4.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
7.4.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
7.5 Distributed Control Strategy for DC–AC ISOS Systems . . . . . . . . 167
7.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
8 An Improved Average Current Control Strategy for DC–AC
Input-Parallel-Output-Parallel Systems . . . . . . . . . . . . . . . . . . . . . . . 175
8.1 Current Three-State Hysteresis Modulation . . . . . . . . . . . . . . . . . . 176
8.2 Improvement of the Output Characteristics of Inverter . . . . . . . . . 178
8.3 Configuration and Control Scheme for DC–AC IPOP Systems . . . . . 180
8.3.1 Configuration of the DC–AC IPOP Systems . . . . . . . . . . . 180
8.3.2 Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
8.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
8.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
9 Input Voltage Sharing Control Strategy for ISOP Systems Under
Extreme Load Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
9.1 Reason of Input Voltages Imbalance of ISOP Systems Under
Extreme Load Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
9.2 Input Voltage Sharing Control Strategy for ISOP Systems Under
Extreme Load Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
9.2.1 Changing the Weighted Values of the IVS Loops . . . . . . . 194
9.2.2 Input Voltage Sharing Auxiliary Circuit . . . . . . . . . . . . . . 197
9.3 Simulation and Experimental Verification . . . . . . . . . . . . . . . . . . 198
9.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
About the Authors
Xinbo Ruan was born in Hubei Province, China, in 1970. He received B.S. and
Ph.D. in electrical engineering from Nanjing University of Aeronautics and
Astronautics (NUAA), Nanjing, China, in 1991 and 1996, respectively.
In 1996, he joined the Faculty of Electrical Engineering Teaching and Research
Division, NUAA, where he became a Professor in the College of Automation
Engineering in 2002 and has been engaged in teaching and research in the field of
power electronics. From August to October 2007, he was a Research Fellow in the
Department of Electronic and Information Engineering, Hong Kong Polytechnic
University, Hong Kong, China. From March 2008 to August 2011, he was also with
the School of Electrical and Electronic Engineering, Huazhong University of
Science and Technology, China. He is a Guest Professor with Beijing Jiaotong
University, Beijing, China, Hefei University of Technology, Hefei, China, and
Wuhan University, Wuhan, China. He is the author or co-author of nine books and
more than 300 technical papers published in journals and conferences. His main
research interests include soft-switching DC–DC converters, soft-switching
inverters, power factor correction converters, modeling the converters, power
electronics system integration, and renewable energy generation system.
Dr. Ruan was a recipient of the Delta Scholarship by the Delta Environment and
Education Fund in 2003 and was a recipient of the Special Appointed Professor
of the Chang Jiang Scholars Program by the Ministry of Education, China, in 2007.
From 2005 to 2013, again from 2017, he served as Vice President of the China
Power Supply Society. From 2014 to 2016, he served as Vice Chair of the
Technical Committee on Renewable Energy Systems within the IEEE Industrial
Electronics Society. Currently, he is an Associate Editor for the IEEE TRANSACTIONS
ON INDUSTRIAL ELECTRONICS, IEEE TRANSACTIONS ON POWER ELECTRONICS, IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS-II, and the IEEE JOURNAL OF EMERGING AND
SELECTED TOPICS ON POWER ELECTRONICS. He was elevated to IEEE Fellow in 2015.
Wu Chen was born in Jiangsu Province, China, in 1981. He received B.S., M.S.,
and Ph.D. in electrical engineering from Nanjing University of Aeronautics and
Astronautics (NUAA), Nanjing, China, in 2003, 2006, and 2009, respectively.
xv
xvi About the Authors
From 2009 to 2010, he was a Senior Research Assistant in the Department of

Electronic Engineering, City University of Hong Kong, Kowloon, Hong Kong,
China. From 2010 to 2011, he was a Postdoctoral Researcher in Future Electric
Energy Delivery and Management Systems Center, North Carolina State
University, Raleigh. Since September 2011, he has been an Associate Research
Fellow with the School of Electrical Engineering, Southeast University, Nanjing,
China, where he has been a Professor since 2016. His main research interests
include soft-switching converters, power delivery, and power electronic system
integration.
Tianzhi Fang was born in Jiangsu Province, China, in 1977. He received B.S. in
electrical engineering and automation from Nanjing University of Aeronautics and
Astronautics (NUAA), Nanjing, China, in 2000, M.S. in control theory and engi-
neering from Jiangsu University, Zhenjiang, China, in 2003, and Ph.D. in electrical
engineering from NUAA, Nanjing, China, in 2009.
In 2009, he joined the Faculty of the College of Automation Engineering,
NUAA, where he is currently an Associate Professor. His main research interests
include series–parallel inverters, grid-connected inverter, and power electronics
system integration.
Kai Zhuang was born in Shandong Province, China, in 1975. He received B.S in
electrical engineering from Jinan University, Jinan, China, in 1998, M.S. in elec-
trical engineering from Anhui University of Technology, Ma’anshan, China, in
2001, and Ph.D. in electrical engineering from Nanjing University of Aeronautics
and Astronautics (NUAA), Nanjing, China, in 2008.
He had worked in GE (China) research center, LG Electronics (Shanghai)
Research Center, Shanghai Delphi Automotive Air-Conditioning System Co., Ltd.
In Nov. 2017, he joined Valeo Powertrain (Shanghai) Co., Ltd, Shanghai, China,
as hardware department manager. His current research interests include iBSG, DC–
DC converter, onboard charger, and wireless power transfer system for electric
vehicles.
Tao Zhang was born in Hubei Province, China, in 1977. He received B.S. in
industrial automation from Daqing Petroleum Institute, Daqing, China, in 2000, and
M.S. in electrical engineering from Nanjing University of Aeronautics and
Astronautics (NUAA), Nanjing, China, in 2005.
In 2005, he joined Astec Power Co., Ltd. and in 2008 joined TDI Power Co.,
Ltd. for design and development of power products. At the beginning of 2011, he
joined the Flex R&D (Shenzhen) Co., Ltd. for the research and development of new
power technology. He joined Innoscience (Zhuhai) Technology Co., Ltd. in 2018,
as AE director responsible for the application development of wide band gap
semiconductor products GaN.
He holds one US patent and two pended US patents.
About the Authors xvii
Hong Yan was born in Hunan Province, China, in 1979. She received B.S. in
automation from Hefei University of Technology, Hefei, China, in 2001, and M.S.
in electrical engineering from Nanjing University of Aeronautics and Astronautics
(NUAA), Nanjing, China, in 2009.
Since April 2009, she joined the College of Electronic and Electrical
Engineering at Bengbu University, where she is currently a Lecturer. Her main
research interests include power electronics system integration and DC–DC con-
verters.
Abbreviations
AC Alternating Current
BJT Bipolar Junction Transistor
CPES Center for Power Electronics Systems
DC Direct Current
DSP Digital Signal Processor
GaN Gallium Nitride
GTO Gate Turn-off Thyristor
HVICs High-Voltage Integrated Circuits
ICS Input Current Sharing
IGBT Insulated Gate Bipolar Transistor
IPEM Integrated Power Electronics Modules
IPM Intelligent Power Module
IPOP Input-Parallel-Output-Parallel
IPOS Input-Parallel-Output-Series
ISOP Input-Series-Output-Parallel
ISOS Input-Series-Output-Series
IVS Input Voltage Sharing
IVSR Input Voltages Sharing Regulator
LSI Large-Scale Integrated
MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
OCS Output Current Sharing
OVR Output Voltage Regulator
OVS Output Voltage Sharing
PEBB Power Electronics Building Block
PFC Power Factor Correction
PFM Pulse Frequency Modulation
PI Proportional-Integral
PLL Phase-Locked Loop
PSFB Phase-Shifted Full-Bridge
PWM Pulse-Width Modulation
xix
xx Abbreviations
RMS Root Mean Square

SCR Silicon Controlled Rectifier
SiC Silicon Carbide
SoC System on Chip
SPICs Smart Power Integrated Circuits
SPWM Sinusoidal Pulse-Width Modulator
ULSI Ultra-Large-Scale Integrated
UPS Uninterruptible Power Supply
VLSI Very-Large-Scale Integration
Chapter 1
Introduction
Abstract Power electronics system integration is one of the effective approaches

to reduce the cost of power electronics products, shorten the development cycle,
and improve the reliability. Generally, power electronics system integration can be
divided into three levels, namely, component-level integration, module-level integra-
tion, and system-level integration. One important branch of system-level integration
is the series–parallel power conversion systems, in which multiple standardized con-
verter modules are connected in series or parallel at the output and input sides to meet
the requirements of different applications. In order to ensure the proper operation of
series–parallel power conversion systems, proper sharing of the input/output voltage
and proper sharing of the input/output current must be ensured. This chapter mainly
introduces the control techniques for the series–parallel power conversion systems
with DC–DC converter and DC–AC inverter as the basic module, respectively, which
will lay a foundation for the narration of the following chapters.
Keywords Power electronics system integration

Series–parallel power conversion system · Input-parallel-output-parallel (IPOP)
Input-parallel-output-series (IPOS) · Input-series-output-parallel (ISOP)
Input-series-output-series (ISOS)
1.1 Development Trend of Power Electronics
Power electronics started with the development of the mercury arc rectifier, which
was invented by Peter Cooper Hewitt in 1902 and used for converting alternating
current (AC) into direct current (DC) [1]. Other types of rectifiers, such as phanotrons
and thyratrons, were gradually introduced in the 1930s. In 1956, the silicon controlled
rectifier (SCR) was invented by Bell Laboratories and commercially introduced by
General Electric Company [2], and after that, power electronics developed rapidly
with the improved switching speed of semiconductor devices. A pioneer of power
electronics, Dr. William E. Newell, pointed out that power electronics was intersti-
tial to all three of the major disciplines of electrical engineering: electronics, power,
© Springer Nature Singapore Pte Ltd. and Science Press, Beijing, China 2019 1
X. Ruan et al., Control of Series-Parallel Conversion Systems, CPSS Power Electronics
Series, https://doi.org/10.1007/978-981-13-2760-5_1
2 1 Introduction
and control at the IEEE Power Electronics Specialists Conference (PESC) in 1973
[3]. In 1989, Dr. Bimal K. Bose expanded and refined the circumscription of power
electronics, and demonstrated that power electronics was an interdisciplinary tech-
nology, including computer-aided design, power semiconductor devices, converter
circuits, electrical machines, very large scale integration (VLSI) circuits, control the-
ory, microcomputers, analog and digital electronics, and so on, as shown in Fig. 1.1
[4]. At present, more and more disciplines are involved in power electronics, such as
modern control theory, microelectronics, material science, environmental science,
and life science, and power electronics has become an independent interdisciplinary
high-tech discipline.
With the rapid development during the last nearly 60 years, power electronics
technology has been widely used in almost all kinds of fields of industrial and agri-
cultural production and daily life. Recently, more attention has been drawn to the
renewable energy development and utilization globally due to the gap between the
increasingly growth of energy demand and shortage of the traditional fossil energy,
which also provides new opportunities for the development of power electronics.
Power electronics technology will play an increasingly important role in renewable
energy generation, flexible AC/DC transmission, electric vehicle and energy conser-
vation, and environmental protection [5–8].
Power semiconductor devices, power conversion technology, and control technol-
ogy are the three main fields involved in power electronics. The power semiconductor
devices are the basis of the development of power electronics technology. Generally,
the power semiconductor devices have gone through four stages of development:
(1) Half-controlled devices: SCR is a typical representation of the half-controlled
device, which has been widely used in low frequency, medium-to-high voltage
AC power conversions.
(2) Full-controlled devices: Gate turn-off thyristor (GTO), bipolar junction transis-
tor (BJT), and metal-oxide-semiconductor field-effect transistor (MOSFET) are
the main three kinds of full-controlled devices. The GTO and BJT are current-
controlled devices, and the MOSFET is voltage-controlled device, which has
higher switching speed than GTO and BJT.
Fig. 1.1 Power Computer-aided

electronics—An design
interdisciplinary technology
Analog and digital Power semiconductor
electronics devices
Power
Microcomputers electronics Converter circuits
and drives
Control theory Electrical machines
VLSI Circuits
1.1 Development Trend of Power Electronics 3
(3) Hybrid devices: Insulated gate bipolar transistor (IGBT) is a minority-carrier

device, which integrates the advantages of the MOSFET and BJT, i.e., the high
input impedance and high switching speed of a MOSFET and the low saturation
voltage of a bipolar transistor. This hybrid combination is that the IGBT has the
conduction characteristics of a bipolar transistor but is voltage-controlled like a
MOSFET.
(4) Power integrated devices: Smart power integrated circuits (SPICs) and high
voltage integrated circuits (HVICs) are the main two kinds of power integrated
devices, which integrate the power semiconductor devices, drive circuits, pro-
tection circuits, and even controllers.
Recently, there has been significant progress in the development of wide bandgap
semiconductor power devices, such as silicon carbide (SiC)-based and gallium nitride
(GaN)-based power devices. SiC-based power devices have become strong competi-
tors to Si-based power devices in medium power conversion applications, while
GaN-based power devices can achieve ultra-fast switching. In summary, the power
devices will be more large capacity, high frequency, modular, and intelligent in the
future [9].
Power conversion technology can be classified into four types based on the forms
of electric energy conversion: (1) AC-to-DC conversion, (2) DC-to-DC conversion,
(3) DC-to-AC conversion, and (4) AC-to-AC conversion. Each electric energy con-
version form can be achieved by various circuit topologies. The development of power
conversion technology makes power electronics equipment have compact size, high
conversion efficiency, and improved comprehensive economic benefit.
Control technology is very important for power electronics technology. Various
control technologies have been rapidly proposed and widely used, such as pulse-
width modulation (PWM) and pulse-frequency modulation (PFM). With the devel-
opment of modern control theory, fuzzy control, genetic control, neural network
control, and so on are introduced to the power electronics.
With the growing applications of power electronics technology, it also faces
various new challenges. At present, most power electronics products are specially
designed according to different purposes and requirements of customers, i.e., custom-
designed products. The design of power electronics products usually is a complex
procedure with long development cycle time and high cost, since many aspects
are involved, such as semiconductor devices, circuit topologies, control, magnetic
material, package, mechanical structure, thermal design, and electromagnetic com-
patibility. Therefore, lots of repeated work exist when developing different power
electronics products, resulting in lower labor efficiency and higher production cost.
In order to reduce the cost and shorten the development cycle time, it is eager to
improve the standardization of power electronics products for large-scale production
to make the products can meet the rapidly changing market and customer needs,
which is also one of major challenges for power electronics technology. The consen-
sus among the world’s power electronics industry and academia is that the effective
way to solve the problem is power electronics system integration, standardization
and modularization [10].
4 1 Introduction
1.2 Power Electronics System Integration
There are two main branches for the development of electronic technology after
the appearance of semiconductor device. One is the microelectronic technology to
process information, and the other is the power electronics technology to process
power (energy). The development of microelectronic technology has experienced
several stages, including discrete devices, large scale integrated (LSI) circuits, very
large scale integrated (VLSI) circuits, ultra large scale integrated (ULSI) circuits,
and system on chip (SoC), and now the integration is still the trend of microelec-
tronic technology. Compared with the microelectronic technology, the development
of power electronics integration is relatively slow. At present, most of power elec-
tronics products are composed of various discrete devices. Inspired by the success
of the development of microelectronics technology, people will think that the cost of
production will be reduced and the development cycle time will be shortened if the
integration is applied in the power electronics, and this is the original intention of
the proposal of power electronics system integration. The goal of power electronics
system integration is to increase the integration levels in the components, including
devices, circuits, controls, and sensors, which are integrated into standardized manu-
facturable modules, and then these standardized modules can be easily used to build
various types of power electronics equipment.
The idea of power electronics system integration was originally proposed by the
US Navy, and the famous concept of power electronics building block (PEBB) was
proposed with the vision of changing the paradigm for designing and manufacturing
electrical high power conversion and control products [11]. After that, the Center for
Power Electronics Systems (CPES) has been doing very well-known work on the
PEBB, including the monolithic integration of high-voltage power devices and low-
voltage devices for controls and sensors, the interconnection of high-power devices
and control devices on a common substrate, thermal management, and integration
of passive high-power components, and CPES developed the integrated power elec-
tronics modules (IPEM), a standardized off-the-shelf module that has revolutionized
power electronics [12].
Generally, the power electronics system integration can be divided into three lev-
els. The first one is component-level integration, including active devices integration
and passive components integration. The active power devices integration includes
active power devices, drive circuits, protection circuits, and communication circuits,
while the passive components integration includes inductors, capacitors, and trans-
formers. The second one is module-level integration, in which a variety of integrated
active devices and/or passive components are integrated together to form highly ver-
satile standardized converter modules. The last one is system-level integration, in
which a number of converter modules are put together to form different kinds of
power conversion systems.
1.2 Power Electronics System Integration 5
1.2.1 Component-Level Integration
The active devices integration refers to integrate active devices, drive circuits, con-
trol circuits, and protect circuits on a common substrate or into a module, leading to
reduced volume and influence of the connection among devices. For instance, intelli-
gent power module (IPM) is a high-function integrated module with IGBT chip and
dedicated integrated circuits for self-protection (over-current, under-voltage, and
over-heating).
The passive components integration includes magnetic components integration
(such as the integration of inductor and transformer, integration of inductors), inte-
gration of magnetic components and capacitors, and integration of magnetic compo-
nents, capacitors, resistors, etc. Two or more discrete inductors and/or transformers
can share a common magnetic core through proper coupling way and parameters
design, leading to reduced magnetic components volume and total losses. The mag-
netic components and capacitive components can be integrated together, for instance,
R. Reeves proposed an integration method for an inductor and a capacitor [13]. The
resistors can also be integrated with magnetic components and capacitive compo-
nents, in which the resistors are used for snubber circuit or control circuit [14].
1.2.2 Module-Level Integration
Module-level integration refers to the integration of various active devices, passive

components, control circuits, and protection circuits for a standardized module with
strong versatility. CPES has proposed multi-chip packaging technology to achieve
power electronics module-level integration. Kinds of power electronics devices in the
form of bare dies are mounted on a ceramic or metal substrate, and the control circuits,
drive circuits, protection circuits, snubber circuits, and sensors are also mounted on
the same substrate in the form of IC bare dies or surface mount packages. All these
devices and circuits are interconnected through thin-film power overlay technology
and then connected with passive components through three-dimensional package
technology to form a converter module to realize power conversion.
1.2.3 System-Level Integration
System-level integration technology refers to integrate various standardized con-

verter modules into systems to meet different power conversion demands. One impor-
tant branch of system-level integration is series–parallel power conversion systems,
in which multiple standardized converter modules are connected in series or parallel
at the output and input sides to meet the demands of different applications [15]. For
instance, the input sides of multiple converter modules can be connected in series for
6 1 Introduction
high input voltage applications, and the output sides of multiple converter modules
can be connected in parallel for large output current applications. Series–parallel
power conversion systems can be categorized into four possible architectures on the
basis of the connection forms, namely, input-parallel-output-parallel (IPOP), input-
parallel-output-series (IPOS), input-series-output-parallel (ISOP), and input-series-
output-series (ISOS), as shown schematically in Fig. 1.2. Each type of series–par-
allel power conversion system has its own specific application areas. With the rapid
expansion of computer and telecommunication industries, distributed power systems
consisting of paralleled modular converters delivering low output voltage and high
output current are still the most popular practical configuration, where IPOP systems
have been widely adopted. ISOP systems can be used in applications where the input
voltage is relatively high and the output voltage is relatively low, such as in high-speed
train power systems, industrial drives, and undersea observatories. For applications
requiring high output voltages, such as X-ray equipment, photovoltaic systems, and
electrostatic precipitator, IPOS systems become the desired choice. Moreover, ISOS
systems are well suited for applications where both the input voltage and output
voltage are high.
+ + + + + + +
vin vin1 Module 1 vo1 v_o vin vin1 Module 1 vo1 +
_ _ _ _ _ _
+ + + +
v_in2 Module 2 vo2
_ v_in2 Module 2 vo2
_
vo
+ + + +
v_inn Module n von v_inn Module n von _
_ _
(a) IPOP (b) IPOS
+ + + + +
+ vin1 Module 1 vo1 v_o + vin1 Module 1 vo1 +
_ _ _ _
+ + + +
v_in2 Module 2 vo2
_ v_in2 Module 2 vo2
_
vin vin vo
+ + + +
_ v_inn Module n von _ v_inn Module n von _
_ _
(c) ISOP (d) ISOS
Fig. 1.2 Four connection architectures of multiple converter modules

1.2 Power Electronics System Integration 7
The advantages of the systems constructed from connecting multiple converter

modules include (a) ease of thermal design as a result of each module handling
only a part of the total power; (b) increased overall system reliability due to
reduced thermal and electrical stresses on the power devices and components; (c)
shortened design process and lowered cost for the system; (d) improved system relia-
bility due to N + 1 redundancy; and (e) ease of expansion of power system capability
[16].
According to the form of energy conversion, the modules in Fig. 1.2 can be
DC–DC converter, DC–AC inverter, AC–DC rectifier, and AC–AC converter. This
book focuses on the series–parallel power conversion systems with DC–DC converter
and DC–AC inverter as the basic modules, respectively, and their recent development
will be introduced as follows.
1.3 DC–DC Series–Parallel Power Conversion Systems
1.3.1 IPOP System
Paralleling of multiple standardized converters has been extensively studied and

widely applied in the power supplies for computers and communications. One basic
objective of IPOP system is to share the load current among the constituent converters.
To do this, a variety of approaches have been proposed, such as droop method, mas-
ter–slave current sharing method, democratic current sharing method, etc. [17–20].
The droop method can be defined as one in which the output voltage droops
as the load current is increased, as shown in Fig. 1.3. Its operation mechanism is
to program the output impedance to achieve current sharing among converters. The
droop method has the advantages of easy implementation, no wire connection among
the control circuits of converters and high modularity and reliability. However, the
current sharing and load regulation are relatively poor.
In the master–slave current sharing method, one module is dedicated to be the
master module and the remaining modules are the slave modules. A typical block
Io1 Io2 V1
V2
Ro1 + Ro2 V Vo
Vo RLd
V1 _ V2
Converter 1 Converter 2 0 Io1 Io2 I

(a) Equivalent circuit (b) Output characteristics
Fig. 1.3 Two-converter IPOP system

8 1 Introduction
_ Vof Comparator 1 Module 1

+ Iref +
Gvo Gi − Drive
Voref _ RS Flip-flop
+ circuit 1
ILf1_f VRAMP 1
Comparator 2 Module 2
+
Gi − Drive
_ RS Flip-flop
+ circuit 2
ILf2_f VRAMP 2
Current-
…
sharing bus
Comparator n Module n
+
Gi − Drive
_ RS Flip-flop
+ circuit n
ILfn_f VRAMP n
Fig. 1.4 A typical block diagram of master–slave current sharing method
diagram of master–slave current sharing method is shown in Fig. 1.4, where module
1 is the master module, which is voltage–current double closed-loop controlled, and
modules 2 to n are the slave modules, which are only current closed-loop controlled.
Gvo is the transfer function of the output voltage regulator, and Gi is the transfer
function of the current regulator. The output of Gvo , I ref , is taken as the current
sharing bus and becomes the common reference for all current closed loops to achieve
current sharing. The limitations of the master–slave current sharing method are poor
fault tolerance since the master failure will disable the entire system and degraded
modularity of the system.
Figure 1.5 shows a typical block diagram of the democratic current sharing
method. As seen, the load current signal of each module is connected to the cur-
rent sharing bus through an ideal diode, and the module with the highest output
current is automatically selected to be the master module and its load current signal
is taken as the current reference for all other modules. The current reference is then
compared with the individual converter load current and the error signal is added to
the voltage reference of each corresponding converter to regulate its load current to
achieve current sharing. Obviously, in the democratic current sharing method, there
is no dedicated master module, leading to good fault tolerance and modularity.
1.3 DC–DC Series–Parallel Power Conversion Systems 9
_ io1 Voref Comparator 1 Module 1

+ + +
Gio Gvo − Drive
_ RS Flip-flop
vof + circuit 1
VRAMP 1
_ io2 Voref Comparator 2 Module 2

+ + +
Gio Gvo − Drive
_ RS Flip-flop
Current- vof + circuit 2
sharing VRAMP 2
bus
…
_ ion Voref Comparator n Module n
+ + +
Gio Gvo − Drive
_ RS Flip-flop
vof + circuit n
VRAMP n
Fig. 1.5 A typical block diagram of democratic current sharing method
1.3.2 IPOS System
IPOS system can be applied in the occasions requiring high output voltages or higher
step-up ratios, such as X-ray equipment, photovoltaic systems, and electrostatic pre-
cipitator [21, 22].
The key issue of the IPOS system is to ensure output voltage sharing (OVS)
among the constituent converters. Due to the output sides are connected in series,
the constituent converters of IPOS system can regulate its own output voltages to be
1/n of the system output voltage (n is the number of converters) to share the output
voltage. However, OVS is affected by the degree of matching among the sampling
circuits and voltage references of constituent converters and it is difficult to obtain
precise system output voltage. A simple common duty cycle control strategy was
proposed in [23] for IPOS system; however, OVS cannot be ensured due to parameters
mismatches such as turns ratio of individual power transformer. Ref. [24] proposed
an OVS control strategy for IPOS system with a common system output voltage
control loop and individual input current control loop for each module. The output
of system output voltage regulator serves as the reference of input current control loop
of each module to achieve input current sharing (ICS) and equal voltage regulation
among the constituent modules, assuming that all the modules are identical. In [25],
the module with maximum output voltage is regarded as the master module and
its output voltage is taken as the reference, which is compared with the individual
module output voltage and the error signal is added to the corresponding output of
the output voltage regulator to regulate the module’s output voltage to achieve OVS.
Hence, it can be seen that OVS of IPOS system can be achieved by both controlling
ICS of modules and directly controlling OVS of modules.
The relationship between ICS and OVS of IPOS system was revealed in [16]. It
was pointed out that achieving ICS implies OVS and vice versa, and a novel OVS
10 1 Introduction
Output voltage sharing loops
Kvo _ vo1f
vo1 Comparator 1
+ +
Gvo_mod − Drive
+ RS Flip-flop
+ circuit 1
vo_EA1 VRAMP 1
Kvo _ vo2f
vo2 Comparator 2
+ +
Gvo_mod − Drive
+ RS Flip-flop
+ circuit 2
vo_EA2
…
VRAMP 2
…
Kvo vo(n−1)f
vo(n−1) _ Comparator (n−1)
+ +
Gvo_mod − Drive
+ RS Flip-flop
vomod_ref + circuit (n−1)
vo_EA(n−1) VRAMP (n−1)
1/n …
+ _ Comparator n
+
Kvo vof − Drive
vo + + RS Flip-flop
+ circuit n
_ VRAMP n
+ vo_EA
Voref Gvo
Output voltage loop
Fig. 1.6 OVS control strategy for IPOS system
control strategy was proposed, as shown in Fig. 1.6. It consists of a common output
voltage control loop to regulate the system output voltage and n − 1 OVS control
loops to achieve OVS for IPOS system. K vo is the sensing gain of the system output
voltage and output voltage of each module. Gvo is the transfer function of the system
output voltage regulator. Gvo_mod is the transfer function of OVS regulator. It can
be seen that the reference voltage signal of each OVS loop is K vo vo /n, vo_EA is the
control signal derived from the system output voltage regulator, and vo_EAj (j 1,
2,…, n − 1) is the control signal derived from each OVS regulator. For the first
n − 1 modules, vo_EAj (j = 1, 2,…, n − 1) is added to vo_EA and then compared with
the sawtooth signal to obtain the duty cycle signal of module j. For the module n,

n−1
vo_EA j is subtracted from vo_EA and then compared with the sawtooth signal to
j1
obtain the duty cycle signal of module n. With the control strategy, the duty cycles of
modules with higher output voltages will decrease while the duty cycles of modules
with lower output voltages will increase, and thus OVS is achieved. From Fig. 1.6, it
can be found that the sum of the duty cycles caused by the OVS loops is zero, which
means that the OVS control loops have no influence on the system output voltage
regulation.
1.3.3 ISOP System
ISOP system can be used in higher input voltage applications such as the electric rail-
way system, where multiple converter modules with lower input voltage are adopted,
which is beneficial for reducing the voltage stress of the power switches. In order to
ensure the proper operation of ISOP system, the basic objective is to ensure input
voltage sharing (IVS) and output current sharing (OCS) among the constituent mod-
ules. The common duty cycle control strategy can also be used for ISOP system [23].
With the common duty cycle for all modules, the input currents of the modules with
higher input voltages will increase to reduce their input voltages, while the input
currents of the modules with lower input voltages will decrease to boost their input
voltages, and finally to achieve IVS. Similar to the IPOS system, IVS is also affected
by the matching of modules’ parameters. A fault-tolerant democratic IVS control
strategy for ISOP system was proposed in [26], as shown in Fig. 1.7. Each input
voltage signal of module is connected to the voltage sharing bus through an idea
diode, producing a common voltage reference signal, which is obtained from one
of the converters with highest input voltage within the ISOP system. The voltage
difference between the common voltage reference and each converter input voltage
is amplified and added to the output of system output voltage regulator for minor
control correction to ensure IVS. Gvcd is the transfer function of IVS loop regulator.
If a converter fails with its input short-circuited, the common voltage reference is
automatically increased to compensate for the loss of the failed converter, leading to
high system reliability.
An IVS control strategy was proposed for ISOP system in [27], as shown in
Fig. 1.8. The control strategy consists of a common output voltage control loop for
achieving desired system output voltage and n − 1 IVS control loops. V in /n is the
reference signal for IVS control loops. vo_EA is the control signal derived from the
system output voltage regulator, and vcd_EAj (j 1, 2,…, n − 1) is the control signal
derived from each IVS regulator. For the first n − 1 modules, vcd_EAj (j 1, 2,…, n
− 1) is subtracted from vo_EA and then compared with the sawtooth signal to obtain

n−1
the duty cycle signal of module j. For the module n, vcd_EA j is added to vo_EA and
j1
then compared with the sawtooth signal to obtain the duty cycle signal of module n.
With the control strategy, the duty cycles of modules with high input voltages will
increase and the duty cycles of modules with low input voltages will decrease, and
finally to achieve IVS. It is proved that the IVS loops are decoupled from one another
and are also decoupled from the system output voltage loop. Thus, the IVS regulator
and system output voltage regulator can be designed independently.
Based on the IVS control strategy shown in Fig. 1.8, an inner current control
loop could be introduced for each module, for the purpose of improving the system
dynamic performance. The feedback signal of inner current control loop can be the
input currents or output currents of the modules. Charge control method could be
also used for the inner current control loops, where the input currents of the modules
are taken as the feedback signals for a two-module ISOP system [28]. In [29], the
12 1 Introduction
Input voltage sharing loops
_ vin1 Comparator 1
_
+ Gvcd − Drive
+ RS Flip-flop
+ circuit 1
Voltage VRAMP 1
sharing bus
_ vin2 Comparator 2
_
+ Gvcd − Drive
RS Flip-flop
+ + circuit 2
VRAMP 2
…
…
_ vinn Comparator n
_
+ Gvcd − Drive
RS Flip-flop
+ + circuit n
VRAMP n
+
Gvo
Voref _
vof
Output voltage loop
Fig. 1.7 Democratic IVS control strategy for ISOP system
output filter inductor currents are taken as the feedback signals for the inner current
control loops with average current control mode.
As shown in Fig. 1.8, the duty cycle of each module regulates both the system
output voltage and corresponding module input voltage. A simple IVS control strat-
egy was proposed in [30], as shown in Fig. 1.9, where the regulation object of the
duty cycle of each module is separated. For the first n − 1 modules, the duty cycles
are used to regulate the input voltage of each module to be V in /n, and obviously the
input voltage of module n is also V in /n. The system output voltage is regulated by
module n.
Sensing of the input voltages of the modules is necessary in the control strategies
[26–30] to achieve IVS. A current cross-feedback control strategy was proposed in
[31] avoiding the sensing of the input voltages. Figure 1.10 shows the control strategy
for two-module ISOP system. Two modules use current-mode control with a common
system output voltage regulator providing the current reference iref for both current
loops. It should be noted that the feedback of current regulator for module 1 is the
output current of module 2, while the feedback of current regulator for module 2
is the output current of module 1. Assuming the system input voltage is constant
and the system works at steady state, if the input voltage V in1 increase while the
input voltage V in2 decreases due to a disturbance, then filter inductor current iLf1
increases while iLf2 decreases. With the control strategy shown in Fig. 1.10, the duty
Input voltage sharing loops
_ vin1 Comparator 1
Vin/n _
+
Gvcd − Drive
+ RS Flip-flop
+ circuit 1
vcd_EA1 VRAMP 1
_ vin2 Comparator 2
_
+
Gvcd − Drive
+ RS Flip-flop
+ circuit 2
vcd_EA2 VRAMP 2
…
…
vin(n−1)
_
_ Comparator (n−1)
+
Gvcd − Drive
+ RS Flip-flop
+ circuit (n−1)
vcd_EA(n−1) VRAMP (n−1)
…
+ Comparator n
+ +
− Drive
+ + RS Flip-flop
+ circuit n
VRAMP n
+ vo_EA
Gvo
Voref _
vof
Output voltage loop
Fig. 1.8 IVS control strategy for ISOP system
cycle of module 1 increases while the duty cycle of module 2 decreases, resulting
in the decrease of V in1 and increase of V in2 , and finally IVS can be achieved. When
the number of the modules increases, the control strategy will become complex due
to mutual cross-feedback among the current signals and the system modularity is
lowered.
1.3.4 ISOS System
ISOS system is suitable for the applications where both the input and output voltages
are relatively high, and it is critical to ensure both IVS and OVS for the stable oper-
ation of ISOS system. Ayyanar et al. proposed a voltage sharing control for ISOS
system [32], which is similar to Fig. 1.8. References [33, 34] pointed out that a weak
natural rebalancing ability exists in the ISOS system with interleaved switching for
14 1 Introduction
vin1 Module 1
_+ Comparator 1
Gvcd − Drive
Vin/n RS Flip-flop
+ circuit 1
VRAMP 1
vin2 Module 2
_+ Comparator 2
Gvcd − Drive
Vin/n RS Flip-flop
+ circuit 2
VRAMP 2
…
…
vin(n−1) Module (n−1)
Comparator (n−1)
_+
Gvcd − Drive
Vin/n RS Flip-flop
+ circuit (n−1)
VRAMP (n−1)
Comparator n Module n
+
Gvo − Drive
Voref _ RS Flip-flop
vof + circuit n
VRAMP n
Fig. 1.9 A simple IVS control strategy for ISOP system
_ iLf2 Comparator 1
+
Output voltage regulator Gi − Drive
RS Flip-flop
+ circuit 1
+ iref Current VRAMP 1
Gvo regulators
Voref _
vof _ iLf1
Comparator 2
+
Gi − Drive
RS Flip-flop
+ circuit 2
VRAMP 2
Fig. 1.10 Current cross-feedback control strategy for two-module ISOP system
different cells. Although the voltage-dependent losses, such as the switching loss,
could enhance the rebalancing ability, the voltage sharing performance is consider-
ably affected by the matching of module parameters and load current.
The current cross-feedback control strategy can also be used for ISOS system to
achieve voltage sharing [35, 36], and its operation principle is the same as that of
Fig. 1.10. Likewise, the control strategy will become complex when the number of
the modules increases.
In conclusion, these prior studies focus on one or two of the four connection
architectures and do not reveal the inherent relationships between the four connec-
tion architectures. In this book, Chap. 2 will systematically analyze the inherent
relationships between the sharing of input voltages/currents and the sharing of out-
put voltages/currents from the view of power conservation, and discuss the stability
of various possible control strategies. Based on the analysis, a general control strategy
is proposed for all the four connection architectures. In Chap. 3, a small-signal model
of ISOP system with phase-shifted PWM full-bridge converter as the basic module is
derived to design the output voltage loop regulator and IVS loop regulator. Moreover,
the design of the IVS loop regulator is analyzed when voltage–current double closed
loop is employed for ISOP system. In Chap. 4, a wireless IVS control strategy for
ISOP system based on positive output voltage gradient method is presented, in which
no control interconnection among the constituent modules is required, leading to a
truly modular design for ISOP system and high system reliability.
1.4 DC–AC Inverter Series–Parallel Power Conversion

Systems
1.4.1 DC–AC Inverter
DC–AC inverter is used for converting a DC voltage into an AC voltage, and there
are various topologies. In this book, the popular single-phase full-bridge inverter
is selected as the basic module to constitute the series–parallel combined systems.
Figure 1.11a shows the single-phase full-bridge inverter, where V in is the input DC
voltage, S 1 (D1 )–S 4 (D4 ) constitute the single-phase inverter bridge, L f is the output
filter inductor, C f is the output filter capacitor, and Z Ld is the load impedance.
For DC–AC inverter, there are mainly two control methods, namely, the volt-
age single closed-loop control and the voltage–current double closed-loop control.
The block diagram of the voltage–current double closed-loop control is shown in
Fig. 1.11b, where the error of the voltage reference voref and the sampling signal of
output voltage vof is sent into the voltage regulator Gvo , and the output signal of Gvo
serves as the current reference iref . Then, the error of the sampling signal of inductor
current iLf and iref is sent to the current regulator Gi . The output signal of Gi is fed into
the sinusoidal pulse-width modulator (SPWM) and it is compared with the triangular
carrier to obtain the drive signals for the four power switches. By removing the inner
current loop in Fig. 1.11b, the voltage single closed-loop control will be obtained,
as shown in Fig. 1.11c. Compared with the voltage single closed-loop control, the
voltage–current double closed-loop control has better dynamic performance and the
current-limiting function.
16 1 Introduction
S1 D1 S3 D3 Lf
io
+
+ iLf iCf
vinv vo
Vin Cf ZLd _
–
S2 D2 S4 D4
(a) Single-phase full-bridge inverter

+ +
voref Gvo Gi SPWM
– iref – S1~S4
vo Kv
vof
iLf Ki
iLf_f
(b) Voltage-current double closed-loop control

+
voref Gvo SPWM
– S1~S4
vo Kv
vof
(c) Voltage single closed-loop control
Fig. 1.11 Single-phase full-bridge inverter and its control block diagram
Regardless of any control method being adopted, multiple DC–AC inverter mod-
ules could be connected in series or parallel at the input and output sides to constitute
the DC–AC inverter series–parallel combined system.
1.4.2 IPOP DC–AC Inverter System
IPOP inverter system, which is commonly known as the parallel inverter system, has
been extensively studied among the four series–parallel combined inverter systems.
This system has been widely used in uninterruptible power supply (UPS), aeronau-
tical static inverter, and so on. The crucial issue of the IPOP inverter system is to
achieve output current sharing of each module. The research aiming at this control
objective has experienced the evolution from centralized control, master–slave con-
trol to distributed control. The control methods for IPOP inverter system can be also
categorized into interconnected control and wireless droop control, and the wireless
droop control is essentially a kind of distributed control.
1.4 DC–AC Inverter Series–Parallel Power Conversion Systems 17
1.4.2.1 Centralized Control
Figure 1.12 shows the block diagram of the centralized control for IPOP inverter
system [37, 38]. In the centralized control method, the phase-locked loop (PLL) in
each inverter module is used to synchronize its output voltage in frequency and phase
with the synchronization pulse signal, which is produced by the crystal oscillator in
the parallel control unit. The total load current io is sensed and divided by the number
of constituent inverter modules connected in parallel, and then serves as the current
sharing reference, iref , for each inverter module. The sensed output current of each
module is compared with iref , obtaining the corresponding current deviation. Thanks
to being synchronized by one synchronization pulse signal, the output voltage of
each inverter module can be almost the same in frequency and phase, and the current
amplitude difference among the inverter modules is caused by the inconsistence of
the voltage amplitude. The aforementioned current deviation is used to compensate
any inequality in voltage amplitude of the inverter modules to achieve output current
sharing of each module.
The implementation of the centralized control is quite simple, and the current
sharing is relatively good. However, the whole parallel system tends to collapse once
the parallel control unit fails. Thus, the redundant and reliability is not high.
io
Fig. 1.12 Block diagram of centralized control for IPOP inverter system
18 1 Introduction
1.4.2.2 Master–Slave Control
Figure 1.13 shows the master–slave control [39–42], where one inverter is the master
module and the others are the slave modules. In Fig. 1.13, K vo is the output voltage
sense gain, K i1 –K in are the filter inductor current sense gain of each module, Gvo is
the transfer function of the output voltage regulator, Gi1 –Gin are the transfer functions
of the current regulator of each module, and Ginv1 –Ginvn are the transfer functions of
the SPWM modulators. The output voltage regulator in the master module generates
the unified current reference signal iref . Since the output filter inductor current of
each module tracks iref , the output current sharing is achieved. The shortcoming of
the master–slave control is that the whole system will be collapsed once the master
module fails.
1.4.2.3 Distributed Control
1. Average Current Control Method
Figure 1.14 shows the average current control, a kind of distributed control [43].
As seen, the voltage reference voref is sent to the output voltage regulators of all the
inverter modules, and the average value of the outputs of the output voltage regulators
of all the modules, iave , serves as the current reference for all the modules. With such
arrangement, the instantaneous current sharing of each inverter module could be
achieved without complex current sharing control circuit. This control method has
the following merits: simple control circuit, prompt current sharing regulating speed,
Fig. 1.13 Block diagram of master–slave control for IPOP inverter system
voref iave
vinv1 _
+ iref1 + + 1 iLf1 io1
Gvo1 _ Gi1 Ginv1 sLf1
_ +_
vof iLf1_f iCf1
Ki1 sCf1
Kvo
Module 1
Output
voltage + ioj +
irefj + 1 Current + vo
synchronous ZLd
n sharing bus
bus + +
vinvn _ iLfn ion

+ + + 1
Gvon Gin Ginvn sLfn
_ irefn _ +_
vof iLfn_f iCfn sC
Kin fn
Kvo
Module n
Fig. 1.14 Average current control method for IPOP inverter system
and ease of implementation of redundancy due to modular completely reciprocal.

However, the current sharing bus among modules is susceptible to interference, which
tends to decrease the current sharing performance. In addition, this control method
has poor output characteristics.
In order to improve the output characteristics of both single module and the
whole system, the load current feed-forward control is introduced [44]. Here, the
feed-forward point is located before the current reference averaging point. In the
improved method, the current sharing performance and the current-limiting function
are remained as the conventional method.
2. Wireless Droop Control
In the aforementioned control methods, the current sharing bus is required, and it is
susceptible to interference. Figure 1.15 shows the wireless droop control [45–49],
which has no current sharing bus. The output characteristic droop circuit is intro-
duced to make the frequency and amplitude of the output voltage of each module
decrease with the increase of the active and reactive power, respectively, and thus
the frequency and amplitude of the output voltage of each module stabilize at a new
equilibrium point. By this means, the control method suppresses the circulating cur-
rent and achieves the output current sharing. Since there is no connection among the
constituent inverter modules, the wireless droop control is not susceptible to inter-
ference and has better redundancy. Nevertheless, due to the droop characteristic, the
output characteristics are poor.
20 1 Introduction
Sine wave ω1 P1
reference Power
generator calculation
Vsinωt V1 Q1 _
vinv1 iLf1
+ iref1 + + 1 + io1
voref1 Gvo1 Gi1 Ginv1 sLf1
– _
– vo1f iLf1_f iCf1 sC
Ki1 f1
Kvo vo
Module 1
ioj + vo
+
ZLd
+
Sine wave ωn Pn
vo
reference Power
generator calculation
Vsinωt Vn Qn _
vinvn iLfn
+ irefn + + 1 + ion
Gvon Gin Ginvn sLfn
vorefn – _
– vonf iLfn_f
Kin iCfn sC
fn
Kvo
Module n
Fig. 1.15 Wireless droop control strategy for IPOP inverter system
1.4.3 IPOS DC–AC Inverter System
Similar with the output current sharing control for the IPOP inverter system, the
output voltage sharing control is only needed for IPOS inverter system. Figure 1.16
shows a three-loop control strategy for IPOS inverter system [50]. The three loops
here refer to the common system output voltage loop, the independent output voltage
sharing loop of each module, and the inner current loop of each module. In Fig. 1.16,
voref is the voltage reference of the system output voltage loop, Gvo is the output
voltage regulator, Gi1 –Gin are the current regulators, L f1 –L fn are the filter inductors,
C f1 –C fn are the filter capacitors, Gvo1 –Gvon are the regulators of output voltage shar-
ing loop, and the voltage reference vomod_ref of output voltage sharing loop is equal
to voref /n. The common output voltage loop regulates the system output voltage, and
the output signal of its regulator Gvo serves as an initial reference signal for the inner
current loop of each module. Since discrete parameters of each module are not well
identical, the output voltage sharing loop is introduced to adjust the reference of the
current loop to achieve output voltage sharing of each module. This control strategy
vomod_ref
Kvo 1/n
vo1
Kvo _
+ Inner current loops _
Gvo1
+ vinv1 1 iLf1 + iCf1 1 vo1
Gi1 Ginv1 sLf1 sCf1
+_ +
vo2 iLf1_f
Kvo _ Ki1
vo2
+ Gvo2 _
+ vinv2 1 iLf2 + iCf2 1
Output voltage Gi2 Ginv2 sLf2 sCf2
+_ + io
sharing loops iLf2_f
Ki2 1
ZLd
+
von +
Kvo _ vo
+ +
Gvon _
+ vinvn 1 iLfn + iCfn 1 von
Gin Ginvn sLfn sCfn
+_ +
voref + iLfn_f
Gvo Kin
_ iref
vof
Kvo
Output voltage loop
Fig. 1.16 Control strategy for IPOS inverter system
can achieve low total harmonic distortion in the system output voltage, fast dynamic
response, and good output voltage sharing performance whether the corresponding
parameters among modules are equal or not.
1.4.4 ISOP DC–AC Inverter System
The crucial issue of the ISOP inverter system is to ensure the input voltage sharing
and the output current sharing among the constituent modules. Figure 1.17 shows
a compound balanced control strategy [51], which consists of three control loops,
namely, the common output voltage loop, the input voltage sharing loop, and the inner
current loop of each module. Here, the current inner loop adopts inductor current
feedback hysteretic control. In Fig. 1.17, Gvo is the output voltage regulator, Gvcd is
the input voltage sharing regulator, and K vi and K vo are the sensor gains of the input
voltage and output voltage, respectively. The common output voltage loop regulates
the system output voltage, and the output signal of output voltage regulator Gvo ,
iref , serves as the initial current reference of all the inner current loops. The input
voltage sharing loop ensures the even input voltage and the equivalence of the output
active power of each module. Since the control object is the inverter whose current
reference signal contains both amplitude and phase information, the multipliers are
introduced here to synchronize the phase of the initial current reference and that of
22 1 Introduction
Vin
n K + ivd1 isv1
Gvcd _
vi _ iref1 vinv1
_ 1 iLf1 + io1
vin1 Gi1 Ginv1 + sLf1 _
Kvi + +_ iCf1
iLf1_f sCf1
Input voltage Ki1
sharing loops
Vin Inner current loops
n + ivd2 isv2
Kvi Gvcd _ +
_ _ iref2 vinv2 1 iLf2 + io2 io vo
vin2 Gi2 Ginv2 + sLf2 ZLd
Kvi + +_ _ ++
iLf2_f iCf2
Ki2 sCf2
Vin
n K + ivdn isvn
vi Gvcd
_
vinn
Kvi _ _
iref + irefn vinvn 1 iLfn + ion
voref + _ Gvo Gin Ginvn + sLfn
+_ _ iCfn
iLfn_f sCfn
Kin
vof
Kvo
Output voltage loop
Fig. 1.17 Compound balanced control strategy for ISOP inverter system
the signal isvj (j 1, 2,…, n), which is used to alter the current reference by the input
voltage sharing loop. Consequently, the output current amplitude is adjusted with the
power factor angle of modular output current being kept the same simultaneously.
Figure 1.18 shows an output-inductor-current cross-feedback control scheme [52],
which consists of two control loops, namely, the common output voltage loop and
the inner current loop of each module. The common output voltage loop regulates
the system output voltage. In Fig. 1.18, Gvo is the output voltage regulator, and its
output signal, iref , serves as the common reference signal of inner current loop of each
module. Here, the current feedback for each individual inner current loop is the sum
of other output inductor currents instead of its own, and so input voltage sharing (IVS)
and output voltage sharing (OCS) are achieved for ISOP inverter system. Although
the control scheme is simple, the need of cross-feedback for output inductor current
is not conducive to the modularization of the system.
1.4.5 ISOS DC–AC Inverter System
The crucial issue of ISOS inverter system is to ensure the input voltage sharing and
the output voltage sharing of each module. A compound balanced control strategy is
proposed [53], as shown in Fig. 1.19. It consists of three control loops, namely, the
system output voltage loop, the input voltage sharing loop, and the inner output filter
capacitor current loop of each module. The output signal of the output voltage regu-
Module 1 _
+ iref + + 1 iLf1 io1
voref _ Gvo _ Gi1 Ginv1 v
inv1 sLf1 +_ iCf1
n
vof
∑i
i=2
Lfi_f
iLf1_f
Ki1
sCf1
Module j _ +
+ + 1 iLfj ioj vo
_ Gij Ginvj sLfj ZLd
n
vinvj +_ +
iCfj +
∑
i =1,i ≠ j
iLfi_f iLfj_f
Kij sCfj
Module n _
+ + 1 iLfn ion
_ Gin Ginvn sLfn
vinvn +_ iCfn
n −1
sCfn
∑i
i =1
Lfi_f
iLfn_f
Kin
Kvo
Fig. 1.18 Output-inductor-current cross-feedback control for ISOP inverter system
lator Gvo , iref , serves as the initial current reference of all inner current loops. Since
the current reference contains the amplitude and phase information, the multipliers
are introduced here to synchronize the phase of the initial current reference and that
of the signal isvj (j 1, 2,…, n), which is used to alter the current reference by input
voltage sharing loop. Here, the output filter capacitor current control is adopted for
the inner current loop, so the input voltage sharing loop only adjusts the amplitude
of the output filter capacitor current with the phase of the output filter capacitor cur-
rent of each module being kept the same. Therefore, only the amplitude of module
output voltage is adjusted while the phase is synchronized. The input voltage sharing
loop ensures the even input voltage and the equal of the output active power of each
module. Thanks to the synchronization of the output voltage of each module, output
voltage sharing (OVS) is achieved ultimately.
An output-voltage cross-feedback control scheme is proposed [54], as shown in
Fig. 1.20. It consists of two control loops, namely, the system output voltage loop and
individual output voltage loop of each module. In Fig. 1.20, voref is the system output
voltage reference, and the output signal of output voltage regulator Gvo , iref , is sent
to all the modules. In the output voltage loop of each module, the reference signal
is the amplitude of the system output voltage reference multiplied by (n − 1)/n,
and the feedback signal is the sum of output voltage amplitude of other modules
except itself. The output voltage regulators Gvo1 –Gvon generate regulating signals
24 1 Introduction
Vin
n K + ivd1 isv1
Gvcd1 _
vi _ iref1
_ vinv1 1 iLf1 iCf1 1 vo1
vin1 Gi1 Ginv1 sLf1 _ sCf1
Kvi + +_ +
iCf1_f
Input voltage Ki1
Vin sharing loops
n K + ivd2 isv2 Inner current loops vo2
vi Gvcd2 _
_ _ iref2 vinv2 1 iLf2 iCf2 1
vin2 Gi2 Ginv2 io
Kvi + +_ + sLf2 _ sCf2
iCf2_f
Ki2 1
Vin ZLd
n K + ivdn isvn
vi Gvcdn
_ vo
vinn
Kvi _ _ _
+ irefn vinvn iCfn
iref 1 1 von
voref Gvo Gin Ginvn sLfn iLfn sCfn
+_ +_ i +
Cfn_f
Kin
vof
Kvo
Output voltage loop
Fig. 1.19 Compound balanced control strategy for ISOS inverter system
iref1 –irefn , which are related to magnitude difference. These signals are multiplied
with iref to obtain the module adjusting signals isv1 –isvn with the same phase and
different amplitudes, which are used to alter the amplitude of module output voltage,
and thus input voltage sharing (IVS) and output voltage sharing (OVS) are achieved
for ISOS inverter system. In this method, the feedback signal for every individual
output voltage loop contains the information of other modules. So, all the modules are
inevitably mutual coupling, which restricts the modularity of ISOS inverter system.
In summary, for DC–AC inverter series–parallel combined system, existing liter-
ature has not analyzed the inherent relationship of the four types of series–parallel
combination systems. So, Chap. 5 will analyze the relationship between the input
and output powers of the above DC–AC inverter series–parallel combined system,
and then put forward a general control strategy so as to form a set of systematic
control theory for DC–AC inverter series–parallel combined system, and lay the
theoretical foundation for the proposition of the specific control scheme of the four
types of series–parallel combination systems. Based on the proposed general control
strategy, Chaps. 6 and 7 will give specific control strategies for the ISOP and ISOS
inverter systems, and put forward the distributed control based on the centralized
control to realize the modularization of the systems. In addition, Chap. 8 will present
an improved average current control strategy for IPOP inverter system to improve
the output characteristics of both single module and the whole system. Moreover,
in this improved method, the current sharing and the current-limiting function are
remained unchanged compared with the conventional method.
1.5 Summary 25
_ v Kvo
of
voref + iref
Gvo
1# Module isv1 _
n −1 iref1 + 1 iLf1 io1
Gvo1 Gi1 Ginv1 sLf1
voref vinv1 +_ i
n +_ Cf1
Kvo n sCf1
∑v
i=2
oi
j# Module isvj _
irefj + 1 iLfj ioj+ vo
Gvoj Gij Ginvj Z
+_ vinvj sLfj +_ + + Ld
iCfj
Kvo n sCfj
∑v
i =1
oi
i≠ j
n# Module isvn _
irefn + 1 iLfn ion
Gvon Gin Ginvn sLfn
+_ vinvn +_ iCfn
Kvo n −1 sCfn
∑v
i =1
oi
Fig. 1.20 Output-voltage cross-feedback control for ISOS inverter system
1.5 Summary
This chapter briefly reviews the history and status of the development of power
electronics. Power electronics system integration, standardization, and modulariza-
tion are one of the effective ways to reduce the cost of producing power electronics
products, shorten the development cycle, and improve the reliability. Standardized
module series–parallel combination system is one of the significant constituent parts
of power electronic system integration, and the research on its control technique to
ensure the stability of the system operation and the power balance of each module
is the primarily crucial issue.
This chapter introduces the advantages and major categories of standardized mod-
ule series–parallel combination system, and elaborates the control techniques for the
series–parallel combination system with DC–DC converter and DC–AC inverter as
the basic module, which will lay a foundation for the narration of the following
chapters.
26 1 Introduction
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Chapter 2
A General Control Strategy for DC–DC
Series–Parallel Power Conversion
Systems
Abstract The inherent relationships between the sharing of input voltages/currents

and the sharing of output voltages/currents are analyzed systematically from the view
of power conservation in this chapter, and the stability of various possible control
strategies is discussed. Based on the analysis, a general control strategy is proposed
for the DC–DC series–parallel power conversion systems, which not only achieves
equilibrium between the constituent modules but also decouples the output voltage
control loop and the sharing control loop. Furthermore, a modularization architecture
for the DC–DC series–parallel power conversion systems is proposed, achieving full
modularization where all the modules are self-contained and standardized, and no
extra control is needed to achieve sharing of voltage and/or current at the input and
output sides. Experimental prototypes are built and tested to validate the proposed
general control strategy and the modularization architecture.
Keywords Sharing of input voltages/current · Sharing of output voltages/current

Stability · General control strategy · Modularization architecture
In Chap. 1, the four basic connection architectures (IPOP, IPOS, ISOP, and ISOS)
of DC–DC series–parallel power conversion systems were introduced. In order to
ensure proper operation of DC–DC series–parallel power conversion systems, the
equilibrium between the constituent modules must be achieved, i.e., proper input
voltage sharing (IVS) and output voltage sharing (OVS) among the constituent mod-
ules when they are connected in series at the input and output sides, respectively,
and proper input current sharing (ICS) and output current sharing (OCS) among the
constituent modules when they are connected in parallel at the input and output sides,
respectively. Previous studies have addressed the issue of sharing of the input and/or
output voltage and/or current. However, these prior studies focus on one or two of the
four connection architectures and do not reveal the inherent relationships between
the four connection architectures. In this chapter, the inherent relationships between
the sharing of input voltages/currents and the sharing of output voltages/currents are
analyzed systematically from the view of power conservation, and the stability of var-
ious possible control strategies are discussed. Based on the analysis, a general control
strategy is proposed for the DC–DC series–parallel power conversion systems, which
30 2 A General Control Strategy for DC–DC Series–Parallel Power …
not only achieves equilibrium between the constituent modules but also decouples
the output voltage control loop and the sharing control loop. Furthermore, a modu-
larization architecture for the DC–DC series–parallel power conversion systems is
proposed, achieving full modularization where all the modules are self-contained
and standardized, and no extra control is needed to achieve sharing of voltage and/or
current at the input and output sides. Experimental prototypes were built and tested
to validate the proposed general control strategy and the modularization architecture.
2.1 Possible Control Strategies for DC–DC Series–Parallel

Power Conversion Systems
For input-parallel-connected systems (IPOP and IPOS), the input voltages of mod-
ules are equal, therefore, we need to make the module output currents equal for
IPOP system and the output module voltages equal for IPOS system, i.e., OCS and
OVS should be ensured for IPOP and IPOS systems, respectively. For input-series-
connected systems (ISOP and ISOS), we not only have to ensure OCS and OVS for
ISOP and ISOS systems, respectively, but also ensure IVS for both ISOP and ISOS
systems. In other words, both IVS and OCS are needed for ISOP system, and both
IVS and OVS are needed for ISOS system.
As discussed before, we can see that if the modules are connected in parallel at
the input sides, only OCS or OVS is needed, and if the modules are connected in
series at the input sides, both IVS and OCS or OVS are needed. Two questions are of
fundamental importance: (1) for IPOP and IPOS systems, as all modules share the
same input voltage, would ICS imply OCS or OVS so that we only need to direct
control to ensure ICS? and (2) for ISOP and ISOS systems, what is the relationship
between IVS and OCS or OVS?
Figure 2.1 shows the four connection architectures of DC–DC series–parallel
power conversion systems. For the j-th (j 1, 2, …, n, n is the number of modules)
module, V in_j and I in_j denote the input voltage and the input current, respectively;
V o_j and I o_j denote the output voltage and the output current, respectively; I cd_j and
I cf_j denote the input and output filter capacitor currents, respectively; and I cin_j and
I co_j denote the input and output currents of the power stage, not including the input
and output filter capacitor currents, respectively. At steady state, since both the input
voltage and the output voltage are constant, the average values of both the input filter
capacitor current and the output filter capacitor current are zero, we have,
Iin_ j Icin_ j ( j 1, 2, . . . , n) (2.1)

Ico_ j Io_ j ( j 1, 2, . . . , n) (2.2)
Then, by power conservation, we have,

2.1 Possible Control Strategies for DC–DC Series–Parallel Power … 31
Iin Iin_1 Icin_1 Ico_1 Io_1 Io Iin Iin_1 Icin_1 Ico_1 Io_1 Io
+ +
+ Icd_1 DC-DC
Icf_1 + + Icd_1 DC-DC
Icf_1 +
Vin_1 Vo_1 Vo Vin_1 Vo_1
Vin _ Converter Cf1 _ Vin _ Converter Cf1 _
Cd1 _ Cd1
Module 1 Module 1
Iin_2 Icin_2 Ico_2 Io_2 Iin_2 Icin_2 Ico_2 Io_2

+ Icd_2 DC-DC
Icf_2 +
Vin_2 Vo_2 Vin_2 Vo_2 Vo
_ Converter Cf2 _ _ Converter Cf2 _
Cd2 Cd2
Module 2 Module 2
Iin_n Icin_n Ico_n Io_n Iin_n Icin_n Ico_n Io_n

+ Icd_n DC-DC
Icf_n + + Icd_n DC-DC
Icf_n +
Vin_n Converter Vo_n Vin_n Converter Vo_n
_ Cdn Cfn _ _ Cdn Cfn _ _
Module n Module n
(a) IPOP (b) IPOS
Iin Iin_1 Icin_1 Ico_1 Io_1 Io Iin Iin_1 Icin_1 Ico_1 Io_1 Io
+ +
+ Icd_1 DC-DC
Icf_1 +
Vin_1 Vo_1 Vo Vin_1 Vo_1
_ Converter Cf1 _ _ Converter Cf1 _
Cd1 _ Cd1
Module 1 Module 1
Iin_2 Icin_2 Ico_2 Io_2 Iin_2 Icin_2 Ico_2 Io_2

+ Icd_2 DC-DC
Icf_2 +
Vin_2 Vo_2 Vin_2 Vo_2 Vo
Vin _ Converter Cf2 _ Vin _ Converter Cf2 _
Cd2 Cd2
Module 2 Module 2
Iin_n Icin_n Ico_n Io_n Iin_n Icin_n Ico_n Io_n

+ Icd_n DC-DC
Icf_n + + Icd_n DC-DC
Icf_n +
Vin_n Converter Vo_n Vin_n Converter Vo_n
_ Cdn Cfn _ _ Cdn Cfn _ _
Module n Module n
(c) ISOP (d) ISOS
Fig. 2.1 Four connection architectures of DC–DC series–parallel power conversion systems
⎧
⎪
⎪ Vo_1 · Io_1 Po1 Pin1 · η1 Vin_1 · Iin_1 · η1
⎪
⎪
⎪
⎨ Vo_2 · Io_2 Po2 Pin2 · η2 Vin_2 · Iin_2 · η2
(2.3)
⎪
⎪
..
⎪
⎪ .
⎪
⎩V · I P P ·η V
o_n o_n on inn n in_n · Iin_n · ηn
where Po1 , Po2 , …, Pon are the output power of the modules, Pin1 , Pin2 , …, Pinn are
the input power of the modules, and η1 , η2 , …, ηn are the conversion efficiencies of
the modules.
2.1.1 IPOP Systems
For IPOP systems, the input voltages of the modules are equal, and the output voltages
of the modules are equal, i.e., V in_1 V in_2 … V in_n and V o_1 V o_2 … V o_n .
If the module input currents are equal, i.e., I in_1 I in_2 … I in_n , then the module
input power are equal, i.e., Pin1 Pin2 … Pinn . According to (2.3), we can get,
Io_1 /η1 Io_2 /η2 · · · Io_n /ηn (2.4)
Equation (2.4) illustrates that the difference among the module output currents is
dependent on the difference of the module efficiencies. In practice, as the topologies
of the modules are identical, the mismatches in the power stages, such as the power
devices, transformers, inductors, and capacitors, are not so large, so that the difference
among the module efficiencies is very little and it will be ignored in the following.
Thus, the module output currents will be nearly evenly shared for IPOP systems. In
other words, achieving ICS implies OCS for IPOP systems.
2.1.2 IPOS Systems
For IPOS systems, the input voltages of the modules are equal, and the output currents
of the modules are equal, i.e., V in_1 V in_2 … V in_n and I o_1 I o_2 … I o_n .
If the module input currents are equal, i.e., I in_1 I in_2 … I in_n , then the module
input power are equal, i.e., Pin1 Pin2 … Pinn . According to (2.3), we can get,
Vo_1 /η1 Vo_2 /η2 · · · Vo_n /ηn (2.5)
Equation (2.5) illustrates that the difference among the module output voltages
is dependent on the difference of the module efficiencies. Thus, the module output
voltages will be nearly evenly shared for IPOS systems. In other words, achieving
ICS implies OVS for IPOS systems.
2.1.3 ISOP Systems
For ISOP systems, the input currents of the modules are equal, and the output voltages
of the modules are equal, i.e., I in_1 I in_2 … I in_n and V o_1 V o_2 … V o_n .
If the module output currents are equal, i.e., I o_1 I o_2 … I o_n , then the module
output power are equal, i.e., Po1 Po2 … Pon . According to (2.3), we have,
Vin_1 · η1 Vin_2 · η2 · · · Vin_n · ηn (2.6)

2.1 Possible Control Strategies for DC–DC Series–Parallel Power … 33
Equation (2.6) illustrates that the difference in the input voltages among the mod-
ules is dependent on the difference of the module efficiencies if the module output
currents are equal.
If IVS control strategy is used to achieve V in_1 V in_2 … V in_n V in /n, then
the module input power are equal, i.e., Pin1 Pin2 … Pinn . According to (2.3),
we have,
Io_1 /η1 Io_2 /η2 · · · Io_n /ηn (2.7)
Equation (2.7) illustrates that the difference in the output currents among the
modules is dependent on the difference of the module efficiencies if the module
input voltages are equal.
In summary, for ISOP systems, if the module input voltages are equal, the module
output currents will be nearly equal, and on the other hand, if the module output cur-
rents are equal, the module input voltages will be nearly equal. So, we can conclude
that once IVS is achieved, OCS is nearly achieved automatically and vice versa. That
is to say, we need to ensure either IVS or OCS.
2.1.4 ISOS Systems
For ISOS systems, the input currents of the modules are equal, and the output currents
of the modules are equal, i.e., I in_1 I in_2 … I in_n and I o_1 I o_2 … I o_n . If
the module output voltages are equal, i.e., V o_1 V o_2 … V o_n , then the module
output power are equal, i.e., Po1 Po2 … Pon . According to (2.3), we have,
Vin_1 · η1 Vin_2 · η2 · · · Vin_n · ηn (2.8)
Equation (2.8) illustrates that the difference in the input voltages among the mod-
ules is dependent on the difference of the module efficiencies if the module output
voltages are equal.
If IVS control strategy is used to achieve V in_1 V in_2 … V in_n V in /n, then
the module input power are equal, i.e., Pin1 Pin2 … Pinn . According to (2.3),
we have,
Vo_1 /η1 Vo_2 /η2 · · · Vo_n /ηn (2.9)
Equation (2.9) illustrates that the difference in the output voltages among the
modules is dependent on the difference of the module efficiencies if the module
input voltages are equal.
In summary, for ISOS systems, we can see that if the module input voltages
are equal, the module output voltages will be nearly equal, and on the other hand,
if the module output voltages are equal, the module input voltages will be nearly
Table 2.1 Relationship between the input sides and output sides
Architecture Input side Output side
Input voltages Input currents Output voltages Output currents
IPOP Equal by Equal sharing Equal by Equal sharing
connection achievable by connection achievable by
control control
IPOS Equal sharing Equal by
achievable by connection
control
ISOP Equal sharing Equal by Equal by Equal sharing
achievable by connection connection achievable by
control control
ISOS Equal sharing Equal by
achievable by connection
control
equal. Thus, we can conclude that once IVS is achieved, OVS is nearly achieved
automatically and vice versa. That is to say, we need to ensure either IVS or OVS.
Based on the above analysis, we have the following conclusions if the module
efficiencies are the same:
(1) for IPOP systems, achieving ICS implies OCS,
(2) for IPOS systems, achieving ICS implies OVS,
(3) for ISOP systems, achieving IVS implies OCS and vice versa,
(4) for ISOS systems, achieving IVS implies OVS and vice versa.
From the earlier discussion, we clearly see that for any of the four connection
architectures, proper sharing of all voltages or currents can be nearly achieved by
directing control efforts to ensure the proper sharing of either the input voltage or
current, as shown in Table 2.1.
2.2 Stability of the Control Strategies
In this section, we examine the stability of the system when the input voltages or
currents are controlled to achieve IVS or ICS, and when the output voltages or
currents are controlled to achieve OVS or OCS. In our analysis, we assume that the
system’s input voltage, output voltage, and load current are kept unchanged when
perturbations are imposed on the input voltage/current and output voltage/current of
the modules.
2.2 Stability of the Control Strategies 35
2.2.1 Controlling at Input Side
Regardless of the connection type at the input side, when ICS (for input-parallel-
connected systems) or IVS (for input-series-connected systems) is achieved, each
converter module behaves as a constant power source as seen at the output side, as
shown in Fig. 2.2, and the module input powers are equal, i.e.,
Vo_ j · Ico_ j Pin j · η const ( j 1, 2, . . . , n) (2.10)
The relationship between the currents at the output side is
Icf_ j Ico_ j − Io_ j ( j 1, 2, . . . , n) (2.11)
For the case where the output sides are connected in parallel, as shown in Fig. 2.2a,
the output voltages of all modules are equal, and from (2.10), the output currents of
all modules are identical. Thus, no perturbation occurs, i.e., the system is stable.
We now examine the case where the output sides are connected in series, as shown
in Fig. 2.2b. We assume that a perturbation occurs in the output filter capacitor
voltages and the output voltages of some modules, e.g., V o_1 increases and V o_2
decreases, while the output voltages of other modules are unchanged. According to
(2.10) and (2.11), I co_1 and I cf_1 vary as shown in Fig. 2.3. Suppose point A is the
equilibrium operating point, when V o_1 increases under perturbation, the operating
point moves to point B. At point B, I co_1 is smaller than I o and V o_1 is higher than
V o /n. Hence, the filter capacitor current I cf_1 is negative, causing C f1 to be discharged
Ico_1 Io_1 Io Ico_1 Io_1 Io

+ +
Constant Icf_1 + Constant Icf_1 +
power source Vo_1 Vo power source Vo_1
(Module 1) Cf1 _ (Module 1) Cf1 _
_
Ico_2 Io_2 Ico_2 Io_2

Constant Icf_2 + Constant Icf_2 +
power source Vo_2 power source Vo_2 Vo
(Module 2) Cf2 _ (Module 2) Cf2 _
Ico_n Io_n Ico_n Io_n

Constant Icf_n + Constant Icf_n +
power source Vo_n power source Vo_n
(Module n) Cfn _ (Module n) Cfn _ _
(a) Output sides connected in parallel (b) Output sides connected in series
Fig. 2.2 Equivalent schematic diagram for the input side control strategies
Fig. 2.3 Currents and

voltage of the output side of Ico_1 (Pin = const)
module 1
A
Io
B
0
Vo Vo_1
n
Icf_1
to supply the deficit current, and as a result, V o_1 decreases, and the operating point
returns to point A. Thus, V o_1 returns to the equilibrium voltage. Similarly, I co_2
increases as V o_2 decreases, and as it becomes larger than I o , the excessive current
charges C f2 to make V o_2 increase and return to the equilibrium voltage. Therefore,
any control strategies intending to achieve ICS and IVS for input-parallel-connected
systems (including IPOP and IPOS) and input-series-connected systems (including
ISOP and ISOS), respectively, are stable.
2.2.2 Controlling at Output Side
Regardless of the type of connection at the output side, when OCS (for output-
parallel-connected systems) or OVS (for output-series-connected systems) is
achieved, each of the converter modules behaves as a constant power sink as seen
from the input side, as shown in Fig. 2.4, and the output powers of all modules are
equal, i.e.,
Vin_ j · Icin_ j Po j /η const ( j 1, 2, . . . , n) (2.12)
The relationship between the currents at the input side is
Icd_ j Iin_ j − Icin_ j ( j 1, 2, . . . , n) (2.13)
For the case where the input sides are connected in parallel, as shown in Fig. 2.4a,
the input voltages of all modules are equal, and the input currents are thus identical.
Hence, no perturbation occurs, i.e., the system is stable.
To examine the case where the input sides are connected in series, as shown in
Fig. 2.4b, we again consider perturbing the input filter capacitor voltages, the input
voltages of some modules, e.g., increasing V in_1 and decreasing V in_2 , while keeping
the input voltages of other modules unchanged. By virtue of constant power, I cin_1
will decrease and I cin_2 will increase, as illustrated in (2.13). According to (2.12) and
Iin Iin_1 Icin_1 Iin Iin_1 Icin_1

+ Icd_1 Constant + Icd_1 Constant
Vin_1 power sink Vin_1 power sink
Vin _ Cd1 _ Cd1
(Module 1) (Module 1)
Iin_2 Icin_2 Iin_2 Icin_2

Vin_2 power sink Vin_2 power sink
_ Cd2 (Module 2) Vin _ Cd2 (Module 2)
Iin_n Icin_n Iin_n Icin_n

+ Icd_n Constant + Icd_n Constant
Vin_n power sink Vin_n power sink
_ Cdn (Module n) _ Cdn (Module n)
(a) Input sides connected in parallel (b) Input sides connected in series
Fig. 2.4 Equivalent schematic diagram for the output side control strategies
(2.13), I cin_1 and I cd_1 can be shown to vary as given in Fig. 2.5. Suppose point A
is the equilibrium operating point when V in_1 is perturbed to increase, the operating
point moves to point B. At point B, I cin_1 is smaller than the system input current I in ,
and it can be derived from (2.13) that the input filter capacitor current I cd_1 is positive,
causing C d1 to be charged up and its voltage increased. Thus, a positive feedback
loop is formed and the operating point continues to move to the right and away from
point A. So, the equilibrium point cannot be resumed. Similarly, if I cin_2 is larger
than I in causing C d2 to be discharged by the unbalanced current, then V in_2 decreases
and fails to return to the equilibrium point. If the module employs a buck-derived
converter when V in_2 continues to decrease, it will not be high enough to provide
the desired voltage, and the output current thus decreases, resulting in unbalanced
output currents of the modules. Moreover, if the module employs a boost-derived
or buck/boost-derived converter, V in_2 will continue to decrease until it is zero and
provides no power to the load, again resulting in unbalanced output currents of
the modules. From the above analysis, we can conclude that any control strategies
intending to achieve OCS and OVS for ISOP and ISOS systems, respectively, are
unstable.
In addition to the above mentioned qualitative analysis, the tool of small-signal
model can be used to prove that any control strategies intending to achieve OCS and
OVS for ISOP and ISOS systems, respectively, are unstable.
Referring to Fig. 2.4b, each converter module presents constant power sink char-
acteristics as seen from the input side of power stage when OCS (for ISOP) or OVS
(for ISOS) is achieved, and the input impedance of each converter module can be
modeled as an equivalent negative resistance [1], i.e.,
Fig. 2.5 Currents and

Icin_1 ( Po = const)
voltage of the input side of
module 1
A Icd_1
Iin
B
0
Vin Vin_1
n
2
v̂in_ j Vin_ j Vin_ j
Rne j − − ( j 1, 2, . . . , n) (2.14)
î cin_ j Icin_ j Vin_ j · Icin_ j
At steady state, we have,
Vin_ j Icin_ j η Po /n ( j 1, 2, . . . , n) (2.15)
where Po is the output power of ISOP or ISOS system.

Combining (2.14) and (2.15), yields,
j ·η·n
2
v̂in_ j Vin_
Rne j − ( j 1, 2, . . . , n) (2.16)
î cin_ j Po
Figure 2.6 shows the small-signal model of input-series-connected systems

employing OVS/OCS control strategies by replacing each module in Fig. 2.4b with
a negative resistance Rnej (j 1, 2, …, n). The total input impedance of each module
at the input terminal is,
Rne j
Z j Rne j //(1/sCd j ) ( j 1, 2, . . . , n) (2.17)
1 + s Rne j Cd j
The individual input voltage perturbation caused by the system input voltage
perturbation v̂in can be expressed as
Zj
v̂in_ j · v̂in ( j 1, 2, . . . , n) (2.18)

n
Zm
m1
According to (2.18), the difference of input voltage perturbations between module

j and module k is
Z j − Zk
v̂ jk v̂in_ j − v̂in_k v̂in ( j, k 1, 2, . . . , n; j k) (2.19)
n
Zm
m1
Fig. 2.6 Small-signal model iîn iˆcin_1

of input-series-connected
systems employing Z1 +
OVS/OCS control strategies ˆvin_1 Rne1
_ Cd1
iˆcin_2
Z2 +
vˆ in_2 Rne2
vˆ in _ Cd2
iˆcin_n
+
Zn
Rnen
vˆ in_n C
_ dn
Equation (2.19) can also be expressed as the response in the difference of input
voltage perturbations of two modules due to perturbation in the system input voltage,
i.e.,
v̂ jk v̂in_ j − v̂in_k Z j − Zk

n ( j, k 1, 2, . . . , n; j k) (2.20)
v̂in v̂in
Zm
m1
For simplicity, letting n 2, substitution of (2.17) into (2.20), yields,
v̂12 (Rne1 − Rne2 ) + s Rne1 Rne2 (Cd2 − Cd1 )

(2.21)
v̂in (Rne1 + Rne2 ) + s Rne1 Rne2 (Cd2 + Cd1 )
At steady state, V in_1 V in_2 V in / 2, substitution the equation into (2.16), we

V 2η
get Rne1 Rne2 − 2Pin o , then (2.21) can be rewritten as
v̂12 s(Cd1 − Cd2 )Vin2 η

(2.22)
v̂in 4Po − s(Cd1 + Cd2 )Vin2 η
In practice, C d1 is impossible equal to C d2 precisely, it can be found from (2.22)

that the transfer function of v̂12 /v̂in has a right-half-plane pole, which implies
unstable operation. Therefore, any control strategies intending to achieve OCS and
OVS for ISOP and ISOS systems, respectively, are unstable, and the root cause is the
negative resistance characteristics of the module’s input impedance with the control
strategies to achieve OCS and OVS.
From the foregoing discussion, we can draw the following conclusions: (1) for the
input-parallel-connected systems, we can directly control efforts to achieve ICS that
will automatically ensure OCS and OVS for IPOP and IPOS systems, respectively.
Alternatively, we can directly control the output currents to achieve OCS for IPOP
systems, or directly control the output voltages to achieve OVS for IPOS systems,
(2) for the input-series-connected systems, we should control the input voltages to
achieve IVS, and OCS or OVS will be achieved automatically. Any attempt to control
the output currents or voltages to achieve OCS or OVS will not be successful because
the control strategy is inherently unstable.
2.3 General Control Strategy for DC–DC Series–Parallel

Power Conversion Systems
In the following analysis, buck-derived converters with PWM control are taken as
the basic modules (such as full-bridge converter, half-bridge converter, forward con-
verter). Regardless of the type of the connection architectures, at least two control
loops are needed, one is to regulate the system output voltage and the other is to con-
trol the sharing of input voltages/currents or output voltages/currents. Basically, the
two control loops are exercised by varying the duty cycles of the modules. However,
varying the duty cycles may affect both the output voltage of the system and the
sharing of the input/output voltages/currents of the modules. Thus, the two control
loops may be coupled, resulting in difficulties in the design of the loops. Here, we
wish to propose a control strategy that decouples the two control loops.
Referring to Fig. 2.1, and assuming the modules are buck-derived converters with
transformer’s turns ratio being one, for the j-th module, the relationship between the
input voltage vin_j and the output voltage vo_j is,
vin_ j · dy_ j vo_ j (2.23)
where d y_j is the duty cycle of the j-th module, and is composed of two components,
i.e.,
dy_ j dvo_ j + dsh_ j (2.24)
where d vo_j is produced by the system output voltage control loop and d sh_j is pro-
duced by the loop controlling the sharing of input voltages/currents or output volt-
ages/currents.
Perturbation and linearization of (2.23) leads to,

Vin_ j + v̂in_ j · Dy + d̂vo_ j + d̂sh_ j Vo_ j + v̂o_ j (2.25)
where Dy , V in_j , and V o_j are the quiescent values, and d̂vo_ j , d̂sh_ j , v̂in_ j and v̂o_ j are
the superimposed small AC perturbations.
Neglecting the second-order nonlinear terms and noting that the DC terms on both
sides of the equation are equal, we retain only the first-order AC terms on both sides
of the equation, i.e.,
2.3 General Control Strategy for DC–DC Series–Parallel Power … 41
Vin_ j d̂vo_ j + Vin_ j d̂sh_ j + Dy v̂in_ j v̂o_ j (2.26)
According to (2.26), we have,

n
n
n
n
Vin_ j d̂vo_ j + Vin_ j d̂sh_ j + Dy · v̂in_ j v̂o_ j (2.27)
j1 j1 j1 j1
For input-parallel-connected systems, V in_j V in , and for input-series-connected

system, V in_j V in /n. For output-parallel-connected systems, v̂o_ j v̂o , and for
output-series-connected systems, v̂o_ j v̂o /n. Hence, (2.27) can be rewritten as
Vin Vin
n n
m1 · d̂vo_ j + m 1 · d̂sh_ j + Dy · m 1 · v̂in m 2 · v̂o (2.28)
n j1 n j1
where m1 n and 1 for the input-parallel-connected and input-series-connected

systems, respectively, and m2 n and 1 for the output-parallel-connected and output-
series-connected systems, respectively.
If we have

n
d̂sh_ j 0 (2.29)
j1
Equation (2.28) can be rewritten as
Vin
n
m1 · d̂vo_ j + Dy · m 1 · v̂in m 2 · v̂o (2.30)
n j1
Equation (2.30) shows that if the sum of the duty cycle variations produced by
the sharing control loops is zero, the system output voltage is only influenced by
input voltage perturbation and the duty cycle perturbation produced by the system
output voltage control loop. That is to say, the loop that controls the sharing of
input voltages/currents or output voltages/currents has no effect on the system output
voltage control loop. Thus, if condition (2.29) is satisfied, the two control loops will
not interfere with each other. Despite this conclusion being drawn from a specific
derivation process for buck-derived converters, it is also applicable to boost-derived
or buck/boost-derived ones.
According to (2.29), we have,

n−1
d̂sh_n − d̂sh_ j (2.31)
j1
In practice, the duty cycle signal is produced by the intersection between the
output signal of the regulator and saw tooth signal V RAMP , i.e.,
v̂sh_EA j
d̂sh_ j ( j 1, 2, . . . , n) (2.32)
VRAMP
where v̂sh_EA j is the output perturbation signal of the regulator for controlling the
sharing of input voltages/currents or output voltages/currents.
Combining (2.31) and (2.32), we have,

n−1
v̂sh_EAn − v̂sh_EA j (2.33)
j1
According to (2.33), a general sharing control strategy for DC–DC series–paral-

lel power conversion systems is proposed, as shown in Fig. 2.7. The system output
voltage control loop ensures the desired system output voltage. vo_EA is the control
signal derived from the output voltage regulator, which is used to produce common
duty cycle signal d vo_j (j 1, 2, …, n) by intersecting with V RAMP . Input/output
variables sharing control loops achieve the equilibrium among the constituent mod-
ules. The control signal V sh_g represents the average value of the total input/output
voltages/currents, which needs to be shared among all the modules, and V sh_fj (j 1,
2, …, n) represents the sensed input or output variable of each module. For example,
for input-series-connected systems, V sh_g is V in /n, and V sh_fj is the module input
voltage. The representation of V sh_g and V sh_fj are shown in Table 2.2. Also, vsh_EAj
(j 1, 2, …, n − 1) represents the control signal derived from the sharing control
loop.
For the first n − 1 modules, vsh_EAj is sent to the inverting input of PWM com-
parator to obtain the duty cycle signal d sh_j , for the module n, the sum of the first
n − 1 vsh_EAj , which is denoted by vsh_EAn , is sent to the inverting input of PWM
comparator to obtain the duty cycle signal d sh_n . It can be found that the proposed
control strategy decouples the system output voltage regulating loop and input/output
variables sharing loops.
For the input-series-connected systems, the final duty cycle of module j is obtained
by subtracting d sh_j from d vo_j (j 1, 2, …, n), while for input-parallel-connected
systems, the final duty cycle of module j is the sum of d sh_j and d vo_j (j 1, 2, …,
n).
Table 2.2 Representation of V sh_fj and V sh_g in four architectures

Architecture V sh_fj (j 1, 2, …, n − 1) V sh_g
IPOP I cin_j or I co_j I in /n or I o /n
IPOS I cin_j or V o_j I in /n or V o /n
ISOP V in_j V in /n
ISOS V in_j V in /n
2.4 Modularization Architecture for DC–DC Series–Parallel Power … 43
_ Vsh_f1 Comparator 1
Vsh_g + /+
Gsh − Drive
+ RS Flip-flop
vsh_EA1 + circuit 1
VRAMP 1
Vsh_f2
_ Comparator 2
+ /+
Gsh − Drive
+ RS Flip-flop
vsh_EA2 + circuit 2
VRAMP 2
Vsh_f(n−1)
+ /+
Gsh − Drive
+ RS Flip-flop
vsh_EA(n−1) + circuit (n−1)
VRAMP (n−1)
Input/output variables
sharing control loops Comparator n
/+
− Drive
vsh_EAn RS Flip-flop
+ + circuit n
vo_EA VRAMP n
+
Voref Gvo
_
vof ISOP and ISOS
/+ + IPOP and IPOS
Output voltage loop
Fig. 2.7 General sharing control strategy for DC–DC series–parallel power conversion systems
2.4 Modularization Architecture for DC–DC

Series–Parallel Power Conversion Systems
Among all the four series–parallel architectures, only IPOP has been successfully
implemented in practice and commercially available in modular forms. In some pre-
vious designs of modular systems, e.g., those reported in [2–5], dedicated control
methods are used for the constituent modules and the entire systems are not separa-
ble into standardized modules. In this section, the modularization architectures are
proposed for IPOS, ISOP, and ISOS systems. The main features are: (a) the basic
converter module has its own power stage and controller, and can operate in stan-
dalone mode; (b) no external controller is needed to achieve sharing of input/output
voltages/currents; and (c) a relatively small number of wires are needed to connect
up the modules to form the entire system.
To achieve modularization, all power stages as well as controllers of all the mod-
ules should be identical. Hence, the sharing control signal vsh_EAn for the module n
can be simplified as

n−1
n−1

vsh_EAn − vsh_EA j − Vsh_g − Vsh_f j G sh
j1 j1

−G sh (n − 1)Vsh_g − (Vsh_f1 + · · · + Vsh_f(n−1) ) (2.34)
The average sharing control signal V sh_g is
Vsh_g (Vsh_f1 + Vsh_f2 + · · · + Vsh_f(n−1) + Vsh_fn )/n (2.35)
Substitution of (2.35) into (2.34), we have,

vsh_EAn −G sh (n − 1)Vsh_g − (n · Vsh_g − Vsh_fn ) G sh (Vsh_g − Vsh_fn ) (2.36)
Based on (2.36), the control strategy depicted earlier in Fig. 2.7 can be redeveloped
as shown in Fig. 2.8.
Since the individual modules can be operated in stand-alone mode, each of them
should have its own output voltage control loop. However, in practice, mismatches
_ Vsh_f1 Comparator 1
Vsh_g + /+
Gsh − Drive
+ RS Flip-flop
vsh_EA1 + circuit 1
VRAMP 1
_ Vsh_f2
/+ Comparator 2
+
Gsh − Drive
+ RS Flip-flop
vsh_EA2 + circuit 2
VRAMP 2
Input/output variables
sharing control loops
Vsh_f(n−1)
+ /+
Gsh − Drive
+ RS Flip-flop
+ circuit (n−1)
vsh_EA(n−1) VRAMP (n−1)
_ Vsh_fn Comparator n
+ /+
Gsh − Drive
vsh_EA(n) + RS Flip-flop
+ circuit n
VRAMP n
+ vo_EA
Gvo
Voref _ ISOP and ISOS
vof /+ + IPOP and IPOS
Output voltage loop
Fig. 2.8 Simplification of the general sharing control strategy for DC–DC series–parallel power
conversion systems
2.4 Modularization Architecture for DC–DC Series–Parallel Power … 45
in the voltage references and output voltage sampling factors of the modules are
inevitable. Thus, when the modules are connected to form a series–parallel power
conversion system, we need to employ signal diodes to ensure only one output voltage
control loop is active and regulates all the outputs of all modules. The final proposed
modularization architecture is shown in Fig. 2.9.
In Fig. 2.9, each dashed line block represents a self-contained module, which can
operate in standalone mode. Taking module 1 as the example, when it is standalone,
we have V sh_f1 V sh_g , i.e., vsh_EA1 is constant and the output voltage is regulated
by its own output voltage control loop. Only two buses, namely, the input/output
variables sharing bus and the common duty cycle bus, are needed when multiple
modules are connected in one of the series–parallel architectures, and no external
controller is required. It can be seen that the full modularization architecture for
DC–DC series–parallel power conversion systems have the following advantages:
(1) all modules are self-contained and standardized, (2) no extra control is needed to
achieve sharing of voltage and/or current at the input and output sides, and (3) easy
to expand system capacity.
Input/output ISOP and ISOS

variables sharing bus /+ + IPOP and IPOS
Vsh_g _ Vsh_f1 vsh_EA1

R Comparator 1
+ /+
Gsh − Drive
+ RS Flip-flop
+ + circuit 1
Gvo VRAMP 1
Voref _
vof Module 1
_ Vsh_f2 vsh_EA2 Comparator 2

R
+ /+
Gsh − Drive
+ RS Flip-flop
+ + circuit 2
Gvo VRAMP 2
Voref _
vof Module 2
Common duty cycle bus

_ Vsh_f(n-1) vsh_EA(n-1)
R Comparator (n−1)
+ /+
Gsh − Drive
+ RS Flip-flop
+ + circuit (n−1)
Gvo VRAMP (n−1)
Voref _
vof Module (n−1)
_ Vsh_fn -vsh_EA(n)
R Comparator n
+ /+
Gsh − Drive
+ RS Flip-flop
+ circuit n
+ Gvo
Voref _ VRAMP n
vof Module n
Fig. 2.9 Modularization architecture for DC–DC series–parallel power conversion systems
From Fig. 2.9, it can be seen that each module regulates its own output voltage
rather than system output voltage. For output-parallel-connected systems, the module
output voltage is also the system output voltage, which will be precisely regulated,
while for the output-series-connected systems, only one module output voltage is
precisely regulated and the other module are indirectly regulated, leading to not very
precise system output voltage.
It should be noted that for IPOS system, the output voltage sharing bus and the
common duty cycle bus are not mandatory because the system’s total output voltage
will be well regulated if individual module manage to regulate its own output voltage;
and for IPOP system, the common duty cycle bus is also unnecessary, and if it is
removed, the current sharing method is similar to that proposed in [6], in which
current-mode control is adopted as an inner current loop.
2.5 Experimental Verification
In order to verify the effectiveness of the proposed general control strategy, we have
constructed four DC–DC power conversion systems, i.e., IPOP, IPOS, ISOP, and
ISOS systems. Each system consists of three basic converter modules, as shown in
Fig. 2.10. The basic converter module is a phase-shifted full-bridge converter with
the following specifications:
• input voltage V in : 270 (±10%) Vdc;
• output voltage V o : 54 Vdc;
• rated output current I o : 20 A;
• switching frequency f s : 100 kHz.
The power stage consists of the following devices and components:
(1) switching device: IRFP460 (International Rectifier);
(2) clamping diodes: DSEI30-06 A (IXYS);
(3) rectifier diodes: APT60D30B (Advanced Power Technology);
(4) resonant inductance: 6 µH (Ferroxcube, E32/16/9, 8 turns);
(5) transformer: Ferroxcube, E42/21/20, primary winding is 15 turns, and secondary
winding is 4 turns × 2 (center-tap full-wave rectifier);
(6) output filter inductor: 30 µH (Ferroxcube, E42/21/15, 15 turns);
(7) output filter capacitor: 4400 µF (2200 µF/100 V × 2—electrolytic).
When the input sides and output sides of the three modules are connected in par-
allel, respectively, an IPOP system is constructed with the following specifications:
system input voltage 270 Vdc ± 10%, system output voltage 54 Vdc, system rated
output current 60 A (20 A × 3).
Figure 2.11 shows the experimental waveforms of the IPOP system corresponding
to a stepped load test and a stepped input voltage test. The individual output currents
are sensed to provide information for the output current sharing bus. Figure 2.11a
shows the output currents of the three modules and system’s output voltage (ac
2.5 Experimental Verification 47
Fig. 2.10 Prototype of DC–DC series–parallel power conversion systems consisting of three basic
modules
coupled) when the system load changes between full load (60 A) and half load
(30 A). We observe here that the output currents of the three modules are well
shared. Figure 2.11b shows the waveforms when the input voltage steps up and
down between 250 and 280 Vdc. Again we see that the output currents are well
shared both at steady state and during transient.
In order to verify that the OCS control is decoupled from the output voltage
control, we use two sets of control parameters. Figures 2.11c, d show the dynamic
responses with the same OCS control parameters but different output voltage control
parameters. It can be seen that the output voltage responses differ. Figures 2.11e,
f show the dynamic response with the same output voltage control parameters but
different OCS control parameters. It can be seen that the output voltage response
remains the same.
In the prototype, the module duty cycle will be regulated fiercely during transient
if the bandwidth of the OCS closed loop is high, which is easy to cause system
oscillation. Hence, the bandwidth of the OCS closed loop is set to be relatively low
in the prototype and the waveforms of output currents have little difference with
different OCS control parameters.
C2 Io:[30A/div] C1 Vin:[100V/div]
C2 M4 Io_1:[20A/div] C1 M3 Io_1:[20A/div]
C4 Io_2:[20A/div] C3 Io_2:[20A/div]
M4 M3
C3 Io_3:[20A/div] C3 C4 Io_3:[20A/div]
C4
C3 C4
C1 C1 Vo:[5V/div] C2 Vo:[5V/div]
C2
Time:[20ms/div] Time:[20ms/div]
(a) Response for stepped load (b) Response for stepped input voltage
C2 Io:[30A/div] C1Vin:[100V/div]
M4 Io_1:[20A/div] M3 Io_2:[20A/div]
C2 C1
M4 M3
C4 1# OCSR, C3 1# OCSR, 1# OCSR,
1# OCSR,
1# OVR 2# OVR 1# OVR 2# OVR
M1 M1 Vo:[5V/div] M2 M2 Vo:[5V/div]
C1 C1 Vo:[5V/div] C2 C2 Vo:[5V/div]
(c) Dynamic responses with same OCS (d) Dynamic responses with same OCS
parameters but different OVR parameters parameters but different OVR parameters
C2 Io:[30A/div] C1 Vin:[100V/div]
C2 M4 Io_1:[20A/div] C1 M3 Io_2:[20A/div]
M4 M3
C4 1# OCSR, 2# OCSR, C3 1# OCSR, 2# OCSR,
C1 C1 Vo:[5V/div] C2 C2 Vo:[5V/div]
(e) Dynamic responses with same OVR (f) Dynamic responses with same OVR
parameters but different OCSparameters parameters but different OCS parameters
Fig. 2.11 Experimental waveforms for IPOP system
If the three modules are connected in parallel at the input sides and in series at
the output sides, we have an IPOS system with the following specifications: system
input voltage 270 Vdc ± 10%, system output voltage 162 Vdc (54 Vdc × 3), system
rated output current 20 A.
C4 Vin:[100V/div]
C4 Io:[10A/div]
C1 Vo_1:[25V/div]
C4 C4
C1 Vo_1:[5V/div] C2 Vo_2:[25V/div]
C1
M3 Vo_3:[25V/div]
C2 C2 Vo_2:[5V/div] C1
M3 M3 Vo_3:[5V/div] C2
C3 Vo:[100V/div]
C3 C3 Vo:[10V/div] M3
Time:[20ms/div] C3 Time:[20ms/div]
Fig. 2.12 Experimental waveforms for IPOS system
Figure 2.12 shows the experimental waveforms of the IPOS system corresponding
to stepped load and stepped input voltage. The output voltage sharing bus and the
common duty cycle bus are removed in the prototype system. Figure 2.12a shows the
output voltages of the three modules (AC coupled) corresponding to a load stepping
between full load (20 A) and half load (10 A), and Fig. 2.12b shows the waveforms
of individual output voltages and the system’s total output voltage corresponding to
an input voltage stepping between 250 and 280 Vdc. It can be seen that the output
voltages are well shared both at steady state and during transient and the system’s
output voltage is also well regulated.
If the three modules are connected in series at the input sides and in parallel at
the output sides, we have an ISOP system with the following specifications: system
input voltage 810 Vdc ± 10% (270 Vdc × 3), system output voltage 54 V, system
rated output current 60 A (20 A × 3).
Figure 2.13 shows the experimental waveforms of the ISOP system corresponding
to stepped load and stepped input voltage. Figure 2.13a shows the input voltages of
the three modules and the system’s output voltage (AC coupled) corresponding to
a load stepping between full load (60 A) and half load (30 A). Here, it is verified
that the input voltages of the three modules are well shared. Figure 2.13b shows the
waveforms corresponding to an input voltage stepping between 740 and 840 V. It can
be seen that input voltages are well shared both at steady state and during transient,
and the sharing of the output current is achieved automatically. In order to verify
that the IVS control is decoupled from the output voltage control, we use two sets of
control parameters. Figures 2.13c, d show the dynamic responses with the same IVS
control parameters but different output voltage control parameters. It can be seen that
the output voltage responses differ. Figures 2.13e, f show the dynamic response with
the same output voltage control parameters but different IVS control parameters. It
can be seen that the output voltage response remains the same. Similarly, the module
duty cycle will be regulated violently during transient if the bandwidth of the IVS
closed loop is high, which is easy to cause system oscillation. Hence, the bandwidth
C4 Vin:[500V/div]
C4 Io:[30A/div]
C4
C1Vin_1:[200V/div]
C1 Vin_1:[200V/div]
C4
C2Vin_2:[200V/div]
C2 Vin_2:[200V/div]
C1 C1
M3Vin_3:[200V/div]
M3Vin_3:[200V/div]
C2 C2
M3 M3
C3 C3Vo:[5V/div] C3 C3 Vo:[5V/div]
C4 Vin:[500V/div]
C4 Io:[30A/div]
C4
M1 Vin_1:[200V/div] M2 Vin_2:[200V/div]
C4
C1 Vin_1:[200V/div] C2 Vin_2:[200V/div]
M1 M2
C1 1# IVSR, 1# IVSR, C2 1# IVSR, 1# IVSR,

C3 Vo:[5V/div] C3 Vo:[5V/div]
C3 C3
(c) Dynamic responses with same IVS (d) Dynamic responses with same IVS
C4 Vin:[500V/div]
C4 Io:[30A/div]
C4
M1 Vin_1:[200V/div] M2 Vin_2:[200V/div]
C4
C1Vin_1:[200V/div] C2 Vin_2:[200V/div]
M1 M2
C1 1# IVSR, 2# IVSR, C2 1# IVSR,

1# OVR 1# OVR 2# IVSR,
1# OVR 1# OVR
C3 C3 Vo:[5V/div] C3 Vo:[5V/div]
C3
parameters but different IVSparameters parameters but different IVSparameters
Fig. 2.13 Experimental waveforms for the ISOP system
of the IVS closed loop is set to be relatively low in the prototype and the waveforms
of input voltages have little difference with different IVS control parameters.
When the input sides and output sides of the three modules are connected in series
respectively, we have the ISOS system with the following specifications: system input
voltage 810 Vdc ± 10% (270 Vdc × 3), system output voltage 162 Vdc (54 Vdc ×
3), system rated output current 20 A.
Figure 2.14 shows the experimental waveforms of the ISOS system corresponding
to stepped load and stepped input voltage. Figures 2.14a, b show the input voltage
of the three modules and the system output voltage corresponding to a load stepping
between full load (20 A) and half load (10 A) and an input voltage stepping between
740 and 840 Vdc, respectively. It can be seen that input voltages are shared both
at steady state and during transient, and sharing of the output voltage is achieved
automatically. In order to verify that the IVS control is decoupled from the output
voltage control, we use two sets of control parameters. Figures 2.14c, d show
the dynamic responses with the same IVS control parameters but different output
voltage control parameters. It can be seen that the output voltage responses differ.
Figures 2.14e, f show the dynamic response with the same output voltage control
parameters but different IVS control parameters. It can be seen that the output
voltage response remains the same.
2.6 Summary
This chapter systematically analyzed the inherent relationships between the sharing
of input voltages/currents and the sharing of output voltages/currents of the DC–DC
series–parallel power conversion systems from the view of power conservation. It is
pointed out that the sharing of input voltages/currents ensures the sharing of output
voltages/currents and vice versa. For input-parallel-connected systems, the control
strategies intending to achieve ICS or OCS (for IPOP) or OVS (for IPOS) can be
used, however; the control strategies intending to achieve OCS (for ISOP) or OVS
(for ISOS) for input-series-connected systems are unstable, and only the control
strategies intending to achieve IVS can be adopted.
A general control strategy was proposed for DC–DC series–parallel power conver-
sion systems, which not only achieves equilibrium between the constituent modules
but also decouples the output voltage control loop and the sharing control loop. Fur-
thermore, modularization architecture for DC–DC series–parallel power conversion
systems was proposed, achieving full modularization where all modules are self-
contained and standardized, and no extra control is needed to achieve sharing of
voltage and/or current at the input and output sides.
A prototype of DC–DC series–parallel power conversion systems consisting of
three converter modules provided experimental results to verify the general control
strategy and modularization architectures.
C4 Vin:[500V/div]
C4 Io:[10A/div]
C4
C4
C1 C1
M3 Vin_3:[200V/div] M3Vin_3:[200V/div]
C2 C2
M3 M3
C3Vo:[100V/div]
C3 Vo:[10V/div]
C3
Time:[20ms/div] C3 Time:[20ms/div]
C4 Vin:[500V/div]
C4 Io:[10A/div]
C4
C4
M1 M1

M3 M3 Vo:[10V/div] M3 Vo:[10V/div]
M3
C3 Vo:[10V/div] C3 Vo:[10V/div]
C3 C3
(c) Dynamic responses with same IVS (d) Dynamic responses with same IVS
C4 Vin:[500V/div]
C4 Io:[10A/div]
C4
C4
C1 Vin_1:[200V/div] C1Vin_2:[200V/div]
M1 M1

M3Vo:[10V/div] M3 M3 Vo:[10V/div]
M3
C3Vo:[10V/div] C3 C3 Vo:[10V/div]
C3
parameters but different IVS parameters parameters but different IVS parameters
Fig. 2.14 Experimental waveforms for ISOS system

References 53
References
1. Erickson, R., Maksimovic, D.: Fundmental of Power Electronics. Klurwer Academic, New York
(2001)
2. Kim, J., Choi, H., Cho, B.H.: A novel droop method for converter parallel operation. IEEE Trans.
Power Electron. 17(1), 25–32 (2002)
3. Ayyanar, R., Giri, R., Mohan, N.: Active input-voltage and load-current sharing in input-series
and output-parallel connected modular DC-DC converters using dynamic input-voltage refer-
ence scheme. IEEE Trans. Power Electron. 19(6), 1462–1472 (2004)
4. Ruan, X., Chen, W., Cheng, L., Tse, C.K., Yan, H., Zhang, T.: Control strategy for input-series-
output-parallel converters. IEEE Trans. Ind. Electron. 56(4), 1174–1185 (2009)
5. Giri, R., Ayyanar, R., Ledezma, E.: Input-series and output-series connected modular DC-DC
converters with active input voltage and output voltage sharing. In: Proceedings of the IEEE
Applied Power Electronics Conference and Exposition, pp. 1751–1756 (2004)
6. Lin, C., Chen, C.: Single-wire current share paralleling of current mode-controlled dc power
supplies. IEEE Trans. Ind. Electron. 47(4), 780–786 (2000)
Chapter 3
Mathematical Model and Closed-Loop
Parameters Design for DC–DC ISOP
System
Abstract This chapter derives the small-signal model of the phase-shifted full-
bridge (PSFB)-based ISOP system, and based on the small-signal model, the general
control strategy proposed in Chap. 2 is proved to be decoupled into n − 1 input voltage
sharing (IVS) closed loops and one output voltage closed loop. The parameters design
of the IVS control loop regulator and output voltage control loop regulator for a two-
module PSFB ISOP system is discussed and verified by the prototype. When the
inner current loop is introduced into the general control strategy, the stability of the
ISOP system with/without the IVS control loops is discussed and the root cause of
system instability is also revealed. Furthermore, the design criteria of the IVS control
loop regulator to keep ISOP system stable are derived.
Keywords Small-signal model · Phase-shifted full-bridge converter

Input voltage sharing · Parameter design · Inner current loop · Stability
In Chap. 2, a general control strategy was proposed for DC–DC series–parallel power
conversion systems, which not only achieves equilibrium between the constituent
modules but also decouples the output voltage control loop and the sharing control
loop. In this chapter, the small-signal model of ISOP system consisting of multiple
phase-shifted full-bridge (PSFB) converters is derived to prove the decoupling of
the system output voltage control loop and IVS control loop, and the design of
the parameters of the two control loops is given. Furthermore, in order to improve
the system dynamic response and realize output current short-circuit protection, the
inner current loop is incorporated into the general control strategy, and the parameters
design of the IVS control loop will be analyzed.
56 3 Mathematical Model and Closed-Loop Parameters Design …
3.1 Small-Signal Model of PSFB-Based ISOP System
3.1.1 Small-Signal Model of PSFB Converter
The circuit configuration of the full-bridge converter is shown in Fig. 3.1, where Q1
~ Q4 (including their body diodes D1 ~ D4 and their intrinsic capacitors C 1 ~ C 4 ) are
four power switches, T r is the high-frequency isolation transformer with primary-
and-secondary-winding ratio K, L r is the resonant inductor, DR1 and DR2 are two
output rectifier diodes, L f is the output filter inductor, C f is the output filter capacitor,
and RLd is the load. Figure 3.2 shows the key waveforms of the PSFB converter [1],
where the switching process is ignored for simplicity. During [t 0 , t 1 ], Q1 and Q2 are
conducting and the primary current ip is flowing through them in freewheeling state.
In the secondary side, DR2 is conducting and the rectified voltage vrect is zero. At
t 1 , Q2 is turned off and Q4 is turned on, then Q1 and Q4 conduct, and vAB is equal
to V in . Both the primary and secondary winding currents decay and the secondary
winding current is lower than the output filter inductor current, thus both DR1 and
DR2 conduct, setting both the primary and secondary winding voltages to zero. The
input voltage V in is applied on the resonant inductor L r , forcing ip to increase linearly.
At t 2 , ip increases to the value of the output filter inductor current iLf reflected to
the primary side, i.e., ip iLf /K. The rectifier diode DR2 turns off and DR1 continues
conducting, vrect rises to the value of input voltage reflected to the secondary side,
i.e., vrect V in /K, both ip and iLf increase linearly. At t 3 , Q1 is turned off and Q3 is
turned on, ip is in freewheeling stage and vrect 0, starting the second half-switching
period.
As shown in Fig. 3.2, during [t 1 , t 2 ], the primary current ip increases from −I 2 to
I 1 , the rectified voltage vrect is zero although vAB = V in . This means that the secondary
side loses the input voltage reflected to the secondary during [t 1 , t 2 ]; in other words,
the secondary effective duty cycle Deff is smaller than the primary duty cycle Dy [2].
Deff can be expressed as
Deff Dy − Dloss (3.1)
DR1 Lf
RLd
Tr +
+
Q1 C1 Tr Q2 C2 * vrect iLf Vo
D1 Lr D2 _ Cf _
A B
*
ip *
Vin
Q3 Q4
D 3 C3 D 4 C4 DR2
Fig. 3.1 Full-bridge converter

3.1 Small-Signal Model of PSFB-Based ISOP System 57
where Dloss is the secondary duty cycle loss.

According to Fig. 3.2, we have [3]
t2 − t1 I1 + I2
Dloss (3.2)
Ts /2 Vin 1
·
L r 2 fs
where T s is the switching period and f s 1/T s is the switching frequency.

Referring to Fig. 3.2, the primary current ip at t 2 is

1 I
I1 Io − (3.3)
K 2
where I o is the output current and I is the ripple current of the output filter inductor
current.
At t 4 , the primary current ip is equal to I 2 and it can be expressed as

1 I 1 − Dy
I2 Io + − Vo (3.4)
K 2 2 fs L f
Substitution of (3.3) and (3.4) into (3.2) yields

1 1 − Dy
Dloss 2Io − Vo (3.5)
Vin 1 2 fs L f
K
L r 2 fs
vAB I2
I1
ip
Vin
0 t
Vin
I2
DyTs/2
DeffTs/2
vrect
Vin/K
0 t
I
iLf
Io
0 t
t0 t1 t2 t3 t4 t5 t6
Fig. 3.2 Key waveforms of the PSFB converter

Due to the fact that the PSFB converter is a buck-derived topology, its secondary
effective duty cycle d eff is the summation of steady-state component Deff and transient
component d̂eff , i.e.,
deff Deff + d̂eff (3.6)
The transformer secondary rectified voltage vrect depends not only on the primary
duty cycle Dy but also on the resonant inductor L r , the switching frequency f s ,
output filter inductor current iLf , and the input voltage V in . Therefore, the small-
signal transfer functions of the converter will depend on L r , f s , and the perturbations
of the output filter inductor current î Lf , input voltage, v̂in , and the primary duty cycle
d̂y . To accurately model the dynamic behavior of the PSFB converter, it is necessary
to find out the contributions of L r , f s , v̂in , î Lf , and d̂y to d̂eff . These effects can be
incorporated in the small-signal model of buck converter to obtain the model of the
PSFB converter.
3.1.1.1 Effect of the Change of the Output Filter Inductor Current

on Duty Cycle Modulation
Figure 3.3 shows the key waveforms of the PSFB converter when the output filter
inductor current iLf is perturbed, where the solid lines represent the steady-state
operation and the dashed line represents the primary current caused by an increase
of iLf by the amount î Lf . The perturbed primary current will reach the reflected filter
inductor current at a later time than it would in the steady-state operation, and the
additional delay time t can be expressed as
î Lf L r
t 2 (3.7)
K Vin
Then, the change of d eff due to î Lf , denoted as d̂i , is

t 4L r f s
d̂i − − î Lf (3.8)
Ts /2 K Vin
The negative sign in (3.8) represents that there will be a reduction in d eff if the
output filter inductor current is increased. It should be noted that the primary duty
cycle keeps unchanged in the perturbation.
3.1.1.2 Effect of the Change of the Input Voltage on Duty Cycle

Modulation
Figure 3.4 shows the key waveforms of the PSFB converter when the input voltage V in
is perturbed, where the solid lines represent the steady-state operation and the dashed
Fig. 3.3 Duty cycle modulation due to the change of the output filter inductor current
Fig. 3.4 Duty cycle

modulation due to the
change of input voltage
line represents the primary current caused by an increase of V in by the amount v̂in . The
perturbed primary current will reach the reflected filter inductor current sooner than
it would in the steady-state operation, and the shortened time t can be expressed as

1 1 − Dy Lr Lr
t 2Io − Vo −
K 2 fs L f Vin Vin + v̂in

1 1 − Dy Lr
2Io − Vo v̂in
K 2 fs L f Vin (Vin + v̂in )

1 1 − Dy Lr
≈ 2Io − Vo v̂in (3.9)
K 2 fs L f Vin2
Then, the change of d eff due to v̂in , denoted as d̂v , is

t 1 − Dy 4L r f s
d̂v Io − Vo v̂in (3.10)
Ts /2 4 fs L f K Vin2
In practice, a relatively larger output filter inductance is usually used to reduce

its current ripple; moreover, the primary duty cycle Dy is always made as large as
possible to minimize the conduction loss caused by the circulating current in the
primary side. Therefore, the second term in the bracket of (3.10) is much less than
I o and (3.10) can be simplified as [2]
4L r f s Io
d̂v v̂in (3.11)
K Vin2
Vin 1
The output current I o can be expressed as Io Deff and (3.11) can be
K RLd
rewritten as
4L r f s Deff
d̂v v̂in (3.12)
K 2 Vin RLd
Equation (3.12) indicates that the effect of v̂in on d eff can be interpreted as an
additional feed-forward of input voltage.
The results of the previous analysis can be incorporated in the small-signal model
of the buck converter, as shown in Fig. 3.5. The small-signal model of the PSFB
converter can be derived by replacing d̂y in Fig. 3.5 by d̂eff , and d̂eff d̂y + d̂i + d̂v ,
as shown in Fig. 3.6. The contribution of d̂i and d̂v is represented by two controlled
sources and the contribution of d̂v by two independent sources. This is to emphasize
that d̂i and d̂v originate from the circuit itself (i.e., î Lf and v̂in ) and are not controlled
by the controller. It can be found that if L r 0, we have d̂i 0 and d̂v 0 according
to (3.8) and (3.12), and if K = 1, the small-signal model of the PSFB converter is
equivalent to that of the buck converter; in other words, the buck converter is a
special case of the PSFB converter.
Fig. 3.5 Small-signal model ˆ

of the buck converter 1: Deff Vin d y Lf
RLd
+
+
_
+ * * Vin dˆy Rcf
_ v̂o
v̂in RLd
Cf
_
Fig. 3.6 Small-signal model of the PSFB converter
3.1.2 Small-Signal Model of the PSFB-Based ISOP System
The circuit architecture of the PSFB-based ISOP system is shown in Fig. 3.7, which
consists of n PSFB converters connected in series at the input sides and in parallel at
the output sides. At steady state, the input voltage and output current of each PSFB
converter are V in /n and I o /n, respectively; thus, the load resistor of each converter is
nRLd . Using the small-signal model of the PSFB converter, the small-signal model
of the PSFB converter in ISOP system can be derived, as shown in Fig. 3.8.
As shown in Fig. 3.8, we have the following equation:,
Vin /n Vin
Ieq 2 (3.13.1)
K · (n RLd ) n K RLd
4L r f s 4n L r f s
d̂i j − î Lf j − î Lf j ( j 1, 2, . . . , n) (3.13.2)
K (Vin /n) K Vin
4L r Deff f s 4L r Deff f s
d̂v j 2 v̂in j 2 v̂in j ( j 1, 2, . . . , n) (3.13.3)
K (Vin /n) · (n RLd ) K Vin RLd
where j represents module j and all the resonant inductors and turns ratios are assumed
to be identical, respectively, i.e., L r1 L r2 ··· L rn L r , and K 1 K 2 ··· K n
K.
Using the small-signal model of the PSFB converter shown in Fig. 3.8, the small-
signal mode of the PSFB-based ISOP system can be obtained, as shown in Fig. 3.9.
iin1 Lf1
Iin RLd
Tr1 +
icd1 +
Lr1 Tr1 * vrect1 iLf1 Vo
+ _ Cf _
vin1 B1
_ C A1
*
d1
ip1 *
Vin iinn
Lfn
Trn
icdn +
Lrn Trn * vrectn iLfn
+ _
vinn Bn
_ C An
*
dn
ipn *
Fig. 3.7 Circuit architecture of the PSFB-based ISOP system
Vin ˆ Vin ˆ
nK
d yj
nK
(
dij + dˆ vj ) Lf
1: Deff /K iˆLfj nRLd
+
* * Rcf
vînj (
I eq dîj + dˆ vj ) I eq dˆyj v̂o
Cf
_
Fig. 3.8 Small-signal model of the PSFB converter in ISOP system
According to Fig. 3.9, we have

⎧
⎪
⎪ D V
⎪ eff v̂in1 + in d̂i1 + d̂v1 + d̂y1 s L f · î Lf1 + v̂o
⎪ (3.14.1)
⎪
⎪
⎪ K
⎪
nK
⎪
⎪
⎪ D Vin
⎨ eff
v̂in2 + d̂i2 + d̂v2 + d̂y2 s L f · î Lf2 + v̂o (3.14.2)
K nK
⎪
⎪
⎪
⎪
.. ..
⎪
⎪ . .
⎪
⎪
⎪
⎪ D V
⎪
⎩
eff
v̂inn +
in
d̂in + d̂vn + d̂yn s L f · î Lfn + v̂o (3.14.n)
K nK
Vin ˆ V
1: Deff /K nK
d y1 in dˆ + dˆ
nK
i1 v1 ( ) iˆLf1 Lf1 RLd
+
+
v̂in1
_ Cd1
* *
(
I eq dî1 + dˆ v1 ) I eq dˆy1
Rcf v̂o
Cf
_
1: Deff /K
Vin ˆ Vin ˆ ˆ
nK
d y2
nK
di2 + d v2 ( ) iˆLf2 Lf2
v̂in
v̂in2
_ Cd2
* *
(
I eq dî2 + dˆ v2 ) I eq dˆy2
……
Vin ˆ Vin ˆ ˆ
nK
d yn
nK
din + d vn ( ) Lfn
1: Deff /K iˆLfn
+
vînn
_ Cdn
* *
(
I eq dîn + dˆ vn ) I eq dˆyn
Fig. 3.9 Small-signal model of the PSFB-based ISOP system

⎧
⎪
⎪ K
⎪
⎪ î in − sC d in1
v̂ Ieq d̂y1 + d̂i1 + d̂v1 + î Lf1 (3.15.1)
⎪
⎪ Deff
⎪
⎪
⎪
⎪
⎪ K
⎨ î in − sCd v̂in2 Ieq d̂y2 + d̂i2 + d̂v2 + î Lf2 (3.15.2)
Deff
⎪
⎪
⎪
⎪ .. ..
⎪
⎪ . .
⎪
⎪
⎪
⎪
⎪ K
⎩ î in − sCd v̂inn Ieq d̂yn + d̂in + d̂vn + î Lfn (3.15.n)
Deff
n
v̂in j v̂in (3.16)
j1

n
v̂o
î Lf j (3.17)
1
j1 + Rcf //RLd
sCf
It should be noted that in the above equations we made the following assuming:
(1) L f1 L f2 … L fn L f , and (2) C d1 C d2 … C dn C d .
The transfer functions and output impedance of the PSFB-based ISOP system can
be derived with the aforementioned equations.
3.1.2.1 Control-to-Output Transfer Function
First, we consider the control-to-output transfer function of module j, and set v̂in 0,
and d̂yk 0 (k = 1, 2, …, n, and k j). Then, adding up all the equations in (3.14)
and combining (3.13.2), (3.13.3), (3.16), and (3.17), we obtain

v̂o
G vd j (s) v̂in 0
d̂y j
d̂ yk 0 (k1,2,...,n, k j)
Vin
(1 + sCf Rcf )
nK
Rcf Lf Rcf Rp
s 2 L f Cf 1 + +s + Rp C f 1 + + nCf Rcf + +n
RLd RLd RLd RLd
G vd (s) ( j 1, 2, . . . , n) (3.18)
where Rp 4L r f s /K 2 .
3.1.2.2 Control-to-Module-Input Transfer Function
To obtain the control-to-module-input transfer function, we first subtract (3.14.2)

from (3.14.1) to obtain

Deff Rp Vin
1+ v̂in1 − v̂in2 + d̂y1 − d̂y2 s L f + Rp î Lf1 − î Lf2
K n RLd nK
(3.19)
Moreover, subtracting (3.15.2) from (3.15.1) gives

Rp Vin
− 1 î Lf1 − î Lf2 2 d̂y1 − d̂y2
n RLd n K RLd

Rp Deff s K Cd
+ 2 2
+ v̂in1 − v̂in2
n K RLd Deff (3.20)
Putting (3.20) into (3.19) yields

v̂in2 − v̂in1 A(s) d̂y2 − d̂y1 (3.21)
2
Deff n RLd Vin + s L f RLd Vin
where A(s) − 2 2 2 2 2
.
n Deff RLd + s Deff L f Rp + n 2 K 2 Cd RLd s Rp + s 2 L f
Likewise, we can obtain

v̂in( j+1) − v̂in j A(s) d̂y( j+1) − d̂y j ( j 1, 2, . . . , n − 1) (3.22)
From (3.22), we can derive

v̂in j v̂in1 − A(s) d̂y1 − d̂y j ( j 1, 2, . . . , n) (3.23)
Letting v̂in 0 and substituting (3.23) into (3.16), we obtain
A(s)
n
v̂in1 A(s)d̂y1 − d̂y j (3.24)
n j1
Substitution of (3.24) into (3.23) yields
A(s)
n
v̂in j A(s)d̂y j − d̂y j ( j 1, 2, . . . , n) (3.25)
n j1
Equation (3.25) can be rewritten in the following matrix form:

⎡ ⎤⎡ ⎤
⎡ ⎤
v̂in1 A(s)(n−1)
− A(s)
. . . − A(s)
d̂
⎢ n n n ⎥⎢ y1
⎥
⎢ ⎥ ⎢ A(s) ⎥⎢ ⎥
⎢ v̂in2 ⎥ ⎢ − A(s) A(s)(n−1)
. . . − ⎥ ⎢ d̂ ⎥
⎢ ⎥ ⎢ n n n ⎥⎢ y2 ⎥
⎢ . ⎥ ⎢ ⎥⎢ ⎥ (3.26)
⎢ . ⎥ ⎢ .. .. .. .. ⎥⎢ .. ⎥
⎣ . ⎦ ⎢ . . . . ⎥⎢ . ⎥
⎣ ⎦⎣ ⎦
v̂inn v̂ 0 − A(s) − A(s) . . . A(s)(n−1) d̂yn
in n n n
3.1.2.3 Input-Voltage-to-Output-Voltage Transfer Function
To find the input-voltage-to-output-voltage transfer function, we let d̂y j 0 (j = 1, 2,

…, n). Then, adding up all the equations in (3.14) and combining (3.13.2), (3.13.3),
(3.16), and (3.17), we can obtain

v̂o
G vg (s)
v̂in d̂y j 0 ( j1,2,...,n)

Deff Rp
1+ (1 + sCf Rcf )
K n RLd

Rcf Lf Rcf Rp
RLd RLd RLd RLd
(3.27)
Fig. 3.10 Small-signal n

model representing the
variation of output current
∑ iˆ
j =1
Lfj
RLd
PSFB- +
Rcf
based
v̂o iô
ISOP _
System Cf
3.1.2.4 System-Input-to-Module-Input Transfer Function
We let d̂y j 0 (j = 1, 2, …, n) and use (3.23) to obtain
v̂in1 v̂in2 · · · v̂inn (3.28)
Substitution of (3.28) into (3.16) yields
v̂in1 v̂in2 · · · v̂inn v̂in /n (3.29)
which can be rewritten as

v̂in j 1
G vin jg (s) G ving (s) ( j 1, 2, . . . , n) (3.30)
v̂in d̂y j 0 ( j1,2,...,n) n
3.1.2.5 System’s Output Impedance
The output impedance of the system can be readily found in Fig. 3.10. First, we
observe that

n
v̂o
î Lf j + î o (3.31)
1
j 1 + Rcf //RLd
sCf
We let v̂in 0 and d̂y j 0 (j = 1, 2, …, n). Then, adding up all the equations in
(3.14) and using (3.13.2), (3.13.3), (3.16), and (3.31) to obtain

v̂o
Z out (s) v̂in 0
î o d̂y j 0 ( j1,2,..., n)
(3.32)
s L f + Rp (1 + sCf Rcf )

Rcf Lf Rcf Rp
RLd RLd RLd RLd
3.1.2.6 Output-Current-to-Module-Input Transfer Function
Putting v̂in 0 and d̂y j 0 (j = 1, 2, …, n) into (3.26), we can readily see that all
the divided capacitor voltages are unrelated to the output current, i.e.,

v̂in j
G vin j io (s) v̂in 0 0 (3.33)
î o d̂y j 0 ( j1,2,...,n)
3.2 Decoupling the Control Loops of the PSFB-Based ISOP

System
In Chap. 2, a general control strategy was proposed for DC–DC series–parallel power
conversion systems. Thus, the control strategy for PSFB-based ISOP system can be
obtained, as shown in Fig. 3.11, which consists of n − 1 IVS control loops and
a common output voltage control loop. Gvcd and Gvo are the transfer functions of
the input voltages sharing regulator (IVSR) and output voltage regulator (OVR),
respectively, and vo_EA is the output signal of the OVR and vin_EAj (j = 1, 2, …, n−1)
is the output signal of each IVSR. V RAMPj is the sawtooth signal and its amplitude is
V pp . For the first n − 1 modules, vin_EAj is subtracted from vo_EA and then compares
with V RAMPj to obtain the duty cycle of module j. For module n, the sum of the first
n − 1 vin_EAj and vo_EA compares with V RAMPj to obtain its duty cycle.
According to (3.18) and (3.26), we can obtain
⎡ ⎤ ⎡ ⎤
v̂in1_d
⎢ ⎥ ⎢
d̂y1
⎥
⎢ v̂in2_d ⎥ ⎢ ⎥
⎢ ⎥ ⎢
⎢ ⎥ d̂ y2 ⎥
⎢ .. ⎥ H⎢ ⎢
⎥
⎥ (3.34)
⎢ . ⎥ ⎢ .. ⎥
⎢ ⎥ ⎢ ⎥
⎢ v̂in(n−1)_d ⎥ ⎣ . ⎦
⎣ ⎦
v̂ d̂yn
o_d
where v̂in j_d denotes the variations resulted from d̂y j (j = 1, 2, …, n), and H is
⎡ ⎤
A(s)(n−1)
− A(s)
. . . − A(s)
− A(s)
⎢ n n n n
⎥
⎢ A(s) ⎥
⎢ − A(s) A(s)(n−1)
. . . − A(s)
− ⎥
⎢ n n n n ⎥
⎢ .. ⎥
H ⎢ .. .. .. .. ⎥.
⎢ . . . . . ⎥
⎢ ⎥
⎢ − A(s) − A(s) . . . A(s)(n−1) − A(s) ⎥
⎣ n n n n ⎦
G vd (s) G vd (s) . . . G vd (s) G vd (s)
_ v Comparator 1
+
in1
vin_EA1 _
Gvcd − Drive
Vin/n + RS Flip-flop
+ circuit 1
VRAMP 1
_ v Comparator 2
+
in2
vin_EA2 _
Gvcd − Drive
+ circuit 2
VRAMP 2
_ v
in(n−1) _ Comparator (n−1)
+
Gvcd − Drive
IVSR + circuit (n−1)
VRAMP (n−1)
vin_EA(n−1)
+ Comparator n
+ +
− Drive
+ + RS Flip-flop
+ circuit n
+ VRAMP n
_ Gvo vo_EA
Voref
vof
Fig. 3.11 Control strategy of the PSFB-based ISOP system
According to Fig. 3.11 and from (3.18), (3.27), (3.30), (3.32), and (3.34), we can
develop the block diagram shown in Fig. 3.12, where 1/V pp is the transfer function
of PWM modulator, and K vc and K vo are the sensor gains of input voltage and output
voltage, respectively.
Denoting the output signals of n − 1 IVSRs and OVR as x̂1 , x̂2 , …, x̂n , respectively,
as shown in Fig. 3.12, we have
⎡ ⎤
d̂y1 ⎡ ⎤⎡ x̂ ⎤
⎢ ⎥ −1 0 0 · · · 0 1 1
⎢ ⎥
⎢ d̂y2 ⎥ ⎢ 0 −1 0 · · · 0 1 ⎥⎢ ⎢ x̂
⎥
⎥
⎢ ⎥ ⎢ ⎥⎢ 2
⎥
⎢ ⎥ 1 ⎢ ⎥ ⎢ .. ⎥
⎢ .. ⎥ ⎢. . . . . . ⎥
⎢ . ⎥ V ⎢ .. .. .. .. .. .. ⎥⎢ . ⎥ (3.35)
⎢ ⎥ pp ⎢ ⎥⎢⎢
⎥
⎥
⎢ ⎥ ⎣ 0 0 0 · · · −1 1 ⎦⎣ x̂n−1 ⎦
⎢ d̂y(n−1) ⎥
⎣ ⎦ 1 1 1 ··· 1 1 x̂n
d̂yn
Substituting (3.35) into (3.34) yields

3.2 Decoupling the Control Loops of the PSFB-Based ISOP System 69
vîn(n -1)f
Kvc
v̂in2f
Kvc
v̂in1f
Kvc
_ _ d̂ y1 v̂in1
+ Gvcd(s)
x̂1
1/Vpp + +
+ v̂in1_d
_ _ d̂ y2 v̂in2
+ Gvcd(s)
x̂2
1/Vpp + +
+ v̂in2_d
_ _ dˆy( n −1) vîn ( n −1)
+ Gvcd(s)
xˆn −1
1/Vpp H + +
+ vîn(n -1)_d
Kvc/n Gving(s)
+ +
+ dˆyn Gvg(s)
v̂in 1/Vpp
+ xˆn + + ++
Gvo(s) Zout(s) iô
v̂oref _ v̂o_d +
v̂of
Kvo v̂o
Fig. 3.12 Block diagram of the control strategy for PSFB-based ISOP system
⎡ ⎤ ⎡ ⎤⎡ ⎤
v̂in1_d −A(s) 0 0 ··· 0 0 x̂1
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢ v̂in2_d ⎥ ⎢ 0 −A(s) ··· 0 0 ⎥⎢ x̂2 ⎥
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢ ⎥ 1 ⎢ . ⎥⎢ . ⎥
⎢ .. ⎥ ⎢ .. .. .. .. .. .. ⎥ ⎢ . ⎥ (3.36)
⎢ ⎥
pp ⎢ ⎥⎢ . ⎥
⎢ . ⎥ V . . . . .
⎢ v̂in(n−1)_d ⎥ ⎢ ⎥⎢ ⎥
⎣ ⎦ ⎣ 0 0 0 · · · −A(s) 0 ⎦⎣ x̂n−1 ⎦
v̂o_d 0 0 0 · · · 0 nG vd (s) x̂n
Incorporating (3.36) into Fig. 3.12, we can obtain the decoupled block diagram, as
shown in Fig. 3.13. As seen, the original n-input-n-output control system is decoupled
into n single-input-single-output closed loops, which consists of n − 1 IVS closed
loops and one output voltage closed loop. Moreover, the n − 1 IVS closed loops are
decoupled from one another and are also decoupled from the output voltage closed
loop. Thus, we can design the parameters of IVSR and OVR independently.
3.3 Closed-Loop Design
This section discusses the parameters design of Gvcd (s) and Gvo (s) based on a two-
module PSFB ISOP system. The specifications of the ISOP system are as follows.
The input voltage V in 540 Vdc, the output voltage V o 60 Vdc, and the output
current is 50 A (the equivalent load resistor RLd 1.2 ). For each PSFB module, the
Gving(s)
x̂ +
+
v̂in Kvc/n Gvcd(s) 1 1/Vpp A(s) v̂in1
+ _
Kvc
v̂in1f
Gving(s)
x̂ + n−1 IVS
+
v̂in Kvc/n Gvcd(s) 2 1/Vpp A(s) v̂in2 control
+ _
loops
Kvc
v̂in2f
Gving(s)
xˆ +
+ vîn ( n −1)
v̂in Kvc/n Gvcd(s) n −1 1/Vpp A(s)
+ _
Kvc
vîn ( n −1)f
iô Zout(s) Gvg(s) v̂in Output

xˆn + +
voltage
v̂oref Gvo(s) 1/Vpp nGvd(s) + v̂o
+ _ control
Kvo loop
v̂of
Fig. 3.13 Decoupled block diagram of the control strategy for PSFB-based ISOP system
transformer turns ratio K = 12:4, the output filter inductor L f 26 µH, the output filter
capacitor C f 3000 µF with equivalent series resistor Rcf 0.015 , the resonant
inductor L r 6.5 µH, the switching frequency f s 100 kHz, the voltage sensor gains
K vc 0.01 and K vo 0.03, and the peak-to-peak voltage of the sawtooth signal V pp
4 Vdc.
The IVS and output voltage control loops are shown in Fig. 3.13. Here, n = 2.
3.3.1 Output Voltage Regulator
It can be readily found in Fig. 3.13 that the loop gain of the output voltage control
loop is
Tvo_c (s) 2K vo G vd (s)G vo (s)/Vpp (3.37)
By setting Gvo (s) 1, the uncompensated loop gain T vo_u (s) is obtained as
3.3 Closed-Loop Design 71
Fig. 3.14 Uncompensated 60

and compensated output 40
voltage loop gains |Tvo_c|
20
(dB) 0
−20
−40 |Tvo_u|
−60
60
30 ∠Tvo_u
0
(°) −30
−60
−90 ∠Tvo_c
−120
−150
10 100 1⋅103 1⋅104 1⋅105
f (Hz)
|Gvo| (db)
20log|Gvo |
R2 0 f
C
0 f
R1 ωz
vi _ ∠Gvo (°)
fz =
R1 −90 2π
vref + 0.1fz fz 10fz
(a) Circuit diagram (b) Bode plots
Fig. 3.15 PI compensator
Tvo_u (s) 2K vo G vd (s)/Vpp (3.38)
With the given parameters of the ISOP system and substituting (3.18) into (3.38),
the Bode plots of T vo _u (s) are depicted, as shown in Fig. 3.14 (dashed lines). As seen,
the uncompensated loop gain is close to zero at low frequencies. In order to increase
the low-frequency loop gain, a proportional–integral (PI) compensator is adopted as
the output voltage regulator, as shown in Fig. 3.15a, which can be expressed as
1
s+
s + ωz1 R2 R2 C
G vo (s) G vo∞ (3.39)
s R1 s
ωz1 1
where the corner frequency of the PI compensator is f z1 .
2π 2π R2 C
The crossover frequency f c1 is chosen to be 10 kHz, which is one-twentieth of
the secondary ripple frequency. As shown in Fig. 3.14, the uncompensated loop gain
at 10 kHz has a magnitude of −17.087 dB, and the compensator should then have a
gain of 17.087 dB at 10 kHz, i.e.,
R2
G vo∞
R1
17.078
10 20 (3.40)
Setting R1 10 k and then R2 71 k. In practice, R2 68 k. To guarantee no

phase angle lag after the compensation, it is usually set 10 f z1 ≤ f c1 . With Fig. 3.15b,
we have
1 5
C ≥ 2.34 (nF) (3.41)
2π f z1 R2 π f c1 R2
Here, C = 10 nF is chosen, and the transfer function of the PI compensator is

s + 1471
G vo (s) 6.8 (3.42)
s
The compensated loop gain T vo_c (s) is shown as solid lines in Fig. 3.14. As shown,
the compensated loop gain has a crossover frequency of 10 kHz with a phase margin
of 85.9°.
3.3.2 IVS Regulator
As shown in Fig. 3.13, the loop gain of the IVS control loop is
Tcd_c (s) K vc G vcd (s)A(s)/Vpp (3.43)
Since Gvinjg (s) 1/n (j = 1, 2, …, n) according to (3.30), it can be concluded

from Fig. 3.13 that the IVS regulator gain should be zero, implying that the IVS
control would be unnecessary when all the modules are identical. Obviously, when
the modules are not identical, the IVS control would be needed. In fact, to facilitate
an accurate design of the compensator, the small-signal model should be further
modified, taking into account the differences of the modules, which is much more
complex and will not be discussed here.
By setting Gvcd (s) 1, the uncompensated loop gain T cd_u (s) is expressed as
Tcd_u (s) K vc A(s)/Vpp (3.44)
With the given parameters of the ISOP system, the Bode plots of T cd _u (s) are
depicted, as shown in Fig. 3.16 (dashed lines).
A PI compensator (see Fig. 3.15a) is employed and its transfer function is
3.3 Closed-Loop Design 73
Fig. 3.16 Uncompensated 60

and compensated IVS loop 30
gains |Tcd_c|
0
(dB) −30
−60 |Tcd_u|
−90
−120
60
0 ∠Tcd_u
(°)
−60
−120
∠Tcd_c
−180
10 100 1⋅103 1⋅104 1⋅105
f (Hz)
s + ωz2
G vcd (s) G vcd∞ (3.45)
s
Suppose that we aim to design a compensator to achieve a crossover frequency of
300 Hz, and the uncompensated loop gain at 300 Hz has a magnitude of approximately
−13.313 dB. Thus, the compensator should have a gain of 13.313 dB at 300 Hz, i.e.,
13.313
G vcd∞ 10 20 (3.46)
Setting R1 10 k and then R2 46.13 k. Here, R2 47 k is chosen. To

guarantee no phase angle lag after the compensation, 10f z2 ≤ f c2 is selected. With
Fig. 3.15b, we have
1 5
C ≥ 0.113 (µF) (3.47)
2π f z2 R2 π f c2 R2
Here, C 0.1 µF is chosen, and the transfer function of the PI compensator is

s + 212.7
G vcd (s) 4.7 (3.48)
s
Substituting (3.48) into (3.43) and with the given system parameters, the com-
pensated loop gain T cd_c (s) is depicted, as shown by the solid lines in Fig. 3.16. It
can be found that the compensated loop gain has a crossover frequency of 300 Hz
with a phase margin 80.5°.
Table 3.1 Parameters of OVR and IVSR

Parameters OVR IVSR
1# G vo (s) 6.8(s + 1471)/s G vcd (s) 4.7(s + 212.7)/s
2# G vo (s) 12(s + 833)/s G vcd (s) 9.1(s + 161.6)/s
3.4 Experimental Verification of the General Control

Strategy
A prototype of ISOP system consisting of two PSFB modules was built in the lab
to verify the correctness of the small-signal model and loop parameters design in
Sects. 3.2 and 3.3, and the specifications are
• input voltage V in 540 Vdc ± 10%,
• output voltage V o 60 Vdc,
• rated output current I o 50 A, and
• switching frequency f s 100 kHz.
Figure 3.17 shows the experimental waveforms of vAB1 , vAB2 , ip1 , ip2 , vrect1 , vrect2 ,
iLf1 , and iLf2 at full load condition, and it can be seen that both the input voltages and
output currents of the two PSFB modules are shared.
Figure 3.18 shows the dynamic responses of the input voltage and output voltage
(AC coupled) of module 1 when the system input voltage is step changed between 486
and 596 Vdc. The parameters of OVR and IVSR are listed in Table 3.1. Figure 3.18a
shows the dynamic responses with the same 1# IVSR parameter but different OVR
parameters. It can be seen that the output voltage responses differ and no change on
the module input voltage. Figure 3.18b shows the dynamic responses with the same
1# OVR parameter but different IVSR parameters. It can be seen that the output
voltage responses keep unchanged.
Figure 3.19 shows the dynamic responses of the input voltage (AC coupled) and
output voltage (AC coupled) of module 1 when the load current is step changed
between 25 and 50 A with different regulator parameters. It can be found that the
load step has no influence on the module input voltage, verifying the correctness of
(3.33).
We can conclude from Figs. 3.18 and 3.19 that IVS control loop is decoupled
from the output voltage control loop.
3.5 Three-Loop Control Strategy for ISOP System
In Sects. 3.2 and 3.3, removing the IVS control loops will lead to a common duty cycle
control strategy with a single-output voltage control loop for the ISOP system, and
the ISOP system is stable. However, the mismatched parameters among the modules
may cause input voltages unbalance, and thus the IVS control loops are needed. The
3.5 Three-Loop Control Strategy for ISOP System 75
vAB1:[400V/div]
ip1:[20A/div]
vAB2:[400V/div]
ip2:[20A/div]
Time:[2μs/div]
(a) Primary voltages and currents of the two PSFB modules
vrect1:[100V/div]
iLf1:[15A/div]
vrect2:[100V/div]
iLf2:[15A/div]
Time:[2μs/div]
(b) Secondary rectified voltages and filter inductor currents of

the two PSFB modules
Fig. 3.17 Experimental waveforms of the ISOP system
inner current loop can be introduced to form a voltage–current double closed loop to
improve the system dynamic response and readily realize output current short-circuit
protection. So, whether the ISOP system with only the voltage–current double closed
loop is stable if the IVS control loops are removed too? If it is unstable, then the IVS
control loops are required, but how to design the IVS regulators? This section will
address these issues.
vin:[200V/div]
vin1:[100V/div] 1# IVSR
1# OVR
vin1:[100V/div]
1# IVSR
2# OVR
vo:[2V/div]
vo:[2V/div]
Time:[20ms/div]
(a) Different OVR parameters
vin:[200V/div]
vin1:[100V/div] 1# IVSR
1# OVR
vin1:[100V/div]
2# IVSR
1# OVR
vo:[2V/div]
vo:[2V/div]
Time:[20ms/div]
(b) Different IVSR parameters
Fig. 3.18 Dynamic responses for stepped input voltage
3.5.1 Positive Resistance
Figure 3.20 shows the control block diagram of the voltage–current double closed
loop for PSFB ISOP system, where iLf1 , iLf2 , …, iLfn are the module output filter
inductor currents, Gc is the gain of inner current loop regulator, and the current
reference signal of the inner current loops is the output of the output voltage regulator.
At steady state, all the inner current loops have the same current reference and
all the modules have the same output filter inductor currents, as well as the output
io:[25A/div]
1# IVSR
vin1:[10V/div] 1# OVR
vin1:[10V/div]
1# IVSR
2# OVR
vo:[2V/div]
vo:[2V/div]
Time:[20ms/div]
(a) Different OVR parameters
io:[25A/div]
1# IVSR
vin1:[10V/div] 1# OVR
vin1:[10V/div]
2# IVSR
1# OVR
vo:[2V/div]
vo:[2V/div]
Time:[20ms/div]
(b) Different IVSR parameters
Fig. 3.19 Dynamic responses for stepped load
currents, which is equivalent to an OCS control strategy. In Chap. 2, it is pointed

out that the ISOP system is unstable with OCS control strategy and the root cause
is that the input impedance of each converter module appears as negative resistance
characteristic when OCS control strategy employed. Therefore, the ISOP system
with only voltage–current double closed loop is unstable if the IVS control loops are
removed.
Thus, if the ISOP system is stable, the input impedance of each converter module
must appear as positive resistance characteristic, and one direct approach is to connect
_ iLf1 Comparator 1
+
Gc − Drive
RS Flip-flop
+ circuit 1
VRAMP 1
_ iLf2 Comparator 2
+
Gc − Drive
RS Flip-flop
Inner current + circuit 2
VRAMP 2
loops
_ iLfn Comparator n
+ +
Gvo Gc − Drive
Voref _ vo_EA RS Flip-flop
vof + circuit n
VRAMP n
Fig. 3.20 Block diagram of voltage–current double closed loop
Fig. 3.21 Small-signal

model of ISOP system with a iîn iˆcin_1
resistor connected to the
input side of each module iîn_cs1
+ ′
Z in1
v̂in1 Rne1 Rp1
_ Cd1
iˆcin _ 2
iîn_cs2
+ ′
Z in2
v̂in2 Rne2 Rp2
vˆ in _ Cd2
iˆcin _ n
iîn_csn
+ ′
Z inn
v̂inn Rnen Rpn
_ Cdn
a positive resistance Rpj (j = 1, 2, …, n) in parallel with the input side the each module,
as shown in Fig. 3.21, where î in_cs j (j = 1, 2, …, n) represents the each module’s input
current perturbation when the voltage–current double closed loop is adopted. The
equivalent input impedance of each module is
Rne j · Rp j
Z in j Rne j //Rp j > 0 ( j 1, 2, . . . , n) (3.49)
Rne j + Rp j
_ v vin_EA1
in1 _ iLf1 Comparator 1
+ iref1+
Gvcd _ Gc - Drive
IVSR + circuit 1
VRAMP 1
_ v vin_EA2 _ iLf2 Comparator 2

in2
+ iref2 +
Gvcd _ Gc - Drive
Vin/n + Inner current RS Flip-flop
+ circuit 2
IVS loops loops VRAMP 2
_ vinn vin_EAn _ iLfn Comparator n

+ irefn +
Gvcd _ Gc - Drive
+ circuit n
VRAMP n
_ vof
+ vo_EA
Gvo
Voref
Output voltage loop
Fig. 3.22 Three-loop control strategy for ISOP system
Thus, we have
Rp j < −Rne j ( j 1, 2, . . . , n) (3.50)
The Rpj can be a real resistor and the resistance of Rpj < −Rnej (j = 1, 2, …, n), due
to the −Rnej (j = 1, 2, …, n), is the equivalent resistance reflecting the input power of
each module, if Rpj < −Rnej (j = 1, 2, …, n), the power dissipated on Rpj (j = 1, 2, …, n)
will be larger than the input power of each module, which is absolutely unacceptable.
When the input impedance of module appears as positive resistance characteristic,
the module input current increases/decreases with the increase/decrease of input
voltage, and consequently the module output current will also increase/decrease, as
well as the module output filter inductor current. Therefore, we can compare the input
voltage of each module with the reference of input voltage of each module V in /n,
and when the input voltage of module is higher/lower than V in /n, the module output
filter inductor current should increase/decrease by introducing a feedback signal to
increase/decrease the current reference signal of the inner current loop. This function
can be implemented by the IVS loops, as shown in Fig. 3.22. Taking module 1 for
example, when its input voltage vin1 is higher than V in /n, leading to the increase of its
current reference signal for inner current loop, thus the output filter inductor current
and output power will increase, as well as the input current of module 1, resulting in
the input impedance of module 1, appears as positive resistance characteristic.
Fig. 3.23 Equivalent

small-signal model for ISOP iîn iˆcin _1
system with three-loop
control strategy
iîn_cs1 iîn_IVS1
+ ′
Z in1
v̂in1 Rne1 Rp1
_ Cd1
iˆcin _ 2
iîn_cs2 iîn_IVS2
+ ′
Z in2
v̂in2 Rne2 Rp2
vˆ in _ Cd2
Ă
iˆcin _ n
iîn_csn iîn_IVSn
+ ′
Z inn
v̂inn Rnen Rpn
_ Cdn
3.5.2 IVS Regulator Design
In Sect. 3.2, it has been pointed out that the IVS control loops and output voltage
control loop are decoupled, and thus we can design the IVS loops and voltage–current
double closed loops independently. In Sect. 3.5.1, it is found that the function of the
IVS loops is equivalent to a positive resistance and the equivalent small-signal model
for ISOP system with three-loop control strategy is shown in Fig. 3.23, where î in_IVS j
(j = 1, 2, …, n) is the module input current perturbation introduced by the IVS control
loops.
According to Fig. 3.22, the individual output filter inductor current perturbation
î Lf_IVS j (j = 1, 2, …, n) caused by the input voltage perturbationv̂in j (j = 1, 2, …, n)
can be expressed as
î Lf_IVS j v̂in j · G vcd ( j 1, 2, . . . , n) (3.51)
Then, the individual output power perturbation p̂o j (j = 1, 2, …, n) is
p̂o j î Lf_IVS j · Vo v̂in j · G vcd · Vo ( j 1, 2, . . . , n) (3.52)

Referring to Fig. 3.23, the individual input power is
pin j vin j · i cin_ j ( j 1, 2, . . . , n) (3.53)
The perturbation equation of (3.53) can be expressed as

Pin j + p̂in j Vin j + v̂in j Icin_ j + î cin_ j

Vin j Icin_ j + v̂in j Icin_ j + Vin j + v̂in j î in_IVS j + î in_cs j
( j 1, 2, . . . , n) (3.54)
where Pinj , V cdj , and I cin_j (j = 1, 2, …, n) are the module input power, input voltage,
and input current at steady state, respectively.
Neglecting the second-order term of (3.54) and noting that the DC terms on both
sides of the equation are equal, we obtain

p̂in j Icin_ j v̂in j + Vin j î in_IVS j + î in_cs j ( j 1, 2, . . . , n) (3.55)
According to power conservation, we have
p̂o j p̂in j · η j ( j 1, 2, . . . , n) (3.56)
Combining (3.52), (3.55), and (3.56) yields

Vo
Icin_ j v̂in j + Vin j î in_IVS j + î in_cs j v̂in j · G vcd · ( j 1, 2, . . . , n) (3.57)
ηj
The negative resistance can be expressed as
v̂in j Vin j
− Rne j ( j 1, 2, . . . , n) (3.58)
î in_cs j Icin
v̂in j Vin j
Rp j ( j 1, 2, . . . , n) (3.59)
î in_IVS j G vcd · Vo η j
Substituting (3.58) and (3.59) into (3.50) leads to

Pin · η j
G vcd > ( j 1, 2, . . . , n) (3.60)
Vo · Vin
Neglecting the difference among the module efficiencies and assuming η1 η2

··· ηn η, according to (3.60), we can obtain
Po · η
G vcd > (3.61)
Vo · Vin
To ensure the stable operation of ISOP system over the whole input voltage and
load range, Gvcd should satisfy the following formula:
Po_max · η
G vcd_min (3.62)
Vo · Vin_min
where V in_min is the minimum input voltage and Po_max is the maximum output power.
3.6 Experimental Verification of the Three-Loop Control

Strategy
In order to verify the correctness of the IVS loop design, an ISOP system prototype
consisting of two PSFB converter modules has been fabricated with the following
specifications:
• input voltage V in 540 Vdc ± 10%,
• rated output current I o 40 A, and
• switching frequency f s 100 kHz.
Figure 3.24 shows the experimental waveforms of the ISOP system with volt-
age–current double closed-loop control strategy (see Fig. 3.20). vin1 , vin2 , io1 , and io2
are the input voltages and output currents of the two modules, respectively, and vo is
the system output voltage. Prior to t 1 , the three-loop control strategy (see Fig. 3.22) is
employed and the ISOP system works stably, and IVS and OCS are achieved between
the two modules. At t 1 , the IVS loops are removed and after that vin1 rises and vin2
declines, but the two modules still share the output current and system output voltage
is still stable until t 2 . At t 2 , the duty cycle of module 2 reaches 1, and its inner current
loop regulator saturates. Thus, the two modules cannot ensure the sharing of output
current, and after a period of time the ISOP system enters the new steady state, where
both the input voltages and output currents of the two modules are unbalanced. Due
to the fact that the PSFB converter is a buck-derived topology, the input voltage of
module 2 will not decline when it is not high enough to provide the desired output
voltage.
Figures 3.25 and 3.26 show the waveforms comparison of the ISOP system with
three-loop control strategy (see Fig. 3.22) and general control strategy (see Fig. 3.11).
Figure 3.25 shows the dynamic responses of input voltages of two modules and output
voltage (AC coupled) for stepped input voltage between 500 and 600 Vdc. Figure 3.26
shows the dynamic responses of input voltages of two modules and output voltage
(AC coupled) for stepped load current between 25 and 50 A. It can be seen that
the input voltages are well shared, and the sharing of the output current is achieved
3.6 Experimental Verification of the Three-Loop Control Strategy 83
C2 vin1: [200V/div]
C3 vin2: [200V/div]
C2/ C3
M2 io1: [10A/div]
M3 io2: [10A/div]
M2/ M3
C4 C4 vo: [1V/div]
t1 t2
Time: [5ms/div]
Fig. 3.24 Experimental waveforms of the ISOP system with voltage–current double closed-loop
control strategy
C1 vin:[500V/div] C1 vin:[500V/div]
C1 C1
C2 vin1:[200V/div] C2 vin1:[200V/div]
C2 C2
C3 C3
C4 C4 vo:[5V/div] C4 C4 vo:[5V/div]
(a) General control strategy (b) Three-loop control strategy
Fig. 3.25 Dynamic responses for stepped input voltage
automatically for the ISOP system regardless with the three-loop control strategy or
the general control strategy. Furthermore, the ISOP system employing the three-loop
control strategy has a better dynamic performance with smaller magnitude of output
voltage overshoot and shorter regulation time in transient.
3.7 Summary
In this chapter, the small-signal model of the PSFB-based ISOP system is derived.
Based on the small-signal model, it is proved that the general control strategy pro-
posed in Chap. 2 for n-module ISOP system can be decoupled into n single-input-
C1 io:[20A/div] C1 io:[20A/div]
C1 C1
C2 C2
C3 C3
C4 C4 vo:[2V/div] C4 C4 vo:[2V/div]
(a) General control strategy (b) Three-loop control strategy
Fig. 3.26 Dynamic responses for stepped load current
single-output closed loops, which consists of n − 1 IVS closed loops and one output
voltage closed loop. Moreover, the n − 1 IVS closed loops are decoupled from one
another and are also decoupled from the output voltage closed loop. The parameters
design of the IVS control loop regulator and output voltage control loop regulator
based on a two-module PSFB ISOP system is discussed and verified by the prototype.
Inner current loop can be introduced into the general control strategy to improve
the system dynamic response and readily realize output current short-circuit protec-
tion. If the IVS loops are removed and only voltage–current double closed loop is
used for the ISOP system, the system is unstable and the root cause is that the input
impedance of each module appears as negative resistance characteristic. Hence, the
IVS loops are indispensable for ensuring the system stability to change the negative
resistance characteristic to the positive resistance characteristic, and this is also the
design criteria IVS control loop regulator.
References
1. Ruan, X., Yan, Y.: Soft-switching techniques for PWM full bridge converters. In: Proceedings
of the IEEE Power Electronics Specialists Conference, pp. 634–639 (2000)
2. Vlatkovic, V., Sabate, J.A., Ridley, R.B., Lee, F.C., Cho, B.H.: Small-signal analysis of the
phase-shifted PWM converter. IEEE Trans. Power Electron. 17(1), 128–135 (1992)
3. Sabate, J.A., Vlatkovic, V., Ridley, R.B., Lee, F.C., Cho, B.H.: Design considerations for high-
voltage high-power full-bridge zero-voltage-switched PWM converter. In: Proceedings of the
IEEE Applied Power Electronics Conference and Exposition, pp. 275–284 (1990)
Chapter 4
Wireless IVS Control Strategies
for Input-Series-Connected Systems
Based on Positive Output Voltage
Gradient Method
Abstract This chapter proposes the wireless input voltage sharing (IVS) control
strategies for the input-series-connected systems based on positive output voltage
gradient method, which increases the output voltage of each module with the increase
of module input voltage. The constituent modules of input-series-connected systems
with the proposed control strategy merely need to sense their own input/output volt-
ages and there is no control interconnection among modules, leading to a truly modu-
lar design and high system reliability. The operation principle of the control strategy
and the system stability are analyzed in this chapter. Experimental prototypes of
the input-series-connected systems consisting of three two-transistor forward mod-
ules have been fabricated and tested to validate the proposed wireless IVS control
strategies.
Keywords Input voltage sharing · Input-series-connected systems

Positive output voltage gradient method · Truly modular design
Multi-module series–parallel power conversion systems can be categorized into

IPOP, IPOS, ISOP, and ISOS systems, where ISOP and ISOS systems are the input-
series-connected systems. It is pointed out in Chap. 2 that only control strategies
intending to achieve IVS for the input-series-connected systems are stable, and the
OCS (for ISOP) and OVS (for ISOS) are achieved automatically. A modularization
architecture for the input-series-connected systems was proposed by distributing the
IVS control loops and output voltage control loop into the individual module and
then interconnecting each module through a common duty cycle bus and an IVS
bus to achieve IVS and the desired output voltage. This implies that the common
duty cycle bus and IVS bus are essential for the system stable operation. When the
buses are disrupted or failed, the operation of systems will be affected or even go to
paralysis which reduces the system reliability to some extent. Therefore, eliminating
the interconnection among the modules is the desired choice.
This chapter proposes the wireless IVS control strategies for the input-series-
connected systems based on positive output voltage gradient method, which increases
the output voltage of each module with the increase of module input voltage. The
86 4 Wireless IVS Control Strategies for Input-Series-Connected …
constituent modules of input-series-connected systems with the proposed control

strategy merely need to sense their own input/output voltages and there is no control
interconnection among modules leading to a truly modular design and high system
reliability [1, 2]. This chapter will analyze the operation principle of the control
strategy and system stability. Experimental prototypes of the input-series-connected
systems consisting of three two-transistor forward modules have been fabricated and
tested to validate the proposed wireless IVS control strategies.
4.1 Genesis of the Wireless IVS Control Strategies Based

on Positive Output Voltage Gradient Method
The DC–DC ISOP system shown in Fig. 4.1 is taken as an example to derive the
wireless IVS control strategy. In Chap. 2, the modularization architecture for DC–DC
series–parallel power conversion systems is proposed (see Fig. 2.9). For the conve-
nience of illustration, the control block diagram for ISOP system is given here, as
shown in Fig. 4.2, where V inj (j 1, 2, …, n) is the input voltage of module j, vofj (j
1, 2, …, n) is the sensed output voltage of each module (also is the system output
voltage), V oref is the output voltage reference, V RAMPj (j 1, 2, …, n) is the sawtooth
signal of the modulator j, Gvo is the transfer function of output voltage control loop
regulator and Gvcd is the transfer function of IVS control loop regulator. The control
strategy of each module consists of an output voltage closed loop and an IVS closed
loop. The signal of common duty cycle bus, vo_EA , is formed by interconnecting the
output signal of the individual output voltage control loop regulator through a diode.
The signal of IVS bus V in_ref is formed by interconnecting the input voltage of each
module through a resistor R, and it is easy to know that V in_ref V in /n, where V in
is the system input voltage. V in_ref serves as the reference voltage of each module
input voltage. The error signal between V in_ref and V inj (j = 1, 2, …, n) is sent to the
corresponding IVS control loop regulator and its output is subtracted from vo_EA and
then compared with the sawtooth signal generating the duty cycle signal of each
module.
Obviously, the reference voltage V in_ref is variable when the system input voltage
V in varies. If we set the V in_ref as a constant value, denoted as V inmod_ref , the IVS bus
can be eliminated. However, if the system input voltage is not equal to n·V inmod_ref ,
the IVS control loop regulators will be saturated and fail to fulfill their function. To
achieve IVS, the error signal between the reference voltage V inmod_ref and V inj (j 1,
2, …, n) can be amplified by a proportional coefficient k up and added to the reference
output voltage V oref as shown in Fig. 4.3. The common duty cycle bus and corre-
sponding diodes can also be removed and finally, the wireless IVS control strategy
for ISOP system is obtained as shown in Fig. 4.4. It can be seen that only the input and
output voltages are sensed for each module and there is no control interconnection
among the constituent modules, which implies that a wireless controller is obtained
and the system reliability can be significantly enhanced. Moreover, all the modules
4.1 Genesis of the Wireless IVS Control Strategies Based … 87
Iin Iin1 Io1 Io

+ +
DC-DC
Vin1 C Cf1 RLd Vo
_ d1 Module 1 _
Iin2 Io2
+ DC-DC
Vin2 C Cf2
Vin _ d2 Module 2
Iinn Ion
+ DC-DC
Vinn C Cfn
_ dn Module n
Fig. 4.1 Circuit diagram of ISOP system
are identical and can operate in stand-alone mode, which means that the loop design
is very simple compared with the other control strategies for the ISOP systems. A
truly modular design can be realized for the ISOP system with the proposed control
strategy.
At steady state, the input voltage of each module varies in the range of [V inmin /n,
V inmax /n], where V inmin and V inmax are the minimum and maximum system input
voltages, respectively. If we set V inmod_ref to be a constant value, such as V inmin /n,
the error signal (V inj − V inmod_ref ) (j 1, 2, …, n) will rise if the module input
voltage increases from V inmin /n. Since the error signal is added to V oref , the system
output voltage will increase. This means that the output voltage increases with the
increase of input voltage and the output voltage has a positive gradient regulation
characteristic. Here, k up is defined as gradient gain.
The operation principle will be analyzed as follows. The ISOP system operates at
steady state and the constituent modules share the system input voltage. Assuming
a perturbation occurs on the input voltages, which causes V in1 to decrease and V in2
to increase and the input voltages of other modules keep unchanged. Thus, we have
V in1 < V in /n < V in2 . Then, the real reference voltage of 1# module output voltage
control loop, [V oref + k up1 (V in1 − V inmod_ref )], will lower than that of 2# module
output voltage control loop, [V oref + k up2 (V in2 − V inmod_ref )]. Due to the fact that the
output sides of the modules are connected in parallel and all the modules have the
same output voltage, for the controller of module 1, the output voltage is considered
to be higher than its corresponding reference voltage, and the duty cycle will be
regulated to reduce the input power of module 1, I in1 will decrease, then the input
voltage of module 1 increases. In the meanwhile, for the controller of module 2, the
R Vin1
_ _ Comparator 1
+
Gvcd − Drive
+ RS Flip-flop
+ + circuit 1
Voref _ Gvo VRAMP 1
vof1
Vin_ref
Module 1
R Vin2
_ _ Comparator 2
+
Gvcd − Drive
+ RS Flip-flop
+ + circuit 2
Voref _ Gvo VRAMP 2
vof2
Module 2
R Vinn
_ _ Comparator n
+
Gvcd − Drive
vo_EA + RS Flip-flop
+ + circuit n
Voref _ Gvo VRAMP n
vofn
Module n
Fig. 4.2 Modularization control block diagram of ISOP system
Vin1 _ vof1
_ _ Comparator 1
+
kup1 Gvo − Drive
Vinmod_ref + RS Flip-flop
Voref + circuit 1
VRAMP 1
Module 1
V_in2 _ vof2
_ Comparator 2
+
kup2 Gvo − Drive
Voref + circuit 2
VRAMP 2
Module 2
Vinn _ v
+
_ _ ofn Comparator n
kupn Gvo − Drive
Voref + circuit n
VRAMP n
Module n
Fig. 4.3 Simplified modularization control block diagram of ISOP system

4.1 Genesis of the Wireless IVS Control Strategies Based … 89
Vin1
_ vof1 Comparator 1
_ + +
kup1 Gvo − Drive
Voref + circuit 1
VRAMP 1
Module 1
Vin2 _ vof2 Comparator 2

_ + +
kup2 Gvo − Drive
Voref + circuit 2
VRAMP 2
Module 2
Vinn _ vofn Comparator n

_ + +
kupn Gvo − Drive
Voref + circuit n
VRAMP n
Module n
Fig. 4.4 Wireless IVS control strategy of ISOP system
output voltage is considered to be lower than its corresponding reference voltage,

and its duty cycle will be regulated to increase the input power of module 2, I in2 will
increase, then the input voltage of module 2 decreases. Finally, two modules return
to the steady state.
From the above analysis, for the ISOP system employing the wireless IVS control
strategy, the module input current increases when the module input voltage increases,
and the module input current decreases when the module input voltage decreases.
Thus, the input impedance of the module appears as positive resistance characteristic
and the control strategy is stable.
According to Fig. 4.4, the output voltage of module j at steady state is
1
Vo j Voref + kup j · Vin j − Vin mod_ref ( j 1, 2, . . . , n) (4.1)
K vo
where K vo is the output voltage sensing gain.

Defining V omin V oref /K vo and setting V inmod_ref V inmin /n, (4.1) can be rewritten
as

kup j Vinmin
Vo j Vomin + Vin j − ( j 1, 2, . . . , n) (4.2)
K vo n
According to (4.2), the curve of the output voltage versus module input voltage
can be depicted as shown in Fig. 4.5. Obviously, each module has a positive output
voltage gradient regulation characteristic.
Fig. 4.5 Positive output

voltage gradient regulation
characteristic Voj
Vomin
Vinmin /n Vinj
4.2 Basic Features of the Input-Series-Connected Systems

with Wireless IVS Control Strategies
4.2.1 ISOP System
For simplicity, a two-module ISOP system is taken as an example to discuss the basic
features of the wireless IVS control strategies.
According to (4.2), the output voltages of two modules can be expressed as

kup1 Vinmin
Vo1 Vo1min + · Vin1 − (4.3)
K vo 2

kup2 Vinmin
Vo2 Vo2min + · Vin2 − (4.4)
K vo 2
It should be noted that here, V o1min and V o2min are used for two modules, respec-
tively, because the reference voltages of the two modules may be mismatched.
For a two-module ISOP system, we have
Vin Vin1 + Vin2 (4.5)

Vo1 Vo2 Vo (4.6)
According to (4.3)–(4.6), we have

Vinmin
kup2 Vin + K vo (Vo2min − Vo1min ) + kup1 − kup2
Vin1 2 (4.7)
kup1 + kup2
Vinmin
kup1 Vin + K vo (Vo1min − Vo2min ) + kup2 − kup1
Vin2 2 (4.8)
kup1 + kup2
kup1 Vo2min + kup2 Vo1min kup1 kup2
Vo − Vinmin
kup1 + kup2 K vo kup1 + kup2
kup1 kup2
+ Vin (4.9)
K vo kup1 + kup2
4.2 Basic Features of the Input-Series-Connected Systems … 91
Combining (4.7) and (4.8), the input voltage sharing error is expressed as

Vin12 Vin1 − Vin2 kup2 − kup1 (Vin − Vinmin ) + 2K vo (Vo2min − Vo1min )

Vin Vin kup1 + kup2 Vin
(4.10)
Equation (4.10) implies that the input sharing error is determined by the gradient
gains, minimum input voltage, and minimum output voltages of the two modules.
According to (4.9), the gradient gain of ISOP system is
dVo kup1 kup2 1 1
(4.11)
dVin K vo kup1 + kup2 K vo 1 1
+
kup1 kup2
Likewise, the gradient gain of ISOP system consisting of n modules is

dVo 1 1
(4.12)
dVin K vo 1 1 1
+ + ··· +
kup1 kup2 kupn
It can be seen that the gradient gain of ISOP system is only determined by the
module gradient gains, and the larger the n, the smaller the gradient gain of ISOP
system, which means that the system has better output voltage regulation perfor-
mance. In particular, when kup1 kup2 · · · kupn kup , the gradient gain of
ISOP system is equal to k up /(nK vo ).
Figure 4.6 shows the dependence of the IVS accuracy on the mismatch of output
voltage set-point (V o1min and V o2min ) for a two-module ISOP system, and Fig. 4.7
shows the dependence of the IVS accuracy on the output voltage gradient gain.
As seen in Fig. 4.6, the IVS accuracy is improved as the output voltage set-point
mismatching decreases, and when the output voltage gradient gains are perfectly
matched, as shown in Fig. 4.6c, the two modules share the input voltage evenly.
From Fig. 4.7, it can be seen that a larger output voltage gradient gain results in
better IVS performance, but the system output voltage regulation performance is
deteriorated.
According to (4.10), (4.11), Figs. 4.6 and 4.7, we can obtain the following conclu-
sions: the larger the module gradient gain, the better the IVS characteristic, but the
system output voltage regulation performance is deteriorated. On the contrary, the
smaller the module gradient gain, the worse the IVS characteristic, but the system
output voltage regulation performance is improved. Therefore, a trade-off must be
made between the IVS and the output voltage regulation performance when design-
ing the control circuit. Hence, the proposed control strategy is more suitable for the
applications with a narrow input voltage range.
Vo Vo
1# 1#
2# 2#
Vo= Vo1= Vo2
Vo= Vo1= Vo2
Vin1 Vin/2 Vin2 Vin Vin1 Vin/2 Vin2 Vin

(a) Large mismatch (b) Small mismatch
Vo
1#, 2#
Vo= Vo1= Vo2
Vin1=Vin2=Vin/2 Vin
(c) No mismatch
Fig. 4.6 Effect of output voltage set-point mismatching on IVS accuracy
Vo 1# Vo
2#
1#
2#
Vo= Vo1= Vo2
Vo= Vo1= Vo2
Vin1 Vin/2 Vin2 Vin Vin1 Vin/2 Vin2 Vin

(a) Large slope (b) Small slope
Fig. 4.7 Effect of output voltage gradient gain on IVS accuracy
4.2.2 ISOS System
Likewise, the wireless IVS control strategy for ISOS system based on positive output
voltage gradient method is shown in Fig. 4.8. It is worth noting that the feedback
signal for each module is the system output voltage V o .
4.2 Basic Features of the Input-Series-Connected Systems … 93
Vin1
_ vof Comparator 1
_ +
kup1 + Gvo − Drive
Voref + Circuit 1
VRAMP 1
Module 1
Vin2 _ vof
_ + Comparator 2
kup2 + Gvo − Drive
Voref + circuit 2
VRAMP 2
Module 2
Vinn _ vof
_ + Comparator n
kupn + Gvo − Drive
Voref + Circuit n
VRAMP n
Module n
Fig. 4.8 Wireless IVS control strategy for ISOS system
A two-module ISOS system is also taken as an example to analyze its features.

Similar to ISOP system, we set V omin V oref /K vo and V inmod_ref V inmin /n according
to Fig. 4.8, we have

kup1 Vinmin kup2 Vinmin
Vo Vo1min + · Vin1 − Vo2min + · Vin2 − (4.13)
K vo 2 K vo 2
It should be noted that here, V o1min and V o2min are used for two modules, respec-
tively, because the reference voltages of the two modules may be mismatched.
For ISOS system, V in V in1 + V in2 . By combining this expression and (4.13),
we have

K vo (Vo2min − Vo1min ) + kup2 Vin − Vinmin 2 + kup1 Vinmin 2
Vin1 (4.14)
kup1 + kup2

K vo (Vo1min − Vo2min ) + kup1 Vin − Vinmin 2 + kup2 Vinmin 2
Vin2 (4.15)
kup1 + kup2
kup1 Vo2min + kup2 Vo1min kup1 kup2
Vo + (Vin − Vinmin ) (4.16)
kup1 + kup2 K vo kup1 + kup2
According to (4.14) and (4.15), the input voltage sharing error is obtained and is
expressed as

Vin12 Vin1 − Vin2 2K vo (Vo2min − Vo1min ) + kup2 − kup1 (Vin − Vinmin )

Vin Vin kup1 + kup2 Vin
(4.17)
Equation (4.17) implies that the input sharing error is determined by the gradient
gains (k up1 and k up2 ) and minimum output voltages of the two modules (V o1min and
V o2min ).
According to (4.16), the gradient gain of two-module ISOS system is
dVo kup1 kup2 1 1
(4.18)
dVin K vo kup1 + kup2 K vo 1 1
+
kup1 kup2
It can be seen that the gradient gain of two-module ISOS system is the same as
that of two-module ISOP system.
Similar to ISOP system, we also can obtain the following conclusions for ISOS
system: the larger the module gradient gain, the better the IVS characteristic, but the
system output voltage regulation performance is deteriorated. On the contrary, the
smaller the module gradient gain, the worse the IVS characteristic, but the system
output voltage regulation performance is improved.
4.3 System Stability
The purpose of this section is to study the stability of the ISOP system with the
wireless IVS control strategy. With no loss of generality and for ease of analysis, the
ISOP system under study consists of two two-transistor forward converter modules
as shown in Fig. 4.9, where C d1 and C d2 are two input divided capacitors, power
switches S 1 and S 2 , diodes D1 and D2 , transformer T r1 , rectifier diodes DR1 and
DR2 , and output filter inductor L f1 form two-transistor forward converter 1, power
switches S 3 and S 4 , diodes D3 and D4 , transformer T r2 , rectifier diodes DR3 and DR4 ,
and output filter inductor L f2 form two-transistor forward converter 2, C f is the output
filter capacitor. The corresponding small-signal model the ISOP system is shown in
Fig. 4.10 [3].
According to Fig. 4.10, we have

K1 Io 1
î o1 î in − sCd1 v̂in1 − d̂y1 (4.19)
Dy1 K1

K2 Io 2
î o2 î in − sCd2 v̂in2 − d̂y2 (4.20)
Dy2 K2

RLd
v̂o î o1 + î o2 (4.21)
sCf RLd + 1
4.3 System Stability 95
Iin Iin1
D R1 Lf1
RLd
D1 +
S1 K1:1
* * io1
+
Vin1 Vo
Cd1 _ Cf
DR2
Tr1 _
D2
S2
Vin DR3 Lf2

Iin2
D3
S3 K2:1
* * io2
+
Vin2
Cd2 _
DR4
Tr2
D4
S4
Fig. 4.9 Circuit diagram of two-module ISOP system
Dy1
1:
iîn K1 Lf1 iô RLd
+
_
+
+ Cd1 Vin1 ˆ iô1
d y1 v̂o
v̂in1 I o1 ˆ K1 Cf
_ d y1 _
K1
Dy2
1: Lf2
v̂in K2
+
_
+ Cd2 Vin2 ˆ iô2

v̂in2 d y2
I o2 ˆ K2
_ d y2
K2
Fig. 4.10 Small-signal model of the ISOP system shown in Fig. 4.9
where d̂y1 and d̂y2 are the perturbations of the duty cycles of two modules, and
v̂in1 and v̂in2 are the perturbations of individual input voltages, î o1 and î o2 are the
perturbations of individual output currents, K 1 and K 2 are turns ratios of the individual
transformers, Dy1 , Dy2 , I o1, and I o2 are steady-state duty cycles and output currents,
respectively.
Assuming k up1 k up2 k up , K 1 K 2 K, and Dy1 Dy2 Dy , we have I o1
I o2 V o /(2RLd ) and V in1 V in2 V in /2. From Fig. 4.4, the expressions of d̂y1 and
d̂y2 are obtained as

d̂y1 G vo kup v̂in1 − K vo v̂o Vpp (4.22)

d̂y2 G vo kup v̂in2 − K vo v̂o Vpp (4.23)
where V pp is the peak-to-peak value of sawtooth signal V RAMP .

Assuming the bandwidths of the output voltage closed loops are high enough, the
perturbation of output voltage v̂o caused by the perturbation of input voltage v̂in can
be expressed as
kup
v̂o v̂in (4.24)
2K vo
Substitution of (4.19), (4.20), (4.22), (4.23), and (4.24) into (4.21), yields
kup Dy (sCf RLd + 1)
v̂in 2î in − sCd1 v̂in1 − sCd2 v̂in2 (4.25)
2K vo K RLd
According to Fig. 4.9, the input power and output power of the ISOP system can
be expressed as
Pin + p̂in (Vin + v̂in )(Iin + î in ) Vin Iin + Vin î in + Iin v̂in + v̂in î in (4.26)
(Vo + v̂o ) 2
2Vo v̂o
Vo2 v̂o2
Po + p̂o + + (4.27)
RLd RLd RLd RLd
where p̂in and p̂o are input and output power perturbations, respectively.
Assuming the conversion efficiency is 100%, the input power is equal to the output
power. So, according to (4.26) and (4.27), we have
Vo2 2Vo v̂o v̂ 2

Vin Iin + Vin î in + Iin v̂in + v̂in î in + + o (4.28)
RLd RLd RLd
Neglecting the second-order terms of (4.28) and noting that the DC terms on both
V2 1
sides of (4.28) are equal, and knowing that Iin o · , substitution of (4.24) into
RLd Vin
(4.28), gives
kup
Vin Vo − Vo2
K vo
î in v̂in (4.29)
RLd Vin2
Substituting (4.29) into (4.25) and considering v̂in v̂in1 + v̂in2 yields
kup Dy (sCf RLd + 1) kup Vin Vo − K vo Vo2

−2 + sCd2
v̂in1 2K vo K RLd K vo R Ld Vin2
(4.30)
v̂in s(Cd2 − Cd1 )
kup Dy (sCf RLd + 1) kup Vin Vo − K vo Vo2
−2 + sCd1
v̂in2 2K vo K RLd K vo R Ld Vin2
(4.31)
v̂in s(Cd1 − Cd2 )
4.3 System Stability 97
From (4.30) and (4.31), the transfer function of the input voltage difference of the
two modules to the total input voltage can be derived as

kup Dy Cf kup Dy kup Vin Vo − K vo Vo2
s + Cd1 + Cd2 + −4
v̂in12 v̂in1 − v̂in2 K vo K K vo K RLd K vo RLd V 2
in

v̂in v̂in s(Cd2 − Cd1 )
(4.32)
In practice, C d1 is impossible to equal to C d2 precisely. Hence, there is a root at the

origin in the characteristic equation of the transfer function v̂in12 /v̂in , which means
that the system is critically stable, i.e., if the input voltage difference exists between
the two modules when there is a system input voltage perturbation, the difference will
neither to converge nor to diverge. However, the actual system is surely damped by the
parasitic resistance of the switches or inductors, so the perturbation will eventually
converge and the ISOP system with the wireless IVS control strategy will be stable
in practice.
4.4 Experimental Verification
In order to verify the theoretical analysis in the previous sections, we have constructed
the input-series-connected systems (ISOP and ISOS) prototype including three two-
transistor forward converter modules in lab, and the specifications of each module
are as follows:
• input voltage V in 100–150 Vdc,
• rated output current I o 5 A,
• switching frequency f s 100 kHz,
• gradient gain k up 5.68 × 10−3 ,
• sensing gain K vo 0.1.
4.4.1 Experimental Results of ISOP System
The specifications of ISOP system are: system input voltage 300–450 Vdc, system
output voltage 50 Vdc, system rated output current 15 A.
Figure 4.11 shows the voltages across the primary windings of the individual
transformers under normal input voltage (400 Vdc) and full load. It can be seen that all
the voltages have almost the same positive amplitudes, which means that the module
input voltages are equal and the module output current sharing automatically. It also
should be noted that the switching signals of the three modules are not interleaved
or synchronized to realize the goal of no control interconnection, and hence, the
C1: Vtr1 [100V/div]
C2: Vtr2 [100V/div]
C3: Vtr3 [100V/div]
C4: Vo [50V/div]
Time: [2μs/div]
Ave
Fig. 4.11 Voltages across the primary windings of individual transformers
55 165
50 150
Vin1 / Vin2 / Vin3 (V)

45 135
Vo (V)
40 120
Vo
Vin1
35 Vin2 105
Vin3
30 90
290 310 330 350 370 390 410 430 450
Vin (V)
Fig. 4.12 Measured system output voltage and three module input voltages
switching frequencies of the three modules are slightly different due to tolerance of
RC parameters, which determine the switching frequency.
Figure 4.12 shows the measured curves of system output voltage and input voltage
of each module when ISOP system input voltage varies from 300 to 450 Vdc. It can
be seen that the system output voltage increases with the increase of system input
voltage, and the output voltage regulation is 5.6% in the whole system input voltage
range from 300 to 450 Vdc. The three module input voltage curves are very close to
each other. Due to small mismatches in the controller parameters among the three
prototypes, such as reference voltages, voltage sensors, and operational amplifiers,
the measured maximum input voltage difference among the three modules is 4 Vdc.
C1: Vin1 [100V/div]
C2: Vin2 [100V/div]
C3: Vin3 [100V/div]
C4: Vo [50V/div]
Time: [10ms/div]
Ave Ave
Fig. 4.13 Responses in individual input voltages and output voltage for stepped system input
voltage
C1: Vin1 [100V/div]
C2: Vin2 [100V/div]
C3 Vin3 [100V/div]
C4: Io [10A/div]
Time: [4ms/div]
Ave Ave
Fig. 4.14 Responses in individual input voltages to stepped load
Figure 4.13 shows the experimental waveforms of the input voltages of the three
modules and the system output voltage corresponding to the system input voltage
stepping between 300 and 450 Vdc. Figure 4.14 shows the experimental waveforms
of the input voltages of the three modules corresponding to load stepping between
full load (15 A) and half load (7.5 A). It can be seen that input voltages are well
shared both at steady state and during transient and sharing of the output current is
achieved automatically.
C1: io1 [5A/div]
C2: io2 [5A/div]
C3: io3 [5A/div]
C4 Vo [50V/div]
Time: [40ms/div]
(a) Output currents of each module
C2: iLf2 [5A/div] C1: iLf1 [5A/div]
C3: iLf3 [5A/div]
C4: Vo [50V/div]
Time: [40ms/div]
(b) Output filter inductor currents of each module
Fig. 4.15 Responses in individual output currents and output filter inductor currents to stepped
load
Figure 4.15 shows the experimental waveforms of the output currents and out-
put filter inductor currents of the three modules corresponding to the load stepping
between full load (15 A) and half load (7.5 A). It can be seen that the load sharing is
achieved both at steady state and during transient.
In order to verify the redundancy of the ISOP system with the wireless IVS control
strategy (see Fig. 4.4), a fault is imitated in the three-module ISOP system by shorting
the input capacitor of one module with a switch in series with a 0.5 resistor, which
C1: Vin1 [100V/div]
C2: Vin2 [100V/div]
C3: Vin3 [100V/div]
C4: Vo [50V/div]
Time: [10ms/div]
Ave
(a) Module 1 is isolated
C1: Vin1 [100V/div]
C2: Vin2 [100V/div]
C3: Vin3 [100V/div]
C4: Vo [50V/div]
Time: [20ms/div]
Ave
(b) Module 1 is inserted
Fig. 4.16 Response of individual input voltages and output voltage when module 1 is isolated and
inserted, respectively
limits the discharging current of the capacitor. Figure 4.16 shows the system response
to a fault of module 1. Figure 4.16a shows the input voltages of the three modules and
the system output voltage corresponding to a short fault of module 1 under system
input voltage V in 310 Vdc and full load condition. It can be seen that the system
input voltage is evenly shared by the remaining two modules when the short switch
C1: vtr1 [100V/div] C2: vtr2 [100V/div]
Time : [4μs/div]
C4: Vo [100V/div] C3: vtr3 [100V/div]
Fig. 4.17 Voltages across the primary windings of individual transformers
is closed. The system output voltage increases slightly because the input voltage
changes from about 100–150 Vdc for module 2 and module 3 and the output voltage
increases according to the positive output voltage regulation.
Figure 4.16b shows the system response when module 1 is inserted into the system
by opening the short switch under system input voltage V in 310 Vdc and full
load condition. After opening the short switch, the input capacitor of module 1 is
charged by the system input current and the input voltage increases, and in the
meanwhile, the input voltages of modules 2 and 3 decrease. After a certain amount
of regulation time, the three modules share the system input voltage and the output
voltage is restored to be stable. The system output voltage decreases slightly because
the input voltage changes from about 155–100 Vdc for modules 2 and 3 and the
output voltage decreases according to the positive output voltage regulation. It can
be seen that without any control interconnection among the modules, redundancy in
combination with hot-swap capability of modules can be easily achieved.
4.4.2 Experimental Results of ISOS System
The specifications of ISOS system are: system input voltage 300–450 Vdc, system
output voltage 150 Vdc, system rated output current 5 A.
Figure 4.17 shows the experimental waveforms of the voltages across the primary
windings of individual transformers under normal input voltage (400 Vdc) and full
load. As seen, all the voltages have almost the same positive amplitudes, which means
that the module input voltages are equal.
Figures 4.18 and 4.19 show the experimental waveforms of the ISOS system
corresponding to stepped input voltage and stepped load, respectively. Figure 4.18
C1: Vin1 [100V/div]

C2: Vin2 [100V/div]
C3: Vin3 [100V/div]
C4: Vo [100V/div]
Time : [20 ms/div]
Ave Ave
(a) Individual input voltages and system output voltage
C1: Vin1 [100V/div]
C2: Vo1 [50V/div]
C3: Vo2 [50V/div]
C4: Vo3 [50V/div]

Time : [20 ms/div]
Ave
(b) Individual output voltages and input voltage of module 1
Fig. 4.18 Responses to stepped input voltage
shows the input voltages and output voltages of the three modules and the system’s
output voltage corresponding to an input voltage stepping between 300 and 450 Vdc
under full load condition. Figure 4.19 shows the input voltages and output voltages
of the three modules corresponding to a load stepping between half load (2.5 A)
and full load (5 A) when system input voltage is 400 Vdc. It can be seen that input
voltages are well shared both at steady state and during transient and the sharing of
the output voltage is achieved automatically.
C1: Vin1 [100V/div]
C2: Vin2 [100V/div]
C3: Vin3 [100V/div]
C4: Io [5A/div]
Time : [10 ms/div]
Ave
(a) Individual input voltages and output current
C1: Vo1 [50V/div]
C2: Vo2 [50V/div]
C3: Vo3 [50V/div]
C4: Io [5A/div]
Time : [10 ms/div]
Ave
(b) Individual output voltages and output current
Fig. 4.19 Responses to stepped load

4.5 Summary 105
4.5 Summary
In order to eliminate the control signal interconnection among the modules and
improve the system reliability, the wireless IVS control strategies based on positive
output voltage gradient method are proposed for the input-series-connected systems
in this chapter. Truly modular input-series-connected systems can be achieved with
the proposed control strategies, where all the modules are totally identical for both
power stages and control stages. Each module is self-contained and no extra super-
visory controller is needed to achieve the input voltage sharing among the modules.
Moreover, there is no any control interconnection among the modules, which con-
siderably increases the redundancy with the improved system reliability and main-
tainability. Experimental results of three-module ISOP and ISOS systems verify the
effectiveness of the wireless IVS control strategies.
References
1. Chen, W., Wang, G., Ruan, X., Jiang, W., Gu, W.: Wireless input-voltage-sharing control strategy
for input-series output-parallel (ISOP) system based on positive output-voltage gradient method.
IEEE Trans. Ind. Electron. 61(11), 6022–6030 (2014)
2. Chen, W., Wang, G.: Decentralized voltage sharing control strategy for fully modular input-
series output-series system with improved voltage regulation. IEEE Trans. Ind. Electron. 62(5),
2777–2787 (2015)
3. Giri, R., Choudhary, V., Ayyanar, R., Mohan, N.: Common-duty-ratio control of input-series
connected modular DC-DC converters with active input voltage and load-current sharing. IEEE
Trans. Ind. Appl. 42(4), 1101–1111 (2006)
Chapter 5
A General Control Strategy for DC–AC
Series–Parallel Power Conversion
Systems
Abstract For the DC–AC series–parallel power conversion systems, the output
power balance includes not only the equaling of the amplitude and frequency of
the modular output voltages and currents but also the equaling of the phase of them.
This means that the equilibrium of both the real and reactive powers should be actual-
ized. In the light of this perspective, this chapter first presents a systematical analysis
of the relationship between the input voltage/current sharing (IVS/ICS) and output
voltage/current sharing (OVS/OCS) of four kinds of DC–AC series–parallel power
conversion system. Then, the control strategies to achieve IVS/ICS and OVS/OCS
and the system stability are discussed. Finally, a general control strategy for the
DC–AC series–parallel power conversion system is presented.
Keywords DC–AC series–parallel power conversion systems

Input voltage sharing · Input current sharing · Output voltage sharing
Output current sharing · Stability · General control strategy
Similar to the DC–DC series–parallel power conversion systems, the DC–AC

series–parallel power conversion systems, which are composed of multiple DC–AC
inverter modules, can also be divided into four kinds, namely, input-parallel-output-
parallel (IPOP), input-parallel-output-series (IPOS), input-series-output-parallel
(ISOP), and input-series-output-series (ISOS). To guarantee normal operation of
these systems, power balance among the constituent DC–AC inverter modules should
be ensured. That is to say, input voltage sharing (IVS) and output voltage sharing
(OVS) should be achieved when the inverter modules are connected in series at the
input and output sides, respectively, and input current sharing (ICS) and output cur-
rent sharing (OCS) should be realized when the inverter modules are connected in
parallel at the input or output sides, respectively.
Different from the DC–DC converters, the output of the DC–AC inverters is in the
form of alternating current. Therefore, in the DC–AC series–parallel power conver-
sion systems, the output power balance includes not only the equaling of the ampli-
tude and frequency of the modular output voltages and currents but also the equaling
of the phase of them. This means that the equilibrium of both the real and reac-
tive powers should be actualized. In this chapter, the relationship between the input
108 5 A General Control Strategy for DC–AC Series–Parallel …
voltage/current sharing (IVS/ICS) and output voltage/current sharing (OVS/OCS) of

the four kinds of DC–AC series–parallel power conversion systems will be analyzed
systematically. Also, the control strategies to achieve IVS/ICS and OVS/OCS and the
stability are discussed. Then, a general control strategy for the four kinds of DC–AC
series–parallel power conversion system is proposed [1, 2].
5.1 Relationship Between Input Voltage/Current Sharing

and Output Voltage/Current Sharing
Figure 5.1 shows the four connection architectures of DC–AC series–parallel power
conversion system with n DC–AC inverter modules. As shown, for the jth module (j
1, 2, …, n), V in_j and I in_j denote the input voltage and the input current, respectively;
vo_j and io_j denote the output voltage and the output current, respectively; I cd_j and
icf_j denote the input and output filter capacitor currents, respectively; and I cin_j and
ico_j denote the input and output currents of the power stage. At steady state, since
both the input voltage and the output voltage are constant, the average values of
both the input filter capacitor current and the output filter capacitor current are zero.
Therefore, we have
Iin_ j Icin_ j ( j 1, 2, . . . , n) (5.1)

i o_ j i co_ j ( j 1, 2, . . . , n) (5.2)
Then, the input power of each DC–AC inverter module can be derived as
⎧
⎪
⎪ P Vin_1 · Iin_1
⎪ in1
⎪
⎪
⎨ Pin2 Vin_2 · Iin_2
(5.3)
⎪
⎪
..
⎪
⎪ .
⎪
⎩P
inn Vin_n · Iin_n
And the output real power and reactive power could be expressed as
⎧
⎪
⎪ Po1 Vo_1 · Io_1 · cos θ1
⎪
⎪
⎪
⎨ Po2 Vo_2 · Io_2 · cos θ2
(5.4)
⎪
⎪
..
⎪
⎪ .
⎪
⎩ Pon Vo_n · Io_n · cos θn
5.1 Relationship Between Input Voltage/Current Sharing … 109
Iin Iin_1 Icin_1 ico_1 io_1 io Iin Iin_1 Icin_1 ico_1 io_1 io
+ Icd_1 icf_1 + + + Icd_1
DC-AC vo DC-AC icf_1 +
Vin_1 Cd1 Cf1 vo_1 ZLd Vin_1 C C v
Vin _ inverter _ _ Vin d1
inverter f1 o_1
_
_ __
Module 1 Module 1
Iin_2 Icin_2 ico_2 io_2 Iin_2 Icin_2 ico_2 io_2
+ Icd_2 DC-AC icf_2 + + Icd_2 icf_2 + +
C C vo_2 DC-AC
Vin_2 d2
inverter f2 Vin_2 Cd2 Cf2 vo_2 ZLd vo
__ _ inverter _
__ _
Module 2 Module 2
Iin_n Icin_n ico_n io_n Iin_n Icin_n ico_n io_n

+ Icd_n DC-AC icf_n + + Icd_n icf_n +
Vin_n Cdn Cfn vo_n Vin_n DC-AC
inverter Cdn Cfn vo_n
_ _ _ inverter _
Module n Module n
(a) IPOP (b) IPOS

Iin Iin_1 Icin_1 ico_1 io_1 io Iin Iin_1 Icin_1 ico_1 io_1 io
+ Icd_1 icf_1 + + + Icd_1 icf_1 +
DC-AC vo DC-AC
Vin_1 Cd1 Cf1 vo_1 ZLd Vin_1 Cd1 Cf1 vo_1
__ inverter _ _ inverter _
__
Module 1 Module 1
Iin_2 Icin_2 ico_2 io_2 Iin_2 Icin_2 ico_2 io_2
+ Icd_2 icf_2 + + Icd_2 icf_2 + +
DC-AC DC-AC
Vin_2 Cd2 Cf2 vo_2 Vin_2 Cd2 Cf2 vo_2 ZLd vo
_
_ inverter _ _ inverter _ _
_
Vin Module 2
Vin Module 2
Iin_n Icin_n ico_n io_n Iin_n Icin_n ico_n io_n

+ Icd_n DC-AC icf_n + + Icd_n DC-AC icf_n +
Vin_n Cdn Cfn vo_n Vin_n Cdn Cfn vo_n
_ inverter _ _ inverter _
Module n Module n
(c) ISOP (d) ISOS
Fig. 5.1 Four connection architectures of DC–AC series–parallel power conversion system
⎧
⎪
⎪ Q o1 Vo_1 · Io_1 · sin θ1
⎪
⎪
⎪
⎨ Q o2 Vo_2 · Io_2 · sin θ2
(5.5)
⎪
⎪
..
⎪
⎪ .
⎪
⎩Q
on Vo_n · Io_n · sin θn
where V o_1 , V o_2 , …, V o_n are the root-mean-square (RMS) values of the output
voltage of each module; I o_1 , I o_2 , …, I o_n are the RMS values of the output current
of each module; and θ 1 , θ 2 , …, θ n are the output power factor angles of each module.
Suppose the efficiencies of the constituent module are equal and the values are
η. So, by power conservation, we have Po j η × Pin j ( j 1, 2, . . . , n). Then,
combining (5.3) and (5.4), we can get
⎧
⎪
⎪ V · I · cos θ1 Vin_1 · Iin_1 · η
⎪ o_1 o_1
⎪
⎪
⎨ Vo_2 · Io_2 · cos θ2 Vin_2 · Iin_2 · η
(5.6)
⎪
⎪
..
⎪
⎪ .
⎪
⎩ Vo_n · Io_n · cos θn Vin_n · Iin_n · η
5.1.1 IPOP Systems
As shown in Fig. 5.1a, for DC–AC IPOP systems, the input voltage and the output
voltage are equal, respectively, i.e., Vin_1 Vin_2 · · · Vin_n , and vo_1 vo_2
· · · vo_n . If input current sharing (ICS) among the DC–AC inverter modules is
achieved, we have Iin_1 Iin_2 · · · Iin_n . Substitution of these three equations
into (5.6) leads to
Io_1 · cos θ1 Io_2 · cos θ2 · · · Io_n · cos θn (5.7)
According to (5.7), if we wish to realize output current sharing (OCS) among the
constituent DC–AC inverter modules, i.e.,
i o_1 i o_2 · · · i o_n (5.8)
One of the following conditions should be satisfied, i.e.,
Io_1 Io_2 · · · Io_n (5.9)

θ1 θ2 · · · θn (5.10)
That is to say, according to (5.7), if (5.9) is valid, then (5.10) is valid; or if (5.10)
is established, then (5.9) is established.
According to the above analysis, it can be concluded that achieving ICS among
the constituent modules can only ensure that the output real powers of the modules
in IPOP systems are equal, and the reactive powers among the modules could not be
guaranteed. In order to ensure the reactive powers among the modules are equal, the
condition (5.9) or (5.10) should be valid, i.e., the amplitudes or phases of the output
currents of the inverter modules should be equal. Thus, OCS could be ensured. This
is quite different from that of DC–DC IPOP systems since the output of DC–DC
converter is in the form of direct current and only the real power is involved.
On the other hand, for the DC–AC IPOP systems, if OCS is ensured, (5.9) and
(5.10) are valid. Substituting these two equations together with Vin_1 Vin_2 · · ·
Vin_n and vo_1 vo_2 · · · vo_n into (5.6) leads to Iin_1 Iin_2 · · · Iin_n ,
which means that ICS is achieved.
5.1.2 IPOS Systems
As shown in Fig. 5.1b, for IPOS systems, the input voltages and the output currents
of the constituent modules are equal, respectively, i.e., Vin_1 Vin_2 · · · Vin_n ,
and i o_1 i o_2 · · · i o_n . If ICS of the constituent modules is achieved, we have
Iin_1 Iin_2 · · · Iin_n . Substitution of these three equations into (5.6) yields
Vo_1 · cos θ1 Vo_2 · cos θ2 · · · Vo_n · cos θn (5.11)
From (5.11), if OVS among the modules are expected, i.e.,
vo_1 vo_2 · · · vo_n (5.12)
One of the following equations should be satisfied, i.e.,
Vo_1 Vo_2 · · · Vo_n (5.13)

θ1 θ2 · · · θn (5.14)
That is to say, according to (5.11), if (5.13) is valid, then (5.14) is valid; or if

(5.14) is established, then (5.13) is established.
According to the above analysis, it can be concluded that achieving ICS among
the modules can only ensure the output real powers of the modules in IPOS systems
are equal, but the equaling of the reactive powers of the modules could not be guar-
anteed. For the purpose of ensuring the reactive powers of the modules are equal, the
condition (5.13) or (5.14) should be valid, i.e., the amplitudes or phases of the output
voltage of the modules should be equal. Thus, OVS could be guaranteed. This is
quite different from DC–DC IPOS systems since the outputs of DC–DC converters
are in the form of direct current and only real power is considered.
On the other hand, for DC–AC IPOS systems, if OVS among the constituent
modules is ensured, (5.13) and (5.14) are valid. Substituting these two equations
together with Vin_1 Vin_2 · · · Vin_n and i o_1 i o_2 · · · i o_n into (5.6), we
can obtain Iin_1 Iin_2 · · · Iin_n , which means that ICS is achieved.
5.1.3 ISOP Systems
As shown in Fig. 5.1c, for ISOP systems, the input currents and the output voltages
of the modules are equal, respectively, i.e., Iin_1 Iin_2 · · · Iin_n , and vo_1
vo_2 · · · vo_n . If IVS among the constituent modules is achieved, we have
Vin_1 Vin_2 · · · Vin_n . Substitution of these three equations into (5.6) yields
Io_1 · cos θ1 Io_2 · cos θ2 · · · Io_n · cos θn (5.15)

From (5.15), if we intend to achieve OCS among the modules, i.e.,
i o_1 i o_2 · · · i o_n (5.16)
Io_1 Io_2 · · · Io_n (5.17)

θ1 θ2 · · · θn (5.18)
That is to say, according to (5.15), if (5.17) is valid, then (5.18) is valid and vice
versa.
According to the above analysis, it can be concluded that achieving IVS among
the modules can only ensure the module output real powers are equal, but the module
reactive powers could not be guaranteed. If the condition (5.17) or (5.18) is valid, i.e.,
the amplitudes or phases of the output currents of the modules are equal, the module
reactive powers could be equal, thus achieving OCS [1]. This is quite different from
that of DC–DC ISOP system in which only the real power is involved.
On the other hand, for DC–AC ISOP systems, if OCS among the modules is
ensured, both (5.17) and (5.18) are valid. Substituting these two equations together
with Iin_1 Iin_2 · · · Iin_n and vo_1 vo_2 · · · vo_n into (5.6), we can get
Vin_1 Vin_2 · · · Vin_n , which means that IVS is achieved.
5.1.4 ISOS Systems
As shown in Fig. 5.1d, for ISOS system, the input currents and the output currents
of the modules are equal, respectively, i.e., Iin_1 Iin_2 · · · Iin_n , and i o_1
i o_2 · · · i o_n . If IVS among the modules is achieved, we have Vin_1 Vin_2
· · · Vin_n . Substitution of these three equations into (5.6) leads to
Vo_1 · cos θ1 Vo_2 · cos θ2 · · · Vo_n · cos θn (5.19)
From (5.19), if OVS among the modules is expected, i.e.,
vo_1 vo_2 · · · vo_n (5.20)
Vo_1 Vo_2 · · · Vo_n (5.21)

θ1 θ2 · · · θn (5.22)
That is to say, according to (5.19), if (5.21) is valid, then (5.22) is valid; or if

(5.22) is established, then (5.21) is established.
According to the above analysis, it can be concluded that achieving IVS among
the modules can only ensure the module output real powers are equal, but the module
reactive powers could not be guaranteed. If the condition (5.21) or (5.22) is valid,
i.e., the amplitudes or phases of the output voltages of the modules are equal, the
module reactive powers could be equal, achieving OVS [2]. This is quite different
from that of DC–DC ISOS systems which have only real power.
On the other hand, for DC–AC ISOS systems, if OVS among the modules is
ensured, both (5.21) and (5.22) are valid. Substituting these two equations together
with Iin_1 Iin_2 · · · Iin_n and i o_1 i o_2 · · · i o_n into (5.6), we can get
Vin_1 Vin_2 · · · Vin_n , which means that IVS is achieved.
According to the above analysis, we can find that, for DC–AC series–parallel
power conversion systems, achieving IVS/ICS among the constituent modules can
only ensure the module output real powers are equal, but the equaling of the module
reactive powers could not be guaranteed. In order to achieve the output reactive power
equilibrium, in addition to achieving IVS/ICS, the amplitudes or phases of the module
output currents (in IPOP and ISOP systems) or the amplitudes or phases of the module
output voltages (in IPOS and ISOS systems) should be ensured. Hereinafter, the
control strategy that controls IVS/ICS and makes the amplitudes or phases of module
output currents or module output voltages be equal is defined as the compound
balanced control strategy [1, 2]. On the other hand, for DC–AC series–parallel power
conversion systems, if OVS/OCS among the modules could be guaranteed, IVS/ICS
will be ensured automatically.
5.2 Stability of the Control Strategies for DC–AC

Series–Parallel Power Conversion Systems
It is pointed out in Chap. 2 that, for DC–DC series–parallel power conversion systems,
if IVS/ICS among the modules could be guaranteed, OVS/OCS will be ensured
automatically, and vice versa. Moreover, it is further pointed out that the IVS/ICS
control strategy could ensure the stable operation of all of four kinds of DC–DC
series–parallel power conversion systems including IPOP, IPOS, ISOP, and ISOS
systems. While the OVS/OCS control strategy could ensure the stable operation
of the input-parallel-connected systems (including IPOP and IPOS systems), the
operation of the input-series-connected systems (including ISOP and ISOS systems)
is unstable. So, do the DC–AC series–parallel power conversion systems have the
similar characteristics as mentioned above? In this section, we examine the stability
of the systems with the possible control strategies discussed in Sect. 5.1. Before the
analysis, we suppose that the system’s input voltage, output voltage, and load current
are kept unchanged when perturbations are imposed on the input voltage/current and
output voltage/current of the modules, and the modules have the same efficiency.
5.2.1 Compound Balanced Control Strategy
Regardless of the connection type at the input side of the DC–AC series–parallel
power conversion system, if the compound balanced control strategy is adopted,
each DC–AC inverter module behaves as a constant power source as seen at the
output side, as shown in Fig. 5.2, and the modular input powers are equal.
For the case where the output sides are connected in parallel, as shown in Fig. 5.2a,
the output voltages of all the modules are equal. With the compound balanced control
strategy, both the module output real powers and reactive powers are, respectively,
equal. Thus, the module output currents are identical. So, no perturbation occurs,
i.e., the system is stable.
For the case where the output sides are connected in series, as shown in Fig. 5.2b,
the output currents of all the modules are equal. Assume that a perturbation occurs
in the output voltages of some two modules, e.g., the amplitude of vo_1 increases
and the amplitude of vo_2 decreases (here we suppose the scheme of controlling the
phase of output voltages to be equal is adopted), while the output voltages of other
modules are unchanged. Since the system output current io is unchanged, the rise
of the amplitude of vo_1 makes module 1 output more real power than other inverter
modules. Hence, the output filter capacitor C f1 will be discharged, making the voltage
amplitude of module 1 descend and return to the equilibrium point. In the meanwhile,
the output filter capacitor C f2 will be charged, and the voltage amplitude of module
2 will increase and returns to the equilibrium point.
In conclusion, with the compound balanced control strategy, all the four series—
parallel power conversion systems could work stably.
ico_1 io_1 io ico_1 io_1 io

+ +
Constant icf_1 + Constant icf_1 +
Power Source vo_1 ZLd vo Power Source vo_1
(Inverter 1) Cf1 _ _ (Inverter 1) Cf1 _
ico_2 io_2 ico_2 io_2

Constant icf_2 + Constant icf_2 +
Power Source vo_2 Power Source vo_2 ZLd vo
(Inverter 2) Cf2 _ (Inverter 2) Cf2 _
ico_n io_n ico_n io_n

Constant icf_n + Constant icf_n +
Power Source vo_n Power Source vo_n
(Inverter n) Cfn _ (Inverter n) Cfn _ _
(a) Output sides connected in parallel (b) Output sides connected in series
Fig. 5.2 Equivalent schematic diagrams for the compound balanced control strategy
5.2 Stability of the Control Strategies for DC–AC Series–Parallel … 115
Iin Iin_1 Icin_1 Iin Iin_1 Icin_1

Vin_1 Power Sink Vin_1 Power Sink
Vin _ Cd1 (Inverter 1) _ Cd1 (Inverter 1)
Iin_2 Icin_2 Iin_2 Icin_2

Vin_2 Power Sink Vin_2 Power Sink
_ Cd2 (Inverter 2) Vin _ Cd2 (Inverter 2)
Iin_n Icin_n Iin_n Icin_n

+ Icd_n Constant + Icd_n Constant
Vin_n Power Sink Vin_n Power Sink
_ Cdn (Inverter n) _ Cdn (Inverter n)
(a) Input-parallel-connected systems (b) Input-series-connected systems
Fig. 5.3 Equivalent schematic diagrams for the output side control strategy
5.2.2 Output Voltage/Current Sharing (OVS/OCS) Control

Strategy
Regardless of the connection type at the output side for the DC–AC series–paral-
lel power conversion systems, if the OVS/OCS control strategy is employed, each
inverter module behaves as a constant power sink as seen at the input side, as shown
in Fig. 5.3, and the modular output powers are equal (which means the active and
reactive powers are, respectively, equal). It is noted that we can only see the input
real power at the input side, so we could draw the same conclusion with the DC–DC
series–parallel power conversion systems, i.e., the OVS/OCS control strategy could
ensure stable operation of the input-parallel-connected systems (including IPOP and
IPOS systems), but the operation of the input-series-connected systems (including
ISOP and ISOS systems) are unstable. The detailed analysis has been given in Sect.
2.2.2 in Chap. 2 and it is not repeated here.
5.3 General Voltage/Current Sharing Control Strategy

for DC–AC Series–Parallel Power Conversion Systems
According to the analysis of the above two sections, we can draw the following
conclusions:
1. For the input-parallel-connected DC–AC systems (including IPOP and IPOS
systems), both compound balanced control strategy and OVS/OCS control strat-
Fig. 5.4 Main circuit of Lf iLf

buck-derived inverter
+ iCf io +
Vin vinv Cf vo
ZLd
– –
egy could ensure stable operation of the systems. With the compound balanced
control strategy, the amplitudes or phases of the modular output currents (for
IPOP system) or modular output voltages (for IPOS system) should be guaran-
teed together with controlling for ICS among the modules. Compared with the
OVS/OCS control strategy, the compound balanced control strategy is quite com-
plicated. Thus, the OCS control strategy is more convenient for DC–AC IPOP
systems, and the OVS control strategy is preferred for IPOS DC–AC systems.
2. For the input-series-connected DC–AC systems (including ISOP and ISOS sys-
tems), OVS/OCS control strategy could not ensure stable operation of the sys-
tems. So, we can only adopt the compound control strategy, i.e., the equaling of
the amplitude or phase of modular output current (for ISOP system) or modular
output voltage (for ISOS system) should be guaranteed together with controlling
for IVS among the modules.
Regardless of the type of the connection architectures, at least two control loops are
needed. One is the output voltage loop for regulating the system output voltage, and
the other one is the input voltages/currents or output voltages/currents sharing loop,
which will be referred to as voltage/current sharing loop hereinafter. With the buck-
derived inverter as the basic module, as shown in Fig. 5.4, a general voltage/current
sharing control strategy for four kinds of DC–AC series–parallel power conversion
systems is proposed, as shown in Fig. 5.5. Likewise, the general voltage/current shar-
ing control strategy for the DC–AC series–parallel power conversion systems with
boost-derived or buck–boost-derived converter as the basic module can be derived,
and it is not repeated here.
The general control strategy includes three closed loops, namely, the system output
voltage loop, which is common for all the inverter modules, the voltage/current
sharing loop, and the current inner loop of each module. Different from the two-
loop control for the DC–DC series–parallel power conversion systems in Sect. 2.3
in Chap. 2, the current inner loop of each module is introduced here. This is because
the equaling of the amplitude or phase of modular output current (for ISOP system)
or modular output voltage (for ISOS system) should be guaranteed except for IVS
among the constituent modules for the purpose of achieving the power balance for the
input-series-connected DC–AC power conversion systems (including ISOP and ISOS
systems). In order to make the phase of output current (for ISOP system) or output
voltage (for ISOS system) of each module identical, the output of the voltage/current
sharing loop of each module is multiplied by the output of the common system output
voltage loop. In the three-loop control strategy, the system output voltage loop aims
5.3 General Voltage/Current Sharing Control Strategy … 117
Voltage/current sharing loop

Vsh_g _ V if_1
sh_f 1 _
+ −/+ + Current SPWM Drive
Gsh
+ iref1 regulator 1 modulator signal 1
vsh_EA1 ish_EA1
_ Vsh_f 2 if_2
_
Gsh
+ iref2 regulator 2 modulator signal 2
vsh_EA2 ish_EA2
…
…
_ Vsh_f (n−1) if_(n−1)
_
Gsh
+ iref(n−1) regulator (n−1) modulator signal (n−1)
vsh_EA(n−1) ish_EA(n−1)
_ Vsh_f n if_n
_
Gsh
+ irefn regulator n modulator signal n
vsh_EAn ish_EAn
+ io_ j ISOP and IPOP

Gvo
voref _ iref if_ j iCf_ j IPOS and ISOS
vof − ISOP and ISOS iLf_ j Four kinds of system
−/+
System output voltage loop + IPOP and IPOS (j = 1, 2, …, n)
Fig. 5.5 General voltage/current sharing control strategy for DC–AC series–parallel power con-
version systems
for regulating the system output voltage, and its output signal, iref , serves as the initial
common reference for all the inner current loops. The voltage/current sharing loop
of each module adjusts the magnitude of iref , leading to the final current reference
for each module, irefj (j 1, 2, …, n).
For the voltage/current sharing loop shown in Fig. 5.5, V sh_g represents the aver-
age value of the total system input/output voltage/current, and V sh_fj (j 1, 2, …, n)
represents the sensed input or output variable of each module. The representations
of V sh_g and V sh_fj for the four kinds of DC–AC series–parallel power conversion
systems are given in Table 5.1. As shown in Table 5.1, for the input-series-connected
DC–AC power conversion systems, V sh_g is V in /n, and V sh_fj is the sensed input
voltage of each module; While for the input-parallel-connected DC–AC power con-
version systems, if the compound balanced control is adopted, V sh_fj is I cin_j , and if
the output side control is employed, V sh_fj is vo_j for IPOS system and io_j for IPOP
system. Furthermore, for the IPOP system, if io_j is taken as the feedback signal of
each current inner loop, all the module output currents will track the common cur-
Table 5.1 Representation of V sh_fj and V sh_g in four connection architectures

Architecture V sh_fj (j = 1, 2, …, n) V sh_g
IPOP I cin_j I in /n
IPOS I cin_j or vo_j I in /n or vo /n
ISOP V in_j V in /n
ISOS V in_j V in /n
rent reference iref , and OCS will be achieved without any additional voltage/current
sharing loop. Thus, the voltage/current sharing loop could be removed.
For the inner current loop of each module in Fig. 5.5, the current feedback signal
if_j can be the output current io_j , the output filter inductor current iLf_j , and the
output filter capacitor current iCf_j (j 1, 2, …, n) of each module. With different
current feedback signals, the sharing of the output voltage/current for the four DC–AC
series–parallel power conversion systems will be different. For example, for the ISOP
system, if the output filter inductor current is chosen as the feedback signal, the
sharing of the output filter inductor current is achieved, and there is output reactive
power difference among the modules when the output filter capacitors are not well
matched; and if the output current is chosen as the feedback signal, OCS could be
achieved even if the output filter capacitors are not well matched [1]. This issue will
be discussed in detail in Chap. 6. For the ISOS system, if the output filter inductor
current is selected as the feedback signal, there is output reactive power difference
among the modules when the output filter capacitors are not well matched; and if the
output filter capacitor current is selected as the feedback signal, the sharing of the
output voltage will be ensured no matter the output filter capacitors are matched or
not [2], which will be elaborated specifically in Chap. 7.
5.4 Summary
This chapter systematically analyzes the inherent relationships between the input
voltages/current sharing and output voltages/current sharing of the DC–AC series—
parallel power conversion systems from the view of power conservation, and dis-
cusses the system stability with the compound balanced control strategy and output
side control strategy. Then, a general voltage/current sharing control strategy is pro-
posed for the DC–AC series–parallel power conversion systems.
(1) For the DC–AC series–parallel power conversion systems, controlling for the
input voltage/current sharing (IVS/ICS) among the constituent modules can only
ensure the equaling of the output real power of each module, but the equaling of
the reactive power could not be guaranteed, i.e., output voltage/current sharing
(OVS/OCS) among the constituent modules could not be achieved. This is quite
5.4 Summary 119
different from the DC–DC series–parallel power conversion systems since it

only has the real power at the output sides.
(2) For the DC–AC series–parallel power conversion systems, controlling at the
output sides to achieve output voltage/current sharing (OVS/OCS) among the
modules can ensure the module output real and reactive powers are equal, respec-
tively. As a consequence, the input power balance among the modules is guar-
anteed, and the input voltage/current sharing (IVS/ICS) is achieved. This is the
same as DC–DC series–parallel power conversion systems.
(3) For the DC–AC series–parallel power conversion systems, the control strategy
that controls the input voltage/current sharing (IVS/ICS) and makes the ampli-
tudes or phases of module output currents or module output voltages be equal is
defined as the compound balanced control, which can ensure stable operation,
and the output side control strategy can only guarantee stable operation of the
input-parallel-connected systems (including IPOP and IPOS systems) but can-
not guarantee stable operation of the input-series-connected systems (including
ISOP and ISOS systems).
(4) For the input-parallel-connected DC–AC power conversion systems (including
IPOP and IPOS systems), both the compound balanced control strategy and
output voltage/current sharing control strategy are effective. Compared to the
compound balanced control strategy, the output voltage/current sharing con-
trol is quite simple and it is usually employed. For the input-series-connected
DC–AC power conversion systems (including ISOP and ISOS systems), only
the compound balanced control strategy could be adopted, that is, the equaling
of the amplitude or phase of the modular output current (for ISOP system) or
modular output voltage (for ISOS system) should be guaranteed together with
the control for achieving input voltage sharing (IVS) among the modules.
References
1. Chen, W.: Research on series-parallel conversion systems consisting of multiple converter mod-
ules (in Chinese). Ph.D. Dissertation, Nanjing University of Aeronautics and Astronautics, Nan-
jing, China (2009)
2. Fang, T.: Control strategies for input-parallel-output-parallel and input-series-output-series con-
nected combined inverter systems (in Chinese). Ph.D. Dissertation, Nanjing University of Aero-
nautics and Astronautics, Nanjing, China (2008)
Chapter 6
Compound Balanced Control Strategy
for DC–AC Input-Series Output-Parallel
Systems
Abstract In this paper, the implementation of the compound balanced control strat-
egy is presented for the DC–AC input-series output-parallel (ISOP) systems to
achieve input voltage sharing (IVS) and output current sharing (OCS). The inductor
current and the output current adopted as the feedback variables for the inner current
loop of each module, respectively, is analyzed and compared. Taking the output-
current-feedback scheme as an example, the decoupling relationship between the
control loops is analyzed and the design of the control loops is given. The simulation
and experimental results are provided to verify the effectiveness of the proposed
control method. Furthermore, this chapter presents a new solution dedicated to dis-
tributed configuration on the basis of centralized control, which can improve the
reliability of the systems.
Keywords Input-series output-parallel system

Compound balanced control strategy · Input voltage sharing
Output current sharing · Closed-loops design
DC–AC input-series-connected systems (including DC–AC ISOP systems and

DC–AC ISOS inverter systems) are very suitable for high input DC voltage appli-
cations such as the urban railway systems, ship-electric-power-distribution systems,
high-speed railway electrical systems, etc. The DC–AC input-series-connected sys-
tems have the following advantages: (1) easy selection of power switches due to the
reduced voltage stress, (2) easy design due to the reduced power level of individual
modules, and (3) high modularity and reliability [1, 2]. The DC–AC ISOP systems
is quite suitable for high input voltage and high output current power conversion
applications, and the primary control objective of the systems is to ensure input volt-
age sharing (IVS) and output current sharing (OCS) for all the constituent modules.
Unlike DC–DC ISOP system, OCS for DC–AC ISOP system means both the mag-
nitudes and phases of the modular output currents are equal due to AC output of
DC–AC ISOP systems.
In Chap. 5, it is pointed out that DC–AC ISOP system needs to adopt the compound
balanced control strategy, i.e., to achieve IVS while ensuring that the magnitudes
or phases of modular currents are equal. In this chapter, the implementation of the
122 6 Compound Balanced Control Strategy for DC–AC …
compound balanced control strategy is presented first. In this method, either the
inductor current or the output current can be adopted as the feedback variable for
the inner current loop. The comparative analysis shows that the method adopting the
output current as the feedback variable can realize IVS and OCS unconditionally.
Then, taking the output-current-feedback method as an example, the decoupling
relationship between the control loops is analyzed and the loop design procedure
is given. Finally, the simulation and experimental results are provided to verify the
effectiveness of the proposed control method. Furthermore, this chapter put forward
a new solution dedicated to distributed configuration on the basis of centralized
control, which can improve the reliability of the systems.
6.1 DC–AC Inverter Topology for the ISOP Systems
In the DC–AC ISOP systems, the DC–AC inverter modules are connected in series
at the input side and in parallel at the output side. This requires the DC–AC inverter
modules that should have the function of galvanic isolation, which could be realized
by a low-frequency transformer or a high-frequency transformer [3–5] as shown in
Fig. 6.1.
As shown in Fig. 6.1a, a line-frequency transformer is introduced at the output
side of the DC–AC inverter. In addition to galvanic isolation, this transformer can
step up/down the output voltage. However, the line-frequency transformer is bulky
and heavy since the frequency is quite low, which is 50 Hz or 60 Hz.
As shown in Fig. 6.1b, the isolated DC–AC inverter is a two-stage configuration.
The first stage is an isolated DC–DC converter, which converts a DC input voltage
* * +
DC-AC vo
Inverter
Vin Line-Frequency _
Transformer
(a) Galvanic isolation realized by alow-frequency transformer

* * +
DC-AC
vo
Vin DC-DC Converter Inverter
with High-Frequency
Transformer _
(b) Galvanic isolation realized by ahigh-frequency transformer
Fig. 6.1 Isolated DC–AC inverter

6.1 DC–AC Inverter Topology for the ISOP Systems 123
into a regulated DC output voltage. Since the DC–DC converter is operated at high
frequency, the transformer is quite small and light. The second stage is a DC–AC
inverter, which converts the DC voltage obtained from the first stage into an AC output
voltage. With the two-stage configuration, the DC–DC converter and DC–AC inverter
could be optimally designed separately, and it is also contributed to the integration
and modularization of the system. So, the high-frequency isolated inverter is chosen
here as the basic inverter module.
The isolated DC–DC converters can be buck-derived, boost-derived, and buck-
boost-derived ones. The buck-derived isolated DC–DC converters include forward,
push-pull, half-bridge, full-bridge, etc. For the full-bridge converter, the power
switches only sustains the input voltage, the utilization rate of the magnetic core
is high, and it is suitable for medium-to-high power conversions. When employing
the phase-shift control, the full-bridge converter could realize soft-switching of the
power devices, leading to reduced switching loss and thus high conversion efficiency
[6]. So, the phase-shifted full-bridge converter is adopted here for the DC–DC stage.
Full-bridge inverter is suitable for high power applications and it can output high
quality voltage since three voltage levels are available. Therefore, the full-bridge
inverter is used here as the DC–AC stage. Figure 6.2 shows the main circuit of the
two-stage inverter module.
Module 1
Full-Bridge DC-DC Converter Ldc1 Full-Bridge Inverter
Iin iin1 iLdc1

Lf1
Q1 Q3 DR1 DR3 S1 S3 io1 io
icd1 Tr
+ A1 + iLf1 iCf 1 +
+
*
*
Vdc1 vinv1 vo
vin1 Cdc1 ZLd
Cd1 _ _ Cf1 _
_ B1
Q2 Q4 DR2 DR4 S2 S4
Vin
iin2
icd2
+
…
vin2 Module 2
Cd2 _
…
iinn
icdn
+
vinn Module n
Cdn _
Fig. 6.2 Main circuit of DC–AC ISOP system

6.2 Implementation of the Compound Balanced Control

Strategy
Figure 6.3 shows the block diagram of the compound balanced control strategy for
the DC–AC ISOP systems [7], which has three control loops, namely the common
system output voltage loop, the input voltage sharing (IVS) loop, and the inner current
loop for each inverter module. In Fig. 6.3, K vi is the sensor gain of module input
voltage, K io is the sensor gain of module output current, K vo is the sensor gain of
the system output voltage, Ginv is the transfer function from the modulating signal to
the voltage across the phase-leg mid-points of the inverter, Gvo is the system output
voltage regulator, Gvcd is the IVS regulator, and Gi is the inner current loop regulator.
The system output voltage loop aims for regulating the system output voltage. The
output of Gvo provides the common initial current reference iref for all the inner
current loops. The IVS loop is used to achieve IVS among the constituent inverter
modules. Generated by Gvcd , the dc deviation signal ivdj (j 1, 2, …, n) along with
the initial current reference iref are sent to the multiplier to obtain the IVS regulating
signal isvj (j 1, 2, …, n), which is then superimposed on the initial current reference
iref to obtain irefj , which serves as the actual current reference of respective modules.
The output current of each module follows irefj , and thus the module output current
amplitude is regulated and the equivalence of the power factor of the module output
current is also ensured. It can be seen that the control scheme can realize IVS and
synchronization of the output current phase of each inverter module simultaneously,
and consequently, IVS and OCS of the system can be achieved.
At steady state, the compound balanced control strategy can realize IVS and
OCS of each inverter module for the DC–AC ISOP system. Suppose a perturbation
occurs to cause the variation of the input-dividing capacitor voltage. For example,
vin1 ascends with its value higher than that of the average input voltage V in /n, which
will result in the decrease of the output of IVS regulator ivd1 and the increase of
the amplitude of corresponding current reference iref1 . Then, the amplitude of output
current io1 traces that of iref1 to rise, which will result in the rise of the output active
power of module 1. Therefore, the input power of module 1 will also increase and
so is the input current iin1 , i.e., iin1 > iin . Since the input-dividing capacitor current
icd1 equals to iin − iin1 , it is obvious that icd1 < 0, which means that the capacitor C d1
is discharged and vin1 will decrease until it returns to V in /n. On the other hand, if a
perturbation leads to the descent of input voltage of some module with its value less
than V in /n, the input voltage will also be adjusted and ultimately rise back to V in /n.
It can be seen that the compound balanced control strategy could also achieve IVS
and OCS at dynamic state.
It is noteworthy that the feedback signal of modular inner current loop in the
control strategy proposed in Fig. 6.3 is the output current ioj , and it also could be the
output filter inductor current iLfj . The DC–AC ISOP systems uses different current
feedback signal will get different OCS effect. If the output filter inductor current
feedback is adopted [8], that is, the output filter inductor current of each module is
employed as the inner current loop feedback on the basis of IVS, the output filter
6.2 Implementation of the Compound Balanced Control Strategy 125
IVS Loop Inner Current Loop iCf1

iref1 _ _ sCf1
+ ivd1 isv1 + + 1 iLf1 io1
Kvi _ Gvcd _ Gi Ginv
Vin + _ vinv1 sLf1 +
n vin1
Kvi
Kio
IVS Loop Inner Current Loop iCf2

iref2 _ _ sCf2
+ ivd2 isv2 + + 1 iLf2 io2
vin2 + _ vinv2 sLf2 +
Kvi
Kio
+ io
…
+ vo
…
ZLd
…
+
IVS Loop Inner Current Loop iCfn
irefn _ _ sCfn
+ ivdn isvn + + 1 iLfn ion
vinn + _ vinvn sLfn +
Kvi
Kio
+ iref
voref _ Gvo
Kvo
Output Voltage Loop
Fig. 6.3 Block diagram of compound balanced control strategy for DC–AC ISOP system
capacitor of each inverter module needs to be identical to ensure OCS (which means
the equivalence of both the active and reactive current). However, the output filter
capacitors of different modules are not matched in the actual prototype. In order to
simplify the analysis, a two-module DC–AC ISOP system is taken as an example
to analyze the effect of unmatched output filter capacitors on the sharing of output
current.
The equivalent circuit of two-module DC–AC ISOP system is shown in Fig. 6.4,
where it is supposed that C f1 > C f2 . Figure 6.5a shows the phasor diagram of voltages
and currents of two-module DC–AC ISOP system with output filter inductor current
feedback, and here, the output filter inductor currents of two inverter modules are
equal, i.e.,
I˙Lf1 I˙Lf2 (6.1)
From Fig. 6.4, we have
I˙o1 I˙Lf1 − I˙Cf1 (6.2a)

I˙o2 I˙Lf2 − I˙Cf2 (6.2b)
Combining (6.1) with (6.2a, 6.2b), we have

Fig. 6.4 Equivalent circuit of two-module DC–AC ISOP system
· ·
ILf1–ILf2
· ·
ICf2 ICf1
· · ·
Io1–Io2 · ICf1
· ICf2
0 Vo
· ·
Io1 0 Vo
(a) With output filter inductor current feedback (b) With output current feedback
Fig. 6.5 Phasor diagrams for different current feedback
I˙o1 − I˙o2 I˙Cf2 − I˙Cf1 jωo (Cf2 − Cf1 )V̇o (6.3)
where ωo is the fundamental angular frequency of the inverter system.

Since C f1 > C f2 , it can be derived from (6.3) that the output current difference
of the two inverter modules, I˙o1 − I˙o2 , lags the output voltage V̇o by 90°, and the
inductive reactive power is presented at the output side of the system. On the contrary,
the capacitive reactive power will be presented if C f1 < C f2 . So, it can be seen that the
unmatched output filter capacitors induce the reactive circulating current between
the inverter modules and OCS cannot be truly realized when the output filter inductor
current feedback control is adopted.
For DC–AC ISOP systems, if the output current feedback is adopted directly [7],
that is, the output current of each inverter module is used instead of the output filter
inductor current as the feedback of the inner current loop of the inverter module on
the basis of IVS, whether the output filter capacitors are matched or not will have no
effects on OCS (which means both the active and reactive currents of the modules
are equal, respectively). Figure 6.5b shows the phasor diagram of the voltages and
currents of two-module DC–AC ISOP system with the output current feedback con-
trol, and here we have I˙o1 I˙o2 at steady state. Thus, it can be derived from (6.2)
that I˙Lf1 − I˙Lf2 I˙Cf1 − I˙Cf2 jωo (Cf1 − Cf2 )V̇o . Since C f1 > C f2 , the difference
of the output filter inductor currents of two inverter modules will lead the output
voltage V̇o by 90°, and the capacitive reactive power is presented at the output side
of the system. On the contrary, the inductive reactive power will be presented if C f1
< C f2 .
Through the above analysis, we can find that for the DC–AC ISOP systems, when
the output filter inductor current feedback control is adopted, OCS can be achieved
Comparator
+
Vdcg _ Gvdc − Phase-Shifted
Drive Signals
+ Control Circuit
VRAMP
Vdcj Kvdc
Fig. 6.6 Closed-loop control block diagram of full-bridge converter as the first stage
only if the output filter capacitors are matched. If the output current feedback control
is employed, OCS could be truly achieved whether the output filter capacitors are
matched or not.
6.3 Closed-Loops Design for DC–AC ISOP Systems
Taking the output current feedback control given in Sect. 6.2 as an example, the
relationship of the control loops and the design of the control loops will be presented.
As shown in Fig. 6.3, the compound balanced control strategy includes three
closed loops, namely the system output voltage loop, IVS loop, and inner current
loop. In addition, for the phase-shifted full-bridge converter as the first stage of
each module, Fig. 6.6 shows the control block diagram, where the output voltage of
the full-bridge converter, V dcj , is sensed with the sensor gain of K vdc , and then is
compared with voltage reference V dcg , and the error is sent into the output voltage
regulator Gvdc . The output of Gvdc is compared with the sawtooth carrier V RAMP , and
the output of the comparator is sent to the phase-shifted control circuit, generating
the drive signals.
6.3.1 Decoupling Relationship Between IVS Loop

and Output Voltage Loop
As seen from Fig. 6.3, the output of the IVS loop of each inverter module, isvj (j 1,
2, …, n), is a part of the reference of the inner current loop of each inverter module,
so the IVS loop and the output voltage loop are coupled each other, and it is very
difficult to design the system directly. So, the analysis of the control block diagram
will be given below.
From Fig. 6.3, the reference of the inner current loop of each inverter module is
the difference between the output of the output voltage regulator iref and the output
of each IVS loop isvj (j 1, 2, …, n), i.e.,
Iref j (s) Iref (s) − Isv j (s) ( j 1, 2, . . . , n) (6.4)

Assuming the parameters of the inverter modules are consistent and simplifying
the inner current loop of each inverter module, the transfer function of each inner
current loop is equal, expressed as
Io j (s)
G c j (s) G c (s) ( j 1, 2, . . . , n) (6.5)
Iref j (s)
Then, Fig. 6.3 can be equivalent to Fig. 6.7a, and the output current of each inverter
module is

Io j (s) G c (s) · Iref j (s) G c (s) · Iref (s) − Isv j (s)
( j 1, 2, . . . , n) (6.6)
G c (s) · Iref (s) − G c (s) · Isv j (s)
According to (6.6), the total output current of the DC–AC ISOP system can be
obtained as

n
n
Io (s) Io j (s) n · G c (s) · Iref (s) − G c (s) · Isv j (s) (6.7)
j1 j1
According to (6.7), Fig. 6.7a can be equivalent to Fig. 6.7b, from which, the
influence of the IVS loops on the output voltage loop of the DC–AC ISOP system
can be derived as

n
Isv j (s)
j 1
⎛ ⎞

n
n
Vin
K vi − vin j G vcd (s)Iref (s) K vi G vcd (s)Iref (s) ⎝Vin − vin j ⎠
j1
n j1
0
(6.8)
Equation (6.8) implies that the total effect of the IVS loops on the system output
voltage loop is zero (as shown in Fig. 6.7c). That is to say, the output voltage loop is
not affected by the IVS loops.
On the other hand, the output signal of the output voltage regulator iref provides the
initial reference for each inner current loop. When iref changes, the actual reference
of each module, irefj , will also change simultaneously so that the output power and
input power of each module vary accordingly. For example, when IVS and OCS are
both achieved initially, the abruptly increasing load would result in a decrease of the
output voltage. In order to ensure the stability of the output voltage, iref will increase
and the output current of each module will also rise. In the meantime, OCS and the
balanced output power of all modules are maintained. By power conservation, the
input current of each module and hence the total input current of the system will all
6.3 Closed-Loops Design for DC–AC ISOP Systems 129
Fig. 6.7 Equivalent block diagram of the output current feedback control for DC–AC ISOP system
Fig. 6.7 (continued)
increase. Since the input current is still being shared and the average current of each
input-dividing capacitor is zero, IVS is maintained. It can be seen that the operation
of the output voltage loop does not change the state of the input voltage of each
module, and so does not affect the operation of the IVS loop.
The above analysis shows that the IVS loop and output voltage loop are decoupled
and can be designed separately when all the inverter modules are identical.
6.3.2 Design of Control Loop of the First-Stage Full-Bridge

Converter
Figure 6.8 shows the topology of the basic inverter module for the DC–AC ISOP
system, which is composed of a full-bridge converter as the first stage and a full-
bridge inverter as the second stage. If the output voltage frequency of the inverter
module is 400 Hz, the input current of the second-stage, iac , contains not only high-
frequency (switching frequency) ripple current, but also the low-frequency (800 Hz)
ripple current. Therefore, the first-stage converter needs a larger output filter capacitor
C dc to filter the low-frequency ripple current for the purpose of reducing the ripple
800Hz
Iin Ldc
iac 400Hz
iLdc
Lf
Q1 Q3 DR1 DR3 S1 S3 io
Tr
+ A + iLf iCf +
*
Vin * Vdc vinv ZLd vo
Cdc Cf _
_ _ B
Q2 Q4 DR2 DR4 S2 S4
Fig. 6.8 The main circuit of single inverter module
of intermediate bus voltage, V dc . However, C dc cannot be infinite, so there is still

low-frequency ripple component of 800 Hz in V dc . In order to reduce the influence
of 800 Hz ripple on the voltage loop, the cutoff frequency of its voltage loop should
be designed to be lower than 800 Hz and it is generally about 1/10 of 800 Hz [9, 10].
In the following, simulation is carried out for the two-stage inverter as shown in
Fig. 6.8. The key specifications are as follows: the input voltage V in 270 V, the
average value of the intermediate bus voltage V dc 180 V, the output voltage vo
115 V/400 Hz, and the output capacity S o 1 kVA. For the first-stage full-bridge
converter, the key parameters are as follows: the transformer turns ratio K 15:13,
the output filter inductor L dc 230 µH, the output filter capacitor C dc 800 µF (with
the equivalent series resistance RCf 0.03 ), the output voltage sensor gain K vo
0.01, the peak-to-peak value of sawtooth carrier V pp 2.1 V, and the switching
frequency f s 100 kHz. For the second-stage full-bridge inverter, the key parameters
are as follows: the output filter inductor L f 400 µH and the output filter capacitor
C f 16 µF.
According to Fig. 6.6, the control block diagram of the output voltage loop of
the first-stage full-bridge converter is shown in Fig. 6.9, where the control-to-output
transfer function Gdc (s) is [11]
Vin
(1 + sCdc RCf )
G dc (s) K
RCf L dc RCf Rp
s 2 L dc Cdc 1 + +s + Rp Cdc 1 + + Cdc RCf + +1
RLd RLd RLd RLd
(6.9)
where Rp 4L r f s /K 2 , and RLd is the equivalent load of the first-stage full-bridge

converter, which is obtained from the second-stage inverter and whose value is deter-
mined by the output active power of the inverter. Considering that the inverter operates
with full resistive load, RLd V 2dc /Po 1802 / 1000 32.4 .
From Fig. 6.9, the output voltage loop gain of the first-stage full-bridge converter
can be obtained as
d̂ y
v̂dcg Gvdc(s) 1/Vpp Gdc(s)
+ _ v̂dc
Kvdc
Fig. 6.9 Control block diagram of the output voltage loop of the first-stage full-bridge converter
Fig. 6.10 Bode diagram of

the output voltage loop gain
of the full-bridge converter at
different cutoff frequencies
Table 6.1 Output voltage regulator Gvdc (s) at different cutoff frequencies
Cutoff frequency/Hz Gvdc (s)
1000 9 + 1.4 × 104 /s
300 2 + 2500/s
80 0.5 + 500/s
Tvo (s) K vdc G vdc (s)G dc (s)/Vpp (6.10)
Figure 6.10 gives the bode diagram of the output voltage loop gain of the full-
bridge converter with different cutoff frequencies, i.e., 1 kHz, 300, and 80 Hz, and
the corresponding transfer functions of output voltage regulator Gvdc (s) are shown
in Table 6.1
Figure 6.11 shows the simulation waveforms of the primary current of transformer
ip , the filter inductor current iLdc , the intermediate bus voltage V dc , and the inverter
output voltage at different cutoff frequencies. Figure 6.11a shows simulation wave-
forms at the cutoff frequency of 1 kHz. As seen, the fluctuation of ip and iLdc of the
first-stage full-bridge converter is relatively large, and the maximum value is almost
twice of the average value. This is because the voltage loop tends to follow and
compensate for the ripple voltage at 800 Hz, which will increase the current stress of
the power devices and magnetic components. Figures 6.11b, c show the simulation
waveforms at the cutoff frequencies of 300 and 80 Hz, respectively. It can be seen
that the pulsation of 800 Hz in ip and iLdc is reduced with the decrease of the cut-
off frequency. Therefore, in order to reduce the current stress of the power devices
and the magnetic components of the full-bridge converter, the cutoff frequency of
the voltage loop is designed relatively low, and it is set at about 1/10 of the output
frequency.
6.3.3 Design of IVS Loop
As illustrated in Sect. 6.3.1, the IVS loop and the system output voltage loop are
decoupled each other, so the IVS loop can be designed separately.
According to Fig. 6.3, the load of each inverter module can be considered to be
composed of two parts, which are determined, respectively, by iref , the output of
the system output voltage loop, and isvj (j 1, 2, …, n) introduced by each IVS
loop. So, from the input side of the inverter module, each inverter can be regarded
as resistances Rvo and RIVSj paralleled as shown in Fig. 6.12. The value of Rvo and
RIVSj are determined by iref and isvj (j 1, 2, …, n), respectively.
6.3.3.1 Derivation of Rvo
If the IVS loops are ignored (see Fig. 6.3), i.e., î sv1 î sv2 . . . î svn 0, iref is the
common reference of the inner current loop of all inverter modules, and the method
will be equivalent to OCS control. So, from the input side, under the role of iref ,
each inverter module can be equivalent to a constant power load. Within the cutoff
frequency range of the current loop, the small-signal model of a constant power load
presents the negative resistance characteristic. From (6.8), it can be seen that the
sum of isvj (j 1, 2, …, n) of each inverter module equals to zero, which means
that the sum of each module power corresponding to isvj also equals to zero and thus
the sum of each inverter module power corresponding to iref serves as the power
of the DC–AC ISOP systems. Therefore, the active power of each inverter module
corresponding to iref is equal, and it is 1/n of the system power Po . So the resistance
Rvo can be expressed as
v̂in j (Vin /n)2

Rvo −Rn − ( j 1, 2, . . . , n) (6.11)
î in_vo j Po /n
6.3.3.2 Derivation of RIVSj
From Fig. 6.7a, the individual output current perturbation Iô_IVS j ( j 1, 2, . . . , n)

of inverter introduced by the input voltage perturbation v̂in j ( j 1, 2, . . . , n) can
be expressed as
10 ip
(A) 0
−10
12
6 iLdc
(A)
0
185 Vdc
(V)
180
175
200
vo
(V)
0
−200
10 11 12 13 14 15 16 17
t (ms)
(a) With voltage loopcut-off frequencyof 1 kHz
10 ip
0
(A)
−10
10
5 iLdc
(A)
0
185 Vdc
(V )
180
175
200
vo
(V)
0
−200
10 11 12 13 14 15 16 17
t (ms)
(b) With voltage loop cut-off frequency of 300 Hz
10 ip
0
(A)
−10
10
5 iLdc
(A)
0
185
Vdc
(V)
180
175
200
vo
(V)
0
−200
10 11 12 13 14 15 16 17
t (ms)
(c) With voltage loop cut-off frequency of 80 Hz
Fig. 6.11 Simulation waveforms at different cutoff frequencies

iîn1
Fig. 6.12 Equivalent
small-signal model of
DC–AC ISOP system + iîn_vo1 iîn_IVS1
Z1′ Rvo
ˆvin1 RIVS1
_ Cd1
iîn2
+ iîn_vo2 iîn_IVS2
Z 2′
vˆ in2 Rvo RIVS2
vˆ in _ Cd2
îinn
…
+ iîn_von iîn_IVSn
Z n′ Rvo RIVSn
ˆvinn
_ Cdn
Iô_IVS j v̂in j · K vi · G vcd · Iref (s) · G c (s) ( j 1, 2, . . . , n) (6.12)
where Iô_IVS j has the same phase with the corresponding load current Iô j ( j
1, 2, . . . , n).
The individual active output power perturbation p̂o_IVS j ( j 1, 2, . . . , n) of

module j corresponding to I o_IVS j can be expressed as

p̂o_IVS j I o_IVS j · Vo · cos θ ( j 1, 2, . . . , n) (6.13)
The individual input power perturbation p̂in_IVS j ( j 1, 2, . . . , n) of module j

corresponding to v̂in j can be expressed as
Vin
p̂in_IVS j Iin v̂in j + î in_IVS j ( j 1, 2, . . . , n) (6.14)
n
Assuming the conversion efficiency for each individual module is 100%, we have
p̂in_IVS j p̂o_IVS j ( j 1, 2, . . . , n) (6.15)
Substituting (6.12) into (6.13), and then substituting (6.13) and (6.14) into (6.15),
yields
v̂in j Vin /n
RIVS j ( j 1, 2, . . . , n)
î in_IVS j K vi G vcd Iref (s)G c (s) · Vo cos θ − Iin
(6.16)
According to Fig. 6.7c, we have I ref (s) Gc (s) I o /n. So, I ref (s) Gc (s) V o cosθ
equals to Po /n. Then, (6.16) can be rewritten as
Vin /n Vin
RIVS j ( j 1, 2, . . . , n) (6.17)
K vi G vcd Po /n − Iin K vi G vcd Po − n Po /Vin
6.3.3.3 Design of IVS Regulator Gvcd
As pointed out in Chap. 3, the OCS control could not ensure the stability of the
DC–DC ISOP system. The essential reason is that the input impedance of each mod-
ule is negative resistance. Similarly, for the DC–AC ISOP system, the OCS control
will lead to an unstable system since the modules present the negative resistance
at the input sides. Equation (6.17) implies that the role of IVS loops is equivalent
to introduce a positive resistance to the input terminal of each module as shown in
Fig. 6.12. So, the equivalent input impedance of each inverter module is
−Rn · RIVS j Rn · RIVS j
Z j Rvo //RIVS j ( j 1, 2, . . . , n) (6.18)
−Rn + RIVS j Rn − RIVS j
In order to ensure the stability of DC–AC ISOP system, the equivalent input
impedance of each inverter module should present positive resistance characteristics,
i.e., Z j > 0. According to (6.18), we can obtain the condition for stability as
Rn > RIVS j ( j 1, 2, . . . , n) (6.19)
Substitution of (6.11) and (6.17) into (6.19), yields
2n
G vcd > G vcd min (6.20)
K vi · Vin
It can be seen that the gain of IVS loop compensator must satisfy (6.20) so that
each inverter module presents positive resistance characteristics and the DC–AC
ISOP system with IVS control strategy is stable.
For simplicity, a two-module DC–AC ISOP system is simulated to verify the
correctness of the IVS loop design. The specifications of the DC–AC ISOP system
are as follows: the system input voltage is 540 V (±10%), the output voltage is
115 VAC/400 Hz, the output capacity is 2 kVA; the module input voltage is 270 V
(±10%), the module output voltage is 115 VAC/400 Hz, the output capacity of each
module is 1 kVA; the input voltage sensor gain is K vi 0.01. The input-dividing
capacitors of the two modules are intentionally set at different values, i.e., C d1
1000 µF and C d2 800 µF.
Figure 6.13 shows the response in the individual input voltages and output currents
of two modules when the system input voltage is step changed from 500 to 600 V.
According to (6.20), it can be obtained that Gvcdmin 0.666 ~ 0.815. As shown in
Figs. 6.13a, b, for Gvcd > Gvcdmin , the two input voltages converge finally, and the
higher values of Gvcd result in a faster correction in the input voltages after a system
input voltage disturbance. As shown in Fig. 6.13c, for Gvcd < Gvcdmin , the two input
320
vin2
vin1
(V) 280
240
20 io2
io1
10
(A) 0
10
20
0 10 20 30 40
t (ms)
(a) G vcd = 8
320 vin2
vin1
(V) 280
240
20 io1 io2
10
(A) 0
10
20
0 10 20 30 40
t (ms)
(b) G vcd = 3
Fig. 6.13 Response to a step change in the system input voltage with different Gvcd
voltages diverge, resulting in a runaway mode. The system cannot work normally
and it is unstable.
6.3.4 Design of Output Voltage Loop
As shown in Fig. 6.7c, the system output voltage loop is decoupled from the IVS
loops. In order to design the compensator for system output voltage loop, it is required
320 vin2
11.66V 15.43V
vin1
(V) 280
240
20 io1 io2
10
(A) 0
10
20
0 5 15 25 35 45 55 65 70
t (ms)
(c) G vcd = 0.25
to derive the transfer function of inner current loop Gc (s) of a single inverter first.
Based on the control strategy shown in Fig. 6.3, when the IVS loops are not consid-
ered, the control block diagram of a single inverter module can be obtained as shown
in Fig. 6.14a. Relocating the feedback node of io backward to the output voltage,
Fig. 6.14b is obtained. Simplifying the part of the diagram in the dashed block of
Fig. 6.14b, c can be obtained. From Fig. 6.14c, the transfer function of inner current
loop Gc (s) can be derived as
Io (s) G i G inv
G c (s) 2 (6.21)
Iref (s) s n Z Ld L f Cf + s L f + n Z Ld + K io G i G inv
From (6.21) and Fig. 6.7c, the loop gain of the system output voltage loop can be
derived as
n K vo G vo G i G inv Z Ld
Tvo (s) (6.22)
s2n Z Ld L f C f + s L f + n Z Ld + K io G i G inv
6.4 Simulation Results
In order to verify the effectiveness of the IVS and OCS control strategy based on
the output current feedback and the output filter inductor current feedback for the
DC–AC ISOP system, the simulation of two-module DC–AC ISOP system is carried
out. The parameters used in the simulation are the same as those given in Sect. 6.3.3.
To obtain the effects of output filter capacitor mismatch on two kinds of control
6.4 Simulation Results 139
(a) iCf
sCf
voref + vinv
_ _
iref + 1 iLf
_ Gvo _ Gi Ginv sLf nZLd vo
+ + io
Kio
Kvo
iCf
(b) sCf
voref +
_ _
iref + vinv 1 iLf
_ Gvo _ Gi Ginv sLf nZLd vo
+ io
io 1
Kio nZLd
Kvo
(c)
voref + iref + vinv nZ Ld
_ Gvo _ Gi Ginv vo
s 2 nZ Ld Lf Cf sLf nZ Ld
io 1
Kio nZLd
Kvo
Fig. 6.14 Equivalent control block diagram of output voltage loop of individual module
methods, a 4.7 µF capacitor is intentionally connected in parallel with the output

filter capacitor of module 1.
Figure 6.15 shows the simulation waveforms of the DC–AC ISOP system with
output current feedback control. The waveforms of the individual input voltage and
the difference between input voltages are shown in Fig. 6.15a. As seen, the input
voltages of the two inverter modules are equal. The waveforms of the system output
voltage, individual output filter inductor current and the difference between these
two currents are shown in Fig. 6.15b, from which it can be seen that the output
filter inductor current of the two inverter modules are different, and the difference
leads the output voltage by 90° with the capacitive reactive power being presented.
Figure 6.15c shows the waveforms of individual output current and the difference
between these two currents. Due to the adoption of the output current feedback, the
output filter capacitor mismatch does not affect the OCS effect, and the output current
of the two inverter modules is equal.
Figure 6.16 shows the simulation waveforms of the DC–AC ISOP system with
output filter inductor current feedback control. The waveforms of individual input
voltage and the difference between input voltages are shown in Fig. 6.16a. As seen,
the input voltages of the two inverter modules are equal. The waveforms of the output
voltage of the system, individual output current and the difference between these two
currents are shown in Fig. 6.16b, from which it can be seen that the output currents
280 vin1
270
(V)
260
250
280
vin2
(V) 270
260
250
5
vin1 –vin2
(V) 0
−5
0 2 4 6 8 10
t (ms)
(a) Simulationwaveformsof input voltages
200
(V) 0 vo
−200
20
iLf1
(A) 0
−20
20
iLf2
(A) 0
−20
5
iLf1 – iLf2
(A) 0
−5
0 2 4 6 8 10
t (ms)
(b) Simulationwaveformsof output filter inductor currents
15
io1
(A) 0
−15
15
io2
(A) 0
−15
5
(A) io1 –io2
0
−5
0 2 4 6 8 10
t (ms)
(c) Simulation waveforms of output currents
Fig. 6.15 Simulation waveforms with output current feedback control

6.4 Simulation Results 141
of the two inverter modules are different, and the difference lags the output voltage
by 90° with the inductive reactive power being presented. Figure 6.16c shows the
waveforms of individual output filter inductor current and the difference between
these two currents. Due to the adoption of the output filter inductor current feedback,
the output filter inductor current of the two inverter modules are equal.
Figures 6.15 and 6.16 verify the validity of the previous theoretical analysis.
6.5 Experimental Results
In order to verify the compound balanced control strategy with output current feed-
back controlled, a 2-kVA two-module DC–AC ISOP system prototype is fabricated in
the laboratory. The specifications of the DC–AC ISOP system and the single inverter
module are the same as the parameters in the simulation given in Sect. 6.4.
6.5.1 Steady-State Experiment
Figure 6.17 gives the steady-state experimental waveforms of the system at full
resistive load (2 kW). The waveforms of individual input voltage, individual output
current, and the difference between these two currents are shown in Fig. 6.17a. As
seen, the input voltage and output current of the two inverter modules are the same,
respectively, which means that IVS and OCS are achieved. The waveforms of the
system output voltage, total output current, and individual output current are shown
in Fig. 6.17b, which indicate that the system outputs a stable sinusoidal voltage.
Figure 6.18 gives the steady-state experimental waveforms of the system at full
inductive load (2 kW, PF 0.75). The waveforms of the individual input voltage,
individual output current, and the difference between these two currents are shown in
Fig. 6.18a, from which we can see that IVS and OCS are well achieved. Figure 6.18b
shows the waveforms of the system output voltage, total output current, and individual
output current. Due to the inductive load, the output voltage leads the total output
current.
6.5.2 Dynamic Experiment
Figures 6.19 and 6.20 give the experimental waveforms of the system at nominal input
voltage when the load current steps up and down between half and full resistive load,
and between half and full inductive load, respectively. Figures 6.19a and 6.20a show
the waveforms of the individual input voltage, system output voltage, and total output
current. As seen, the input voltages are shared equally during the transient condition.
It should be noted that the input voltage source of the system is not an ideal one,
280 vin1
270
(V)
260
250
280
vin2
(V) 270
260
250
5
vin1 –vin2
(V) 0
−5
0 2 4 6 8 10
t (ms)
(a) Simulationwaveformsof input voltages
200
(V) 0 vo
−200
15
io1
(A) 0
−15
15
io2
(A) 0
−15
5 io1 – io2
(A) 0
−5
0 2 4 6 8 10
t (ms)
(b) Simulationwaveformsof output currents
20
iLf1
(A) 0
−20
20
(A) iLf2
0
−20
5
iLf1 –iLf2
(A) 0
−5
0 2 4 6 8 10
t (ms)
(c) Simulationwaveformsof output filter inductor currents
Fig. 6.16 Simulation waveforms with output filter inductor current feedback control
6.5 Experimental Results 143
C1 vin1 : [100V/div]
C1
C3 io1 : [25A/div]
C3
C2
C4 io2 : [25A/div]
C4
F2
F2 io1 io2 : [25A/div]
Time: [2ms/div]
(a) Experimental waveformsof input voltages and output currents
C1 vo : [200V/div]
C1
F2
F2 io : [25A/div] C3 io1 : [25A/div]

C3
C4
C4 io2 : [25A/div]
Time: [2ms/div]
(b) Experimental waveformsof output voltages and output currents
Fig. 6.17 Experimental waveforms at full resistive load
the input voltage has slight drop or rise when the load current steps up and down.
Figures 6.19b and 6.20b show the waveforms of the individual input voltage and
output current. As seen, the output currents are shared equally both at steady state
and transient.
Figures 6.21 and 6.22 give the experimental waveforms of the input voltage step-
ping between 486 V (90%V in ) and 594 V (110%V in ) at full resistive and inductive
load, respectively. Figures 6.21a and 6.22a show the waveforms of individual input
voltage, system output voltage, and total output current. As seen, the input voltages
of the two modules are shared equally during the transient condition and the system
C1
C3 io1 : [25A/div]
C3
C2
C4 io2 : [25A/div]
C4
F2
F2 io1 – io2 : [25A/div]

Time: [2ms/div]
(a) Experimental waveformsof input voltages and output currents
C1 vo : [200V/div]
C1
F2
F2 io : [25A/div] C3 io1 : [25A/div]

C3
C4
C4 io2 : [25A/div]
Time: [2ms/div]
(b) Experimental waveformsof output voltages and output currents
Fig. 6.18 Experimental waveforms at full inductive load
output voltage is stable. Figures 6.21b and 6.22b show the waveforms of the individ-
ual input voltage and output current. As seen, the output currents of the two modules
are shared equally during the transient condition.
C1 C3 vo : [200V/div]
C3
C2
C4
C4 io : [25A/div]
Time: [5ms/div]
(a) Experimental waveforms of input voltages,
output voltage and output currents
C1 C4 io1 : [10A/div]
C4
C2
C3
C3 io2 : [10A/div]
Time: [5ms/div]
(b) Experimental waveforms of input voltages
and individual output currents
Fig. 6.19 Experimental waveforms under step change of resistive load
6.5.3 Comparison of the Output Current Feedback

and Output Filter Inductor Current Feedback
Further comparative experiments on the compound balanced control strategies with

the output current feedback and the output filter inductor current feedback are con-
ducted. Figure 6.23a gives the experimental waveforms of the system with output
current feedback control. It can be seen that the mismatch of output filter capac-
C1 C3 vo : [200V/div]
C3
C2
C4
C4 io : [25A/div]
Time: [5ms/div]
C1 C4 io1 : [10A/div]
C4
C2
C3
C3 io2 : [10A/div]
Time: [5ms/div]
Fig. 6.20 Experimental waveforms under step change of inductive load
itor has no influence on the sharing of output currents between the two modules.
However, the unmatched output filter capacitors introduce the difference between
the output filter inductor currents. Figure 6.23b gives the experimental waveforms of
the system with output filter inductor current feedback control. As seen, the output
filter inductor current of the two inverter modules are almost the same, but there
is reactive current between the two inverter modules, which is consistent with the
previous analysis.
C2 vo : [200V/div]
C2/C4
C3
C1
C1 io : [25A/div]
Time: [10ms/div]

C2 io1 : [10A/div]
C2/C4
C3
C1
Time: [10ms/div] C1 io2 : [10A/div]

Fig. 6.21 Experimental waveforms with step change of system input voltage at full resistive load
The steady state and dynamic experiments prove that the IVS and OCS control
strategy based on output current feedback can achieve IVS and OCS under various
circumstances. Furthermore, with the method adopted, the disturbance of input volt-
age and load can be restrained and the reliability of the system can also be guaranteed.
C3 vo : [200V/div]
C1/C3
C2
C4
C4 io : [25A/div]
Time: [10ms/div]

C3 io1 : [10A/div]
C1/C3
C2
C4
Time: [10ms/div] C4 io2 : [10A/div]

Fig. 6.22 Experimental waveforms with step change of system input voltage at full inductive load
6.6 Distributed IVS/OCS Control Strategy
In the control scheme shown in Fig. 6.3, all the inverter modules share a common
voltage loop, and this control scheme is actually a kind of centralized control strategy.
Therefore, a distributed control is presented here to make sure that all the inverter
modules are fully modularized. The failure of any module will not affect the nor-
6.6 Distributed IVS/OCS Control Strategy 149
C3 vo : [200V/div]
C1 io1 : [25A/div]
C2 io2 : [25A/div]
M4 io1 – io2: [5A/div]
M2 iLf1: [25A/div]
M1 iLf2: [25A/div]
M3 iLf1 – iLf2: [10A/div]

Time: [2ms/div]
(a) Experimental waveforms with output current feedback control
C2 vo : [200V/div]
M1 io1 : [25A/div]
M2 io2 : [25A/div]
M3 io1 – io2: [10A/div]

C1 iLf1: [25A/div]
C3– iLf2: [25A/div]
F1 iLf1 – iLf2: [5A/div]

Time: [2ms/div]
(b) Experimental waveforms with output filter inductor current feedback control
Fig. 6.23 Experimental waveforms of two control strategies with different current feedback when
the output filter capacitors are unmatched
mal operation of the DC–AC ISOP systems, so as to improve the reliability and
redundancy of the DC–AC ISOP systems.
Figure 6.24 presents the distributed control strategy for the DC–AC ISOP system
[12], which also includes the output voltage loop, IVS loop, and inner current loop.
Different from the centralized control strategy, the output voltage loops are scattered
in each inverter module. All the modules communicate with each other by three
buses, namely the output voltage reference synchronous bus (vref synchronous bus),
the IVS bus, and the average current bus (iave bus). It can be seen that all the inverter
modules in the system are completely reciprocal, and so distribution and modularity
are fully achieved. In this distributed control strategy, the output voltage of each
inverter module is regulated by its respective output voltage loop. All the output
voltage references are synchronized by the digital signal processor (DSP) to generate
the output voltage reference synchronous bus. Since the components of the feedback
networks and regulators maybe not well matched, the output signals of every output
voref Vin iave

n
+ ivd1 isv1
Kvi _ Gvcd Inner Current Loop iCf1
vin1 _ iref1 vinv1 _ iLf1 sC
Kvi IVS Loop _ f1
+ + 1
_ Gi Ginv sLf1 +
voref + ig1 + io1
_ Gvo
Ki
Kvo
Output Voltage Loop
+ ivd2 isv2
Kvi _ Gvcd Inner Current Loop iCf2
vin2 _ iref2 vinv2 _ iLf2 _ sCf2
Kvi IVS Loop + + 1
_ Gi Ginv sLf2 +
voref + ig2 + io2
_ Gvo
Ki
Kvo
Output Voltage Loop
vref + +
IVS + io vo
…
+ 1 ZLd
…
Synchronous iave +
Bus
…
Bus n Bus
…
+ ivdn isvn
Kvi _ Gvcd Inner Current Loop iCfn
vinn
Kvi IVS Loop
_ irefn vinvn _ iLfn _ sCfn
+ + 1
_ Gi Ginv sLfn +
voref + ign + ion
_ Gvo
Ki
Kvo
Output Voltage Loop
Fig. 6.24 Block diagram of distributed control strategy for DC–AC ISOP system
voltage regulators (namely igj ) are not exactly the same. So, they are averaged,
forming the iave bus. The signal iave is sent to all the inverter modules and served as
the common initial current reference. The IVS bus signal comes from all the modules
through an averaging circuit and its value is V in /n, which provides the input voltage
reference for all the inverter modules. The output signals of modular IVS loops ivdj (j
1, 2, …, n) multiply iave and then superimpose on iave to produce the actual current
reference signal of each module, irefj . The purpose of the multiplier circuit is to ensure
that output filter inductor current of each inverter module tracks the reference irefj to
attain the same phase. In the meanwhile, the IVS loop modifies the magnitude of the
output filter inductor current (and adjusts the output active power of each module)
to ensure IVS and OCS. Basically, the distributed control strategy still adopts the
conception of compound balanced control to realize the power balance of the system.
Similar with the centralized control mentioned before, the OCS effect is different
for the DC–AC ISOP system in the distributed control system when taking the output
6.6 Distributed IVS/OCS Control Strategy 151
filter inductor current and the output current as feedback signal. And, the decoupling
relationships between loops and parameters design is similar to that in the centralized
control strategy, which are not repeated here.
6.7 Summary
This chapter proposes the compound control scheme for the DC–AC ISOP systems
to obtain IVS and OCS. In the proposed control scheme, the inner current loop of
each inverter module can adopt the output filter inductor current feedback and the
output current feedback as well. Among them, the former scheme can realize OCS
when the output filter capacitors are matched, and the latter scheme can achieve OCS
unconditionally. Taking the latter scheme as an example, the IVS loop and the system
output voltage loop are analyzed and it is pointed out that they are decoupled and can
be designed separately. A two-module DC–AC ISOP system prototype is fabricated
and tested in the laboratory, and the experimental results verify the effectiveness of
the proposed control strategy and the parameters design of the control loops.
Furthermore, a distributed control scheme is proposed on the basis of the cen-
tralized control, and it disperses all the control loops into each inverter module and
achieves modularity completely.
References
1. Chen, W., Zhuang, K., Ruan, X.: Input-series and output-parallel connected inverter system
for high input voltage applications. IEEE Trans. Power Electron. 24(9), 2127–2137 (2009)
1585–1596 (2010)
3. Silva, C., Oliveira, D., Bascope R.: A dc-ac converter with high frequency isolation. In: Pro-
ceedings of IEEE International Symposium on Industrial Electronics, pp. 953–958 (2007)
4. Xue, Y., Chang, L., Kjaer, S.B., Bordonau, J., Shimizu, T.: Topologies of single-phase invert-
ers for small distributed power generators: an overview. IEEE Trans. Power Electron. 19(5),
1305–1314 (2004)
5. Kjaer, S.B., Pedersen, J.K., Blaabjerg, F.: A review of single-phase grid-connected inverters
for photovoltaic modules. IEEE Trans. Ind. Appl. 41(5), 1292–1306 (2005)
6. Ruan, X.: Soft-Switching PWM Full-Bridge Converters. Wiley, Singapore (2014)
7. Chen, W.: Research on series-parallel conversion systems consisting of multiple converter
modules (in Chinese). PhD Dissertation. Nanjing University of Aeronautics and Astronautics,
Nanjing, China (2009)
8. Zhuang, K., Ruan, X.: Control strategy to achieve input voltage sharing and output current
sharing for input-series-output-parallel inverter. In: Proceedings of IEEE Power Electronics
Specialists Conference, pp. 3655–3658 (2008)
9. Andersen, G.K., Klumpner, C., Kjaer, S.B., Blaabjerg, F.: A new green power inverter for fuel
cells. In: Proceedings of IEEE Power Electronics Specialists Conference, pp. 727–733 (2002)
10. Liu, C., Lai, J.: Low frequency current ripple reduction technique with active control in a fuel
cell power system with inverter load. IEEE Trans. Power Electron. 22(4), 1429–1436 (2007)
11. Vlatkovic, V., Sabate, J.A., Ridley, R.B., Lee, F.C., Cho, B.H.: Small-signal analysis of the
phase-shifted PWM converter. IEEE Trans. Power Electron. 17(1), 128–135 (1992)
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superior reliability for fully modular input-series-output-parallel inverter system. IEEE Trans.
Power Electron. 32(1), 723–735 (2017)
Chapter 7
Compound Balanced Control Strategy
for DC–AC Input-Series-Output-Series
Systems
Abstract DC–AC input-series-output-series (ISOS) systems are very suitable for

high input voltage and high output voltage power conversion applications. The imple-
mentation of the compound balanced control strategy is presented for the DC–AC
ISOS system to achieve input voltage sharing (IVS) and output voltage sharing
(OVS). The output filter inductor current or the output filter capacitor current adopted
as the feedback signal for the inner current loops of each module, respectively, is ana-
lyzed and compared. Taking the output-filter-capacitor-current method as an exam-
ple, the decoupling relationship between the control loops is analyzed and the loop
design procedure is given. The simulation and experimental results are provided to
verify the effectiveness of the proposed control method. Furthermore, this chapter
presents a new solution dedicated to distributed configuration on the basis of cen-
tralized control, which can improve the reliability of the system.
Keywords Input-series-output-parallel system

Compound balanced control strategy · Input voltage sharing
Output voltage sharing · Closed-loop designs
As one of the input-series-connected DC–AC power conversion systems, the DC–AC

input-series-output-series (ISOS) system is composed of multiple DC–AC inverter
modules with low input voltage and low output voltage, which are connected in series
both at the input side and output side, and thus it is suitable for high input voltage
and high output voltage applications. The key issue of the DC–AC ISOS systems
is to achieve input voltage sharing (IVS) and output voltage sharing (OVS) of the
constituent modules simultaneously. Different from the DC–DC ISOS systems, the
output voltage of the DC–AC ISOS system is an AC one. So, in order to achieve
OVS, it is required to control both the magnitude and phase of output voltages of all
the modules to be equal. As a consequence, both the active and reactive powers of
the modules will be balanced.
154 7 Compound Balanced Control Strategy …
In Chap. 5, it is pointed out that the DC–AC ISOS systems needs to adopt the
compound balanced control strategy, i.e., to realize IVS and ensure the magnitude
or phase of the modular output voltages be equal. In this chapter, an implementation
of the compound balanced control strategy is proposed. In the proposed control
strategy, the output filter inductor current or the output filter capacitor current could
be the feedback signal for the inner current loops of each module. The analysis
shows that the output filter capacitor current feedback can realize IVS and OVS
among the constituent modules no matter the output filter capacitors of modules are
well matched or not. As an example, the compound balanced control strategy with
output filter capacitor current feedback is analyzed, and it is shown that the IVS
control loops and the system output voltage loop are decoupled each other. Then, the
parameters design for all the control loops is presented. Simulation and experimental
results are given to verify the validity of the proposed compound balanced control
strategy. Finally, based on the compound balanced control strategy, a distributed
control scheme is proposed to achieve full modularity of the DC–AC ISOS systems.
7.1 Implementation of the Compound Balanced Control

Strategy
Figure 7.1 gives the configuration of the DC–AC ISOS systems consisting of n
inverter modules. The basic inverter module in the DC–AC ISOS systems adopts
the two-stage configuration consisting of the first-stage DC–DC converter and
the second-stage DC–AC inverter. Here, the phase-shifted full-bridge converter is
employed as the first-stage, and the full-bridge inverter is adopted as the second
stage.
As described in Sect. 5.1.4, the compound balanced control strategy means ensur-
ing the equaling the amplitude or phase of modular output voltages while controlling
the input voltage sharing. According to this idea, Fig. 7.2 shows an implementation
of the compound balanced control strategy for the DC–AC ISOS system [1], which
includes three control loops, namely, the common system output voltage loop, the
IVS loop, and the inner current loop of each inverter module (Here the module output
filter capacitor current is taken as the feedback signal for each inner current loop).
The common system output voltage loop guarantees the stability of the system output
voltage, and its output signal iref acts as the common initial current reference for all
the inner current loops. Here iref contains both the amplitude and the phase informa-
tion. In the IVS loop, the system input voltage divided by n and the input voltage
of each module are sensed with sensor gain of K vi and compared. The voltage error
is sent into the IVS regulator Gvcd , whose output signal ivdj (j 1, 2,…, n) serves
as the current reference amplitude correction signal of each module. By multiplying
ivdj and iref , the current correction signal isvj (j 1, 2, …, n) is obtained with the
same phase as that of iref . Then, isvj is superimposed on the initial reference iref to
adjust the amplitude of the current reference of each module. Since the current inner
loop adopts the capacitor current feedback of each module, the IVS loop only alters
Module 1
Full-Bridge DC-DC Converter L Full-Bridge Inverter
DR1 DR3 dc1
Iin iin1 iLdc1

Tr Lf1
Q1 Q3 S1 S3 io1 io
icd1 A1 +
+ iLf1 iCf1 +
+
*
*
Vdc1 vinv1 vo1
v Cdc1 _
Cd1 _in1 _ _ B1
Cf1
+
Vin
Q2 Q4 S2 S4 ZLd v_o
DR2 DR4
icd2
+ +
…
vin2 Module 2 vo2
Cd2 _ … _
iinn
icdn
+ +
vinn Module n von
Cdn _ _
Fig. 7.1 Configuration of the DC–AC ISOS system
the amplitude of the output filter capacitor current reference of each module, and
the phase of the current reference is always synchronized. As a result, all the output
filter capacitor currents have the same phase by tracking the synchronized reference.
Since the filter capacitor current of each module leads the corresponding module
output voltage by 90°, the module output voltages have the same phase, i.e.,
θ1 θ2 · · · θn (7.1)
where θ 1 , θ 2, …, θ n are the output power factor angle of each inverter module.
With the IVS loop, we have
Vin1 Vin2 · · · Vinn (7.2)
At steady state, the average current of the input dividing capacitor of each module
is zero, so we have
Iin1 Iin2 · · · Iinn (7.3)
It is supposed that the conversion efficiency of each inverter module is 100%. So,
by power conservation, we have
IVS Loop Inner Current Loop

iref1 _
+ ivd1 isv1 vinv1 iCf1 1 vo1
Kvi _ Gvcd + 1 iLf1
Vin _ Gi Ginv
vin1 + _ + sLf +_ sCf
n Kvi
Ki
IVS Loop Inner Current Loop vo2

iref2 _
+ ivd2 isv2 vinv2 iLf2 iCf2 1
Kvi Gvcd + 1
_ _ _ Gi Ginv sLf sCf
vin2 + + +_ io
Kvi
Ki 1
ZLd
…
…
+
+ vo
…
IVS Loop Inner Current Loop
irefn _ _
+ ivdn isvn vinvn + iCfn 1 von
Kvi _ Gvcd + 1
_ Gi Ginv
vinn + _ + sLf iLfn sCf
Kvi
Ki
+ iref
voref _ Gvo
Kvo
System Output Voltage Loop
Fig. 7.2 Compound balanced control strategy for DC–AC ISOS system
Pin j Vin j · Iin j Vo j · Io · cos θ j Po j ( j 1, 2, . . . , n) (7.4)
where Pinj and Poj are the input power and output active power of each module,
respectively.
Substitution of (7.2) and (7.3) into (7.4) leads to
Vo1 · cos θ1 Vo2 · cos θ2 · · · Von · cos θn (7.5)
Vo1 Vo2 · · · Von (7.6)
According to (7.1) and (7.6), we have
vo1 vo2 · · · von (7.7)
As discussed above, the implementation of the compound balanced control strat-

egy as shown in Fig. 7.2 can achieve IVS and OVS simultaneously, and it is referred
to as the combined control of IVS and output phase synchronization.
For the DC–AC ISOS systems, the feedback signal of the inner current loop
of each module in Fig. 7.2 can also be the output filter inductor current. In this
· ·
· ILf2 Vo2 ·
ICf1
ICf1 · f1
IL
· · · ·
ICf2 Vo ICf2 Vo
· ·
0 Io 0 Io
· · ·
Vo1 Vo1 Vo2 · ·
Vo1=Vo2
(a) With filter inductor current feedback (b) With filter capacitor current feedback
Fig. 7.3 Steady-state phasor diagram of the output variables of DC–AC ISOS system with different
current feedback when C f1 > C f2
case, the IVS loop can still ensure IVS as well as the output active power balance
among the inverter modules [1]. However, when the output filter inductor current is
selected as the feedback signal for the inner current loop, all of module filter inductor
currents could have the same phase. For achieving OVS, all the module output filter
capacitor should be well matched. Here, a two-module DC–AC ISOS system is
illustrated as an example. For this system, we have iLfj iCfj + io (j = 1, 2), where,
iLfj is the output filter inductor current, iCfj is the output filter capacitor current, and
io is output current of the system. So, if the output filter capacitors are equal, the
equaling of the output filter inductor currents (iLf1 iLf2 ) will ensure that the output
filter capacitor currents are equal, i.e., iCf1 iCf2 , leading to vo1 vo2 . As a result,
OVS can be achieved. If the output filter capacitors of two modules are not matched,
for example, C f1 > C f2 , the IVS loop regulates so that each module’s filter inductor
current shares the same phase while differing in amplitude, and the final steady-
state phasor diagram is shown in Fig. 7.3a. It can be seen that the output voltage
difference between the two modules, vo1 − vo2 , lags load current io by 90°, which
means there is a difference of the reactive power between the two modules, and it
presents the capacitive reactive power. On the contrary, if the output filter capacitor
current is selected as the feedback signal, when there is a difference between the
output filter capacitors of two modules (also assuming C f1 > C f2 ), the IVS loop could
ensure active power balance (i.e., (7.5) is established), and the role of the output
synchronization could guarantee the establishment of (7.1). Thus, OVS is achieved
(i.e. (7.7) is established). So, if the output filter capacitors is not matched, the IVS
loop will adjust the capacitor current to attain the difference amplitude but the same
phase at steady state as shown in Fig. 7.3b. From the above analysis, with the output
filtering inductor current feedback, OVS can be achieved only if the output filter
capacitors of the module are matched; and with the output filter capacitor current
feedback, OVS can be achieved no matter the output filter capacitors are matched or
not.
Vdc _
irefj + -h
vinv 1 iLf iCf 1 voj
_ h + sLf +_ sCf
if -Vdc io
Ki
Fig. 7.4 Control block diagram of inverter with three-state hysteresis modulation
7.2 Decoupling the Control Loops
As seen in Fig. 7.2, in the combined control of IVS and output phase synchronization,
there are n + 1 variables including the system output voltage and n modular input
voltages, which need to be controlled. These variables seem to interfere with each
other and it is very difficult to analyze and design regulators of the system directly.
It is, thus, necessary to explore the relationship of these variables to reduce the
complexity of the system.
In Fig. 7.2, Gvcd and Gvo are the transfer functions of the IVS regulator and
the output voltage regulator, respectively. In this chapter, the three-state hysteresis
modulation is employed in the inner current loop, which will be described in detail
in Chap. 8. Figure 7.4 shows the control block diagram of each inverter module.
With well-designed current tracking, the inner current loop, as shown in the dashed
box in Fig. 7.4, can be reduced to a current follower with a gain equal to 1/K i [2, 3].
The equivalent control block diagram of Fig. 7.2 is reorganized in Fig. 7.5a, from
which we have

n
n
1
vo vo j i ref − i sv j ·
j1 j1
s K i Cf
⎛ ⎞ ⎛ ⎞

n
1 1 n
n
⎝ni ref − i sv j ⎠ · ⎝i ref − i sv j ⎠ · (7.8)
j1
s K i Cf n j1 s K i Cf
According to (7.8), Fig. 7.5a can be further simplified as shown in Fig. 7.5b, and
we have

n

i sv1 + i sv2 + · · · + i svn (Vin n − vin j ) · K vi · G vcd · i ref
j1
⎛ ⎞

n
⎝Vin − vin j ⎠ · K vi · G vcd · i ref
j1
0 (7.9)
7.2 Decoupling the Control Loops 159
+ ivd1 isv1
Kvi _ Gvcd _
Vin iref1
n vin1 + 1 1 vo1
Kvi IVS Loop Ki sCf1
+ ivd2 isv2
Kvi _ Gvcd _
iref2 +
vin2 + 1 1 vo2 +
Kvi Ki sCf2 vo
IVS Loop
…
+
…
…
+ ivdn isvn
Kvi _ Gvcd _
vinn + irefn 1 1 von
Kvi IVS Loop Ki sCfn
Inner Current Loop
+ iref
voref _ Gvo
Kvo
(a) Equivalent control block diagram of Figure 7.2
+ ivd1 isv1
Kvi _ Gvcd
Vin
n vin1
Kvi IVS Loop
ivd2 +
+ isv2 + 1
Kvi _ Gvcd
n
…
vin2 +
Kvi IVS Loop
…
+ ivdn isvn
Kvi _ Gvcd
vinn
Kvi IVS Loop
_
+ iref + n
_ Gvo vo
voref sKiCf
Kvo
(b) Further equivalent contro l block diagram
Fig. 7.5 Decoupling analysis of DC–AC ISOS system with compound balanced control strategy
+ ivd1 isv1
Kvi _ Gvcd
Vin
n vin1
Kvi IVS Loop
ivd2 +
+ isv2 + =0
Kvi _ Gvcd
…
vin2 +
Kvi IVS Loop
…
+ ivdn isvn
Kvi _ Gvcd
vinn
Kvi IVS Loop
+ iref n
Gvo vo
voref _ sKiCf
Kvo
(c) Decoupling block diagram
According to (7.9), Fig. 7.5b can be further simplified as shown in Fig. 7.5c.
Equation (7.9) means that the IVS loops have no effect on the system output voltage
loop.
The output of the system output voltage regulator iref serves as the initial current
reference for the inner current loop of each module. When iref changes, the current
reference of each module, irefj , will change simultaneously so that the output power
and input power of each module vary accordingly. For example, when IVS and OVS
are both achieved initially, the abruptly increasing load would result in a decrease of
the output voltage. In order to keep the output voltage unchanged, iref will increase,
and the output filter capacitor current and then the output voltage of each module
will rise. In the meantime, OVS and the balanced output power of all modules are
maintained. According to the principle of power conservation, the input current of
each module and hence the total input current of the system will all increase. Since
the input current is still being shared and the average current of each input dividing
capacitor is zero, IVS is maintained. It can be seen that the operation of the IVS
loops is not affected by the system output voltage loop. From the previous analysis,
7.2 Decoupling the Control Loops 161
Fig. 7.6 Block diagram of + n

the output voltage loop voref _ Gvo sKiCf vo
vof
Kvo
it is clear that the IVS loop and the system output voltage loop work independently
and they are decoupled from each other. Thus, the two control loops can be designed
separately.
7.3 Design of the Control Loops for the DC–AC ISOS

Systems
With no loss of generality, a two-module DC–AC ISOS system is taken as an example

in the following to illustrate the design of the IVS loop and output voltage loop.
The main parameters of the system are as follows: the number of modules n is
2, the input voltage is 540 V (±10%), the output voltage is 230 V AC/400 Hz, the
output capacity is 2 kVA, the input dividing capacitor C d is 1000 µF, the system
output voltage sensor gain K vo is 0.031, the input voltage sensor gain K vi is 0.03.
The main parameters of each module are as follows: the input voltage is 270 V
(±10%), the output voltage is 115 V AC/400 Hz, the output capacity is 1 kVA, the
output filter inductor L f is 600 µH, the output filter capacitor C f is 30 µF, the inner
current loop sensor gain K i is 0.2. In addition, the parameters of the first-stage full-
bridge converter of each module are given in Sect. 6.3.2 and they are not repeated
here.
7.3.1 Design of the Output Voltage Loop
From Fig. 7.5c, the control block diagram of the system output voltage loop is
extracted as shown in Fig. 7.6. From Fig. 7.6, the loop gain of the system output
voltage loop can be derived as
n K vo G vo (s)
Tvo_c (s) (7.10)
s K i Cf
Substituting the above related parameters into (7.10) and letting Gvo (s) 1, the
uncompensated loop gain can be obtained which is expressed as
n K vo 1.03 × 104
Tvo_u (s) (7.11)
s K i Cf s
Fig. 7.7 PI regulator
For the sake of improving the tracking precision of the output voltage with the
reference, a PI regulator is adopted as the output voltage regulator (see Fig. 7.7a),
with the transfer function expressed as
1
s+
R2 R2 C s + ωz
G vo (s) · G vo∞ (7.12)
R1 s s
1
where the turning frequency of PI regulator is f z .
2π R2 C
The three-state hysteresis current controlled inverter has a broad distribution of
harmonics in the output voltage and its switching frequency is variable. Denoting its
sampling frequency by f k , the three-state hysteresis current controlled inverter can
be equivalent to the PWM inverter whose switching frequency is a quarter of f k [4,
5]. In this chapter, the sampling frequency of the inverter f k is 100 kHz. Then, the
switching frequency of the equivalent PWM inverter f s is 25 kHz. One-fifth of f s , i.e.,
f c 5 kHz [6], is set as the cutoff frequency of the compensated output voltage loop.
Figure 7.8 gives the Bode diagram of the uncompensated output voltage loop gain,
from which we can find the magnitude of the uncompensated loop gain is −9.66 dB
at 5 kHz. Thus, the PI compensator should have a gain of 9.66 dB at 5 kHz, i.e.,
R2 9.66
G vo∞ 10 20 3.04 (7.13)
R1
Here, R1 is chosen as 10 k, then we have R2 30.4 k. Finally, R2 30 k is

chosen. It can be found in Fig. 7.7b that the PI regulator will not bring large phase
lag when 10f z ≤ f c . So, we have
1 5
C ≥ 10.61 (nF) (7.14)
2π f z R2 π f c R2
We choose C = 10 nF. Then, the transfer function of the PI regulator can be derived
as
7.3 Design of the Control Loops for the DC–AC ISOS Systems 163
Fig. 7.8 Bode diagram of

the uncompensated and
compensated loop gains of
the system output voltage
closed loop
s + 3.33 × 103
G vo (s) 3 · (7.15)
s
The Bode diagram of the compensated output voltage loop gain is sketched in
Fig. 7.8. It can be found that the compensated loop gain has a cutoff frequency of
5 kHz with a phase margin of 83.9°.
7.3.2 Design of the Control Loop of the First-Stage Converter

and IVS Loop
For the first-stage phase-shifted full-bridge converter, the intermediate DC bus volt-
age closed-loop control is adopted, and its design is similar to that in Sect. 6.3.2.
Meanwhile, the design of the IVS loop can also refer to Sect. 6.3.3. Similarly, we
can conclude that, if the IVS loop compensator gain satisfies (6.20), each module of
the DC–AC ISOS systems could show positive resistance characteristic at the input
side and then the system can be stable.
7.4 Simulation and Experimental Verification
In order to verify the effectiveness of the compound balanced control strategy, a

two-module DC–AC ISOS system is taken as an example in the simulation and
experiments. The main parameters of this system have been given in Sect. 7.2.
280 vin1 vin2

270
(V)
260
200 vo1 vo2 vo1-vo2
(V)
-200
20 400 vo
(A)
(V)
0 0 io
-20 -400
0.110 0.112 0.114 0.116 0.118 0.120
t (ms)
(a) Full resistive load
280
vin1 vin2
270
(V)
260
200 vo1 vo2 vo1-vo2
(V)
-200
20 400 vo
io
(A)
(V)
0 0
-20 -400
0.110 0.112 0.114 0.116 0.118 0.120
t (ms)
(b) Full inductive load
Fig. 7.9 Simulation waveforms at steady state
7.4.1 Simulation Results
Figures 7.9a, b gives the steady-state simulation waveforms of the system with the
full resistive and full inductive load (cos θ = 0.75), respectively. As shown, the system
achieves IVS and OVS under various load conditions.
Figure 7.10 shows the system dynamic simulation waveforms. Figure 7.10a gives
the system simulation waveforms at full resistive load (2 kW) with the input voltage
stepping between 486 V (90% of the rated input voltage) and 594 V (110% of the
rated input voltage). Figure 7.10b gives the system simulation waveforms at rated
input voltage (540 V) conditions with the load current stepping between 1/3 full load
and full load. It can be seen from the waveforms that IVS and OVS are well achieved
during the transients.
7.4 Simulation and Experimental Verification 165
640
560
(V)
vin
480
320
280
(V)
vin1 vin2
240
200 vo1 vo2 vo1-vo2
(V)
-200
58 60 62 64 66 68 70 72
t (ms)
(a) Step-input-voltage condition
20 io
0
(A)
-20
280
(V)
270
vin1 vin2
260
200 vo1 vo2 vo1-vo2
(A)
-200
82 84 86 88 90 92
t (ms)
(b) Under step-load
Fig. 7.10 Dynamic simulation waveforms
Figure 7.11 shows the steady-state simulation waveforms of the system at full
resistive load with an unmatched output filter capacitor (C f1 30 µF, C f2 25 µF).
It can be found in Fig. 7.11a that when the output filter capacitor current feedback is
adopted, the output filter capacitor currents of two modules have the same phase but
the different amplitude, and the output voltage of each module are equal. This implies
that the unmatched output filter capacitors do not influence OVS when employing the
output filter capacitor current feedback. From Fig. 7.11b, it can be found that when
the output filter inductor current feedback is employed, the output filter inductor
currents of two modules have the same phase but different amplitude, and the output
Fig. 7.11 Steady-state simulation waveforms of the two kinds of current feedback with unmatched
output filter capacitor (at full resistive load)
voltages of two modules have phase difference and vo1 lags behind vo2 . The difference
between the two voltages vo1 − vo2 lags load current io by 90°, which indicates that
there is the reactive power difference at the outputs of two modules. The simulation
results in Fig. 7.11 are in agreement with the theoretical analysis in Sect. 7.1.
7.4.2 Experimental Results
In order to further validate the effectiveness of the proposed compound balanced

control strategy, a two-module DC–AC ISOS system prototype is built in the lab
and the experiment has been carried out. The parameters are the same as that of the
simulation.
Figure 7.12 shows the experimental waveforms at steady state with full resistive
and full inductive load (cos θ = 0.75). As seen, the system achieves IVS and OVS
under various load conditions. Figure 7.13a, b shows the dynamic experimental
waveforms when the input voltage of the system is step changed between 486 and
594 V and when the load is step changed between 1/3 full load and full load. As
seen, IVS and OCS are well achieved during the transient.
Obviously, the compound balanced control strategy can effectively realize IVS
and OVS both at steady state and during the transient.
Figure 7.14a, b shows the steady-state experimental waveforms of the two-module
DC–AC ISOS system (at full resistive load) with output filter capacitor current feed-
back and output filter inductor current feedback, respectively. Here, the output filter
capacitors are intentionally set at different values, i.e., C f1 30 µF, C f2 25 µF. As
shown in Fig. 7.14a, despite the difference between the output filter capacitors, the
two modules can still effectively achieve OVS when using the output filter capacitor
current feedback. While from Fig. 7.14b we can find that when adopting the output
filter inductor current feedback, the difference between the output filter capacitors
leads to a phase difference between the output voltages of the two modules, and vo1
lags vo2. The difference between the two voltages vo1 − vo2 lags the load current
io by 90°, indicating the existence of output reactive power difference between the
two modules. Obviously, even if the output filter capacitors are not matched, the
filter capacitor current feedback control can still achieve OVS among the constituent
modules.
7.5 Distributed Control Strategy for DC–AC ISOS Systems
The compound balanced control strategy proposed in Sect. 7.1 includes three control
loops, namely, the system output voltage loop, the IVS loop and inner current loop
of each module. The output voltage loop is common used for all modules, and
this scheme is a centralized control without realizing full modularity of the system.
Therefore, in this section, a distributed control method [7] is given and its control
block diagram is shown in Fig. 7.15, where each module has three independent control
loops: IVS loop, output voltage loop, and inner current loop. And the communication
among the modules is achieved through the buses, in which the input voltage sharing
bus signal is obtained by the average circuit and its value is V in /n.
M1 vin1 : [100V/div]
C1 vo1 : [200V/div]
C1/M1
C2/M2
F1 F1 vo1-vo2 : [200V/div] C2 vo2 : [200V/div]

C3: vo[400V/div] M4: io[20A/div]
C3/M4
Time: [2ms/div]
(a) At full resistive load
C1 vo1 : [200V/div]
C1/M1
C2/M2

C3/M4
Time: [2ms/div]
(b) At full inductive load
Fig. 7.12 Experimental waveforms under steady state
Additionally, the output voltage references of all the modules can be synchronized
with DSP to form the output voltage reference bus denoted as voref . Moreover, the
output voltage feedback signals of all the modules, vofj , are averaged to generate the
output voltage average bus, denoted as vof_ave . The error between voref and vof_ave
is sent to each output voltage regulator. It should be noted that from Fig. 7.15, the
average feedback signal vof_ave of each module is obtained as
vof_ave (K vo · vo1 + K vo · vo2 + · · · + K vo · von ) K vo · vo /n (7.16)

7.5 Distributed Control Strategy for DC–AC ISOS Systems 169
M1 vin : [100V/div]
M1 C2 vo1 : [200V/div]
C2/M2
M3
C3
Time: [10ms/div]
(a) Under step-input-voltage condition
M1 M1 io : [20A/div]
C2 vo1 : [200V/div]
C2
M2
C3/M3
Time: [5ms/div]
(b) Under step-load
Fig. 7.13 Dynamic experimental waveforms.
Equation (7.16) shows that it is the average of all the module’s output voltages that
tracks the synchronous voltage reference voref in each independent output voltage
loop. So, the control effect here is equivalent to that of the previous centralized
control strategy in which the output voltage of the system is adjusted to realize
its sinusoidal output. However, different from the centralized control strategy, the
proposed distributed control strategy has a set of independent output voltage loop for
each inverter module. In addition, the common current reference bus signal iave of
each module is also obtained by means of the average circuit, and the inner current
loop of each module is independent of each other. It can be seen that in the distributed
C1 vo1 : [200V/div]
C1/M1
C2/M2

C3/M4
Time: [2ms/div]
(a) With the output filter capacitor current feedback
M2 vin2 : [100V/div] C1 vo1 : [200V/div]

C1/M1
C2/M2

C3/M4
Time: [2ms/div]
(b) With the output filter inductor current feedback
Fig. 7.14 Steady-state experimental waveforms of the two kinds of current feedback with
unmatched output filter capacitor (at full resistive load)
control method, the control circuits are scattered in individual modules so that each
module can work independently and the true modularity is achieved for the system.
The control mechanism of the input and output voltage sharing of the proposed
strategy can be further illustrated as follows. Actually, the IVS loop alters the real
power at the output terminal to achieve IVS. Since the output signals of the IVS
regulator ivdj are DC components while the variables at the output terminal are AC
quantities. So the multipliers are introduced here to multiply the DC deviation ivdj
with the AC variable iave . In this way, the phase of the signal that is used to tune
the current reference by the IVS loop is kept the same with that of the original
common current reference iave so as to ensure the synchronization of the current
reference, irefj , with the IVS loop only slightly adjusting the magnitude of it. From
the compound balanced control conception, we know that both IVS and OVS could
be achieved under IVS control combined with the synchronization of the power factor
angle of each module simultaneously. So here the output filter capacitor feedback
voref Vin vof_ave
n iave
IVS Loop
+ ivd1 isv1
Kvi _ Gvcd Inner Current Loop
vin1 _ iref1 vinv1 _ iLf1 iCf1
Kvi + + 1 1 vo1
_ G i G inv sLf +_ sCf
voref + ig1 +
_ Gvo
vof_ave Ki
Output Voltage Loop
Kvo
IVS Loop
+ ivd2 isv2
vin2 _ iref2 vinv2 _ iLf2 iCf2
Kvi + + 1 1
_ G i G inv sCf vo2
voref + ig2 + sLf +_
_ Gvo
vof_ave Ki
Output Voltage Loop
Kvo io
Output 1
IVS + Common
7.5 Distributed Control Strategy for DC–AC ISOS Systems
Output
…
ZLd
…
Bus
Voltage 1 + + + 1 Current +
Voltage Average n n
…
+ + Reference +
Reference Bus
…
Bus vo
Bus +
IVS Loop
+ ivdn isvn
vinn _ irefn vinvn _ iLfn _ iCfn
Kvi + + 1 1 von
_ G i G inv sLf + sCf
voref + ign +
_ Gvo
vof_ave Ki
Output Voltage Loop
Kvo
171
Fig. 7.15 Block diagram of distributed control strategy for DC–AC ISOS system
is adopted for the inner current loops. Since the output voltage lags the output filter
capacitor current in phase by 90° and all the output filter capacitor currents track the
synchronous current references, phase synchronization of the output voltages of all
the modules is fulfilled.
Similar with the aforementioned centralized control, the output filter inductor
current feedback can also be used in the distributed control of DC–AC ISOS systems,
which is not repeated here.
7.6 Summary
Aiming for achieving IVS and OVS for the DC–AC ISOS systems, this chapter
presents an implementation of the compound balanced control strategy, i.e., the
combined control strategy of IVS and output phase synchronization. For the inner
current loop, when adopting the output filter inductor current feedback, OVS can be
realized only if the output filter capacitors are well matched; while when the output
filter capacitor current feedback is adopted, OVS can be achieved no matter the output
filter capacitors are matched or not. The compound balanced control strategy with
the output filter capacitor current feedback is analyzed, and it is pointed out that the
IVS loop and the system output voltage loop are decoupled each other, and these
control loops can be designed independantly.
A prototype of two-module DC–AC ISOS systems has been fabricated in the lab.
The simulation and experimental results show that the proposed combined control
of IVS and output phase synchronization is effective.
Moreover, based on the centralized control, a distributed control scheme is pro-
posed, in which all the control loops are dispersed into each module, and hence the
modularity of the system is achieved.
References
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3. Chen, L., Xiao, L., Gong, C., Yan, Y.: Circulating current’s characteristics analysis and the
control strategy of parallel system based on double close-loop controlled VSI. In: Proceedings
of the IEEE Power Electronics Specialists Conference, pp. 4791–4797 (2004)
4. Venkataramanan, G., Divan, D.M., Jahns, T.M.: Discrete pulse modulation strategies for high-
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5. Venkataramanan, G., Divan, D.M.: Pulse width modulation with resonant dc link converters.
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6. Li, A., Zhang, C.: Modern Inverter Technology and its Application. Science Press, Beijing,
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Chapter 8
An Improved Average Current Control
Strategy for DC–AC
Input-Parallel-Output-Parallel Systems
Abstract For the DC–AC input-parallel-output-parallel (IPOP) systems, the output

current sharing control strategy is popular and effective to achieve output current
sharing (OCS) among the constituent modules, and the average current control is
usually adopted. The load current feed-forward scheme is incorporated into the aver-
age current control and the load current feed-forward node is located before the
current-limiting unit, for not only improving the DC–AC IPOP system output volt-
age characteristics but also limiting the load current. The prototype of two-module
DC–AC IPOP systems is built in the lab, and the steady-state and dynamic experi-
ments are provided to verify the superiority of the proposed improved strategy.
Keywords Input-parallel-output-parallel systems · Average current control

Load current feed-forward · Output characteristics
Three-state hysteresis modulation
The DC–AC input-parallel-output-parallel (IPOP) systems, commonly known as the

parallel inverter system, features ease of system capacity expansion and achievement
of N + 1 redundancy of system, improving the system reliability. It has been widely
used in uninterruptible power supply (UPS), aeronautical static inverters, etc.
It has been pointed out in Chap. 5 that the output current sharing control strategy or
the compound input current sharing control strategy could be applied to DC–AC IPOP
system. Comparatively, the output current sharing control is quite simpler than the
compound input current sharing control strategy, and it is usually employed. In Sect.
1.4.1, various implementations of the output current sharing control strategy have
been presented [1–13]. Centralized control and master–slave control are simple, but
they have poor redundancy owing to relying on the central control unit or the master
module to operate. Wireless droop control is not susceptible to interference and is easy
to implement the redundancy due to no connection among the constituent modules,
but the output characteristics are poor. As one of the distributed control schemes,
the average current control has the merits of simple control circuit, prompt current
sharing regulating speed, and ease of implementation of hot-swap and redundant
control. However, the DC–AC IPOP system with the average current control also has
the defect of poor output characteristics. For tackling this issue, the chapter proposes
176 8 An Improved Average Current Control …
a control strategy of the inductor current feedback combined with the load current
feed forward, which can greatly improve the output characteristics with preservation
of the original current-limiting function.
8.1 Current Three-State Hysteresis Modulation
In this chapter, the basic module in the DC–AC IPOP systems still adopts the
two-stage configuration consisting of full-bridge DC–DC converter and full-bridge
inverter, as shown in Fig. 8.1. Same as that in Chaps. 6 and 7, the first-stage full-
bridge DC–DC converter controls its output voltage V dc . The second-stage full-bridge
inverter adopts double closed-loop control, composed of outer voltage control and
inner current loop. The inner current loop adopts the three-state hysteresis modulation
and the control variable is the filter inductor current iLf .
The operating waveforms of the three-state hysteresis modulation are given in
Fig. 8.2, where iref is the current reference, if is the sensed filter inductor current, 2h
is the current hysteresis, and Clk is the sampling clock. If if < iref − h at the sampling
instant, power switches S 1 and S 4 are turned on, and the output voltage of inverter
bridge, vinv , is equal to +V dc , which is defined as +1 state. Because V dc > vo , iLf is
forced to increase. If if > iref + h at the sampling instant, S 2 and S 3 are turned on, and
thus vinv −V dc , which is defined as −1 state. Because −V dc < vo , iLf declines. If
if is within the hysteresis width at the sampling instant, i.e., iref − h < if < iref + h, S 2
and S 4 are turn on, or S 1 and S 3 are turned on, and thus vinv 0, which is defined
as zero state. At zero state, iLf is freewheeling, and whether it increases or decreases
depends on the polarity of the output voltage vo , namely, if vo is positive, iLf declines;
and if vo is negative, iLf rises. The rates of the rise and decline of iLf in zero state
are smaller than that of +1 and −1 state, respectively. Since the inverter could be
Full-Bridge DC-DC Converter Ldc Full-Bridge Inverter

Iin DR1 DR3
iLdc
Lf
Q1 Q3 Tr S1 S3 io
+ A + iLf +
*
*
Vdc vinv ZLd vo

Vin Cdc _
_ Cf
_ B
Q2 Q4 S2 S4
DR2 DR4
Fig. 8.1 Main circuit topology of basic inverter module

8.1 Current Three-State Hysteresis Modulation 177
operated at +1, 0, and −1 states, the above current control is called the three-state
hysteresis modulation.
In summary, at the sampling instant, the operating state S is determined as
⎧
⎪
⎨ +1, i f < i ref − h
S 0, i ref − h < i f < i ref + h (8.1)
⎪
⎩ −1, i f > i ref + h
As shown in Fig. 8.2, it is noteworthy that the operating state does not change
immediately once the inductor current exceeds the hysteresis band, and it does only
when the sampling clock comes. In addition, when the output voltage is in positive
(negative) half cycle, the inverter switches between +1 (or −1) and 0 states. This
implies that the inverter is operated with unipolar modulation. Compared with the
bipolar modulation where the state of the inverter is modulated between +1 state and
−1 state [14], the three-state hysteresis modulation has the following advantages:
(1) The ripple of filter inductor current is relatively small. (2) Due to the presence of
freewheeling mode, the feedback energy to the intermediate bus is relatively small
and thus has little influence on the DC bus voltage.
Figure 8.3a shows the double closed-loop control block diagram of the second-
stage full-bridge inverter, where the outer voltage loop Gvo adopts PI regulator,
and the inner current loop adopts the three-state hysteresis modulation. voref is the
output voltage reference, vo is the output voltage, K vo is the sensor gain of the output
voltage, and C f is the output filter capacitor, and Z Ld is the load impedance. Generally,
Fig. 8.2 Operating waveforms of three-state hysteresis modulation

Fig. 8.3 Double closed-loop control block diagram
the switching frequency is much higher than the output frequency, the inner loop
(referring to the dashed frame in Fig. 8.3a) can be simplified as the current follower
whose magnification is 1/K iL [15]. Thus, Fig. 8.3a can be reduced to Fig. 8.3b when
the load current feed forward is not included.
8.2 Improvement of the Output Characteristics of Inverter
As mentioned above, a PI regulator is chosen as the outer voltage regulator for the
inverter module. Although the output voltage static error could be very small with
properly designed PI regulator, it cannot be fully eliminated. In order to improve the
output characteristics, the load current feed forward [16] is introduced as shown with
the dashed lines in Fig. 8.3b, where K io is load current sensor gain. The load current
feed-forward could be located at point ➀ or ➁, and the function of the current-limiting
unit is different, which will be analyzed later. Obviously, under normal operating
condition when the current-limiting unit is not activated, the output characteristics
of the inverter are the same. With the current-limiting unit omitted, by replacing the
feed-forward signal io with vo , Fig. 8.3b can be equivalent to Fig. 8.4a. By simplifying
the transfer function from iLf to vo in the dashed box, Fig. 8.4a can be further reduced
to Fig. 8.4b.
As mentioned above, the voltage regulator adopted a PI regulator is expressed as
1
G vo (s) K PI + . Hence, according to Fig. 8.4b, the transfer function from the
sτPI
output voltage reference to the output voltage can be derived as
8.2 Improvement of the Output Characteristics of Inverter 179
io 1
Kio
ZLd
voref + + iref iLf io vo
Gvo 1/KiL _ ZLd
+ _ +
sCf
Kvo
(a) Equivalent control block diagram with current-limiting unit omitted
io 1
Kio ZLd
voref + + iref iLf ZLd vo
Gvo 1/KiL
+ _ 1+sCfZLd
Kvo
(b) Further equivalent control block diagram
Fig. 8.4 Transfer function derivation of the inverter module
1
K PI s +
Vo (s) τPI
(8.2)
Voref (s) K iL − K io K vo
s 2 K iL Cf + s + K vo K PI +
Z Ld τPI
where the load Z Ld can be expressed in the following form:
Z Ld |Z Ld |(cos ϕ + j sin ϕ) (8.3)
where |Z Ld | is the magnitude of the load, and ϕ is the power factor angle of the load.
If ϕ = 0, the load is purely resistive; if ϕ > 0, the load is inductive; and If ϕ < 0, the
load is capacitive.
Substituting (8.3) into (8.2), we have

2 ω2 + 1
K PI
Vo ( jω) 2
τPI

2 2
Voref ( jω)
K vo ω(K iL − K io ) sin ϕ (K iL − K io ) cos ϕ
− Cf K iL ω2 + + + K vo K PI ω2
τPI |Z Ld | |Z Ld |
(8.4)
According to (8.4), when the load current feed forward is not introduced, i.e.,
K io 0, with the parameters of the inverters given in Sect. 8.4, the curves of the
output voltage versus the load current with different ϕ can be depicted as shown in
Fig. 8.5. From Fig. 8.5, it can be found that, (1) When the load is resistive or inductive
(ϕ ≥ 0°), the output voltage declines with the increase of the load current, and the
larger the ϕ is the more the output voltage declines; and (2) When the load is capacitive
(ϕ < 0°), the output voltage rises with the increase of the load current, and the larger
Fig. 8.5 Output voltage characteristics with and without the load current feed forward
the ϕ is the more the output voltage rises. In conclusion, the output characteristics
are relatively poor when the load current feed-forward is not incorporated.
When the load current feed forward is introduced and K io is set to be equal to K iL ,
it can be found from (8.4) V o is independent of the load as shown in Fig. 8.5, which
is the desired output characteristic.
In conclusion, when introducing the load current feed-forward and letting K io
K iL , the output voltage of inverter is independent of the load and the optimal output
characteristics is achieved. At this time, the feedback signal is the capacitor current in
the current loop [16]. When the load current feed-forward node is located at point ➀,
the current-limiting unit (as shown in Fig. 8.3b) actually limits the capacitor current,
and the load current cannot be limited since the capacitor current does not contain the
information of the load current. When the load current feed-forward node is located
at point ➁, the current-limiting unit limits the inductor current and thus the load
current. So, it is desirable to locate the load current feed-forward node at point ➁.
8.3 Configuration and Control Scheme for DC–AC IPOP

Systems
8.3.1 Configuration of the DC–AC IPOP Systems
As illustrated above, the DC–AC IPOP systems generally adopts the OCS control
strategy, which could be implemented with centralized, master–slave, or distributed
control. The distributed control includes average current control and wireless droop
control. In this chapter, the average current distributed control is adopted [7], and the
8.3 Configuration and Control Scheme for DC–AC IPOP Systems 181
system configuration is shown in Fig. 8.6a. As seen, there are two signals among the
control circuits of each module. One is the synchronizing signal syn, which ensures
the sinusoidal voltage references of modules synchronous, and the synchronizing
circuit is shown in Fig. 8.6b. The other is the averaging current reference iave , which
is obtained by averaging all the outputs of modular voltage regulators as shown in
Fig. 8.6c. iave is regarded as the common current reference of all the current regulators
achieving the current sharing among the modules. K 1 is the output relay and K 2 is
the current reference access-control relay. Once a module fails, its K 1 and K 2 will
be turned off, and the driving signals for the switches will be disabled. The other
modules will supply the load.
8.3.1.1 Synchronous Circuit
To ensure stable operation of the DC–AC IPOP systems, the amplitude, frequency
and phase of the output voltage of each inverter module are all required to be consis-
tent. The voltage reference of each module is generated by the high-precision D/A
chip (MAX507) of the respective module, the frequencies of the output voltages of
modules can be the same. Figure 8.6b gives the phase synchronizing circuit for the
voltage reference [17], in which each voltage reference tracks the phase information
of the synchronizing bus, syn. In each inverter module, a rising edge is emitted via
signal port PB1 at the positive zero-crossing point of the voltage reference, and it
induces a rising edge on the synchronizing bus. For the synchronizing bus, the first
rising edge signal is regarded as the valid signal, and it is sent to the capture port
CAP1 as a common synchronizing signal to fulfill the transmission and judgment of
synchronizing signal. CAP1 captures the trailing edge and generates the synchronous
interrupt request, and the DSP enters capture interrupt service routine. Here, the phase
of the corresponding voltage reference starts from the positive zero-crossing of sinu-
soidal wave, achieving the zero-crossing phase-lock. From Fig. 8.6b, it can be found
that as long as port PB1 of DSP of any inverter module is high, synchronous bus syn
is high, which is tracked by the other inverter modules to achieve synchronization.
With the synchronizing circuit, the phase difference of the output voltage in each
cycle can be corrected, and the safety and reliable operation of the DC–AC IPOP
systems will be ensured.
8.3.1.2 Instantaneous Average Circuit
In addition to ensuring synchronization of the output voltage phase, the output current
sharing control is required for achieving power sharing among the inverter modules
for DC–AC IPOP systems. So, it is better to produce the averaging instantaneous
current reference for the modules, and the averaging circuit is shown in Fig. 8.6c,
where irefj is the inductor current reference signal of jth inverter module (j = 1, 2, …,
n). The average value of the current reference signals can be obtained as
Vin vo syn iave
K1
Inverter 1
iref1
K2
syn
DSP 1
K1
Inverter 2
iref2
K2
syn
DSP 2
K1
Inverter n
irefn
K2
syn
DSP n
(a) Block diagram of system structure
syn
+15V +15V +15V

INV1 INV2 INVn
PB11 PB12 PB1n
CAP11 CAP12 CAP1n
(b) Synchronizing circuit
_ _ _
iave iave iave
iref1 + iref2 + irefn +
R R R
iave
(c) Current reference instantaneous averaging circuit
Fig. 8.6 Block diagram of IPOP inverter

8.3 Configuration and Control Scheme for DC–AC IPOP Systems 183

i ave (i ref1 + i ref2 + · · · + i refn ) n (8.5)
And iave serves as the common current reference for each module.
From (8.5) and Fig. 8.6c, we can also see that this averaging circuit, which is
equally distributed in each module, is independent on the number of parallel inverter
modules. Thus, the distributed control method can achieve redundant control of the
DC–AC IPOP systems.
8.3.2 Control Scheme
As indicated in [7], the outputs of voltage regulators of all the inverter modules are
averaged, and the average signal serves as the current reference for the inductor
current of all inverter modules and it is independent on a particular module, allowing
hot-swap of any module. The block diagram of the average current distributed control
for DC–AC IPOP systems is shown in Fig. 8.7, where each inner current loop of three-
state hysteresis modulation has been simplified as a current follower, and the load
current feed forward is incorporated to improve the output characteristics. According
to the analysis of Sect. 8.2, when the load current feed forward is located before the
current-limiting unit K ioj K iLj (j = 1, 2, …, n), the output voltage will be independent
of the load, while the current-limiting function is preserved.
8.4 Experimental Results
To verify the validity of the theoretical analysis, a 2-kVA two-module DC–AC IPOP
system prototype is fabricated in the laboratory. The specifications of the inverter
module are as follows: Rated output power: Po_mod 1 kVA, input voltage V in
270 VDC, output voltage V o 115 VAC/400 Hz, output filter inductor L f 600 µH,
sensor gain K ioj K iLj 0.2.
Figure 8.8 gives the measured output voltage versus the output current of the
system with and without the load current feed forward at the resistive load. As
seen, the output characteristics of the system have been greatly improved with the
introduction of the load current feed-forward scheme.
Figure 8.9 gives the experimental waveforms of a single inverter when the load
is step changed between the rated resistive load current and over current. Here, the
output current of the inverter is limited at 1.5 times of the rated load. As seen, the
inductor current is limited and thus the load current is limited, and the inverter has
good dynamic performance.
Figure 8.10 gives the experimental waveforms of the DC–AC IPOP system when
the load steps up and down between the rated resistive load current and overcurrent.
It also can be seen that the load currents of the two inverter modules are successfully
voref iave
Kio
iCf1 _ sCf1
+
voref + iLf1 io1
Gvo1 iref1 1/KiL1
+_ +
vof
Kvo
Module # 1
Average Current Bus
+ ioj + vo
irefj + 1 +
n ZLd
+ +
Kio
+
voref + iLfn ion
Gvon irefn 1/KiLn
+_ + _
vof iCfn
sCfn
Kvo
Module #n
Fig. 8.7 Block diagram of the control in DC–AC IPOP systems
116.0
115.5
115.0
Output voltage (V)
114.5
114.0
113.5
113.0 Without the load current feed-forward

With the load current feed-forward
112.5
0 5 10 15 20
Output current (A)
Fig. 8.8 Measured output characteristics curves of the system
limited, and the DC–AC IPOP system exhibits excellent dynamic performance. It
is evident that the current-limiting function is effective, which is well in agreement
with the theoretical analysis.
vo [100V/div]
iL [10A/div]
io [10A/div]
Time: [5ms/div]
Fig. 8.9 Experimental waveforms of a single inverter module with stepped load current
vo [100V/div]
io1 [10A/div]
io2 [10A/div]
Time: [5ms/div]
Fig. 8.10 Experimental waveforms of the DC–AC IPOP system with stepped load current
Figure 8.11 gives steady-state experimental waveforms of the DC–AC IPOP sys-
tem with the improved method at full resistive load. As seen, the difference between
the output currents of the two inverter modules is fully eliminated, which means OCS
is achieved.
Figure 8.12 shows the dynamic experimental waveforms of the DC–AC IPOP
system when the load current is step changed between the full resistive load and
no-load. It can be seen that the output currents of the two modules are equal during
the transient showing that OCS is also achieved.
Figure 8.13a shows the experimental waveforms of the system output voltage vo ,
output current of module 1, io1 , output current of module 2, io2 , when module 2 is
plugged into the DC–AC IPOP system. As seen, before module 2 is plugged into
Fig. 8.11 Steady-state waveforms of the DC–AC IPOP system at full resistive load
Fig. 8.12 Dynamic waveforms of the DC–AC IPOP system
the system, module 1 provides all the load current; and when module 2 is plugged
into the system, io1 declines, and io2 increases from zero, and finally, they provide
the load current equally, and there is no obvious distortion in vo . Figure 8.13b gives
the experimental waveforms when module 2 is plugged out from the DC–AC IPOP
system. When the control circuit produces the plug-out command, power switches in
module 2 are turned off, and module 2 is plugged out from the DC–AC IPOP system
after about eight output cycles due to the delay of the output relay operation. So,
during the period, module 1 supplies power to the load and the output filter capacitor
of module 2, and io2 initially reduces to the output filter capacitor current and then
reduces to zero after around 20 ms. It can be seen that there is no obvious distortion
in vo in the above process. Figure 8.13 illustrates that the DC–AC IPOP system has
excellent dynamic performance, and hot-swap is also achieved.
8.5 Summary 187
v o [100V/div]
i o1 [5A/div]
i o2 [5A/div]
Time: [2ms/div]
(a) Module 2 is plugged into the IPOP operation
v o [100V/div]
io1[5A/div]
io2[5A/div]
Time: [2ms/div]
(b) Module 2 is cut off from thedc-ac IPOP system
Fig. 8.13 Hot-swap waveforms of the DC–AC IPOP system
8.5 Summary
This chapter first introduces the main circuit topology and control method of the
inverter module, and the operation principle of the current three-state hysteresis
modulation is also presented. The load current feed-forward scheme is incorpo-
rated for making the output voltage of the inverter independent of load current. It
is worth noting that the load current feed-forward node should be located before
the current-limiting unit, for not only improving the inverter output characteristics
but also limiting the load current. This idea is also extended to the DC–AC IPOP
systems.
Second, this chapter puts forward the system architecture of average current
distributed control strategy, which includes two critical signal buses, namely, syn-
chronous voltage reference bus and average current reference bus. The voltage ref-
erence of each inverter module tracks the phase information of synchronous bus for
the purpose of synchronization. In the meanwhile, the current references of all mod-
ules are averaged to obtain the common current reference signal for each module so
as to realize output current sharing among the modules. With this average current
distributed control, the DC–AC IPOP system achieves the hot-swap function and
redundant ability.
Finally, the prototype of two-module DC–AC IPOP systems is built in the lab,
and the steady-state and dynamic experiments are provided. The experimental results
are consistent with the theoretical analysis verifying the superiority of the proposed
improved strategy and also realizing hot-swap of DC–AC IPOP system.
References
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Chapter 9
Input Voltage Sharing Control Strategy
for ISOP Systems Under Extreme Load
Conditions
Abstract Input-series and output-parallel (ISOP) systems are very suitable for high
input voltage and high power applications. Input voltage sharing (IVS) and output
current sharing (OCS) of the constituent modules in the ISOP systems should be
ensured. This chapter reveals the failure mechanism of IVS of the ISOP systems
under extreme load conditions. Based on the existed IVS control strategies, this
chapter proposes two methods, including changing the weighted averages of IVS
loops and adding an IVS auxiliary circuit, to achieve IVS of the modules under
the extreme load conditions. The experimental results are presented to verify the
effectiveness of the proposed methods.
Keywords Input-series output-parallel system · Extreme load conditions

Input voltage sharing · Weighted average · Auxiliary circuit
For the ISOP systems, including the DC–DC ISOP system and DC–AC ISOP sys-
tem, the control strategies proposed from Chaps. 2 to 7 realize IVS all by adjusting
the module output power by means of regulating the duty cycle of the constituent
modules. When the ISOP systems operate under extreme load conditions such as
light load or short-circuit, the module output powers are very small, and the duty
cycles are also very small. With the small duty cycle, the adjustment range of the duty
cycle is limited, and the abovementioned control strategies cannot ensure IVS any-
more, which may cause the module with higher input voltage damaged. This chapter
will reveal the failure mechanism of IVS of the ISOP systems under extreme load
conditions. Furthermore, this chapter will propose two methods, including changing
the weighted averages of IVS loop and adding an auxiliary IVS circuit to achieve
IVS for ISOP systems under extreme load conditions [1].
192 9 Input Voltage Sharing Control Strategy for ISOP Systems …
Iin Iin1 Io1 Io

+ Icd1 DC-DC +
Vin1 (DC-AC) Vo
_ Cd1 Module Cf1 RLd _
Module 1
Vin Iin2 Io2

+ Icd2 DC-DC
Vin2 (DC-AC)
_ Cd2 Module Cf2
Module 2
Fig. 9.1 Two-module ISOP system
9.1 Reason of Input Voltages Imbalance of ISOP Systems

Under Extreme Load Conditions
In Chaps. 2 and 5, the conversion efficiencies of the modules are assumed to be equal.
However, this is impossible in practical circuits. This section will analyze the effect
of mismatched conversion efficiencies on IVS under extreme load conditions.
For simplification of analysis, a two-module ISOP system is taken as an example
as shown in Fig. 9.1. Assuming the ISOP system operates at steady state and denoting
the loss of module as Plossj (j = 1, 2), we have

Pin1 Po1 + Ploss1
(9.1)
Pin2 Po2 + Ploss2
where Pin1 and Po1 are the input power and output power of module 1, respectively
and Pin2 and Po2 are the input power and output power of module 2, respectively.
At steady state, the average currents of the input dividing capacitors are zero, i.e.,
I cd1 = I cd2 0, then the input currents of two modules are equal, i.e.,
Iin1 Iin2 Iin (9.2)
With the help of IVS loops, the input voltages of two modules are equal, i.e.,
Vin1 Vin2 Vin /2 (9.3)
Combining (9.2) and (9.3), we have
Pin1 Vin1 Iin1 Vin2 Iin2 Pin2 (9.4)

9.1 Reason of Input Voltages Imbalance of ISOP Systems … 193
This means that if IVS is achieved, the module input powers will be balanced.
Combining (9.1) and (9.4), we have
Po2 − Po1 Ploss1 − Ploss2 (9.5)
Assuming Ploss1 > Ploss2 , we have
Po1 < Po2 (9.6)
From the above analysis, if the module losses are not identical, the IVS loops
will adjust the module output power. The output power of the module with larger
losses will be reduced and the output power of the module with lower losses will
be increased. By doing so, the module input powers will be balanced and thus IVS
between the modules is ensured. Obviously, the difference of the module output
powers equals the difference of the module losses. Therefore, in order to realize
IVS, the total output power of the ISOP system must be higher than the difference
of the module losses. Only with this condition, it is possible for the IVS loops to
regulate the module output power to make the module input powers be balanced. In
the meanwhile, the IVS loops must have enough regulation ability to ensure that the
difference of the module output powers can compensate the difference of the module
losses.
The output power of ISOP systems is close to zero under extreme load conditions,
i.e., light load, no–load, or short-circuit, but the difference of the module losses may
still exist and larger than the system output power, which means that the IVS loops
cannot compensate for the difference of the module losses by regulating the module
output power, leading to input voltages imbalance of the ISOP systems.
According to (9.5), we have
Po2 − Po1 Ploss1 − Ploss2
Io2 − Io1 (9.7)
Vo Vo
Equation (9.7) indicates that control strategies to ensure IVS for ISOP systems will
cause output currents imbalance among the modules when the module conversion
efficiencies are different. The output voltage of ISOP systems is close to zero under
the short-circuit condition with current-limiting. It will cause large output current
different among the modules even if the difference of the module losses is smaller
when IVS is ensured. The module with larger output current may fail due to the
overcurrent of the power devices. Therefore, we need to not only limit the system
total output current but also limit the individual module output current under the
condition of short-circuit current-limiting.
Fig. 9.2 Equivalent loss

model under extreme load
conditions
Cd1 Rloss1
Cd2 Rloss2
Vin
Cdn Rlossn
9.2 Input Voltage Sharing Control Strategy for ISOP

Systems Under Extreme Load Conditions
In Sect. 9.1, it is pointed out that under extreme load conditions, the difference among
the module losses is the main reason of the input voltages imbalance of ISOP systems
with the control strategies mentioned in the previous chapters. Under extreme load
conditions, the output power of each module is very small and approximately equal
to its loss, therefore, the equivalent loss model of ISOP system under extreme load
conditions can be illustrated in Fig. 9.2, where Rlossj (j = 1, 2, …, n) represents the
module loss and it should be noted that Rlossj varies depending on the input voltage.
At steady state, all Rlossj (j = 1, 2, …, n) have the same flowing current. Hence, the
larger the Rlossj , the higher the module input voltage is, and the smaller Rlossj , the
lower the module input voltage is. Thus, it is required that Rloss1 Rloss2 ··· Rlossn
for achieving IVS. There are two methods to achieve IVS for ISOP systems under
extreme load conditions, that is, (1) regulating Rlossj (j = 1, 2, …, n) to be equal and
(2) connecting a parallel adjustable resistance to Rlossj (j = 1, 2, …, n) to make the
all the equivalent resistances to be equal as shown in Fig. 9.3.
9.2.1 Changing the Weighted Values of the IVS Loops
At light load, there is no need for all modules in the ISOP systems to work, and
only a few of modules can be activated for supplying the needed load power. For
the disabled modules, their equivalent resistances Rloss are infinite. If we can make
the modules work intermittently and adjust their working time, then the equivalent
resistances of modules can be adjusted to be equal to realize IVS under extreme load
conditions.
9.2 Input Voltage Sharing Control Strategy for ISOP … 195
Fig. 9.3 Method of

achieving equal equivalent
resistance R1
Cd1 Rloss1
R2
Cd2 Rloss2
Vin
Rn
Cdn Rlossn
The DC–DC ISOP system is taken as an example to discuss the IVS control
strategy under extreme load conditions, which is also suitable for the DC–AC ISOP
system. For the convenience of illustration, the IVS control strategy for DC–DC
ISOP system (see Fig. 3.19) is redrawn here as shown in Fig. 9.4. In order to explain
the proposed control strategy with changeable weighted values of the IVS loops,
the weighted value K vcd is added to the output of IVS regulators. When K vcd = 1,
Fig. 9.4 is the same as Fig. 3.19. When the input voltage of module j (j = 1, 2,…, n)
is lower than V in /n, the output of the IVS regulator vin_EAj increases and the current
reference of the inner current loop declines, and when the current reference of inner
current loop declines to be lower than zero, vEAj will be also lower than zero, which
is lower than the minimum setting value of PWM controller, then the drive signals
will be shut down and this module is disabled [2]. Then, the input current I inj
0 and the current of the dividing capacitor I cdj = I in , which charges the dividing
capacitor and the module input voltage rises. When the module input voltage rises
to be higher V in /n, vin_EAj declines, the current reference of inner current loop as
well as the corresponding vEAj increases to be higher than the minimum setting value
of PWM controller, then the drive signals will be turned on and the module works
again. It can be seen that the modules will work intermittently if the weighted value
K vcd is large enough to achieve IVS.
To avoid severely regulating the module output current in transient, the weighted
value K vcd cannot be too large. However, this cannot ensure the intermittent work
of the modules under extreme load conditions. In other words, we hope that K vcd
1 at heavy load and K vcd > 1 at light load. So, two weighted values are set in the
control strategy, i.e., 1 and K vcd_light , corresponding to the heavy load and light load
conditions, respectively as shown in Fig. 9.5. The two weighted values are selected by
a single-pole double-throw, which is controlled by a comparator. When the system
output current io is larger than the threshold current I th , the output of comparator
is low level and the weighted value of 1 is selected; and if io is smaller than I th ,
the output of comparator is high level and the weighted value K vcd_light is selected.
Generally, the module loss is very small at light load, and the difference among the
– vin1 ivcd1 – iLf1 vEA1 Comparator 1

+ – + _
Gvcd Kvcd Gc Drive
Vin/n vin_EA1 + RS Flip-flop
+ circuit 1
VRAMP 1
– vin2 ivcd2 – iLf2 vEA2 Comparator 2

+ – + _
Gvcd Kvcd Gc Drive
Vin/n RS Flip-flop
vin_EA2 + Inner current + circuit 2
IVS loops loops VRAMP 2
– vinn ivcdn – iLfn vEAn Comparator n

+ – + _
Gvcd Kvcd Gc Drive
Vin/n vin_EAn + RS Flip-flop
+ circuit n
VRAMP n
vof
–
+ Gvo
Voref vo_EA
Output voltage loop
Fig. 9.4 IVS control strategy for ISOP system
– io
Con Comp
+ Ith
– vin1 1 – iLf1 vEA1 Comparator1

+ – + _
Gvcd Gc Drive
Vin/n vin_EA1 Kvcd_light + RS Flip-flop
Vcl_mod + circuit 1
VRAMP 1
– vin2 1 – iLf2 vEA2 Comparator 2

+ – + _
Gvcd Gc Drive
Vin/n Kvcd_light RS Flip-flop
vin_EA2 + Inner current + circuit 2
Vcl_mod VRAMP 2
IVS loops loops
– vinn
1 – iLfn vEAn Comparator n
+ – + _
Gvcd Gc Drive
Vin/n vin_EAn Kvcd_light + RS Flip-flop
Vcl_mod + circuit n
VRAMP n
vof
–
+ Gvo
Voref vo_EA
Vcl_total
Output voltage loop
Fig. 9.5 Control strategy with changeable weighted values of IVS loops
module losses can be considered to be less than 5%I o , where I o is the system rated
output current. So, we set I th 5%I o .
The output current of ISOP system has to be limited to protect the system. So,
a Zener diode is introduced to the output of the output voltage regulator, and the
Zener voltage V cl_total corresponds to the limited system output current as shown in
Fig. 9.5. In the meanwhile, Zener diodes are introduced to the current references of
the inner current loops to limit the individual module output current, and the Zener
9.2 Input Voltage Sharing Control Strategy for ISOP … 197
voltage V cl_mod corresponds to the limited module output current. V cl_mod must be
higher than V cl_total for ensuring that the IVS loops could adjust the inner current
loops during the system current-limiting.
9.2.2 Input Voltage Sharing Auxiliary Circuit
Referring to the control strategy with changeable weighted values of IVS loops as
shown in Fig. 9.5, when the output of ISOP system is shorted, the adjustment of the
IVS loops to the current reference of inner current loops is limited by V cl_mod . This
means that the IVS loops fail to adjust the current reference of the inner current loop,
and cannot achieve IVS under short-circuit condition, and it is only effective at light
load. Therefore, we have to introduce IVS auxiliary circuits to the input sides of the
modules when short-circuit occurs to regulate the equivalent resistances of all the
modules to be equal for IVS.
Because the module losses are different and vary with the input voltage, the IVS
auxiliary circuits should have the following features: (1) the equivalent resistance
of the IVS auxiliary circuit is adjustable; (2) ease of modularization; (3) the IVS
auxiliary circuits are only enabled when IVS is not achieved under extreme load
conditions to avoid extra loss under normal load conditions.
The IVS auxiliary circuits with adjustable resistance and the corresponding control
circuits are shown in Fig. 9.6. Each IVS auxiliary circuit is composed of a resistor
Rreg and a switch Qaj (j = 1, 2, …, n). Qaj is PWM controlled and the equivalent
resistance of the IVS auxiliary circuit is Rreg /DQaj , where DQaj is the duty cycle of
Qaj . When DQaj 1, the power dissipated by Rreg must be larger than the maximum
difference among the module losses. When the ISOP system works at normal load,
the IVS loops can realize IVS among modules, and Qaj is shut off.
When the system total output power is lower than the difference among the module
losses, the input voltage of the module with larger Rloss will increase from the average
value. Until the module input voltage is higher than the allowed maximum input
voltage V mod_max , the IVS auxiliary circuit starts to work and regulate DQaj to adjust
the power dissipated by Rreg , limiting the module input voltage at V mod_max . The IVS
auxiliary circuit can ensure the ISOP system working normally under extreme load
conditions, and its structure is simple, but the loss under extreme load conditions is
increased.
To ensure the stable operation of ISOP system in the full load range, we can utilize
the IVS auxiliary circuit or combine the IVS auxiliary circuit with the control strategy
with changeable weighted values of the IVS loops. When the output current is lower
than I th , we can use the control strategy with changeable weighted values of the IVS
loops to realize IVS and the auxiliary circuit is disabled. When the ISOP system
output is shorted with current-limiting, the output current is higher than I th , the IVS
auxiliary circuit will be activated to limit the module input voltage at V mod_max to
ensure the system work stably.
RLd
+
Rreg
Module 1 Vo
Cd1 Qa1 Cf
–
Rreg
Module 2
Cd2 Qa2
Vin
Rreg
Module n
Cdn Qan
(a) IVS auxiliary circuit

VRAMPComparator
_
Vmod_max _ Qaj Driver
EA +
Vinj +
(b) Control circuit of IVS auxiliary circuit
Fig. 9.6 IVS auxiliary circuit and control circuit
9.3 Simulation and Experimental Verification
A DC–DC ISOP system consisting of two phase-shifted full-bridge (PSFB) converter

modules is taken as an example as shown in Fig. 9.7, to verify the effectiveness of the
proposed methods to realize IVS under extreme load conditions. The specifications
of the ISOP system are as follows: input voltage V in 540 Vdc, output voltage V o
48 Vdc, and rated system output current I o 104 A. The main parameters of the
PS-FB converters are as follows: switching frequency f s 100 kHz, filter inductance
L f1 L f2 10 µH, resonant inductance L r1 L r2 6 µH, and transformer turns ratio
K = 14:3. To simulate the module loss, resistors with two different resistances are
connected in series with the power switches, i.e., Rl1 0.5 and Rl2 2 , and it is
readily to know that Rloss1 < Rloss2 when the input voltages of two modules are equal
under extreme load conditions. The threshold current I th is set at 10%I o , i.e., I th
10.4 A. Rreg is chosen as 1 k, and its dissipated power is 73 W when Qaj (j = 1, 2) is
always ON and the module input voltage is 270 Vdc. V mod_max is set at 110%V in /2,
i.e., V mod_max 297 Vdc.
Figure 9.8 shows the simulation waveforms of the ISOP system employing the
IVS control strategy (see Fig. 9.4 and K vcd 1) under no-load condition. vin1 and
vin2 are the input voltages of modules 1 and 2, respectively, vAB1 and vAB2 are the
Module 1
Lf1
RLd
T1 +
+ iLf1
Q11 Q12 * DR11 vrect1 Vo
Rreg T1 Cf
+ Rl1 Lr1 Rl1 – –
Vin1 A1 * B1
Rl1 ip1 Rl1 *
– DR12
Qa1
Q13 Q14
Vin Lf2
T2
+ iLf2
Q21 Q22 * DR21 v
rect2
Rreg
+ Rl2 Lr2 T2 Rl2 –
Vin2 A2 * B2
Rl2 ip2 Rl2 *
– DR22
Qa2
Q23 Q24
Module 2
Fig. 9.7 Circuit diagram of ISOP system consisting of two PSFB modules
400
vin2
300
(V)
200 vin1
100
400
200
vAB1
(V)
0
−200
−400
400
200
vAB2
(V)
0
−200
−400
9.500m 9.504m 9.508m 9.512m 9.516m 9.520m 9.524m 9.528m
t (s)
Fig. 9.8 Simulation waveforms with the IVS control strategy (see Fig. 9.4 and K vcd 1)
voltages across the middle points of the phase-legs of the two modules. It can be
seen that vin2 is much higher than vin1 due to Rloss1 < Rloss2 and the voltage difference
reaches 220 Vdc, and IVS is not realized under no-load condition.
275
vin1
(V)
270
vin2
265
400
200 vAB1
(V)
0
−200
−400
400
200 vAB2
(V)
0
−200
−400
38.77m 38.78m 38.79m 38.80m 38.81m 38.82m 38.83m 38.84m 38.85m
t (s)
Fig. 9.9 Simulation waveforms with the IVS control strategy (see Fig. 9.5 and K vcd_light 2) under
no-load condition
Figure 9.9 shows the simulation waveforms of the ISOP system when employing
the control strategy with changeable weighted values of the IVS loops (see Fig. 9.5
and K vcd_light 2) under no-load condition. It can be seen that module 1 works
intermittently due to Rloss1 < Rloss2 and the average input voltages of two modules are
approximately the same.
Figure 9.10 shows the simulation waveforms of the ISOP system when employing
the control strategy (see Fig. 9.4) and IVS auxiliary circuit under no-load condition.
Figure 9.10a shows the waveforms under no-load condition at steady state, where
Qa2 is the drive signal of power switch in the IVS auxiliary circuit of module 2. The
IVS auxiliary circuit of module 2 works due to Rloss1 < Rloss2 and controls the input
voltage of module 2 at 110%V in /2, i.e., 297 Vdc. Figure 9.10b shows the waveforms
corresponding to load stepping between half load and no load. At half load, the system
output power is larger than the difference between the module losses, the IVS loops
can realize IVS and the auxiliary circuit is disabled. At no load, the input voltage
of module 2 rises and when it reaches 297 Vdc, the IVS auxiliary circuit of module
2 works and controls the input voltage of module 2 at 297 Vdc, and consequently,
the input voltage of module 1 is controlled at 243 Vdc, and the system can operate
steadily.
Figure 9.11a shows the simulation waveforms of the ISOP system with the con-
trol strategy (see Fig. 9.5) and without the IVS auxiliary circuit under short-circuit
current-limiting condition. The system output current is limited at 110 A. It can be
seen that vin2 is higher than vin1 due to Rloss1 < Rloss2 , the current reference of inner
current loop of module 2 increases and when its IVS loop regulator is saturated,
400
vin2
300
(V)
200 vin1
100
400
200
vAB1
(V)
0
−200
−400
400
200 vAB2
(V)
0
−200
−400
20
Qa2
(V)
10
0
21.662m 21.666m 21.670m 21.674m 21.678m 21.682m 21.686m 21.690m
t (s)
(a) Waveforms at steady state

60
40 io
(A)
20
0
−20
60
40 vo
(V)
20
0
350
vin2
300
(V)
250
vin1
200
20
Qa2
(V)
10
0
2.0m 4.0m 6.0m 8.0m 10.0m 12.0m 14.0m
t (s)
(b) Waveforms corresponding to stepped load
Fig. 9.10 Simulation waveforms with the control strategy (see Fig. 9.4) and IVS auxiliary circuit
under no-load condition
the output current of module 2 is 65 A, which is the sum of average limited output
current 55 and 10 A corresponding to the regulation of IVS loop. The output current
of module 1 is 45 A and the difference of the input voltages of two modules reaches
100 Vdc.
70
60 iLf2
(A)
50
40 iLf1
30
350
300 vin2
(V)
250 vin1
200
400
200 vAB1
(V)
0
-200
-400
400
200 vAB2
(V)
0
-200
-400
19.76m 19.78m 19.8m 19.82m 19.84m 19.86m 19.88m
t (s)
(a) Without IVS auxiliary circuit
70 iLf2
60
(A)
50
iLf1
40
30
350
vin2
300
(V)
250
vin1
200
400
200 vAB1
(V)
0
-200
-400
400
200 vAB2
(V)
0
-200
-400
20
Qa2
(V)
10
0
17.24m 17.26m 17.28m 17.30m 17.32m 17.34m 17.36m
t (s)
(b) With IVS auxiliary circuit
Fig. 9.11 Simulation waveforms of ISOP system with the control strategy (see Fig. 9.5) under
short-circuit current-limiting condition
Figure 9.11b shows the simulation waveforms of the ISOP system with both the
control strategy (see Fig. 9.5) and the IVS auxiliary circuit under short-circuit current-
limiting condition. It can be seen that the input voltage of module 2 is controlled at
297 Vdc and its output current is 60 A.
An ISOP system prototype is also built in our lab with the same specifications as
that in the simulation. For each module with rated input voltage 270 Vdc and under
no-load condition, the measured module losses are 48.7 and 33.4 W for modules
1 and 2, respectively, and the power difference is 15.3 W. Figure 9.12a shows the
experimental waveforms of the ISOP system with the IVS control strategy (see
Fig. 9.4 and K vcd 1) when the system output current is 1 A, i.e., the system output
power is 48 W. It can be seen that two modules share the system input voltage well
because the system output power is larger than the difference of two module losses.
Figure 9.12b shows the experimental waveforms of the ISOP system with the IVS
control strategy (see Fig. 9.4 and K vcd 1) under no-load condition. It can be seen
that the input voltage of module 2 is much higher than that of module 1 because the
no-load loss of module 2 is smaller than that of module 1 with the same input voltage,
and the difference of the module input voltages reaches 180 Vdc. Therefore, the ISOP
system must adopt special IVS control strategy under extreme load conditions.
Figure 9.13 shows the experimental waveforms of ISOP system when employing
the control strategy with changeable weighted values of the IVS loops under no-load
condition. Figure 9.13a shows the waveforms at steady state. The waveforms of vAB
are distorted because the frequency of vAB is 100 kHz but the time scale of the figure
is 500 ms/div. The waveforms of vin1 and vin2 indicate that the two modules work
intermittently because the two dividing capacitors charge and discharge alternately,
leading to the input voltages rise and fall alternately. The average values of the
module input voltages are approximately equal. Figure 9.13b shows the waveforms
corresponding to load stepping between quarter load and no load. The experimental
results shown in Fig. 9.13 verify that the control strategy with changeable weighted
values of the IVS loops can ensure the IVS in the full load range.
Figure 9.14 shows the experimental waveforms of the ISOP system with the
control strategy (see Fig. 9.4 and K vcd 1) and IVS auxiliary circuit under no-load
condition. Here, V mod_max is set at 110%V in /2, i.e., V mod_max 297 Vdc. Figure 9.14a,
b show the waveforms of vin1 , vin2 , vAB1 , vAB2 , and the drive signal of the auxiliary
circuit of module 2 at steady state. As seen, the input voltage of module 2 is controlled
at 297 Vdc with the help of IVS auxiliary circuit, and the input voltage of module 1
is controlled at 243 Vdc. Figure 9.14c shows the waveforms corresponding to load
stepping between quarter load (25 A) and no load. It can be seen that the IVS is
achieved by the control strategy, and the IVS auxiliary circuit is disabled when the
output power is larger than the difference between the module losses. Under no-
load condition, the IVS auxiliary circuit of module 2 starts to work when the input
voltage of module 2 rises to 297 Vdc and regulates the input voltage module 2 at 297
Vdc, and consequently, the input voltage of module 1 is controlled at 243 Vdc. The
experimental results shown in Fig. 9.14 verify that the IVS auxiliary circuit works
well under no-load condition.
C1: vin2 [100V/div]
C2: vin1 [100V/div]
C1/C2
C3: vAB1 [400V/div]
C3
C4: vAB2 [400V/div]

C4
Time: [2μs/div]
(a) Output current is 1 A
C1: vin2 [100V/div]
C2: vin1 [100V/div]
C1/C2
C3 C3: vAB1 [400V/div]
C4: vAB2 [400V/div]

C4
Time: [2μs/div]
(b) No-load
Fig. 9.12 Experimental waveforms with the IVS control strategy (see Fig. 9.4 and K vcd 1)
Figure 9.15 shows the experimental waveforms of the ISOP system with the
control strategy (see Fig. 9.4 and K vcd 1) and IVS auxiliary circuit under short-
circuit current-limiting condition. For the sake of safety, the system output current is
limited at 50 A and output current of each module is limited at 27.5 A (110%I o /2).
From Fig. 9.15a, it can be seen that the output current of module 2 is limited at 27.5
A because the no-load loss of module 2 is smaller than that of module 1 under the
same input voltage, and output current of module 1 is 22.5 A. Figure 9.15b shows
that the input voltage of module 2 is controlled at 297 Vdc with the help of IVS
C1: vin2 [100V/div]
C2: vin1 [100V/div]
C1/C2
C4: vAB2 [400V/div]
C4
Time: [500ms/div]
(a) Waveforms of steady state
C3 C3: io [20A/div]
C1: vin2 [100V/div]
C2: vin1 [100V/div]
C1/C2
Time: [500ms/div]
(b) Waveforms corresponding to stepped load
Fig. 9.13 Experimental waveforms of ISOP system when employing the control strategy with
changeable weighted values of the IVS loops under no-load condition
auxiliary circuit, and the input voltage of module 1 is 243 Vdc. Figure 9.15c shows
the waveforms corresponding to load stepping between 25 A and limited current
(50 A). It can be seen that the IVS is achieved by the control strategy and the IVS
auxiliary circuit is disabled under normal load condition. The experimental results
shown in Fig. 9.15 verify that the IVS auxiliary circuit works well under short-circuit
current-limiting condition.
C1: vin2 [100V/div]
C2: vin1 [100V/div]
C1/C2
C3
C3: vAB1 [400V/div]
C4: vAB2 [400V/div]

C4
Time: [2μs/div]
(a) Waveforms of vin1, vin2, vAB1, and vAB2 of steady state
C1: vin2 [100V/div]
C2: vin1 [100V/div]
C1/C2
C3
C3: Qa2 [10V/div]
Time: [2μs/div]
(b) Waveforms of vin1, vin2 and drive signal of auxiliary circuit of module 2
C4: io [20A/div]
C4
C1: vin2 [100V/div]
C2: vin1 [100V/div]

C3
C3: Qa2 [20V/div]
C1/C2
Time: [500ms/div]
(c) Waveforms corresponding to load stepping
Fig. 9.14 Experimental waveforms of ISOP system with the control strategy (see Fig. 9.4) and IVS
auxiliary circuit under no-load condition
M1: iLf1 [10A/div] C2: iLf2 [10A/div]
M1/C2
C4: vAB2 [400V/div]

C4
Time: [2μs/div]
(a) Waveforms of vAB1, vAB2, iLf1, and iLf2 of steady state
C2: vin2 [100V/div]
C1: vin1 [100V/div]
C1/C2
C3
C3: Qa2 [10V/div]
Time: [2μs/div]
(b) Waveforms of vin1, vin2 and drive signal of auxiliary circuit of module 2
C4 C4: vo [40V/div]
C2: vin2 [100V/div]
C1: vin1 [100V/div]
C3
C3: Qa2 [20V/div]
C1/C2
Time: [500 ms/div]

(c) Waveforms corresponding to load stepping
Fig. 9.15 Experimental waveforms of ISOP system with the control strategy (see Fig. 9.4) and IVS
auxiliary circuit under short-circuit current-limiting condition
9.4 Summary
This chapter reveals the failure mechanism of IVS of the ISOP systems employing
the control strategies proposed from Chaps. 2 to 7 under extreme load conditions,
and points out that when the output power of the ISOP systems is smaller than the
difference among the module losses, these control strategies cannot regulate enough
module output power to compensate for the loss difference, leading to the IVS failure.
Moreover, output currents imbalance will occur under short-circuit current-limiting
condition. To solve these problems, two methods of achieving IVS under extreme
load conditions was proposed, namely the control strategy with changeable weighted
values of the IVS loops and the IVS auxiliary circuit. It is recommended that the
control strategy with changeable weighted values of the IVS loops should be used
under light-load or no-load condition, and the IVS auxiliary circuit should be used
under short-circuit current-limiting condition. The effectiveness of the two methods
is verified by simulation and experimental results.
References
1. Yan, H., Ruan, X., Chen, W.: The input voltage sharing control strategy for input-series and
output-parallel converter under extreme conditions. In: Proceedings of IEEE Energy Conversion
Congress and Exposition, pp. 662–667 (2009)
2. UCC3895 BiCMOS advanced phase-shift PWM controller datasheet, http://www.ti.com/lit/ds/
symlink/ucc3895.pdf
Index
A Constituent inverter modules, 17, 19, 124

Active current, 125, 126 Controlled sources, 60
Active power, 4, 21, 23, 124, 126, 131, 133, Converter circuit, 2
150, 156, 157 Corner frequency, 71
Aeronautical static inverter, 16, 175 Cross-feedback control, 12, 22, 23
Alternating current (AC), 1, 107 Cross-feedback for output inductor current, 22
Auxiliary circuit, 197, 200, 203, 208 Crossover frequency, 71–73
Average current control, 12, 18, 24, 175, 180 Crystal oscillator, 17
Current
B closed-loop controlled, 8
Bipolar junction transistor, 2 cross-feedback control strategy, 12, 14
Bipolar modulation, 177 deviation, 17
BJT, see Bipolar junction transistor follower, 158, 178, 183
Body diode, 56 hysteresis, 158, 162, 176, 177, 187
Boost-derived converter, 116 imbalance, 193, 208
Buck/boost-derived converter, 37 reference, 8, 12, 15, 18–21, 23, 76, 79, 117,
Buck-derived converter, 37, 40, 41 124, 150, 154, 161, 171, 172, 176, 181,
Bus voltage, 130–132, 164, 177 183, 195, 196, 200
ripple, 57, 60, 130, 177
C sharing, 7, 8, 17–19, 51, 116, 118, 119,
Central control unit, 175 175, 181, 188
Centralized control, 16, 17, 24, 122, 148–151, sharing reference, 41
169, 171, 172, 175 sharing regulating speed, 18
Changeable weighted values, 195–197, 200, Current-limiting, 19, 24, 176, 178, 180, 183,
203, 208 185, 188, 193, 197, 200, 202–204, 207,
Circulating current, 19, 60, 126 208
Common current reference, 118, 171, 181, 183, Current sharing bus, 8
188
Common output voltage control loop, 10, 11, D
67 DC, see Direct current
Compensator, 71–73, 136, 137, 163, 164 DC–AC inverter, 7, 15, 16, 24, 25, 107, 108,
Compound balanced control strategy, 21, 22, 110, 114, 122, 153, 154
113–115, 118, 119, 121, 124, 125, 127, Decoupling relationship, 122, 151
141, 154, 156, 164–166, 168, 172 Deficit current, 36
Constant power source, 35, 114 Democratic current sharing, 7–9
Series, https://doi.org/10.1007/978-981-13-2760-5
210 Index
Device, 3–5, 123, 132, 193 G

Digital signal processor, 149 Gallium nitride, 3
Direct current, 110, 111 Galvanic isolation, 122
Discharging current, 101 GaN, see Gallium nitride
Distributed control, 16, 18, 24, 148–151, 154, Gate turn-off thyristor, 2
169, 171, 172, 175, 180, 183, 188 Genetic control, 3
Drive Gradient gain, 87, 91, 92, 94, 97
circuit, 3–5 GTO, see Gate turn-off thyristor
signal, 15, 127, 195, 200, 203
DSP, see Digital signal processor H
Duty cycle, 9–13, 40–42, 45–47, 49, 56, 58, Half-bridge, 40, 123
59, 67, 74, 82, 85–87, 95, 191, 197 Half-controlled device, 2
Dynamic response, 21, 47, 49, 51, 55, 74, 75, Half load, 47, 49, 51, 99, 100, 103
82, 84 Heavy load, 195
High voltage integrated circuit, 3
E HIVC, see High voltage integrated circuit
Electric vehicle, 2 Hot-swap, 102, 175, 183, 187, 188
Electromagnetic compatibility, 3 Hysteresis width, 176
Equilibrium
point, 19, 37, 114 I
voltage, 36 ICS, see Input current sharing
Equivalent negative resistance, 37 IGBT, see Insulated gate bipolar transistor
Equivalent resistance, 79, 194, 197 Inductive load, 141, 143, 144, 164, 165, 168
Excessive current, 36 Inductor-current cross-feedback control, 22, 23
Extreme load condition, 191–195, 197, 198, Inductor current feedback hysteretic control, 21
203, 208 Inner current control loop, 11, 12
Inner output filter capacitor current loop, 22
F Input
Fault tolerance, 8 current perturbation, 78, 80
Feedback signal, 11, 23, 79, 92, 117, 118, 124, current sharing, 9, 29, 107, 110, 119, 175
150, 154, 156, 157, 170 impedance, 3, 37–39, 77–79, 84, 89, 136
Filter capacitor, 15, 20, 22, 23, 30, 35, 36, 46, power, 31–33, 35, 79, 81, 87, 96, 108, 114,
56, 70, 94, 108, 114, 118, 125, 126, 130, 119, 124, 128, 135, 156, 161, 192, 193
131, 138, 139, 146, 151, 154, 155, 157, side, 5, 30, 34–37, 46, 48, 50, 61, 78, 114,
164, 166, 167, 170, 172, 177, 186 115, 122, 133, 153, 164, 197
Filter inductor, 12, 15, 18, 20, 46, 56–59, 70, terminal, 38, 136, 171
76, 79, 80, 94, 100, 118, 124–126, 131, voltage, 6, 11, 12, 15, 21–23, 29, 30,
132, 138, 139, 141, 142, 145, 150, 151, 32–34, 36, 38–42, 46–51, 56, 58, 60,
154, 156, 157, 161, 164, 166, 167, 170, 61, 67–69, 74, 79, 81, 82, 85–87, 89,
172, 176, 177, 183 91, 95, 97–99, 101, 102, 105, 108, 110,
Freewheeling, 56, 176, 177 111, 113, 117–119, 121, 123, 124, 128,
Full-bridge, 15, 40, 46, 55, 56, 123, 127, 131, 136–139, 141, 143, 150, 153, 154,
130–132, 154, 161, 164, 176, 177, 198 158, 161, 164, 166, 169, 183, 192–195,
Full-controlled device, 2 197, 198, 200, 203, 204
Full load, 47, 49, 51, 74, 97, 99–103, 164, 166, voltage perturbations, 38, 80, 97, 133
197, 203 voltage sharing, 9, 11, 21–23, 29, 107, 121,
Full resistive load, 131, 141, 143, 147, 164, 153
166, 185, 186 voltage sharing error, 91, 93
Fundamental angular frequency, 126 voltage sharing regulator, 21
Fuzzy control, 3 Input-dividing capacitor voltage, 124
Index 211
Input-parallel-connected systems, 30, 35, 36, Neural network, 3

39, 41, 42, 51, 113, 115, 119 Neural network control, 3
Input-parallel-output-parallel, 6, 107, 175
Input-parallel-output-series, 6, 9, 11, 30, 32, O
39, 46, 48, 85, 107, 111, 113, 117, 119 OCS, see Output current sharing
Input-series-connected systems, 35, 36, 38–42, Output
51, 85, 86, 90, 97, 105, 113, 115, 119, characteristics, 19, 24, 175, 178, 180, 183,
121 184, 188
Input-series-output-parallel, 6, 107 current feedback control, 126, 127, 129,
Input-series-output-series, 6, 13, 22, 24, 30, 33, 138, 141, 145
34, 36–39, 42, 43, 46, 50, 52, 85, 92, 94, current sharing, 11, 16, 17, 19–21, 24, 29,
102, 107, 112, 113, 115, 116, 118, 119, 46, 97, 107, 110, 121, 175, 181
153, 154, 156, 159, 161, 164–166, 172 voltage, 6, 7, 9–13, 15, 17–24, 29, 30,
Insulated gate bipolar transistor (IGBT), 3 32–35, 40–42, 44–47, 49, 51, 55, 65,
Intelligent power module (IPM), 5 69–71, 74, 82, 84–87, 89–92, 94,
Interconnected control, 16 97–99, 102, 103, 105, 108–111, 113,
Interleaved switching, 13 114, 116–119, 122–124, 126–128,
Intrinsic capacitors, 56 131–133, 136–139, 141, 143, 149, 151,
IPM, see Intelligent power module 153–155, 158, 161, 162, 164, 167, 169,
IPOP, see Input-parallel-output-parallel 171, 172, 176–181, 183, 187, 196, 198
IPOS, see Input-parallel-output-series voltage control loop regulator, 86
ISOP, see Input-series-output-parallel voltage/current sharing control, 119
ISOS, see Input-series-output-series voltage regulator, 8–11, 18, 20–23, 42, 67,
IVS, see Input voltage sharing 127, 128, 132, 150, 158, 162, 170
IVSR, see Input voltages sharing regulator voltage sharing, 20, 22–24, 29, 153
Output-voltage cross-feedback control, 23, 25
L OVR, see Output voltage regulator
Light load, 191, 193–195, 197 OVS, see Output voltage sharing
Linearization, 40
Line-frequency transformer, 122 P
Load Parallel control unit, 17
current, 7, 8, 19, 34, 74, 113, 135, 141, 157, Parasitic resistance, 97
164, 167, 176, 178–180, 183, 185–187 Peak-to-peak voltage, 70
current feed-forward control, 178, 180 Perturbation, 34–36, 38–42, 58, 78, 80, 81, 87,
regulation, 7 95–97, 113, 114, 124, 133, 135
sharing, 100 PFC, see Power factor correction
PFM, see Pulse-frequency modulation
M Phase lag, 163
Magnetic core, 5, 123 Phase-leg mid-points, 124
Master–slave current sharing, 7, 8 Phase-locked loop, 17
Mercury arc rectifier, 1 Phase-shift control, 123
Microelectronic, 2, 4 Phase-shifted full-bridge converter, 123
Minority-carrier device, 3 Phase synchronization, 156, 158, 172
Modularization architecture, 30, 43, 45, 51, 85, Phasotron
86 Photovoltaic system, 6, 9
Module efficiencies, 32–34, 81 PI, see Proportional-integral
Mutual cross-feedback, 13 PLL, see Phase-locked loop
Plugged into, 186
N Plugged out, 186
Natural rebalancing ability, 13 Positive feedback loop, 37
Negative resistance, 38, 39, 77, 81, 84, 133, Positive gradient regulation characteristic, 87
136 Positive resistance, 77, 79, 80, 84, 89, 136, 164
Negative resistance characteristics, 84 Positive zero-crossing point, 181
212 Index
Power balance, 25, 107, 116, 150, 157 signal, 10, 11, 67, 70, 86, 96
Power electronics building block, 4 SCR, see Silicon controlled rectifier
Power electronics system Secondary rectified voltage, 58
integration, 3, 4, 25 Secondary side, 56
modularization, 3, 25 Second stage, 123, 130
standardization, 3, 25 Semiconductor devices, 1–4
Power factor Series–parallel combined systems, 15
angles, 22, 109, 155, 172, 179 Series–parallel power conversion system, 5–7,
correction, 154 29, 30, 42, 45, 51, 55, 67, 85, 86,
Power integrated device, 3 107–109, 113–119
Power switch, 11, 15, 56, 94, 121, 123, 176, Short-circuit, 193, 197, 202–205, 208
186, 198, 200 Short fault, 101
Primary-and-secondary-windings ratio, 56 Short switch, 101, 102
Primary current, 56–59, 132 SiC, see Silicon carbide
Primary duty cycle, 56, 58, 60 Silicon carbide, 3
Proportional coefficient, 86 Silicon controlled rectifier, 1
Proportional–integral, 71 Single-phase full-bridge inverter, 15, 16
Protection circuit, 3–5 Sinusoidal pulse-width modulator, 18
PSFB, see Phase-shifted full-bridge converter Smart power integrated circuit, 3
Pulse-frequency modulation, 3 Small-signal model, 15, 37–39, 55, 58, 60, 61,
Pulse-width modulation, 3 72, 74, 78, 80, 83, 94, 133
Push-pull, 123 Soft-switching, 123
PWM comparator, 42 SPIC, see Smart power integrated circuit
PWM, see Pulse width modulation SPWM, see Sinusoidal pulse-width modulator
Static error, 178
R Stepped input voltage, 46, 49, 51, 82, 102
Rated output current, 46, 48, 49, 51, 97, 196 Stepped load, 46, 49, 51, 82, 99, 102, 185
Reactive current, 125, 126, 146 Switching frequency, 57, 58, 70, 98, 130, 131,
Reactive power, 19, 107, 108, 110–115, 118, 162, 178, 198
126, 139, 153, 157, 165, 167 Switching loss, 14, 123
Real power, 108, 110–115, 118, 171 Synchronization of the output current phase,
Rebalancing ability, 14 124
Rectifier diodes, 46, 56, 94 Synchronization pulse signal, 17
Redundancy, 7, 19, 100, 102, 105, 149, 175 Synchronizing bus, 181
Regulator, 9–12, 15, 18, 20, 41, 71, 72, 76, 84,
86, 124, 150, 158, 171, 178, 181, 183, T
195, 196, 200 Three control loops, 21, 22, 124, 154, 168
Resonant inductance, 46, 198 Three-dimensional package technology, 5
Right-half-plane pole, 39 Three-loop control strategy, 20, 80, 82, 116
Ripple current, 130 Three-state hysteresis modulation, 158, 176,
Rising edge, 181 177, 183
RMS, see Root-mean-square Three voltage level, 123
Root-mean-square, 109 Threshold current, 195, 198
Thyratron, 1
S Total harmonic distortion, 21
Sampled output voltage Total load current, 17
Sampling Turning frequency, 162
clock, 176, 177 Turns ratio, 9, 40, 61, 70, 95, 131
factor, 45 Two-stage inverter, 123, 131
frequency, 162 Two-transistor forward converter, 94, 97
signal, 15
Saturation voltage, 3 U
Sawtooth Unbalanced current, 37
carrier, 127, 131 Uncompensated loop gain, 70–72, 162, 163
Index 213
Uninterruptible power supply, 16 W

Unipolar modulation, 177 Wire connection, 7
UPS, see Uninterruptible power supply Wireless droop control, 16, 19, 20, 175, 181
Wireless IVS control strategy, 15, 86, 89,
V 92–94, 97, 100
Voltage
amplitude, 17, 23, 114 Z
disturbance, 12, 136, 147 Zero-crossing phase-lock, 181
diverge, 136 Zero state, 176
Voltage-controlled device, 2
Voltage–current double closed-loop, 8, 15, 75,
76, 80, 84

Control of Series Parallel Conversion Systems Compress

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Control of Series Parallel Conversion Systems Compress

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CPSS Power Electronics Series

Xinbo Ruan · Wu Chen

Readership: Research scientists in universities, research institutions and the

More information about this series at http://www.springer.com/series/15422

Kai Zhuang Tao Zhang

ISSN 2520-8853 ISSN 2520-8861 (electronic)

Jointly published with Science Press, Beijing, China

Library of Congress Control Number: 2018957246

Chapters 6 and 7 present the implementation of the compound balanced control

Nanjing, China Xinbo Ruan

This research monograph systematically summarizes the research work on the

2.2 Stability of the Control Strategies . . . . . . . . . . . . . . . . . . . . . . .. 34

5 A General Control Strategy for DC–AC Series–Parallel Power

7.3.1 Design of the Output Voltage Loop . . . . . . . . . . . . . . . . . 161

From 2009 to 2010, he was a Senior Research Assistant in the Department of

RMS Root Mean Square

Abstract Power electronics system integration is one of the effective approaches

Keywords Power electronics system integration

1.1 Development Trend of Power Electronics

Fig. 1.1 Power Computer-aided

Control theory Electrical machines

(3) Hybrid devices: Insulated gate bipolar transistor (IGBT) is a minority-carrier

1.2 Power Electronics System Integration

1.2.1 Component-Level Integration

1.2.2 Module-Level Integration

Module-level integration refers to the integration of various active devices, passive

1.2.3 System-Level Integration

System-level integration technology refers to integrate various standardized con-

(a) IPOP (b) IPOS

(c) ISOP (d) ISOS

Fig. 1.2 Four connection architectures of multiple converter modules

The advantages of the systems constructed from connecting multiple converter

1.3 DC–DC Series–Parallel Power Conversion Systems

1.3.1 IPOP System

Paralleling of multiple standardized converters has been extensively studied and

Converter 1 Converter 2 0 Io1 Io2 I

Fig. 1.3 Two-converter IPOP system

_ Vof Comparator 1 Module 1

Fig. 1.4 A typical block diagram of master–slave current sharing method

_ io1 Voref Comparator 1 Module 1

_ io2 Voref Comparator 2 Module 2

Fig. 1.5 A typical block diagram of democratic current sharing method

1.3.2 IPOS System

Output voltage sharing loops

Output voltage loop

Fig. 1.6 OVS control strategy for IPOS system

1.3.3 ISOP System

Input voltage sharing loops

Fig. 1.7 Democratic IVS control strategy for ISOP system

Input voltage sharing loops

Fig. 1.8 IVS control strategy for ISOP system

1.3.4 ISOS System

Fig. 1.9 A simple IVS control strategy for ISOP system

1.4 DC–AC Inverter Series–Parallel Power Conversion

1.4.1 DC–AC Inverter

(a) Single-phase full-bridge inverter

(b) Voltage-current double closed-loop control

(c) Voltage single closed-loop control

1.4.2 IPOP DC–AC Inverter System

1.4.2.1 Centralized Control

1.4.2.2 Master–Slave Control

1.4.2.3 Distributed Control

1. Average Current Control Method

vinvn _ iLfn ion