Power Sequencing Diagram

fab#sc1105
PPBUS_G3H
Suona

CHGR_EN_MVR
Suona → U6960 EN

PP3V3_G3H_RTC
U6960

PP3V3_G3H
Calpe VOUT_RTC

PP1V8_SLPS2R
Calpe Buck3

PMU_CLK32K_SOC_R
Calpe CLKOUT0_32K → H9M

PP1V8_AWAKE
Calpe Buck3 SW1 → H9M

PP1V8_SLPS2R_PMUVDDGPIO
Calpe Buck3 SW2 → Calpe

PP1V1_SLPS2R
Calpe Buck4 → H9M

PP0V8_SLPS2R
Calpe LDO0 → H9M

PP0V82_SLPS2R
Calpe Buck2 → H9M

PP3V3_AWAKE
Calpe V3P3 SW1 → H9M

PPVDDCPUSRAM_AWAKE
Calpe Buck1 → H9M

PP0V9_SLPDDR
Calpe Buck5 → H9M

P1V1_SLPDDR_SOCFET_EN
Calpe GPIO25 → U7901 EN

PP1V1_SLPDDR
U7901 → H9M

SOC_XTAL24M_IN
Enabled internally by H9M

PP1V2_AWAKE
Calpe LDO2 → H9M

PPVDDCPU_AWAKE
Calpe Buck0 → H9M

PMU_COLD_RESET_L
Calpe NRESET → H9M

PMU_SYS_ALIVE
Calpe SYS_ALIVE → H9M

PMU_ACTIVE_READY
Calpe ACTIVE_READY → H9M

<H9M loads secure ROM; SMC battery trap>

PMU_VDDMAIN_EN
Calpe VPWR_EN → U7650

PP3V3_G3H
U7650

<Calpe VOUT_RTC internal switch opens>

P3V3MAIN_PGOOD
PU to PP3V3_G3H | U7650 → Calpe GPIO1

<Calpe INIT CONFIG>

PP3V_G3H
Calpe LDO1 → PCH

PMU_CLK32K_PCH_R
Calpe CLKOUT1_32K → PCH

PCH_RTC_RESET_L
Calpe LDO1_POK → PCH

P5VG3S_EN
Calpe GPIO4 → U7650

PP5V_G3S
U7650 VR1

P3V3G3S_EN
Calpe GPIO6 → U8210

PP3V3_G3S
U8210

P1V8G3S_EN
Calpe GPIO7 → U822

PP1V8_G3S
U8220

P5VG3S_PGOOD
PU to PP1V8_G3S | U7650 → Calpe GPIO5

PMU_CLK32K_WLANBT_R
Calpe CLKOUT2_32K → WLAN/BT

<SMC checks SSD power source (Calpe or Ocarina)>

SSD_PMU_RESET_L
Ocarina | H9M GPIO19 → Ocarina PMIC_RESET*

PP1V8_SSD
Ocarina | Ocarina Buck1 → SSD

PP0V9_SSD
Ocarina | Ocarina Buck0 → SSD

SSD0_VR_P2V7_EN
Ocarina | Ocarina VEN1 → SSD

SSD0_OCARINA_WP_L
Ocarina | Ocarina WP_L → SSD

SSD0_OCARINA_PFN
Ocarina | Ocarina PFN_L → SSD

SSD0_OCARINA_LPB_L
Ocarina | Ocarina LPBN → SSD

PP1V8_SSD
Calpe | Calpe Buck10 → SSD

PP0V9_SSD
Calpe | Calpe Buck9 → SSD

NAND_DISCHARGE_EN
Calpe | Calpe GPIO21 → SSD

P2V7NAND_EN
Calpe | Calpe GPIO20 → SSD

P2V7NAND_PGOOD
Calpe | VR → Calpe GPIO19

NAND_WP_L
Calpe | Calpe GPIO23 → SSD

SSD0_OCARINA_RESET_L
Ocarina | Ocarina RESET_L → SSD

NAND_RESET_L
Calpe | Calpe GPIO22 → SSD

<SSD enabled. H9M booted to gOS.>

<Power button press>

PMU_ONOFF_L
PU to PP3V3_G3H_RTC |
Power Button → Calpe BUTTON1
PP3V3_S5
Calpe V3P3_SW2 → PCH
VCCDSW, VCCPRIM_3P3
CPU_C10_GATE_L
PU to PP3V3_S5 |
PCH → Calpe HIO_SW_EN, more
PCH_HSIO_PWR_EN
PU to PP3V3_S5 |
PCH → U8230 PP1V05_PRIMSW enable

PM_SLP_S0_L
PCH → U1930 Level Shifter

PP1V8_S5
Calpe Buck3 SW3 → PCH VCCPRIM_1P8
PM_SLP_S0_1V8_L
U1930 powered by PP1V8_S5 |
U1930 Level Shifter → H9M SLP_S0B,
Calpe SYS_SLEEP*
PPVCC_PRIM_CORE
Calpe Buck7 → PCH VCCPRIM_CORE

PP1V05_PRIM
Calpe Buck8 → PCH VCCPRIM_1P05

PP1V05_PRIMSW
U8230 FET → PCH VCCPRIM_GATED_1P05

SMC_RSMRST_L
H9M RSMRST* → PCH RSMRST* (level shifted)

<SMC waits for eSPI reset to deassert.>

<PCH will begin deasserting SLP_Sx signals over eSPI.>

EPSI_RESET_L
PCH → H9M
PCH_PWRBTN_L
PU to PP3V3_S5 |
CALPE SYS_BTN → PCH PWRBTN_L

PM_SLP_S5_L
PCH → H9M (eSPI and pin)

PM_SLP_S4_L
PCH → H9M (eSPI and pin)

PP1V8_S3
Calpe Buck3 SW4 → Memory VDD1

PVDDQ_EN
Calpe GPIO11 → U8100 enable

PP1V1_S3
U8100 → CPU VDDQ, Memory VDD2

P1V1_S3_PGOOD
PU to PVDDQ_EN |
U8100 PGOOD → U8150 enable
PP0V6_S3
U8150 → Memory VDDQ

PVDDQ_PGOOD
U8150 PGOOD → Calpe GPIO12

PM_SLP_S3_L
PCH → H9M (eSPI and pin)

PP1V05_S0
Calpe Buck8 SW2 → CPU VCCST, VCCPLL
CPU_VCCST_PWRGD
Level shifted from ALL_SYS_PWRGD, PU to
PP1V05_S0 | U1920 → CPU VCCST_PWRGD

PVCCPLLOC_EN
Calpe GPIO18 → U8245

P1V1_S0SW_FET_EN
PVCCPLLOC_EN AND CPU_C10_GATE_L → U8240

PP1V1_S0SW
U8240 → CPU VCCPLL_OC

PP1V_S5SW
Calpe HIO_SW → CPU VCCSTG

PP1V8_S0_CPU_OPVR
Calpe Buck3_SW5 → PCH VCC1P8_OPVR

CPU_OPVR_SLP_S3_L
PU to PP1V8_S0_CPU_OPVR

CPU_OPVR_C10_GATE_L
Level shifted from CPU_C10_GATE_L |
U1940 → PCH SLP_S0_N_1P8V

ALL_SYS_PWRGD
CALPE SYS_ACTIVE → PCH OPVR_EN_1P8

CPU_VR_EN
PCH OPVR_VCCIN_VR_EN_1P8 → IMVP9 VR_ENABLE

CPU_VR_READY
IMVP9 VR_READY → PCH OPVR_VCCIN_VR_RDY_1P8

PPVCC_S0_CPU
IMVP9 → CPU VCCIN

CPUVR_PGOOD
PCH OPVR_PWRGOOD_OUT_1P8V → Calpe GPIO8

SMC_SYSRST_L
H9M SYS_RESET → PCH SYS_RESET
through level shifter
SMC_PCH_PWROK
H9M PCH_PWROK → PCH PCH_PWROK
through level shifter
SMC_PCH_SYS_PWROK
H9M SYS_PWROK → PCH SYS_PWROK
through level shifter

PLT_RST_L
PCH PLTRST_L → System