Professional Documents
Culture Documents
BC556/557/558/559/560
1 TO-92
1. Collector 2. Base 3. Emitter
hFE Classification
Classification A B C
hFE 110 ~ 220 200 ~ 450 420 ~ 800
-50 1000
-40 IB = -350µA
IB = -300µA
-25 IB = -200µA
-20 IB = -150µA
10
-15 IB = -100µA
-10
IB = -50µA
-5
1
-0 -0.1 -1 -10 -100
-2 -4 -6 -8 -10 -12 -14 -16 -18 -20
-10 -100
-1 V BE(sat) -10
-0.1 -1
VCE(sat)
-0.01 -0.1
-0.1 -1 -10 -100 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2
1000
VCE = -5V
f=1MHz
10 IE = 0
Cob(pF), CAPACITANCE
100
1 10
-1 -10 -100 -1 -10
TO-92
+0.25
4.58 –0.15
4.58 ±0.20
0.46 ±0.10
14.47 ±0.40
+0.10
1.27TYP 1.27TYP 0.38 –0.05
[1.27 ±0.20] [1.27 ±0.20]
3.60 ±0.20
3.86MAX
(0.25)
+0.10
0.38 –0.05
1.02 ±0.10
(R2.29)
Dimensions in Millimeters
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support
when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
Advance Information Formative or In This datasheet contains the design specifications for
Design product development. Specifications may change in
any manner without notice.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
DAC0808
8-Bit D/A Converter
General Description Features
The DAC0808 is an 8-bit monolithic digital-to-analog con- n Relative accuracy: ± 0.19% error maximum
verter (DAC) featuring a full scale output current settling time n Full scale current match: ± 1 LSB typ
of 150 ns while dissipating only 33 mW with ± 5V supplies. n Fast settling time: 150 ns typ
No reference current (IREF) trimming is required for most ap- n Noninverting digital inputs are TTL and CMOS
plications since the full scale output current is typically ± 1 compatible
LSB of 255 IREF/256. Relative accuracies of better than n High speed multiplying input slew rate: 8 mA/µs
± 0.19% assure 8-bit monotonicity and linearity while zero
n Power supply voltage range: ± 4.5V to ± 18V
level output current of less than 4 µA provides 8-bit zero ac-
curacy for IREF≥2 mA. The power supply currents of the n Low power consumption: 33 mW @ ± 5V
DAC0808 is independent of bit codes, and exhibits essen-
tially constant device characteristics over the entire supply
voltage range.
The DAC0808 will interface directly with popular TTL, DTL or
CMOS logic levels, and is a direct replacement for the
MC1508/MC1408. For higher speed applications, see
DAC0800 data sheet.
DS005687-1
Dual-In-Line Package
DS005687-2
Top View
Order Number DAC0808
See NS Package M16A or N16A
Small-Outline Package
DS005687-13
Ordering Information
ACCURACY OPERATING
TEMPERATURE RANGE N PACKAGE (N16A) SO PACKAGE
(Note 1) (M16A)
8-bit 0˚C≤TA≤+75˚C DAC0808LCN MC1408P8 DAC0808LCM
Note 1: Devices may be ordered by using either order number.
www.national.com 2
Absolute Maximum Ratings (Note 2) Storage Temperature Range −65˚C to +150˚C
If Military/Aerospace specified devices are required, Lead Temp. (Soldering, 10 seconds)
please contact the National Semiconductor Sales Office/ Dual-In-Line Package (Plastic) 260˚C
Distributors for availability and specifications. Dual-In-Line Package (Ceramic) 300˚C
Power Supply Voltage Surface Mount Package
VCC +18 VDC Vapor Phase (60 seconds) 215˚C
VEE −18 VDC Infrared (15 seconds) 220˚C
Digital Input Voltage, V5–V12 −10 VDC to +18 VDC
Applied Output Voltage, VO −11 VDC to +18 VDC Operating Ratings
Reference Current, I14 5 mA Temperature Range TMIN ≤ TA ≤ TMAX
Reference Amplifier Inputs, V14, V15 VCC, VEE DAC0808 0 ≤TA ≤ +75˚C
Power Dissipation (Note 4) 1000 mW
ESD Susceptibility (Note 5) TBD
Electrical Characteristics
(VCC = 5V, VEE = −15 VDC, VREF/R14 = 2 mA, and all digital inputs at high logic level unless otherwise noted.)
Symbol Parameter Conditions Min Typ Max Units
Er Relative Accuracy (Error Relative (Figure 4) %
to Full Scale IO)
DAC0808LC (LM1408-8) ± 0.19 %
Settling Time to Within 1⁄2 LSB TA = 25˚C (Note 7), 150 ns
(Includes tPLH) (Figure 5)
tPLH, tPHL Propagation Delay Time TA = 25˚C, (Figure 5) 30 100 ns
TCIO Output Full Scale Current Drift ± 20 ppm/˚C
MSB Digital Input Logic Levels (Figure 3)
VIH High Level, Logic “1” 2 VDC
VIL Low Level, Logic “0” 0.8 VDC
MSB Digital Input Current (Figure 3)
High Level VIH = 5V 0 0.040 mA
Low Level VIL = 0.8V −0.003 −0.8 mA
I15 Reference Input Bias Current (Figure 3) −1 −3 µA
Output Current Range (Figure 3)
VEE = −5V 0 2.0 2.1 mA
VEE = −15V, TA = 25˚C 0 2.0 4.2 mA
IO Output Current VREF = 2.000V,
R14 = 1000Ω,
(Figure 3) 1.9 1.99 2.1 mA
Output Current, All Bits Low (Figure 3) 0 4 µA
Output Voltage Compliance (Note 3) Er ≤ 0.19%, TA = 25˚C
VEE = −5V, IREF = 1 mA −0.55, +0.4 VDC
VEE Below −10V −5.0, +0.4 VDC
SRIREF Reference Current Slew Rate (Figure 6) 4 8 mA/µs
Output Current Power Supply −5V ≤ VEE ≤ −16.5V 0.05 2.7 µA/V
Sensitivity
Power Supply Current (All Bits (Figure 3)
Low)
ICC 2.3 22 mA
IEE −4.3 −13 mA
Power Supply Voltage Range TA = 25˚C, (Figure 3)
VCC 4.5 5.0 5.5 VDC
VEE −4.5 −15 −16.5 VDC
Power Dissipation
3 www.national.com
Electrical Characteristics (Continued)
(VCC = 5V, VEE = −15 VDC, VREF/R14 = 2 mA, and all digital inputs at high logic level unless otherwise noted.)
Symbol Parameter Conditions Min Typ Max Units
All Bits Low VCC = 5V, VEE = −5V 33 170 mW
VCC = 5V, VEE = −15V 106 305 mW
All Bits High VCC = 15V, VEE = −5V 90 mW
VCC = 15V, VEE = −15V 160 mW
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 3: Range control is not required.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute Maixmum Ratings, whichever is lower. For this device,
TJMAX = 125˚C, and the typical junction-to-ambient thermal resistance of the dual-in-line J package when the board mounted is 100˚C/W. For the dual-in-line N pack-
age, this number increases to 175˚C/W and for the small outline M package this number is 100˚C/W.
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: All current switches are tested to guarantee at least 50% of rated current.
Note 7: All bits switched.
Note 8: Pin-out numbers for the DAL080X represent the dual-in-line package. The small outline package pinout differs from the dual-in-line package.
Typical Application
DS005687-23
DS005687-3
Typical Performance Characteristics VCC = 5V, VEE = −15V, TA = 25˚C, unless otherwise noted
DS005687-14 DS005687-15
DS005687-16
www.national.com 4
Typical Performance Characteristics VCC = 5V, VEE = −15V, TA = 25˚C, unless otherwise
noted (Continued)
DS005687-18
DS005687-17 DS005687-19
DS005687-20
DS005687-21 DS005687-22
Unless otherwise specified: R14 = R15 = 1 kΩ, C = 15 pF, pin 16 to VEE; RL = 50Ω, pin 4 to ground.
Curve A: Large Signal Bandwidth Method of Figure 7, VREF = 2 Vp-p offset 1V above ground.
Curve B: Small Signal Bandwidth Method of Figure 7, RL = 250Ω, VREF = 50 mVp-p offset 200 mV above ground.
Curve C: Large and Small Signal Bandwidth Method of Figure 9 (no op amp, RL = 50Ω), RS = 50Ω, VREF = 2V, VS = 100 mVp-p
centered at 0V.
5 www.national.com
www.national.com
6
DS005687-4
DS005687-6
DS005687-7
7 www.national.com
Test Circuits (Continued)
DS005687-8
DS005687-9
DS005687-10
www.national.com 8
Test Circuits (Continued)
DS005687-11
DS005687-12
9 www.national.com
Application Hints (Continued) der. The reference current may drift with temperature, caus-
ing a change in the absolute accuracy of output current.
to VEE on pin 16, using the values of the previous paragraph. However, the DAC0808 has a very low full-scale current drift
The negative reference voltage must be at least 4V above with temperature.
the VEE supply. Bipolar input signals may be handled by con- The DAC0808 series is guaranteed accurate to within ± 1⁄2
necting R14 to a positive reference voltage equal to the peak LSB at a full-scale output current of 1.992 mA. This corre-
positive input level at pin 15. sponds to a reference amplifier output current drive to the
When a DC reference voltage is used, capacitive bypass to ladder network of 2 mA, with the loss of 1 LSB (8 µA) which
ground is recommended. The 5V logic supply is not recom- is the ladder remainder shunted to ground. The input current
mended as a reference voltage. If a well regulated 5V supply to pin 14 has a guaranteed value of between 1.9 and 2.1 mA,
which drives logic is to be used as the reference, R14 should allowing some mismatch in the NPN current source pair. The
be decoupled by connecting it to 5V through another resistor accuracy test circuit is shown in Figure 4. The 12-bit con-
and bypassing the junction of the 2 resistors with 0.1 µF to verter is calibrated for a full-scale output current of 1.992
ground. For reference voltages greater than 5V, a clamp di- mA. This is an optional step since the DAC0808 accuracy is
ode is recommended between pin 14 and ground. essentially the same between 1.5 and 2.5 mA. Then the
If pin 14 is driven by a high impedance such as a transistor DAC0808 circuits’ full-scale current is trimmed to the same
current source, none of the above compensation methods value with R14 so that a zero value appears at the error am-
apply and the amplifier must be heavily compensated, de- plifier output. The counter is activated and the error band
creasing the overall bandwidth. may be displayed on an oscilloscope, detected by compara-
tors, or stored in a peak detector.
OUTPUT VOLTAGE RANGE Two 8-bit D-to-A converters may not be used to construct a
The voltage on pin 4 is restricted to a range of −0.55 to 0.4V 16-bit accuracy D-to-A converter. 16-bit accuracy implies a
when VEE = −5V due to the current switching methods em- total error of ± 1⁄2 of one part in 65,536 or ± 0.00076%, which
ployed in the DAC0808. is much more accurate than the ± 0.019% specification pro-
The negative output voltage compliance of the DAC0808 is vided by the DAC0808.
extended to −5V where the negative supply voltage is more
MULTIPLYING ACCURACY
negative than −10V. Using a full-scale current of 1.992 mA
and load resistor of 2.5 kΩ between pin 4 and ground will The DAC0808 may be used in the multiplying mode with
yield a voltage output of 256 levels between 0 and −4.980V. 8-bit accuracy when the reference current is varied over a
Floating pin 1 does not affect the converter speed or power range of 256:1. If the reference current in the multiplying
dissipation. However, the value of the load resistor deter- mode ranges from 16 µA to 4 mA, the additional error contri-
mines the switching time due to increased voltage swing. butions are less than 1.6 µA. This is well within 8-bit accu-
Values of RL up to 500Ω do not significantly affect perfor- racy when referred to full-scale.
mance, but a 2.5 kΩ load increases worst-case settling time A monotonic converter is one which supplies an increase in
to 1.2 µs (when all bits are switched ON). Refer to the sub- current for each increment in the binary word. Typically, the
sequent text section on Settling Time for more details on out- DAC0808 is monotonic for all values of reference current
put loading. above 0.5 mA. The recommended range for operation with a
DC reference current is 0.5 to 4 mA.
OUTPUT CURRENT RANGE
The output current maximum rating of 4.2 mA may be used SETTLING TIME
only for negative supply voltages more negative than −8V, The worst-case switching condition occurs when all bits are
due to the increased voltage drop across the resistors in the switched ON, which corresponds to a low-to-high transition
reference current amplifier. for all bits. This time is typically 150 ns for settling to within
± 1⁄2 LSB, for 8-bit accuracy, and 100 ns to 1⁄2 LSB for 7 and
ACCURACY 6-bit accuracy. The turn OFF is typically under 100 ns. These
Absolute accuracy is the measure of each output current times apply when RL ≤ 500Ω and CO ≤ 25 pF.
level with respect to its intended value, and is dependent Extra care must be taken in board layout since this is usually
upon relative accuracy and full-scale current drift. Relative the dominant factor in satisfactory test results when measur-
accuracy is the measure of each output current level as a ing settling time. Short leads, 100 µF supply bypassing for
fraction of the full-scale current. The relative accuracy of the low frequencies, and minimum scope lead length are all
DAC0808 is essentially constant with temperature due to the mandatory.
excellent temperature tracking of the monolithic resistor lad-
www.national.com 10
Physical Dimensions inches (millimeters) unless otherwise noted
Dual-In-Line Package
Order Number DAC0808
NS Package Number N16A
11 www.national.com
DAC0808 8-Bit D/A Converter
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
19-4323; Rev 11; 2/03
MAX220–MAX249
The MAX220–MAX249 family of line drivers/receivers is Superior to Bipolar
intended for all EIA/TIA-232E and V.28/V.24 communica- ♦ Operate from Single +5V Power Supply
tions interfaces, particularly applications where ±12V is
(+5V and +12V—MAX231/MAX239)
not available.
♦ Low-Power Receive Mode in Shutdown
These parts are especially useful in battery-powered sys-
(MAX223/MAX242)
tems, since their low-power shutdown mode reduces
power dissipation to less than 5µW. The MAX225, ♦ Meet All EIA/TIA-232E and V.28 Specifications
MAX233, MAX235, and MAX245/MAX246/MAX247 use ♦ Multiple Drivers and Receivers
no external components and are recommended for appli- ♦ 3-State Driver and Receiver Outputs
cations where printed circuit board space is critical. ♦ Open-Line Detection (MAX243)
Selection Table
Power No. of Nominal SHDN Rx
Part Supply RS-232 No. of Cap. Value & Three- Active in Data Rate
Number (V) Drivers/Rx Ext. Caps (µF) State SHDN (kbps) Features
MAX220 +5 2/2 4 0.1 No — 120 Ultra-low-power, industry-standard pinout
MAX222 +5 2/2 4 0.1 Yes — 200 Low-power shutdown
MAX223 (MAX213) +5 4/5 4 1.0 (0.1) Yes ✔ 120 MAX241 and receivers active in shutdown
MAX225 +5 5/5 0 — Yes ✔ 120 Available in SO
MAX230 (MAX200) +5 5/0 4 1.0 (0.1) Yes — 120 5 drivers with shutdown
MAX231 (MAX201) +5 and 2/2 2 1.0 (0.1) No — 120 Standard +5/+12V or battery supplies;
+7.5 to +13.2 same functions as MAX232
MAX232 (MAX202) +5 2/2 4 1.0 (0.1) No — 120 (64) Industry standard
MAX232A +5 2/2 4 0.1 No — 200 Higher slew rate, small caps
MAX233 (MAX203) +5 2/2 0 — No — 120 No external caps
MAX233A +5 2/2 0 — No — 200 No external caps, high slew rate
MAX234 (MAX204) +5 4/0 4 1.0 (0.1) No — 120 Replaces 1488
MAX235 (MAX205) +5 5/5 0 — Yes — 120 No external caps
MAX236 (MAX206) +5 4/3 4 1.0 (0.1) Yes — 120 Shutdown, three state
MAX237 (MAX207) +5 5/3 4 1.0 (0.1) No — 120 Complements IBM PC serial port
MAX238 (MAX208) +5 4/4 4 1.0 (0.1) No — 120 Replaces 1488 and 1489
MAX239 (MAX209) +5 and 3/5 2 1.0 (0.1) No — 120 Standard +5/+12V or battery supplies;
+7.5 to +13.2 single-package solution for IBM PC serial port
MAX240 +5 5/5 4 1.0 Yes — 120 DIP or flatpack package
MAX241 (MAX211) +5 4/5 4 1.0 (0.1) Yes — 120 Complete IBM PC serial port
MAX242 +5 2/2 4 0.1 Yes ✔ 200 Separate shutdown and enable
MAX243 +5 2/2 4 0.1 No — 200 Open-line detection simplifies cabling
MAX244 +5 8/10 4 1.0 No — 120 High slew rate
MAX245 +5 8/10 0 — Yes ✔ 120 High slew rate, int. caps, two shutdown modes
MAX246 +5 8/10 0 — Yes ✔ 120 High slew rate, int. caps, three shutdown modes
MAX247 +5 8/9 0 — Yes ✔ 120 High slew rate, int. caps, nine operating modes
MAX248 +5 8/8 4 1.0 Yes ✔ 120 High slew rate, selective half-chip enables
MAX249 +5 6/10 4 1.0 Yes ✔ 120 Available in quad flatpack package
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+5V-Powered, Multichannel RS-232
Drivers/Receivers
ABSOLUTE MAXIMUM RATINGS—MAX220/222/232A/233A/242/243
MAX220–MAX249
Supply Voltage (VCC) ...............................................-0.3V to +6V 20-Pin Plastic DIP (derate 8.00mW/°C above +70°C) ..440mW
Input Voltages 16-Pin Narrow SO (derate 8.70mW/°C above +70°C) ...696mW
TIN..............................................................-0.3V to (VCC - 0.3V) 16-Pin Wide SO (derate 9.52mW/°C above +70°C)......762mW
RIN (Except MAX220) ........................................................±30V 18-Pin Wide SO (derate 9.52mW/°C above +70°C)......762mW
RIN (MAX220).....................................................................±25V 20-Pin Wide SO (derate 10.00mW/°C above +70°C)....800mW
TOUT (Except MAX220) (Note 1) .......................................±15V 20-Pin SSOP (derate 8.00mW/°C above +70°C) ..........640mW
TOUT (MAX220)...............................................................±13.2V 16-Pin CERDIP (derate 10.00mW/°C above +70°C).....800mW
Output Voltages 18-Pin CERDIP (derate 10.53mW/°C above +70°C).....842mW
TOUT ...................................................................................±15V Operating Temperature Ranges
ROUT .........................................................-0.3V to (VCC + 0.3V) MAX2_ _AC_ _, MAX2_ _C_ _ .............................0°C to +70°C
Driver/Receiver Output Short Circuited to GND.........Continuous MAX2_ _AE_ _, MAX2_ _E_ _ ..........................-40°C to +85°C
Continuous Power Dissipation (TA = +70°C) MAX2_ _AM_ _, MAX2_ _M_ _ .......................-55°C to +125°C
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)....842mW Storage Temperature Range .............................-65°C to +160°C
18-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW Lead Temperature (soldering, 10s) .................................+300°C
Note 1: Input voltage measured with TOUT in high-impedance state, SHDN or VCC = 0V.
Note 2: For the MAX220, V+ and V- can have a maximum magnitude of 7V, but their absolute difference cannot exceed 13V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX220/222/232A/233A/242/243
(VCC = +5V ±10%, C1–C4 = 0.1µF‚ MAX220, C1 = 0.047µF, C2–C4 = 0.33µF, TA = TMIN to TMAX‚ unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
RS-232 TRANSMITTERS
Output Voltage Swing All transmitter outputs loaded with 3kΩ to GND ±5 ±8 V
Input Logic Threshold Low 1.4 0.8 V
All devices except MAX220 2 1.4
Input Logic Threshold High V
MAX220: VCC = 5.0V 2.4
All except MAX220, normal operation 5 40
Logic Pull-Up/lnput Current µA
SHDN = 0V, MAX222/242, shutdown, MAX220 ±0.01 ±1
VCC = 5.5V, SHDN = 0V, VOUT = ±15V, MAX222/242 ±0.01 ±10
Output Leakage Current µA
VCC = SHDN = 0V, VOUT = ±15V ±0.01 ±10
Data Rate 200 116 kbps
Transmitter Output Resistance VCC = V+ = V- = 0V, VOUT = ±2V 300 10M Ω
Output Short-Circuit Current VOUT = 0V ±7 ±22 mA
RS-232 RECEIVERS
RS-232 Input Voltage Operating Range ±30 V
All except MAX243 R2IN 0.8 1.3
RS-232 Input Threshold Low VCC = 5V V
MAX243 R2IN (Note 2) -3
All except MAX243 R2IN 1.8 2.4
RS-232 Input Threshold High VCC = 5V V
MAX243 R2IN (Note 2) -0.5 -0.1
All except MAX243, VCC = 5V, no hysteresis in shdn. 0.2 0.5 1
RS-232 Input Hysteresis V
MAX243 1
RS-232 Input Resistance 3 5 7 kΩ
TTL/CMOS Output Voltage Low IOUT = 3.2mA 0.2 0.4 V
TTL/CMOS Output Voltage High IOUT = -1.0mA 3.5 VCC - 0.2 V
Sourcing VOUT = GND -2 -10
TTL/CMOS Output Short-Circuit Current mA
Shrinking VOUT = VCC 10 30
2 _______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
ELECTRICAL CHARACTERISTICS—MAX220/222/232A/233A/242/243 (continued)
MAX220–MAX249
(VCC = +5V ±10%, C1–C4 = 0.1µF‚ MAX220, C1 = 0.047µF, C2–C4 = 0.33µF, TA = TMIN to TMAX‚ unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
SHDN = VCC or EN = VCC (SHDN = 0V for MAX222),
TTL/CMOS Output Leakage Current ±0.05 ±10 µA
0V ≤ VOUT ≤ VCC
EN Input Threshold Low MAX242 1.4 0.8 V
EN Input Threshold High MAX242 2.0 1.4 V
Operating Supply Voltage 4.5 5.5 V
MAX220 0.5 2
No load
VCC Supply Current (SHDN = VCC), MAX222/232A/233A/242/243 4 10
mA
Figures 5, 6, 11, 19 3kΩ load MAX220 12
both inputs MAX222/232A/233A/242/243 15
TA = +25°C 0.1 10
TA = 0°C to +70°C 2 50
Shutdown Supply Current MAX222/242 µA
TA = -40°C to +85°C 2 50
TA = -55°C to +125°C 35 100
SHDN Input Leakage Current MAX222/242 ±1 µA
SHDN Threshold Low MAX222/242 1.4 0.8 V
SHDN Threshold High MAX222/242 2.0 1.4 V
CL = 50pF to 2500pF,
RL = 3kΩ to 7kΩ, MAX222/232A/233A/242/243 6 12 30
Transition Slew Rate VCC = 5V, TA = +25°C, V/µs
measured from +3V MAX220 1.5 3 30
to -3V or -3V to +3V
MAX222/232A/233A/242/243 1.3 3.5
Transmitter Propagation Delay tPHLT
MAX220 4 10
TLL to RS-232 (Normal Operation), µs
Figure 1 MAX222/232A/233A/242/243 1.5 3.5
tPLHT
MAX220 5 10
MAX222/232A/233A/242/243 0.5 1
Receiver Propagation Delay tPHLR
MAX220 0.6 3
RS-232 to TLL (Normal Operation), µs
Figure 2 MAX222/232A/233A/242/243 0.6 1
tPLHR
MAX220 0.8 3
Receiver Propagation Delay tPHLS MAX242 0.5 10
µs
RS-232 to TLL (Shutdown), Figure 2 tPLHS MAX242 2.5 10
Receiver-Output Enable Time, Figure 3 tER MAX242 125 500 ns
Receiver-Output Disable Time, Figure 3 tDR MAX242 160 500 ns
Transmitter-Output Enable Time MAX222/242, 0.1µF caps
tET 250 µs
(SHDN Goes High), Figure 4 (includes charge-pump start-up)
Transmitter-Output Disable Time
tDT MAX222/242, 0.1µF caps 600 ns
(SHDN Goes Low), Figure 4
Transmitter + to - Propagation MAX222/232A/233A/242/243 300
tPHLT - tPLHT ns
Delay Difference (Normal Operation) MAX220 2000
Receiver + to - Propagation MAX222/232A/233A/242/243 100
tPHLR - tPLHR ns
Delay Difference (Normal Operation) MAX220 225
_______________________________________________________________________________________ 3
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
MAX220-02
MAX220-03
1µF V+
8 OUTPUT LOAD CURRENT 1µF CAPS
10 FLOWS FROM V+ TO V-
6 EITHER V+ OR V- LOADED V+
0.1µF CAPS
ALL CAPS +5V
OUTPUT CURRENT (mA)
4 9 1µF +5V
4 _______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
ABSOLUTE MAXIMUM RATINGS—MAX223/MAX230–MAX241
VCC ...........................................................................-0.3V to +6V 20-Pin Wide SO (derate 10 00mW/°C above +70°C).......800mW
V+ ................................................................(VCC - 0.3V) to +14V 24-Pin Wide SO (derate 11.76mW/°C above +70°C).......941mW
V- ............................................................................+0.3V to -14V 28-Pin Wide SO (derate 12.50mW/°C above +70°C) .............1W
Input Voltages 44-Pin Plastic FP (derate 11.11mW/°C above +70°C) .....889mW
TIN ............................................................-0.3V to (VCC + 0.3V) 14-Pin CERDIP (derate 9.09mW/°C above +70°C) ..........727mW
RIN......................................................................................±30V 16-Pin CERDIP (derate 10.00mW/°C above +70°C) ........800mW
Output Voltages 20-Pin CERDIP (derate 11.11mW/°C above +70°C) ........889mW
TOUT ...................................................(V+ + 0.3V) to (V- - 0.3V) 24-Pin Narrow CERDIP
ROUT .........................................................-0.3V to (VCC + 0.3V) (derate 12.50mW/°C above +70°C) ..............1W
Short-Circuit Duration, TOUT ......................................Continuous 24-Pin Sidebraze (derate 20.0mW/°C above +70°C)..........1.6W
Continuous Power Dissipation (TA = +70°C) 28-Pin SSOP (derate 9.52mW/°C above +70°C).............762mW
14-Pin Plastic DIP (derate 10.00mW/°C above +70°C)....800mW Operating Temperature Ranges
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)....842mW MAX2 _ _ C _ _......................................................0°C to +70°C
20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW MAX2 _ _ E _ _ ...................................................-40°C to +85°C
24-Pin Narrow Plastic DIP MAX2 _ _ M _ _ ...............................................-55°C to +125°C
(derate 13.33mW/°C above +70°C) ..........1.07W Storage Temperature Range .............................-65°C to +160°C
24-Pin Plastic DIP (derate 9.09mW/°C above +70°C)......500mW Lead Temperature (soldering, 10s) .................................+300°C
16-Pin Wide SO (derate 9.52mW/°C above +70°C).........762mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX223/MAX230–MAX241
(MAX223/230/232/234/236/237/238/240/241, VCC = +5V ±10; MAX233/MAX235, VCC = 5V ±5%‚ C1–C4 = 1.0µF; MAX231/MAX239,
VCC = 5V ±10%; V+ = 7.5V to 13.2V; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Voltage Swing All transmitter outputs loaded with 3kΩ to ground ±5.0 ±7.3 V
MAX232/233 5 10
No load,
VCC Power-Supply Current MAX223/230/234–238/240/241 7 15 mA
TA = +25°C
MAX231/239 0.4 1
MAX231 1.8 5
V+ Power-Supply Current mA
MAX239 5 15
MAX223 15 50
Shutdown Supply Current TA = +25°C µA
MAX230/235/236/240/241 1 10
Input Logic Threshold Low TIN; EN, SHDN (MAX233); EN, SHDN (MAX230/235–241) 0.8 V
TIN 2.0
Input Logic Threshold High EN, SHDN (MAX223); V
2.4
EN, SHDN (MAX230/235/236/240/241)
Logic Pull-Up Current TIN = 0V 1.5 200 µA
Receiver Input Voltage
-30 30 V
Operating Range
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+5V-Powered, Multichannel RS-232
Drivers/Receivers
ELECTRICAL CHARACTERISTICS—MAX223/MAX230–MAX241 (continued)
MAX220–MAX249
(MAX223/230/232/234/236/237/238/240/241, VCC = +5V ±10; MAX233/MAX235, VCC = 5V ±5%‚ C1–C4 = 1.0µF; MAX231/MAX239,
VCC = 5V ±10%; V+ = 7.5V to 13.2V; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Normal operation
SHDN = 5V (MAX223) 0.8 1.2
TA = +25°C, SHDN = 0V (MAX235/236/240/241)
RS-232 Input Threshold Low V
VCC = 5V Shutdown (MAX223)
SHDN = 0V, 0.6 1.5
EN = 5V (R4IN, R5IN)
Normal operation
SHDN = 5V (MAX223) 1.7 2.4
TA = +25°C, SHDN = 0V (MAX235/236/240/241)
RS-232 Input Threshold High V
VCC = 5V Shutdown (MAX223)
SHDN = 0V, 1.5 2.4
EN = 5V (R4IN‚ R5IN)
RS-232 Input Hysteresis VCC = 5V, no hysteresis in shutdown 0.2 0.5 1.0 V
RS-232 Input Resistance TA = +25°C, VCC = 5V 3 5 7 kΩ
TTL/CMOS Output Voltage Low IOUT = 1.6mA (MAX231/232/233, IOUT = 3.2mA) 0.4 V
TTL/CMOS Output Voltage High IOUT = -1mA 3.5 VCC - 0.4 V
0V ≤ ROUT ≤ VCC; EN = 0V (MAX223);
TTL/CMOS Output Leakage Current 0.05 ±10 µA
EN = VCC (MAX235–241 )
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Drivers/Receivers
__________________________________________Typical Operating Characteristics
MAX220–MAX249
MAX223/MAX230–MAX241
TRANSMITTER OUTPUT VOLTAGE (VOH)
TRANSMITTER OUTPUT vs. LOAD CAPACITANCE AT TRANSMITTER SLEW RATE
VOLTAGE (VOH) vs. VCC DIFFERENT DATA RATES vs. LOAD CAPACITANCE
8.5 MAX220-04 7.4 12.0
MAX220-06
MAX220-05
1 TRANSMITTER LOADED TA = +25°C
2 TRANSMITTERS
LOADED 7.2 11.0 VCC = +5V
LOADED, RL = 3kΩ
8.0 10.0 C1–C4 = 1µF
7.0
6.8
VOH (V)
MAX220-09
MAX220-08
MAX220-07
V- LOADED,
VOL (V)
VOL (V)
V+ AND V- V+ LOADED,
160kbits/sec NO LOAD
-7.5 -6.8 0 EQUALLY
80kbits/sec ON V+ NO LOAD
1 TRANS- -2 LOADED ON V-
-7.0 20Kkbits/sec
-8.0 MITTER
LOADED -4
-7.2
2 TRANS- 3 TRANS- -6
-8.5
MITTERS MITTERS -7.4
-8
LOADED LOADED ALL TRANSMITTERS UNLOADED
-9.0 -7.6 -10
4.5 5.0 5.5 0 500 1000 1500 2000 2500 0 5 10 15 20 25 30 35 40 45 50
VCC (V) LOAD CAPACITANCE (pF) CURRENT (mA)
V+
V-
SHDN*
500ms/div
*SHUTDOWN POLARITY IS REVERSED
FOR NON MAX241 PARTS
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+5V-Powered, Multichannel RS-232
Drivers/Receivers
ABSOLUTE MAXIMUM RATINGS—MAX225/MAX244–MAX249
MAX220–MAX249
Supply Voltage (VCC) ...............................................-0.3V to +6V Continuous Power Dissipation (TA = +70°C)
Input Voltages 28-Pin Wide SO (derate 12.50mW/°C above +70°C) .............1W
TIN‚ ENA, ENB, ENR, ENT, ENRA, 40-Pin Plastic DIP (derate 11.11mW/°C above +70°C) ...611mW
ENRB, ENTA, ENTB..................................-0.3V to (VCC + 0.3V) 44-Pin PLCC (derate 13.33mW/°C above +70°C) ...........1.07W
RIN .....................................................................................±25V Operating Temperature Ranges
TOUT (Note 3).....................................................................±15V MAX225C_ _, MAX24_C_ _ ..................................0°C to +70°C
ROUT ........................................................-0.3V to (VCC + 0.3V) MAX225E_ _, MAX24_E_ _ ...............................-40°C to +85°C
Short Circuit (one output at a time) Storage Temperature Range .............................-65°C to +160°C
TOUT to GND ............................................................Continuous Lead Temperature (soldering,10s) ..................................+300°C
ROUT to GND............................................................Continuous
Note 4: Input voltage measured with transmitter output in a high-impedance state, shutdown, or VCC = 0V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX225/MAX244–MAX249
(MAX225, VCC = 5.0V ±5%; MAX244–MAX249, VCC = +5.0V ±10%, external capacitors C1–C4 = 1µF; TA = TMIN to TMAX; unless oth-
erwise noted.)
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Drivers/Receivers
ELECTRICAL CHARACTERISTICS—MAX225/MAX244–MAX249 (continued)
MAX220–MAX249
(MAX225, VCC = 5.0V ±5%; MAX244–MAX249, VCC = +5.0V ±10%, external capacitors C1–C4 = 1µF; TA = TMIN to TMAX; unless oth-
erwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY AND CONTROL LOGIC
MAX225 4.75 5.25
Operating Supply Voltage V
MAX244–MAX249 4.5 5.5
MAX225 10 20
No load
VCC Supply Current MAX244–MAX249 11 30
mA
(Normal Operation) 3kΩ loads on MAX225 40
all outputs MAX244–MAX249 57
TA = +25°C 8 25
Shutdown Supply Current µA
TA = TMIN to TMAX 50
Leakage current ±1 µA
Control Input Threshold low 1.4 0.8
V
Threshold high 2.4 1.4
AC CHARACTERISTICS
CL = 50pF to 2500pF, RL = 3kΩ to 7kΩ, VCC = 5V,
Transition Slew Rate 5 10 30 V/µs
TA = +25°C, measured from +3V to -3V or -3V to +3V
Transmitter + to - Propagation
tPHLT - tPLHT 350 ns
Delay Difference (Normal Operation)
Receiver + to - Propagation
tPHLR - tPLHR 350 ns
Delay Difference (Normal Operation)
Receiver-Output Enable Time, Figure 3 tER 100 500 ns
Receiver-Output Disable Time, Figure 3 tDR 100 500 ns
MAX246–MAX249
5 µs
(excludes charge-pump startup)
Transmitter Enable Time tET
MAX225/MAX245–MAX249
10 ms
(includes charge-pump startup)
Transmitter Disable Time, Figure 4 tDT 100 ns
Note 5: The 300Ω minimum specification complies with EIA/TIA-232E, but the actual resistance when in shutdown mode or VCC =
0V is 10MΩ as is implied by the leakage specification.
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+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
MAX220-11
MAX220-12
VCC = 5V VCC = 5V WITH ALL TRANSMITTERS DRIVEN
8 LOADED WITH 5kΩ
16 V+ AND V- LOADED 8.5
TRANSMITTER SLEW RATE (V/µs)
6 EITHER V+ OR 10kb/sec
14 8.0 20kb/sec
V- LOADED
OUTPUT VOLTAGE (V)
V+, V (V)
1µF CAPACITORS
10 0 8 TRANSMITTERS 7.0 60kb/sec
40kb/s DATA RATE DRIVING 5kΩ AND
8 8 TRANSMITTERS -2
2000pF AT 20kbits/sec 6.5
LOADED WITH 3kΩ -4 V- LOADED
6 6.0 100kb/sec
-6 V+ AND V- LOADED
200kb/sec
4 5.5
-8
V+ LOADED ALL CAPACITIORS 1µF
2 -10 5.0
0 1 2 3 4 5 0 5 10 15 20 25 30 35 0 1 2 3 4 5
LOAD CAPACITANCE (nF) LOAD CURRENT (mA) LOAD CAPACITANCE (nF)
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+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+3V
0V* 50% 50%
+3V INPUT
INPUT
0V
VCC
OUTPUT 50% 50%
V+ GND
OUTPUT 0V
V-
tPHLR tPLHR
tPHLS tPLHS
tPLHT tPHLT
EN
RX OUT 1kΩ
RX IN RX VCC - 2V
+3V
SHDN
a) TEST CIRCUIT 0V
150pF
+3V OUTPUT DISABLE TIME (tDT)
EN INPUT V+
0V +5V
EN
OUTPUT ENABLE TIME (tER) 0V
+3.5V -5V
RECEIVER V-
OUTPUTS
+0.8V
a) TIMING DIAGRAM
b) ENABLE TIMING
+3V
EN
0V 1 OR 0 TX
EN INPUT
OUTPUT DISABLE TIME (tDR) 3kΩ 50pF
VOH
VOH - 0.5V
RECEIVER VCC - 2V
OUTPUTS
VOL + 0.5V b) TEST CIRCUIT
VOL
c) DISABLE TIMING
Figure 3. Receiver-Output Enable and Disable Timing Figure 4. Transmitter-Output Disable Timing
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+5V-Powered, Multichannel RS-232
Drivers/Receivers
Table 1a. MAX245 Control Pin Configurations
MAX220–MAX249
RA1–RA4 3-State,
1 0 Shutdown All 3-State All Active All Active
RA5 Active
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Drivers/Receivers
Table 1d. MAX247/MAX248/MAX249 Control Pin Configurations
MAX220–MAX249
TRANSMITTERS RECEIVERS
OPERATION MAX247 TA1–TA4 TB1–TB4 RA1–RA4 RB1–RB5
ENTA ENTB ENRA ENRB
STATUS MAX248 TA1–TA4 TB1–TB4 RA1–RA4 RB1–RB4
MAX249 TA1–TA3 TB1–TB3 RA1–RA5 RB1–RB5
0 0 0 0 Normal Operation All Active All Active All Active All Active
All 3-State, except
0 0 0 1 Normal Operation All Active All Active All Active RB5 stays active on
MAX247
0 0 1 0 Normal Operation All Active All Active All 3-State All Active
All 3-State, except
0 0 1 1 Normal Operation All Active All Active All 3-State RB5 stays active on
MAX247
0 1 0 0 Normal Operation All Active All 3-State All Active All Active
All 3-State, except
0 1 0 1 Normal Operation All Active All 3-State All Active RB5 stays active on
MAX247
0 1 1 0 Normal Operation All Active All 3-State All 3-State All Active
All 3-State, except
0 1 1 1 Normal Operation All Active All 3-State All 3-State RB5 stays active on
MAX247
1 0 0 0 Normal Operation All 3-State All Active All Active All Active
All 3-State, except
1 0 0 1 Normal Operation All 3-State All Active All Active RB5 stays active on
MAX247
1 0 1 0 Normal Operation All 3-State All Active All 3-State All Active
All 3-State, except
1 0 1 1 Normal Operation All 3-State All Active All 3-State RB5 stays active on
MAX247
Low-Power Low-Power
1 1 0 0 Shutdown All 3-State All 3-State
Receive Mode Receive Mode
Low-Power
1 1 1 0 Shutdown All 3-State All 3-State All 3-State
Receive Mode
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+5V-Powered, Multichannel RS-232
Drivers/Receivers
_______________Detailed Description mode, in three-state mode, or when device power is
MAX220–MAX249
14 ______________________________________________________________________________________
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Drivers/Receivers
nominal 5kΩ values. The receivers implement Type 1 Shutdown—MAX222–MAX242
MAX220–MAX249
interpretation of the fault conditions of V.28 and On the MAX222‚ MAX235‚ MAX236‚ MAX240‚ and
EIA/TIA-232E. MAX241‚ all receivers are disabled during shutdown.
The receiver input hysteresis is typically 0.5V with a On the MAX223 and MAX242‚ two receivers continue to
guaranteed minimum of 0.2V. This produces clear out- operate in a reduced power mode when the chip is in
put transitions with slow-moving input signals, even shutdown. Under these conditions‚ the propagation
with moderate amounts of noise and ringing. The delay increases to about 2.5µs for a high-to-low input
receiver propagation delay is typically 600ns and is transition. When in shutdown, the receiver acts as a
independent of input swing direction. CMOS inverter with no hysteresis. The MAX223 and
MAX242 also have a receiver output enable input (EN
Low-Power Receive Mode for the MAX242 and EN for the MAX223) that allows
The low-power receive-mode feature of the MAX223, receiver output control independent of SHDN (SHDN
MAX242, and MAX245–MAX249 puts the IC into shut- for MAX241). With all other devices‚ SHDN (SHDN for
down mode but still allows it to receive information. This MAX241) also disables the receiver outputs.
is important for applications where systems are periodi- The MAX225 provides five transmitters and five
cally awakened to look for activity. Using low-power receivers‚ while the MAX245 provides ten receivers and
receive mode, the system can still receive a signal that eight transmitters. Both devices have separate receiver
will activate it on command and prepare it for communi- and transmitter-enable controls. The charge pumps
cation at faster data rates. This operation conserves turn off and the devices shut down when a logic high is
system power. applied to the ENT input. In this state, the supply cur-
Negative Threshold—MAX243 rent drops to less than 25µA and the receivers continue
The MAX243 is pin compatible with the MAX232A, differ- to operate in a low-power receive mode. Driver outputs
ing only in that RS-232 cable fault protection is removed enter a high-impedance state (three-state mode). On
on one of the two receiver inputs. This means that control the MAX225‚ all five receivers are controlled by the
lines such as CTS and RTS can either be driven or left ENR input. On the MAX245‚ eight of the receiver out-
floating without interrupting communication. Different puts are controlled by the ENR input‚ while the remain-
cables are not needed to interface with different pieces of ing two receivers (RA5 and RB5) are always active.
equipment. RA1–RA4 and RB1–RB4 are put in a three-state mode
when ENR is a logic high.
The input threshold of the receiver without cable fault
protection is -0.8V rather than +1.4V. Its output goes Receiver and Transmitter Enable
positive only if the input is connected to a control line Control Inputs
that is actively driven negative. If not driven, it defaults The MAX225 and MAX245–MAX249 feature transmitter
to the 0 or “OK to send” state. Normally‚ the MAX243’s and receiver enable controls.
other receiver (+1.4V threshold) is used for the data line The receivers have three modes of operation: full-speed
(TD or RD)‚ while the negative threshold receiver is con- receive (normal active)‚ three-state (disabled)‚ and low-
nected to the control line (DTR‚ DTS‚ CTS‚ RTS, etc.). power receive (enabled receivers continue to function
Other members of the RS-232 family implement the at lower data rates). The receiver enable inputs control
optional cable fault protection as specified by EIA/TIA- the full-speed receive and three-state modes. The
232E specifications. This means a receiver output goes transmitters have two modes of operation: full-speed
high whenever its input is driven negative‚ left floating‚ transmit (normal active) and three-state (disabled). The
or shorted to ground. The high output tells the serial transmitter enable inputs also control the shutdown
communications IC to stop sending data. To avoid this‚ mode. The device enters shutdown mode when all
the control lines must either be driven or connected transmitters are disabled. Enabled receivers function in
with jumpers to an appropriate positive voltage level. the low-power receive mode when in shutdown.
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+5V-Powered, Multichannel RS-232
Drivers/Receivers
Tables 1a–1d define the control states. The MAX244 The MAX249 provides ten receivers and six drivers with
MAX220–MAX249
has no control pins and is not included in these tables. four control pins. The ENRA and ENRB receiver enable
The MAX246 has ten receivers and eight drivers with inputs each control five receiver outputs. The ENTA
two control pins, each controlling one side of the and ENTB transmitter enable inputs control three dri-
device. A logic high at the A-side control input (ENA) vers each. There is no always-active receiver. The
causes the four A-side receivers and drivers to go into device enters shutdown mode and transmitters go into
a three-state mode. Similarly, the B-side control input a three-state mode with a logic high on both ENTA and
(ENB) causes the four B-side drivers and receivers to ENTB. In shutdown mode, active receivers operate in a
go into a three-state mode. As in the MAX245, one A- low-power receive mode at data rates up to
side and one B-side receiver (RA5 and RB5) remain 20kbits/sec.
active at all times. The entire device is put into shut- __________Applications Information
down mode when both the A and B sides are disabled
(ENA = ENB = +5V). Figures 5 through 25 show pin configurations and typi-
cal operating circuits. In applications that are sensitive
The MAX247 provides nine receivers and eight drivers to power-supply noise, VCC should be decoupled to
with four control pins. The ENRA and ENRB receiver ground with a capacitor of the same value as C1 and
enable inputs each control four receiver outputs. The C2 connected as close as possible to the device.
ENTA and ENTB transmitter enable inputs each control
four drivers. The ninth receiver (RB5) is always active.
The device enters shutdown mode with a logic high on
both ENTA and ENTB.
The MAX248 provides eight receivers and eight drivers
with four control pins. The ENRA and ENRB receiver
enable inputs each control four receiver outputs. The
ENTA and ENTB transmitter enable inputs control four
drivers each. This part does not have an always-active
receiver. The device enters shutdown mode and trans-
mitters go into a three-state mode with a logic high on
both ENTA and ENTB.
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+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V INPUT C3
TOP VIEW
C5
16
1 VCC
C1+ 1 16 VCC C1+ V+ 2 +10V
C1 +5V TO +10V
V+ 2 3 C1-
15 GND VOLTAGE DOUBLER
4
C1- 3 C2+ +10V TO -10V 6 -10V
14 T1OUT C2 5 C2- VOLTAGE INVERTER
V-
C4
C2+ 4 MAX220 13 R1IN
+5V
MAX232
C2- 5 MAX232A 12 R1OUT 400kΩ
V- 6 11 T1IN T1OUT 14
11 T1IN
+5V
T2OUT 7 10 T2IN TTL/CMOS RS-232
INPUTS 400kΩ OUTPUTS
R2IN 8 9 R2OUT 10 T2IN T2OUT 7
GND
15
+5V INPUT C3
TOP VIEW ALL CAPACITORS = 0.1µF
C5
17
2 VCC 3 +10V
C1+ +5V TO +10V
C1 V+
(N.C.) EN 1 4 C1- VOLTAGE DOUBLER
20 SHDN
5
(N.C.) EN 1 C1+ 2 C2+ 7 -10V
18 SHDN 19 VCC
C2 +10V TO -10V V-
6 C2- C4
VOLTAGE INVERTER
C1+ 2 17 VCC V+ 3 18 GND
V+ 3 C1- 4 +5V
16 GND 17 T1OUT (EXCEPT MAX220)
400kΩ
C1- 4 15 T1OUT C2+ 5 MAX222 16 N.C.
MAX242 12 T1IN T1OUT 15
C2+ 5 MAX222 14 R1IN C2- 6 15 R1IN +5V
MAX242 TTL/CMOS RS-232
V- 7 400kΩ (EXCEPT MAX220)
C2- 6 13 R1OUT 14 R1OUT INPUTS OUTPUTS
11 T2IN T2OUT 8
V- 7 12 T1IN T2OUT 8 13 N.C.
T2OUT 8 11 T2IN R2IN 9 12 T1IN 13 R1OUT R1IN 14
R2IN 9 10 R2OUT R2OUT 10 11 T2IN
TTL/CMOS 5kΩ RS-232
OUTPUTS INPUTS
DIP/SO 10 R2OUT R2IN 9
SSOP
1 (N.C.) EN 5kΩ
( ) ARE FOR MAX222 ONLY. 18
GND SHDN
PIN NUMBERS IN TYPICAL OPERATING CIRCUIT ARE FOR DIP/SO PACKAGES ONLY.
16
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+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V
TOP VIEW
0.1
28 27
+5V VCC VCC
400kΩ
T1IN
3 11
ENR 1 +5V T1OUT
28 VCC
ENR 2 400kΩ
27 VCC
T2IN
T1IN 3 4 12
26 ENT T2OUT
+5V
T2IN 4 25 T3IN 400kΩ
R1OUT 5 MAX225 24 T4IN T3IN
25 18
+5V T3OUT
R2OUT 6 23 T5IN
400kΩ
R3OUT 7 22 R4OUT
T4IN
24 17
R3IN 8 21 R5OUT +5V T4OUT
R2IN 9 20 R5IN 400kΩ
T5IN T5OUT
R1IN 10 19 R4IN 23 16
T1OUT 11 18 T3OUT ENT
26 15
T2OUT 12 17 T4OUT T5OUT
SO R2OUT R2IN
6 9
5kΩ
R3OUT R3IN
7 8
MAX225 FUNCTIONAL DESCRIPTION
5kΩ
5 RECEIVERS
5 TRANSMITTERS R4OUT R4IN
22 19
2 CONTROL PINS
1 RECEIVER ENABLE (ENR) 5kΩ
1 TRANSMITTER ENABLE (ENT)
R5OUT R5IN
21 20
5kΩ
1 ENR
2 ENR
PINS (ENR, GND, VCC, T5OUT) ARE INTERNALLY CONNECTED. GND GND
CONNECT EITHER OR BOTH EXTERNALLY. T5OUT IS A SINGLE DRIVER. 13 14
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+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V INPUT
TOP VIEW 1.0µF
11
12 1.0µF
C1+ VCC 13
1.0µF 14 +5V TO +10V V+
C1- VOLTAGE DOUBLER
15
C2+ +10V TO -10V 17
1.0µF VOLTAGE INVERTER V-
16 C2-
1.0µF
+5V
400kΩ
7 T1IN T1OUT 2
T1
T3OUT 1 28 T4OUT +5V
GND 10 19 R5OUT*
8 R1OUT R1IN 9
VCC 11 18 R5IN* R1
5kΩ
C1+ 12 17 V-
V+ 13 16 C2- R2IN 4
5 R2OUT
R2
C1- 14 15 C2+
5kΩ
Wide SO/
SSOP LOGIC 26 R3OUT R3IN 27 RS-232
R3
OUTPUTS INPUTS
5kΩ
22 R4OUT R4IN 23
R4
5kΩ
19 R5OUT R5IN 18
R5
*R4 AND R5 IN MAX223 REMAIN ACTIVE IN SHUTDOWN 5kΩ
NOTE: PIN LABELS IN ( ) ARE FOR MAX241 24 EN (EN) SHDN 25
(SHDN)
GND
10
______________________________________________________________________________________ 19
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V INPUT
TOP VIEW 1.0µF
7 1.0µF
8 C1+ VCC
V+ 9
1.0µF 10 C1- +5V TO +10V
VOLTAGE DOUBLER
T3OUT 1 20 T4OUT 11
C2+ +10V TO -10V 13
1.0µF 12 V-
T1OUT 2 19 T5IN C2- VOLTAGE INVERTER
1.0µF
T2OUT 3 18 N.C. +5V
400kΩ
T2IN 4 17 SHDN 5 T1IN T1OUT 2
T1
T1IN 5 MAX230 16 T5OUT +5V
400kΩ
GND 6 15 T4IN 4 T2IN T2OUT 3
T2
VCC 7 14 T3IN +5V
400kΩ
C1+ 8 13 V-
TTL/CMOS 14 T3IN T3OUT 1 RS-232
T3
V+ 9 12 C2- INPUTS +5V OUTPUTS
400kΩ
C1- 10 11 C2+ 15 T4IN T4OUT 20
T4
+5V
400kΩ
DIP/SO 19 T5IN T5OUT 16
T5
N.C. x 18 GND
17 SHDN
6
+5V INPUT
TOP VIEW 1.0µF +7.5V TO +12V
13 (15)
1 VCC 14 (16)
C1+ V+
1.0µF 2 +12V TO -12V 3
C1- VOLTAGE CONVERTER V-
C2
+5V 1.0µF
C+ 1 14 V+ C+ 1 16 V+
400kΩ
C- 2 13 VCC C- 2 15 VCC (10) (13)
8 T1IN T1OUT 11
T1
V- 3 12 GND V- 3 14 GND +5V
TTL/CMOS RS-232
T2OUT 4 MAX231 11 T1OUT T2OUT 4 MAX231 13 T1OUT INPUTS 400kΩ OUTPUTS
R2IN 5 10 R1IN R2IN 5 12 R1IN 7 T2IN T2OUT 4
T2
R2OUT 6 9 R1OUT R2OUT 6 11 R1OUT
(11) (12)
9 R1OUT R1IN 10
T2IN 7 8 T1IN T2IN 7 10 T1IN R1
GND
PIN NUMBERS IN ( ) ARE FOR SO PACKAGE 12 (14)
20 ______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V INPUT
1.0µF
TOP VIEW 7
+5V VCC
400kΩ
2 T1IN T1OUT 5
T2IN 1 20 R2OUT
+5V
T1IN 2 19 R2IN TTL/CMOS RS-232
INPUTS 400kΩ
R1OUT 3 OUTPUTS
18 T2OUT 1 T2IN T2OUT 18
R1IN 4 17 V-
3 R1OUT R1IN 4
T1OUT 5 MAX233 16 C2-
MAX233A
GND 6 15 C2+ TTL/CMOS 5kΩ
RS-232
OUTPUTS OUTPUTS
VCC 7 14 V+ (C1-)
(V+) C1+ 13 C1- (C1+) 20 R2OUT R2IN 19
8
GND 9 12 V- (C2+) 8 (13) 5kΩ C2+ 11 (12)
DO NOT MAKE C1+
CONNECTIONS TO 13 (14) 15
(V-) CS- 10 11 C2+ (C2-) C1-
THESE PINS C2+
12 (10) 16
INTERNAL -10 V- C2-
DIP/SO POWER SUPPLY 17 V-
10 (11)
C2-
INTERNAL +10V 14 (8) V+
GND GND
POWER SUPPLY
6 9
( ) ARE FOR SO PACKAGE ONLY.
+5V INPUT
1.0µF
TOP VIEW
6 1.0µF
7
C1+ VCC 8
+5V TO +10V V+
1.0µF 9
C1- VOLTAGE DOUBLER
10
C2+ +10V TO -10V 12
1.0µF VOLTAGE INVERTER V-
11 C2- 1.0µF
T1OUT 1 16 T3OUT
+5V
T2OUT 2 15 T4OUT
400kΩ
T2IN 3 14 T4IN 4 T1IN T1OUT 1
T1
T1IN 4 MAX234 13 T3IN +5V
GND 5 12 V- 400kΩ
VCC 6 11 C2- 3 T2IN T2OUT 3
T2
C1+ 7 10 C2+ TTL/CMOS +5V RS-232
INPUTS 400kΩ OUTPUTS
V+ 8 9 C1-
13 T3IN T3OUT 16
T3
DIP/SO +5V
400kΩ
14 T4IN T4OUT 15
T4
GND
5
______________________________________________________________________________________ 21
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V INPUT
TOP VIEW 1.0µF
12
VCC
+5V
400kΩ
8 T1IN T1OUT 3
T1
+5V
400kΩ
7 T2IN T2OUT 4
T2
+5V
400kΩ
TTL/CMOS 15 T3IN T3OUT 2 RS-232
T3
INPUTS OUTPUTS
T4OUT 1 24 R3IN +5V
400kΩ
T3OUT 2 23 R3OUT T4OUT 1
16 T4IN
T4
T1OUT 3 22 T5IN
+5V
T2OUT 4 21 SHDN 400kΩ
R2IN 5 MAX235 20 EN 22 T5IN T5OUT 19
T5
R2OUT 6 19 T5OUT
T2IN 7 18 R4IN
9 R1OUT R1IN 10
T1
T1IN 8 17 R4OUT
5kΩ
R1OUT 9 16 T4IN
17 R4OUT R4IN 18
R4
5kΩ
14 R5OUT R5IN 13
R5
5kΩ
20 EN 21
SHDN
GND
11
22 ______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
TOP VIEW +5V INPUT
1.0µF
9 1.0µF
10 11
C1+ VCC V+
1.0µF +5V TO +10V
12
C1- VOLTAGE DOUBLER
13 15
C2+ V-
1.0µF +10V TO -10V
14 C2- 1.0µF
VOLTAGE INVERTER
+5V
400kΩ
7 T1IN T1OUT 2
T1
C1+ 10 15 V-
V+ 11 14 C2- R1IN 4
5 R1OUT
R1
C1- 12 13 C2+
5kΩ
DIP/SO
22 R2OUT R2IN 23 RS-232
TTL/CMOS R2
OUTPUTS INPUTS
5kΩ
17 R3OUT R3IN 16
R3
5kΩ
20 EN 21
SHDN
GND
______________________________________________________________________________________ 23
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
TOP VIEW
+5V INPUT
1.0µF
9 1.0µF
10 VCC 11
C1+ V+
+5V TO +10V
1.0µF 12 VOLTAGE DOUBLER
C1-
13 15
C2+ V-
1.0µF +10V TO -10V
14 VOLTAGE INVERTER 1.0µF
C2-
+5V
400kΩ
5kΩ
17 R3OUT R3IN 16
R3
5kΩ
GND
8
24 ______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
TOP VIEW
+5V INPUT
1.0µF
9 1.0µF
10 VCC 11
C1+ V+
+5V TO +10V
1.0µF 12
C1- VOLTAGE DOUBLER
13
C2+ 15
1.0µF +10V TO -10V V-
14 VOLTAGE INVERTER
C2- 1.0µF
+5V
400kΩ
V+ 11 14 C2-
DIP/SO 5kΩ
4 R2OUT R2IN 3
R2
5kΩ
17 R4OUT R4IN 16
R4
5kΩ
GND
8
______________________________________________________________________________________ 25
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
TOP VIEW
7.5V TO 13.2V
+5V INPUT INPUT
1.0µF
4 5
6 VCC V+
C1+ 8
V-
+10V TO -10V
1.0µF 7 1.0µF
C1- VOLTAGE INVERTER
+5V
400kΩ
24 T1IN T1OUT 19
T1
R1OUT 1 24 T1IN +5V
400kΩ
R1IN 2 23 T2IN
TTL/CMOS 23 T2IN T2OUT 20
GND 3 22 R2OUT T2 RS-232
INPUTS OUTPUTS
+5V
VCC 4 21 R2IN
400kΩ
V+ 5 MAX239 20 T2OUT
16 T3IN T3OUT 13
C+ 6 19 T1OUT T3
C- 7 18 R3IN
DIP/SO
TTL/CMOS 17 R3OUT R3IN 18 RS-232
R3
OUTPUTS INPUTS
5kΩ
11 R4OUT R4IN 12
R4
5kΩ
10 R5OUT R5IN 9
R5
5kΩ
14 EN 15
N.C.
GND
3
26 ______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V INPUT
1.0µF
TOP VIEW
19
25 1.0µF
C1+ VCC 26
1.0µF 27 +5V TO +10V V+
C1- VOLTAGE DOUBLER
28
C2+ +5V TO -10V 30
1.0µF VOLTAGE INVERTER V-
29 C2- 1.0µF
+5V
400kΩ
15 T1IN T1OUT 7
T1
+5V
400kΩ
14 T2IN T2OUT 8
T2
R3OUT
T2OUT
T1OUT
T3OUT
T4OUT
R2IN
R3IN
N.C.
N.C.
N.C.
T5IN
+5V
400kΩ
+5V
400kΩ
N.C. 12 44 N.C. 38 T4IN T4OUT 5
T4
R2OUT 13 43 SHDN
T2IN 14 42 EN +5V
400kΩ
T1IN 15 41 T5OUT
R1OUT 16 40 R4IN 2 T5IN T5OUT 41
T5
R1IN 17 39 R4OUT
GND 18 MAX240 38 T4IN R1IN 17
16 R1OUT
VCC 19 37 T3IN R1
N.C. 20 36 R5OUT 5kΩ
N.C. 21 35 R5IN
N.C. 22 34 N.C. 13 R2OUT R2IN 10
R2
23
24
25
26
27
28
29
30
31
32
33
5kΩ
OUTPUTS INPUTS
5kΩ
Plastic FP
39 R4OUT R4IN 40
R4
5kΩ
36 R5OUT R5IN 35
R5
5kΩ
42 EN 43
SHDN
GND
18
______________________________________________________________________________________ 27
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
16
1
C1+ VCC
2 +10V
0.1µF +5V TO +10V V+
3 C1- VOLTAGE DOUBLER
4
C2+
C1+ 1 16 VCC +10V TO -10V 6 -10V
0.1µF 5 C2- V-
VOLTAGE INVERTER
V+ 2 15 GND 0.1µF
C1- 3 14 T1OUT +5V
V- 6 11 T1IN +5V
TTL/CMOS RS-232
INPUTS 400kΩ OUTPUTS
T2OUT 7 10 T2IN
DIP/SO
12 R1OUT R1IN 13
28 ______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V
TOP VIEW 1µF
1µF
20
21
C1+ VCC 22
1µF
TB4OUT
TA4OUT
TA3OUT
TA2OUT
TA1OUT
TB1OUT
TB2OUT
TB3OUT
23 C1- +5V TO +10V VOLTAGE DOUBLER V+
RA4IN
RA5IN
RB5IN
24 26
C2+ V- 1µF
1µF 25 C2-
6 5 4 3 2 1 44 43 42 41 40 +10V TO -10V VOLTAGE INVERTER
2 TA1OUT +5V +5V TB1OUT 44
400kΩ
15 TA1IN TB1IN 30
RA3IN 7 39 RB4IN
RA2IN 8 38 RB3IN +5V +5V
2 TA2OUT TB2OUT 43
RA1IN 9 37 RB2IN
400kΩ
RA1OUT 10 36 RB1IN 16 TA2IN TB2IN 29
RA2OUT 11 35 RB1OUT
RA3OUT 12
MAX244 34 RB2OUT 3 TA3OUT +5V +5V TB3OUT 42
RA4OUT 13 33 RB3OUT 400kΩ
RA5OUT 14 32 RB4OUT 17 TA3IN TB3IN 28
TA1IN 15 31 RB5OUT
4 TA4OUT +5V +5V TB4OUT 41
TA2IN 16 30 TB1IN
400kΩ
TA3IN 17 29 TB2IN 18 TA4IN TB4IN 27
9 RA1IN RB1IN 36
18 19 20 21 22 23 24 25 26 27 28
TA4IN
GND
C1+
V+
C1-
C2+
C2-
V-
TB4IN
TB3IN
VCC
5kΩ 5kΩ
5kΩ 5kΩ
MAX249 FUNCTIONAL DESCRIPTION
10 RECEIVERS 11 RA2OUT RB2OUT 34
5 A-SIDE RECEIVER 7 RA3IN RB3IN 38
5 B-SIDE RECEIVER
8 TRANSMITTERS 5kΩ 5kΩ
4 A-SIDE TRANSMITTERS
4 B-SIDE TRANSMITTERS 12 RA3OUT RB3OUT 33
NO CONTROL PINS 6 RA4IN RB4IN 39
5kΩ 5kΩ
13 RA4OUT RB4OUT 32
5 RA5IN RB5IN 40
5kΩ 5kΩ
14 RA5OUT RB5OUT 31
GND
19
______________________________________________________________________________________ 29
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V
TOP VIEW
1µF
40
VCC
ENR 1 40 VCC 16 TA1OUT +5V +5V TB1OUT 24
400kΩ
TA1IN 2 39 ENT
2 TA1IN TB1IN 38
TA2IN 3 38 TB1IN
17 TA2OUT +5V +5V TB2OUT 23
TA3IN 4 37 TB2IN
400kΩ
TA4IN 5 36 TB3IN
3 TA2IN TB2IN 37
RA5OUT 6 35 TB4IN
RA4OUT 7
MAX245 34 RB5OUT 18 TA3OUT +5V +5V TB3OUT 22
400kΩ
RA3OUT 8 33 RB4OUT
4 TA3IN TB3IN 36
RA2OUT 9 32 RB3OUT
19 TA4OUT +5V +5V TB4OUT 21
RA1OUT 10 31 RB2OUT
400kΩ
RA1IN 11 30 RB1OUT 5 TA4IN TB4IN 35
RA2IN 12 29 RB1IN
1 ENR ENT 39
RA3IN 13 28 RB2IN
11 RA1IN RB1IN 29
RA4IN 14 27 RB3IN
RA5IN 15 26 RB4IN
5kΩ 5kΩ
TA1OUT 16 25 RB5IN
TA4OUT 19 22 TB3OUT
5kΩ 5kΩ
GND 20 21 TB4OUT
9 RA2OUT RB2OUT 31
DIP 13 RA3IN RB3IN 27
5kΩ 5kΩ
8 RA3OUT RB3OUT 32
MAX245 FUNCTIONAL DESCRIPTION
14 RA4IN RB4IN 26
10 RECEIVERS
5 A-SIDE RECEIVERS (RA5 ALWAYS ACTIVE)
5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE) 5kΩ 5kΩ
8 TRANSMITTTERS
7 RA4OUT RB4OUT 33
4 A-SIDE TRANSMITTERS
15 RA5IN RB5IN 25
2 CONTROL PINS
1 RECEIVER ENABLE (ENR)
5kΩ 5kΩ
1 TRANSMITTER ENABLE (ENT)
6 RA5OUT RB5OUT 34
GND
20
30 ______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V
TOP VIEW
1µF
40
VCC
ENA 1 40 VCC +5V +5V
16 TA1OUT TB1OUT 24
TA1IN 2 39 ENB
400kΩ
TA2IN 3 38 TB1IN
2 TA1IN TB1IN 38
TA3IN 4 37 TB2IN +5V +5V
TA4IN 5 36 TB3IN 17 TA2OUT TB2OUT 23
400kΩ
RA5OUT 6 35 TB4IN
3 TA2IN TB2IN 37
RA4OUT 7 MAX246 34 RB5OUT +5V +5V
RA3OUT 8 33 RB4OUT 18 TA3OUT TB3OUT 22
5kΩ 5kΩ
MAX246 FUNCTIONAL DESCRIPTION
10 RECEIVERS 8 RA3OUT RB3OUT 32
5 A-SIDE RECEIVERS (RA5 ALWAYS ACTIVE)
14 RA4IN RB4IN 26
5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE)
8 TRANSMITTERS
5kΩ 5kΩ
4 A-SIDE TRANSMITTERS
4 B-SIDE TRANSMITTERS 7 RA4OUT RB4OUT 33
2 CONTROL PINS 15 RA5IN RB5IN 25
ENABLE A-SIDE (ENA)
ENABLE B-SIDE (ENB) 5kΩ 5kΩ
6 RA5OUT RB5OUT 34
GND
20
______________________________________________________________________________________ 31
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V
TOP VIEW
1µF
40
1 ENTA VCC ENTB 39
ENTA 1 40 VCC +5V +5V
16 TA1OUT TB1OUT 24
TA1IN 2 39 ENTB
400kΩ
TA2IN 3 38 TB1IN 2 TA1IN TB1IN 38
TA3IN 4 37 TB2IN +5V +5V
17 TA2OUT TB2OUT 23
TA4IN 5 36 TB3IN
400kΩ
RB5OUT 6 35 TB4IN 3 TA2IN TB2IN 37
RA4OUT 7 MAX247 34 RB4OUT +5V +5V
18 TA3OUT TB3OUT 22
RA3OUT 8 33 RB3OUT
400kΩ
RA2OUT 9 32 RB2OUT
4 TA3IN TB3IN 36
RA1OUT 10 31 RB1OUT +5V +5V
19 TA4OUT TB4OUT 21
ENRA 11 30 ENRB
400kΩ
RA1IN 12 29 RB1IN
5 TA4IN TB4IN 35
RA2IN 13 28 RB2IN
6 RB5OUT RB5IN 25
RA3IN 14 27 RB3IN
RA4IN 15 26 RB4IN 5kΩ
TA1OUT 16 25 RB5IN
TA3OUT 18 23 TB2OUT
5kΩ 5kΩ
TA4OUT 19 22 TB3OUT
32 ______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
TOP VIEW +5V
1µF
1µF
20
21
C1+ VCC 22
TA4OUT
TA3OUT
TA2OUT
TA1OUT
TB1OUT
TB2OUT
TB3OUT
TA4OUT
1µF V+
23 C1-
RA3IN
RA4IN
RB4IN
+5V TO +10V VOLTAGE DOUBLER 26
24 V-
C2+ 1µF
6 5 4 3 2 1 44 43 42 41 40 1µF 25 C2- +10V TO -10V VOLTAGE INVERTER
18 ENTA ENTB 27
+5V +5V
1 TA1OUT TB1OUT 44
RA2IN 7 39 RB3IN 400kΩ
RA1IN 8 38 RB2IN 14 TA1IN TB1IN 31
ENRA 9 37 RB1IN +5V +5V
RA1OUT 10 36 ENRB 2 TA2OUT TB2OUT 43
RA2OUT 11 35 RB1OUT 400kΩ
RA3OUT 12
MAX248 34 RB2OUT 15 TA2IN TB2IN 30
RA4OUT 13 33 RB3OUT +5V +5V
3 TA3OUT TB3OUT 42
TA1IN 14 32 RB4OUT
TA2IN 15 31 TB1IN 400kΩ
16 TA3IN TB3IN 29
TA3IN 16 30 TB2IN
TA4IN 17 29 TB3IN
+5V +5V
4 TA4OUT TB4OUT 41
400kΩ
18 19 20 21 22 23 24 25 26 27 28
17 TA4IN TB4IN 28
ENTA
GND
C1+
V+
C1-
C2+
C2-
V-
ENTB
TB4IN
VCC
8 RA1IN RB1IN 37
PLCC
5kΩ 5kΩ
5kΩ 5kΩ
13 RA4OUT RB4OUT 32
9 ENRA ENRB 36
GND
19
______________________________________________________________________________________ 33
+5V-Powered, Multichannel RS-232
Drivers/Receivers
MAX220–MAX249
+5V
TOP VIEW 1µF
1µF
20
21
C1+ VCC 22
TA3OUT
TA2OUT
TA1OUT
TB1OUT
TB2OUT
TB3OUT
1µF V+
23 C1-
RA3IN
RA4IN
RA5IN
RB5IN
RB4IN
+5V TO +10V VOLTAGE DOUBLER 26
24 V-
C2+ 1µF
6 5 4 3 2 1 44 43 42 41 40 1µF 25 C2- +10V TO -10V VOLTAGE INVERTER
18 ENTA ENTB 27
+5V +5V
1 TA1OUT TB1OUT 44
RA2IN 7 39 RB3IN 400kΩ
RA1IN 8 38 RB2IN 15 TA1IN TB1IN 30
ENRA 9 37 RB1IN +5V +5V
RA1OUT 10 36 ENRB 2 TA2OUT TB2OUT 43
RA2OUT 11 35 RB1OUT 400kΩ
RA3OUT 12
MAX249 34 RB2OUT 16 TA2IN TB2IN 29
RA4OUT 13 33 RB3OUT +5V +5V
3 TA3OUT TB3OUT 42
RA5OUT 14 32 RB4OUT
TA1IN 15 31 RB5OUT 400kΩ
17 TA3IN TB3IN 28
TA2IN 16 30 TB1IN
8 RA1IN RB1IN 37
TA3IN 17 29 TB2IN
18 19 20 21 22 23 24 25 26 27 28 5kΩ 5kΩ
ENTA
GND
C1+
V+
C1-
C2+
C2-
V-
ENTB
TB3IN
VCC
10 RA1OUT RB1OUT 35
7 RA2IN RB2IN 38
PLCC
5kΩ 5kΩ
11 RA2OUT RB2OUT 34
MAX249 FUNCTIONAL DESCRIPTION
6 RA3IN RB3IN 39
10 RECEIVERS
5 A-SIDE RECEIVERS
5kΩ 5kΩ
5 B-SIDE RECEIVERS
6 TRANSMITTERS 12 RA3OUT RB3OUT 33
3 A-SIDE TRANSMITTERS 5 RA4IN RB4IN 40
3 B-SIDE TRANSMITTERS
4 CONTROL PINS
5kΩ 5kΩ
ENABLE RECEIVER A-SIDE (ENRA)
ENABLE RECEIVER B-SIDE (ENRB) 13 RA4OUT RB4OUT 32
ENABLE RECEIVER A-SIDE (ENTA) 4 RA5IN RB5IN 41
ENABLE RECEIVER B-SIDE (ENTB)
5kΩ 5kΩ
14 RA5OUT RB5OUT 31
9 ENRA ENRB 36
GND
19
34 ______________________________________________________________________________________
+5V-Powered, Multichannel RS-232
Drivers/Receivers
___________________________________________Ordering Information (continued)
MAX220–MAX249
PART TEMP RANGE PIN-PACKAGE PART TEMP RANGE PIN-PACKAGE
MAX222CPN 0°C to +70°C 18 Plastic DIP MAX232AC/D 0°C to +70°C Dice*
MAX222CWN 0°C to +70°C 18 Wide SO MAX232AEPE -40°C to +85°C 16 Plastic DIP
MAX222C/D 0°C to +70°C Dice* MAX232AESE -40°C to +85°C 16 Narrow SO
MAX222EPN -40°C to +85°C 18 Plastic DIP MAX232AEWE -40°C to +85°C 16 Wide SO
MAX222EWN -40°C to +85°C 18 Wide SO MAX232AEJE -40°C to +85°C 16 CERDIP
MAX222EJN -40°C to +85°C 18 CERDIP MAX232AMJE -55°C to +125°C 16 CERDIP
MAX222MJN -55°C to +125°C 18 CERDIP MAX232AMLP -55°C to +125°C 20 LCC
MAX223CAI 0°C to +70°C 28 SSOP MAX233CPP 0°C to +70°C 20 Plastic DIP
MAX223CWI 0°C to +70°C 28 Wide SO MAX233EPP -40°C to +85°C 20 Plastic DIP
MAX223C/D 0°C to +70°C Dice* MAX233ACPP 0°C to +70°C 20 Plastic DIP
MAX223EAI -40°C to +85°C 28 SSOP MAX233ACWP 0°C to +70°C 20 Wide SO
MAX223EWI -40°C to +85°C 28 Wide SO MAX233AEPP -40°C to +85°C 20 Plastic DIP
MAX225CWI 0°C to +70°C 28 Wide SO MAX233AEWP -40°C to +85°C 20 Wide SO
MAX225EWI -40°C to +85°C 28 Wide SO MAX234CPE 0°C to +70°C 16 Plastic DIP
MAX230CPP 0°C to +70°C 20 Plastic DIP MAX234CWE 0°C to +70°C 16 Wide SO
MAX230CWP 0°C to +70°C 20 Wide SO MAX234C/D 0°C to +70°C Dice*
MAX230C/D 0°C to +70°C Dice* MAX234EPE -40°C to +85°C 16 Plastic DIP
MAX230EPP -40°C to +85°C 20 Plastic DIP MAX234EWE -40°C to +85°C 16 Wide SO
MAX230EWP -40°C to +85°C 20 Wide SO MAX234EJE -40°C to +85°C 16 CERDIP
MAX230EJP -40°C to +85°C 20 CERDIP MAX234MJE -55°C to +125°C 16 CERDIP
MAX230MJP -55°C to +125°C 20 CERDIP MAX235CPG 0°C to +70°C 24 Wide Plastic DIP
MAX231CPD 0°C to +70°C 14 Plastic DIP MAX235EPG -40°C to +85°C 24 Wide Plastic DIP
MAX231CWE 0°C to +70°C 16 Wide SO MAX235EDG -40°C to +85°C 24 Ceramic SB
MAX231CJD 0°C to +70°C 14 CERDIP MAX235MDG -55°C to +125°C 24 Ceramic SB
MAX231C/D 0°C to +70°C Dice* MAX236CNG 0°C to +70°C 24 Narrow Plastic DIP
MAX231EPD -40°C to +85°C 14 Plastic DIP MAX236CWG 0°C to +70°C 24 Wide SO
MAX231EWE -40°C to +85°C 16 Wide SO MAX236C/D 0°C to +70°C Dice*
MAX231EJD -40°C to +85°C 14 CERDIP MAX236ENG -40°C to +85°C 24 Narrow Plastic DIP
MAX231MJD -55°C to +125°C 14 CERDIP MAX236EWG -40°C to +85°C 24 Wide SO
MAX232CPE 0°C to +70°C 16 Plastic DIP MAX236ERG -40°C to +85°C 24 Narrow CERDIP
MAX232CSE 0°C to +70°C 16 Narrow SO MAX236MRG -55°C to +125°C 24 Narrow CERDIP
MAX232CWE 0°C to +70°C 16 Wide SO MAX237CNG 0°C to +70°C 24 Narrow Plastic DIP
MAX232C/D 0°C to +70°C Dice* MAX237CWG 0°C to +70°C 24 Wide SO
MAX232EPE -40°C to +85°C 16 Plastic DIP MAX237C/D 0°C to +70°C Dice*
MAX232ESE -40°C to +85°C 16 Narrow SO MAX237ENG -40°C to +85°C 24 Narrow Plastic DIP
MAX232EWE -40°C to +85°C 16 Wide SO MAX237EWG -40°C to +85°C 24 Wide SO
MAX232EJE -40°C to +85°C 16 CERDIP MAX237ERG -40°C to +85°C 24 Narrow CERDIP
MAX232MJE -55°C to +125°C 16 CERDIP MAX237MRG -55°C to +125°C 24 Narrow CERDIP
MAX232MLP -55°C to +125°C 20 LCC MAX238CNG 0°C to +70°C 24 Narrow Plastic DIP
MAX232ACPE 0°C to +70°C 16 Plastic DIP MAX238CWG 0°C to +70°C 24 Wide SO
MAX232ACSE 0°C to +70°C 16 Narrow SO MAX238C/D 0°C to +70°C Dice*
MAX232ACWE 0°C to +70°C 16 Wide SO MAX238ENG -40°C to +85°C 24 Narrow Plastic DIP
* Contact factory for dice specifications.
______________________________________________________________________________________ 35
+5V-Powered, Multichannel RS-232
Drivers/Receivers
___________________________________________Ordering Information (continued)
MAX220–MAX249
Package Information
For the latest package outline information, go to
www.maxim-ic.com/packages.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
36 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
PIC16F87X
28/40-pin 8-Bit CMOS FLASH Microcontrollers
Devices Included in this Data Sheet: Pin Diagram
• PIC16F873 • PIC16F876 PDIP
• PIC16F874 • PIC16F877
MCLR/VPP/THV 1 40 RB7/PGD
Microcontroller Core Features: RA0/AN0 2 39 RB6/PGC
RA1/AN1 3 38 RB5
• High-performance RISC CPU RA2/AN2/VREF- 4 37 RB4
RA3/AN3/VREF+ 5 36 RB3/PGM
• Only 35 single word instructions to learn
RA4/T0CKI 6 35 RB2
• All single cycle instructions except for program RA5/AN4/SS 7 34 RB1
PIC16F877/874
branches which are two cycle RE0/RD/AN5 8 33 RB0/INT
RE1/WR/AN6 9 32 VDD
• Operating speed: DC - 20 MHz clock input
RE2/CS/AN7 10 31 VSS
DC - 200 ns instruction cycle VDD 11 30 RD7/PSP7
• Up to 8K x 14 words of FLASH Program Memory, VSS 12 29 RD6/PSP6
Up to 368 x 8 bytes of Data Memory (RAM) OSC1/CLKIN 13 28 RD5/PSP5
OSC2/CLKOUT 14 27 RD4/PSP4
Up to 256 x 8 bytes of EEPROM data memory
RC0/T1OSO/T1CKI 15 26 RC7/RX/DT
• Pinout compatible to the PIC16C73B/74B/76/77 RC1/T1OSI/CCP2 16 25 RC6/TX/CK
• Interrupt capability (up to 14 sources) RC2/CCP1 17 24 RC5/SDO
RC3/SCK/SCL 18 23 RC4/SDI/SDA
• Eight level deep hardware stack RD0/PSP0 19 22 RD3/PSP3
• Direct, indirect and relative addressing modes RD1/PSP1 20 21 RD2/PSP2
DIP, SOIC
MCLR/VPP/THV 1 28 RB7/PGD
RA0/AN0 2 27 RB6/PGC
RA1/AN1 3 26 RB5
PIC16F876/873
RA2/AN2/VREF- 4 25 RB4
RA3/AN3/VREF+ 5 24 RB3/PGM
RA4/T0CKI 6 23 RB2
RA5/AN4/SS 7 22 RB1
VSS 8 21 RB0/INT
OSC1/CLKIN 9 20 VDD
OSC2/CLKOUT 10 19 VSS
RC0/T1OSO/T1CKI 11 18 RC7/RX/DT
RC1/T1OSI/CCP2 12 17 RC6/TX/CK
RC2/CCP1 13 16 RC5/SDO
RC3/SCK/SCL 14 15 RC4/SDI/SDA
RA3/AN3/VREF+
MCLR/VPP/THV
RA2/AN2/VREF-
RB7/PGD
RB6/PGC
RA1/AN1
RA0/AN0
PLCC
RB5
RB4
NC
NC
6
5
4
3
2
1
44
43
42
41
40
RA4/T0CKI 7 39 RB3/PGM
RA5/AN4/SS 8 38 RB2
RE0/RD/AN5 9 37 RB1
RE1/WR/AN6 10 36 RB0/INT
RE2/CS/AN7 11 PIC16F877 35 VDD
VDD 12 34 VSS
VSS 13
PIC16F874 33 RD7/PSP7
OSC1/CLKIN 14 32 RD6/PSP6
OSC2/CLKOUT 15 31 RD5/PSP5
RC0/T1OSO/T1CK1 16 30 RD4/PSP4
NC 17 9 RC7/RX/DT
18
19
20
21
22
23
24
25
26
27
282
RC1/T1OSI/CCP2
RC3/SCK/SCL
RC4/SDI/SDA
RC6/TX/CK
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RC5/SDO
NC
RC4/SDI/SDA
RC6/TX/CK
RC2/CCP1
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC5/SDO
NC
QFP
44
43
42
41
40
39
38
37
36
35
34
RC7/RX/DT 1 33 NC
RD4/PSP4 2 32 RC0/T1OSO/T1CKI
RD5/PSP5 3 31 OSC2/CLKOUT
RD6/PSP6 4 30 OSC1/CLKIN
RD7/PSP7 5 PIC16F877 29 VSS
VSS 6 28 VDD
VDD 7
PIC16F874 27 RE2/AN7/CS
RB0/INT 8 26 RE1/AN6/WR
RB1 9 25 RE0/AN5/RD
RB2 10 24 RA5/AN4/SS
RB3/PGM 11 23 RA4/T0CKI
12
13
14
15
16
17
18
19
20
21
22
RA3/AN3/VREF+
MCLR/VPP/THV
NC
NC
RB6/PGC
RB7/PGD
RB4
RB5
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
Key Features
PICmicro™ Mid-Range Reference PIC16F873 PIC16F874 PIC16F876 PIC16F877
Manual (DS33023)
Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz DC - 20 MHz
Resets (and Delays) POR, BOR POR, BOR POR, BOR POR, BOR
(PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST)
FLASH Program Memory 4K 4K 8K 8K
(14-bit words)
Data Memory (bytes) 192 192 368 368
EEPROM Data Memory 128 128 256 256
Interrupts 13 14 13 14
I/O Ports Ports A,B,C Ports A,B,C,D,E Ports A,B,C Ports A,B,C,D,E
Timers 3 3 3 3
Capture/Compare/PWM modules 2 2 2 2
Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART
Parallel Communications — PSP — PSP
10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels
Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions
RE0/AN5/RD
RE1/AN6/WR
MCLR VDD, VSS RE2/AN7/CS
access can occur and is detailed in this section. The CALL, RETURN 13
EEPROM data memory block is detailed in RETFIE, RETLW
Section 4.0.
Additional information on device memory may be found Stack Level 1
in the PICmicro Mid-Range Reference Manual,
Stack Level 2
(DS33023).
CALL, RETURN 13
RETFIE, RETLW
1FFFh
Stack Level 1
Stack Level 2
Stack Level 8
17FFh
1800h
Page 3
1FFFh
File
Address
General General
Purpose Purpose accesses accesses
Register Register
20h-7Fh A0h - FFh
96 Bytes 96 Bytes 16Fh 1EFh
170h 1F0h
Note: When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the
TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device.
The PIE1 register contains the individual enable bits for Note: Bit PEIE (INTCON<6>) must be set to
the peripheral interrupts. enable any peripheral interrupt.
Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clear.
The PIR1 register contains the individual flag bits for Note: Interrupt flag bits get set when an interrupt
the peripheral interrupts. condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt bits are clear prior to enabling an
interrupt.
2.3.2 STACK
Data
Memory(1)
Note: When using the SSP module in SPI slave mode and SS enabled, the A/D converter must be set to one of
the following modes where PCFG3:PCFG0 = 0100,0101, 011x, 1101, 1110, 1111.
RB0/INT
RB3/PGM RD TRIS Latch
Schmitt Trigger RD Port
Buffer Q D
Note: When using Low Voltage ICSP Programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the
TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device.
FIGURE 3-5: PORTC BLOCK DIAGRAM Note 1: I/O pins have diode protection to VDD and VSS.
(PERIPHERAL OUTPUT 2: Port/Peripheral select signal selects between port
data and peripheral output.
OVERRIDE) RC<0:2> 3: Peripheral OE (output enable) is only activated if
RC<5:7> peripheral select is active.
PORT/PERIPHERAL Select(2)
Data Latch
D Q I/O
WR pin(1)
TRIS CK Q N
TRIS Latch
VSS
Schmitt
RD TRIS Trigger
Peripheral
OE(3) Q D
EN
RD
PORT
Peripheral Input
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
RD TRIS
Q D
ENEN
RD PORT
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
The write will not initiate if the above sequence is not is set. The WREN bit must be set on a previous instruc-
exactly followed (write 55h to EECON2, write AAh to tion. Both WR and WREN cannot be set with the same
EECON2, then set WR bit) for each byte. It is strongly instruction.
recommended that interrupts be disabled during this At the completion of the write cycle, the WR bit is
code segment. cleared in hardware and the EEPROM Write Complete
Additionally, the WREN bit in EECON1 must be set to Interrupt Flag bit (EEIF) is set. EEIF must be cleared by
enable writes. This mechanism prevents accidental software.
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
4.8.2 PROGRAM FLASH MEMORY The microcontroller can read and execute instructions
out of the internal FLASH program memory, regardless
To protect against spurious writes to FLASH program of the state of the code protect configuration bits. How-
memory, the WRT bit in the configuration word may be ever the WRT configuration bit and the code protect bits
programmed to ‘0’ to prevent writes. The write initiate have different effects on writing to program memory.
sequence must also be followed. WRT and the config- Table 4-1 shows the various configurations and status
uration word cannot be programmed by user code, only of reads and writes. To erase the WRT or code protec-
through the use of an external programmer. tion bits in the configuration word requires that the
device be fully erased.
10Eh EEDATH — — EEPROM data resister high xxxx xxxx uuuu uuuu
8Dh PIE2 — (1) — EEIE BCLIE — — CCP2IE -r-0 0--0 -r-0 0--0
0Dh PIR2 — (1) — EEIF BCLIF — — CCP2IF -r-0 0--0 -r-0 0--0
Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented read as ’0’. Shaded cells are not used during FLASH/
EEPROM access.
Note 1: These bits are reserved; always maintain these bits clear.
8
M 1
0
RA4/T0CKI U M
X SYNC
Pin U 2 TMR0 reg
1 0
X Cycles
T0SE
T0CS
PSA Set Flag Bit T0IF
on Overflow
PRESCALER
0
M 8-bit Prescaler
U
Watchdog 1 X 8
Timer
8 - to - 1MUX PS2:PS0
PSA
0 1
WDT Enable bit
MUX PSA
WDT
Time-out
Note: To avoid an unintended device RESET, the instruction sequence shown in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from
Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1: TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0: TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
T1CKI
(Default high)
T1CKI
(Default low)
6.3 Timer1 Operation in Synchronized If T1SYNC is cleared, then the external clock input is
Counter Mode synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
Counter mode is selected by setting bit TMR1CS. In caler stage is an asynchronous ripple-counter.
this mode, the timer increments on every rising edge of
In this configuration, during SLEEP mode, Timer1 will
clock input on pin RC1/T1OSI/CCP2, when bit
not increment even if the external clock is present,
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
since the synchronization circuit is shut off. The pres-
bit T1OSCEN is cleared.
caler however will continue to increment.
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
2: For the PIC16F873/876, the Schmitt Trigger is not implemented in external clock mode.
0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,
18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
(1)
8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/874; always maintain these bits clear.
0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
(1) 0000 0000 0000 0000
8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/874; always maintain these bits clear.
In Capture mode, CCPR1H:CCPR1L captures the Timer1 must be running in timer mode or synchronized
16-bit value of the TMR1 register when an event occurs counter mode for the CCP module to use the capture
on pin RC2/CCP1. An event is defined as: feature. In asynchronous counter mode, the capture
operation may not work.
• Every falling edge
• Every rising edge 8.1.3 SOFTWARE INTERRUPT
• Every 4th rising edge
When the capture mode is changed, a false capture
• Every 16th rising edge
interrupt may be generated. The user should keep bit
An event is selected by control bits CCP1M3:CCP1M0 CCP1IE (PIE1<2>) clear to avoid false interrupts and
(CCP1CON<3:0>). When a capture is made, the inter- should clear the flag bit CCP1IF following any such
rupt request flag bit CCP1IF (PIR1<2>) is set. The change in operating mode.
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is 8.1.4 CCP PRESCALER
read, the old captured value will be lost.
There are four prescaler settings, specified by bits
8.1.1 CCP PIN CONFIGURATION CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
In Capture mode, the RC2/CCP1 pin should be config- the prescaler counter is cleared. Any reset will clear the
ured as an input by setting the TRISC<2> bit. prescaler counter.
Note: If the RC2/CCP1 pin is configured as an Switching from one capture prescaler to another may
output, a write to the port can cause a cap- generate an interrupt. Also, the prescaler counter will
ture condition. not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recom-
FIGURE 8-1: CAPTURE MODE OPERATION mended method for switching between capture pres-
BLOCK DIAGRAM calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
Set flag bit CCP1IF
Prescaler (PIR1<2>)
÷ 1, 4, 16
EXAMPLE 8-1: CHANGING BETWEEN
RC2/CCP1
CAPTURE PRESCALERS
CCPR1H CCPR1L
Pin CLRF CCP1CON ;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
and Capture
Enable ; the new precscaler
edge detect
; move value and CCP ON
TMR1H TMR1L MOVWF CCP1CON ;Load CCP1CON with this
CCP1CON<3:0> ; value
Q’s
0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on the PIC16F873/876; always maintain these bits clear.
0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
(1)
8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
92h PR2 Timer2 module’s period register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear.
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
SDI (SMP = 0)
bit7 bit0
SDI (SMP = 1)
bit7 bit0
SSPIF
SCK (CKP = 0)
SCK (CKP = 1)
SDI (SMP = 0)
bit7 bit0
SSPIF
SS
SCK (CKP = 0)
SCK (CKP = 1)
SDI (SMP = 0)
bit7 bit0
SSPIF
POR, MCLR,
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BOR WDT
0Bh, 8Bh,
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: These bits are reserved on the 28-pin devices; always maintain these bits clear.
SSPADD reg
9.2.1.3 SLAVE TRANSMISSION An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software
When the R/W bit of the incoming address byte is set and the SSPSTAT register is used to determine the sta-
and an address match occurs, the R/W bit of the tus of the byte transfer. The SSPIF flag bit is set on the
SSPSTAT register is set. The received address is falling edge of the ninth clock pulse.
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCL pin is held low. As a slave-transmitter, the ACK pulse from the master
The transmit data must be loaded into the SSPBUF receiver is latched on the rising edge of the ninth SCL
register, which also loads the SSPSR register. Then the input pulse. If the SDA line is high (not ACK), then the
SCL pin should be enabled by setting bit CKP (SSP- data transfer is complete. When the not ACK is latched
CON<4>). The master must monitor the SCL pin prior by the slave, the slave logic is reset and the slave then
to asserting another clock pulse. The slave devices monitors for another occurrence of the START bit. If the
may be holding off the master by stretching the clock. SDA line was low (ACK), the transmit data must be
The eight data bits are shifted out on the falling edge of loaded into the SSPBUF register, which also loads the
the SCL input. This ensures that the SDA signal is valid SSPSR register. Then the SCL pin should be enabled
during the SCL high time (Figure 9-7). by setting the CKP bit.
SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Data in SCL held low
sampled while CPU
responds to SSPIF
SSPIF
BF (SSPSTAT<0>)
cleared in software From SSP interrupt
SSPBUF is written in software service routine
CKP (SSPCON<4>)
9.2.2 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag is set (eighth
The addressing procedure for the I2C bus is such that bit), and on the falling edge of the ninth bit (ACK bit), the
the first byte after the START condition usually deter- SSPIF flag is set.
mines which device will be the slave addressed by the
master. The exception is the general call address, When the interrupt is serviced, the source for the inter-
which can address all devices. When this address is rupt can be checked by reading the contents of the
used, all devices should, in theory, respond with an SSPBUF to determine if the address was device spe-
acknowledge. cific or a general call address.
The general call address is one of eight addresses In 10-bit mode, the SSPADD is required to be updated
reserved for specific purposes by the I2C protocol. It for the second half of the address to match, and the UA
consists of all 0’s with R/W = 0 bit is set (SSPSTAT<1>). If the general call address is
sampled when GCEN is set while the slave is config-
The general call address is recognized when the Gen- ured in 10-bit address mode, then the second half of
eral Call Enable bit (GCEN) is enabled (SSPCON2<7> the address is not necessary, the UA bit will not be set,
is set). Following a start-bit detect, 8-bits are shifted and the slave will begin receiving data after the
into SSPSR and the address is compared against acknowledge (Figure 9-8).
SSPADD. It is also compared to the general call
address and fixed in hardware.
FIGURE 9-8: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE)
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPIF
BF
(SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV '0'
(SSPCON<6>)
GCEN '1'
(SSPCON2<7>)
While in sleep mode, the I2C module can receive A reset disables the SSP module and terminates the
addresses or data. When an address match or com- current transfer.
plete byte transfer occurs, wake the processor from
sleep (if the SSP interrupt is enabled).
TABLE 9-3 REGISTERS ASSOCIATED WITH I2C OPERATION
POR, MCLR,
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BOR WDT
0Bh, 8Bh,
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Dh PIR2 — (2) — EEIF BCLIF — — CCP2IF -r-0 0--0 -r-0 0--0
8Dh PIE2 — (2) — EEIE BCLIE — — CCP2IE -r-0 0--0 -r-0 0--0
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in I2C mode.
Note 1: These bits are reserved on the 28-pin devices; always maintain these bits clear.
2: These bits are reserved on these devices; always maintain these bits clear.
Internal SSPM3:SSPM0,
Data Bus SSPADD<6:0>
Read Write
SSPBUF Baud
Rate
Generator
SDA Shift
clock cntl
Acknowledge
Generate
SCL
In multi-master mode, the interrupt generation on the The master device generates all of the serial clock
detection of the START and STOP conditions allows pulses and the START and STOP conditions. A trans-
the determination of when the bus is free. The STOP fer is ended with a STOP condition or with a Repeated
(P) and START (S) bits are cleared from a reset or Start condition. Since the Repeated Start condition is
when the MSSP module is disabled. Control of the I 2C also the beginning of the next serial transfer, the I2C
bus may be taken when bit P (SSPSTAT<4>) is set, or bus will not be released.
the bus is idle with both the S and P bits clear. When In Master Transmitter mode serial data is output
the bus is busy, enabling the SSP Interrupt will gener- through SDA, while SCL outputs the serial clock. The
ate the interrupt when the STOP condition occurs. first byte transmitted contains the slave address of the
In multi-master operation, the SDA line must be moni- receiving device (7 bits) and the Read/Write (R/W) bit.
tored for abitration to see if the signal level is the In this case, the R/W bit will be logic '0'. Serial data is
expected output level. This check is performed in hard- transmitted 8 bits at a time. After each byte is transmit-
ware, with the result placed in the BCLIF bit. ted, an acknowledge bit is received. START and STOP
The states where arbitration can be lost are: conditions are output to indicate the beginning and the
end of a serial transfer.
• Address Transfer
• Data Transfer In Master receive mode, the first byte transmitted con-
• A Start Condition tains the slave address of the transmitting device
• A Repeated Start Condition (7 bits) and the R/W bit. In this case, the R/W bit will be
• An Acknowledge Condition logic '1'. Thus the first byte transmitted is a 7-bit slave
address followed by a '1' to indicate receive bit. Serial
9.2.7 I2C MASTER MODE SUPPORT data is received via SDA, while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
Master Mode is enabled by setting and clearing the byte is received, an acknowledge bit is transmitted.
appropriate SSPM bits in SSPCON and by setting the START and STOP conditions indicate the beginning
SSPEN bit. Once master mode is enabled, the user and end of transmission.
has six options.
The baud rate generator used for SPI mode operation
- Assert a start condition on SDA and SCL. is now used to set the SCL clock frequency for either
- Assert a Repeated Start condition on SDA and 100 kHz, 400 kHz or 1 MHz I2C operation. The baud
SCL. rate generator reload value is contained in the lower 7
- Write to the SSPBUF register initiating trans- bits of the SSPADD register. The baud rate generator
mission of data/address. will automatically begin counting on a write to the SSP-
- Generate a stop condition on SDA and SCL. BUF. Once the given operation is complete (i.e. trans-
- Configure the I2C port to receive data. mission of the last data bit is followed by ACK) the
- Generate an Acknowledge condition at the end internal clock will automatically stop counting and the
of a received byte of data. SCL pin will remain in its last state
A typical transmit sequence would go as follows:
2
Note: The MSSP Module, when configured in I C a) The user generates a Start Condition by setting
Master Mode, does not allow queueing of the START enable bit (SEN) in SSPCON2.
events. For instance, the user is not b) SSPIF is set. The module will wait the required
allowed to initiate a start condition and start time before any other operation takes
immediately write the SSPBUF register to place.
initiate transmission before the START c) The user loads the SSPBUF with address to
condition is complete. In this case, the transmit.
SSPBUF will not be written to and the
d) Address is shifted out the SDA pin until all 8 bits
WCOL bit will be set, indicating that a write
are transmitted.
to the SSPBUF did not occur.
e) The MSSP Module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register ( SSPCON2<6>).
f) The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
g) The user loads the SSPBUF with eight bits of
data.
h) DATA is shifted out the SDA pin until all 8 bits
are transmitted.
SDA DX DX-1
BRG decrements
(on Q2 and Q4 cycles)
BRG
03h 02h 01h 00h (hold off) 03h 02h
value
SCL
TBRG
S
1st Bit
SDA
Falling edge of ninth clock Write to SSPBUF occurs here.
End of Xmit
TBRG
SCL TBRG
Sr = Repeated Start
Transmission of a data byte, a 7-bit address or either In transmit mode, the ACKSTAT bit (SSPCON2<6>) is
half of a 10-bit address is accomplished by simply writ- cleared when the slave has sent an acknowledge
ing a value to SSPBUF register. This action will set the (ACK = 0), and is set when the slave does not acknowl-
buffer full flag (BF) and allow the baud rate generator to edge (ACK = 1). A slave sends an acknowledge when
begin counting and start the next transmission. Each it has recognized its address (including a general call),
bit of address/data will be shifted out onto the SDA pin or when the slave has properly received its data.
after the falling edge of SCL is asserted (see data hold
time spec). SCL is held low for one baud rate gener-
ator rollover count (TBRG). Data should be valid before
SCL is released high (see data setup time spec).
When the SCL pin is released high, it is held that way
for TBRG. The data on the SDA pin must remain stable
for that duration and some hold time after the next fall-
ing edge of SCL. After the eighth bit is shifted out (the
falling edge of the eighth clock), the BF flag is cleared
and the master releases SDA allowing the slave device
being addressed to respond with an ACK bit during the
ninth bit time, if an address match occurs or if data was
received properly. The status of ACK is read into the
ACKDT on the falling edge of the ninth clock. If the
master receives an acknowledge, the acknowledge
status bit (ACKSTAT) is cleared. If not, the bit is set.
After the ninth clock, the SSPIF is set and the master
clock (baud rate generator) is suspended until the next
data byte is loaded into the SSPBUF, leaving SCL low
and SDA unchanged (Figure 9-14).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock, the master will de-assert
the SDA pin allowing the slave to respond with an
acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared, and the baud rate generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0 of 10-bit address ACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
BF (SSPSTAT<0>)
PEN
R/W
FIGURE 9-14: I 2C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS)
Bus Master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPIF at end
of receive Set SSPIF interrupt
Set SSPIF interrupt at end of acknow-
Set SSPIF interrupt ledge sequence
at end of receive
at end of acknowledge
SSPIF sequence
Set P bit
Cleared in software Cleared in software Cleared in software Cleared in software (SSPSTAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSPIF
responds to SSPIF
BF
(SSPSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPOV
FIGURE 9-15: I 2C MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS)
ACKEN
TBRG TBRG
SDA D0 ACK
SCL 8 9
SSPIF
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
Clock arbitration occurs when the master, during any While in sleep mode, the I2C module can receive
receive, transmit, or repeated start/stop condition, addresses or data, and when an address match or
deasserts the SCL pin (SCL allowed to float high). complete byte transfer occurs, wake the processor from
When the SCL pin is allowed to float high, the baud rate sleep (if the SSP interrupt is enabled).
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is 9.2.17 EFFECTS OF A RESET
sampled high, the baud rate generator is reloaded with
A reset disables the SSP module and terminates the
the contents of SSPADD<6:0> and begins counting.
current transfer.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device (Figure 9-18).
SCL
SDA
SDA
SCL
Set bus collision
interrupt.
BCLIF
SDA
SCL
Set SEN, enable start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL=1 SSP module reset into idle state.
SEN
SDA sampled low before
START condition. Set BCLIF.
S bit and SSPIF set because
BCLIF SDA = 0, SCL = 1
SSPIF and BCLIF are
cleared in software.
SSPIF
SDA = 0, SCL = 1
TBRG TBRG
SDA
FIGURE 9-22: BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPIF
Less than TBRG TBRG
SDA SDA pulled low by other master.
Reset BRG and assert SDA
SCL s
SCL pulled low after BRG
Timeout
SEN
Set SEN, enable start
sequence if SDA = 1, SCL = 1
BCLIF '0'
SSPIF
SDA = 0, SCL = 1 Interrupts cleared
Set SSPIF in software.
SDA
SCL
RSEN
BCLIF
Cleared in software
S '0' '0'
TBRG TBRG
SDA
SCL
S '0' '0'
PEN
BCLIF
P '0' '0'
SDA
PEN
BCLIF
P '0'
SSPIF '0'
DEVICE
Rp Rp
Rs Rs
SDA
SCL
Cb=10 - 400 pF
Note: I2C devices with input levels related to VDD must have one common supply
line to which the pull-up resistor is also connected.
The Universal Synchronous Asynchronous Receiver Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to
be set in order to configure pins RC6/TX/CK and
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com- RC7/RX/DT as the Universal Synchronous Asynchro-
nous Receiver Transmitter.
munications Interface or SCI). The USART can be con-
figured as a full duplex asynchronous system that can The USART module also has a multi-processor com-
communicate with peripheral devices such as CRT ter- munication capability using 9-bit address detection.
minals and personal computers, or it can be configured
as a half duplex synchronous system that can commu-
nicate with peripheral devices such as A/D or D/A inte-
grated circuits, serial EEPROMs etc.
REGISTER 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
Write to TXREG
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit
Word 1
TXIF bit
(Transmit buffer
reg. empty flag)
Write to TXREG
Word 1 Word 2
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit Start Bit Bit 0
TXIF bit
(interrupt reg. flag) Word 1 Word 2
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear.
RC7/RX/DT
Pin Buffer Data
and Control Recovery RX9
Interrupt RCIF
Data Bus
RCIE
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
SPBRG
÷ 64 MSb RSR register LSb
or
÷ 16
Baud Rate Generator Stop (8) 7 • • • 1 0 Start
RC7/RX/DT
Pin Buffer Data
and Control Recovery RX9
SPEN
RX9 Enable
ADDEN Load of
RX9 Receive
Buffer
ADDEN
RSR<8> 8
Interrupt RCIF
Data Bus
RCIE
Load RSR
Bit8 = 0, Data Byte Bit8 = 1, Address Byte WORD 1
RCREG
Read
RCIF
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(receive buffer) because ADDEN = 1.
Load RSR
Bit8 = 1, Address Byte Bit8 = 0, Data Byte WORD 1
RCREG
Read
RCIF
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(receive buffer) because ADDEN was not updated and still = 0.
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Write to
TXREG reg
Write word1 Write word2
TXIF bit
(Interrupt flag)
TRMT
TRMT bit
’1’ ’1’
TXEN bit
Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'.
PCFG3: AN7(1) AN6(1) AN5(1) AN4 AN3 AN2 AN1 AN0 CHAN /
VREF+ VREF-
PCFG0 RE2 RE1 RE0 RA5 RA3 RA2 RA1 RA0 Refs(2)
0000 A A A A A A A A VDD VSS 8/0
0001 A A A A VREF+ A A A RA3 VSS 7/1
0010 D D D A A A A A VDD VSS 5/0
0011 D D D A VREF+ A A A RA3 VSS 4/1
0100 D D D D A D A A VDD VSS 3/0
0101 D D D D VREF+ D A A RA3 VSS 2/1
011x D D D D D D D D VDD VSS 0/0
1000 A A A A VREF+ VREF- A A RA3 RA2 6/2
1001 D D A A A A A A VDD VSS 6/0
1010 D D A A VREF+ A A A RA3 VSS 5/1
1011 D D A A VREF+ VREF- A A RA3 RA2 4/2
1100 D D D A VREF+ VREF- A A RA3 RA2 3/2
1101 D D D D VREF+ VREF- A A RA3 RA2 2/2
1110 D D D D D D D A VDD VSS 1/0
1111 D D D D VREF+ VREF- D A RA3 RA2 1/2
A = Analog input
D = Digital I/O
Note 1: These channels are not available on the 28-pin devices.
2: This column indicates the number of analog channels available as A/D inputs and the numer of analog channels
used as voltage reference inputs.
111
RE2/AN7(1)
110
RE1/AN6(1)
101
RE0/AN5(1)
100
RA5/AN4
VAIN
(Input voltage) 011
RA3/AN3/VREF+
010
A/D RA2/AN2/VREF-
Converter
001
RA1/AN1
VDD 000
RA0/AN0
VREF+
(Reference
voltage)
PCFG3:PCFG0
VREF-
(Reference
voltage)
VSS
PCFG3:PCFG0
Note 1: Not available on 28-pin devices.
= TAMP + TC + TCOFF
= 2µS + TC + [(Temperature -25°C)(0.05µS/°C)]
TC = CHOLD (RIC + RSS + RS) In(1/2047)
= - 120pF (1kΩ + 7kΩ + 10kΩ) In(0.0004885)
= 16.47µS
TACQ = 2µS + 16.47µS + [(50°C -25×C)(0.05µS/×C)
= 19.72µS
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leak-
age specification.
4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
VDD
Sampling
Switch
VT = 0.6V
RS ANx RIC ≤ 1k SS RSS
CHOLD
VA CPIN I LEAKAGE = DAC capacitance
5 pF VT = 0.6V ± 500 nA = 120 pF
VSS
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion Starts
Set GO bit
ADRES is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is connected to analog input.
10-Bit Result
ADFM = 1 ADFM = 0
7 2107 0 7 0765 0
0000 00 0000 00
8Ch PIE1 (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PSPIE
1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
89h(1) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
CP1 CP0 DEBUG — WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0 Register: CONFIG
Address 2007h
bit13 bit0
bit 13-12:
bit 5-4: CP1:CP0: Flash Program Memory Code Protection bits (2)
11 = Code protection off
10 = 1F00h to 1FFFh code protected (PIC16F877, 876)
10 = 0F00h to 0FFFh code protected (PIC16F874, 873)
01 = 1000h to 1FFFh code protected (PIC16F877, 876)
01 = 0800h to 0FFFh code protected (PIC16F874, 873)
00 = 0000h to 1FFFh code protected (PIC16F877, 876)
00 = 0000h to 0FFFh code protected (PIC16F874, 873)
bit 11: DEBUG: In-Circuit Debugger Mode
1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins.
0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger.
bit 10: Unimplemented: Read as ‘1’
bit 9: WRT: Flash Program Memory Write Enable
1 = Unprotected program memory may be written to by EECON control
0 = Unprotected program memory may not be written to by EECON control
bit 8: CPD: Data EE Memory Code Protection
1 = Code protection off
0 = Data EEPROM memory code protected
bit 7: LVP: Low Voltage In-Circuit Serial Programming Enable bit
1 = RB3/PGM pin has PGM function, low voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6: BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3: PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE. Ensure the
Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
The PIC16F87X can be operated in four different oscil- Mode Freq OSC1 OSC2
lator modes. The user can program two configuration XT 455 kHz 68 - 100 pF 68 - 100 pF
bits (FOSC1 and FOSC0) to select one of these four 2.0 MHz 15 - 68 pF 15 - 68 pF
modes: 4.0 MHz 15 - 68 pF 15 - 68 pF
• LP Low Power Crystal HS 8.0 MHz 10 - 68 pF 10 - 68 pF
• XT Crystal/Resonator 16.0 MHz 10 - 22 pF 10 - 22 pF
• HS High Speed Crystal/Resonator These values are for design guidance only. See
• RC Resistor/Capacitor notes at bottom of page.
Resonators Used:
12.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS 455 kHz Panasonic EFO-A455K04B ± 0.3%
2.0 MHz Murata Erie CSA2.00MG ± 0.5%
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT 4.0 MHz Murata Erie CSA4.00MG ± 0.5%
pins to establish oscillation (Figure 12-1). The 8.0 MHz Murata Erie CSA8.00MT ± 0.5%
PIC16F87X oscillator design requires the use of a par- 16.0 MHz Murata Erie CSA16.00MX ± 0.5%
allel cut crystal. Use of a series cut crystal may give a All resonators used did not have built-in capacitors.
frequency out of the crystal manufacturers specifica-
tions. When in XT, LP or HS modes, the device can
have an external clock source to drive the OSC1/
CLKIN pin (Figure 12-2).
MCLR
SLEEP
WDT WDT
Module Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset S
BODEN
OST/PWRT
OST
Chip_Reset
10-bit Ripple counter R Q
OSC1
(1) PWRT
On-chip
RC OSC 10-bit Ripple counter
Enable PWRT
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
EEIF
EEIE
PSPIF
PSPIE
ADIF Wake-up (If in SLEEP mode)
T0IF
ADIE T0IE
RCIF INTF
RCIE INTE
Interrupt to CPU
TXIF RBIF
TXIE RBIE
SSPIF
SSPIE
PEIE
CCP1IF
CCP1IE GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
BCLIF
BCLIE
0
M Postscaler
1 U
WDT Timer
X 8
8 - to - 1 MUX PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 5-1)
0 1
MUX PSA
WDT
Note: PSA and PS2:PS0 are bits in the OPTION_REG register. Time-out
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of these bits.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4) TOST(2)
INT pin
INTF flag
(INTCON<1>) Interrupt Latency
(Note 2)
GIE bit Processor in
(INTCON<7>)
SLEEP
INSTRUCTION FLOW
PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h
Instruction Inst(0004h)
fetched Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0005h)
Instruction SLEEP Inst(PC + 1) Dummy cycle Dummy cycle
executed Inst(PC - 1) Inst(0004h)
The instruction set is highly orthogonal and is grouped k = 11-bit immediate value
into three basic categories:
• Byte-oriented operations A description of each instruction is available in the
• Bit-oriented operations PICmicro™ Mid-Range Reference Manual,
(DS33023).
• Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU Family
Reference Manual (DS33023).
CLRW Clear W
Syntax: [ label ] CLRW
BTFSC Bit Test, Skip if Clear
Operands: None
Syntax: [label] BTFSC f,b
Operation: 00h → (W)
Operands: 0 ≤ f ≤ 127 1→Z
0≤b≤7
Status Affected: Z
Operation: skip if (f<b>) = 0
Description: W register is cleared. Zero bit (Z)
Status Affected: None is set.
Description: If bit ’b’ in register ’f’ is ’1’, the next
instruction is executed.
If bit ’b’, in register ’f’, is ’0’, the
next instruction is discarded, and
a NOP is executed instead, making
this a 2TCY instruction.
DECF Decrement f
Syntax: [label] DECF f,d INCF Increment f
Operands: 0 ≤ f ≤ 127 Syntax: [ label ] INCF f,d
d ∈ [0,1] Operands: 0 ≤ f ≤ 127
Operation: (f) - 1 → (destination) d ∈ [0,1]
Status Affected: Z Operation: (f) + 1 → (destination)
Description: Decrement register ’f’. If ’d’ is 0, Status Affected: Z
the result is stored in the W regis- Description: The contents of register ’f’ are
ter. If ’d’ is 1, the result is stored incremented. If ’d’ is 0, the result
back in register ’f’. is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
MOVWF Move W to f
IORWF Inclusive OR W with f Syntax: [ label ] MOVWF f
Syntax: [ label ] IORWF f,d Operands: 0 ≤ f ≤ 127
Operands: 0 ≤ f ≤ 127 Operation: (W) → (f)
d ∈ [0,1]
Status Affected: None
Operation: (W) .OR. (f) → (destination)
Description: Move data from W register to reg-
Status Affected: Z ister 'f'.
Description: Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is
placed in the W register. If 'd' is 1
the result is placed back in regis-
ter 'f'.
NOP No Operation
Syntax: [ label ] NOP
MOVF Move f Operands: None
Syntax: [ label ] MOVF f,d Operation: No operation
Operands: 0 ≤ f ≤ 127 Status Affected: None
d ∈ [0,1]
Description: No operation.
Operation: (f) → (destination)
Status Affected: Z
Description: The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0, des-
tination is W register. If d = 1, the
destination is file register f itself. d
= 1 is useful to test a file register
since status flag Z is affected.
Description: Subtract (2’s complement method) Description: Exclusive OR the contents of the
W register from register 'f'. If 'd' is 0, W register with register 'f'. If 'd' is
the result is stored in the W regis- 0, the result is stored in the W
ter. If 'd' is 1, the result is stored register. If 'd' is 1, the result is
back in register 'f'. stored back in register 'f'.
14.5 MPLAB-SIM Software Simulator ICEPIC is a low-cost in-circuit emulation solution for the
Microchip Technology PIC16C5X, PIC16C6X,
The MPLAB-SIM Software Simulator allows code PIC16C7X, and PIC16CXXX families of 8-bit one-time-
development in a PC host environment by simulating programmable (OTP) microcontrollers. The modular
the PICmicro series microcontrollers on an instruction system can support different subsets of PIC16C5X or
level. On any given instruction, the data areas can be PIC16CXXX products through the use of
examined or modified and stimuli can be applied from interchangeable personality modules or daughter
a file or user-defined key press to any of the pins. The boards. The emulator is capable of emulating without
execution can be performed in single step, execute until target application circuitry being present.
break, or trace mode.
14.9 MPLAB-ICD In-Circuit Debugger
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft- Microchip’s In-Circuit Debugger, MPLAB-ICD, is a pow-
ware Simulator offers the flexibility to develop and erful, low-cost run-time development tool. This tool is
debug code outside of the laboratory environment mak- based on the flash PIC16F877 and can be used to
ing it an excellent multi-project software development develop for this and other PICmicro microcontrollers
tool. from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
14.6 MPLAB-ICE High Performance
PIC16F87X. This feature, along with Microchip’s In-Cir-
Universal In-Circuit Emulator with cuit Serial Programming protocol, offers cost-effective
MPLAB IDE in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
The MPLAB-ICE Universal In-Circuit Emulator is
Development Environment. This enables a designer to
intended to provide the product development engineer
develop and debug source code by watching variables,
with a complete microcontroller design tool set for
single-stepping and setting break points. Running at
PICmicro microcontrollers (MCUs). Software control of
full speed enables testing hardware in real-time. The
MPLAB-ICE is provided by the MPLAB Integrated
MPLAB-ICD is also a programmer for the flash
Development Environment (IDE), which allows editing,
PIC16F87X family.
“make” and download, and source debugging from a
single environment.
24CXX/
25CXX/
TABLE 14-1:
HCSXXX
PIC14000
MCP2510
PIC16C5X
PIC16C6X
PIC16C7X
PIC16C8X
PIC17C4X
MCRFXXX
PIC16F62X
PIC16F8XX
PIC16C7XX
PIC16C9XX
PIC17C7XX
PIC18CXX2
PIC12CXXX
PIC16CXXX
MPLAB Integrated
Development Environment
á
á
á
á
á
á
á
á
á
á
á
á
MPLAB C17 Compiler
á á
á á
MPLAB C18 Compiler
Software Tools
MPASM/MPLINK
MPLAB-ICE **
á á
á á
á á á
PICMASTER/PICMASTER-CE
á á á
á á á
ICEPIC Low-Cost á á á
Emulators
In-Circuit Emulator
á á á á
á á á á
á á á á
á á á á
á á á á
á á á á
á á á á
á á á á
MPLAB-ICD In-Circuit
* *
Debugger
á
á
á
PICSTARTPlus
Low-Cost Universal Dev. Kit **
á
á
á
á
á
á
á
á
á
á
á
á
á
á
PRO MATE II
Universal Programmer **
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
Programmers Debugger
SIMICE
á
†
DEVELOPMENT TOOLS FROM MICROCHIP
PICDEM-1
á á
á
á
á
PICDEM-2 † †
á
á á
á
PICDEM-3
á
PICDEM-14A
á
PICDEM-17
á
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB-ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77
** Contact Microchip Technology Inc. for availability date.
†
Development tool is available on select devices.
PIC16F87X
DS30292B-page 149
PIC16F87X
NOTES:
6.0 V
5.5 V
5.0 V
4.5 V
Voltage
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
16 MHz 20 MHz
Frequency
6.0 V
5.5 V
5.0 V
4.5 V
Voltage
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz 10 MHz
Frequency
FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0 V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
Note 2: FMAX has a maximum frequency of 10MHz.
6.0 V
5.5 V
5.0 V
PIC16CXXX-04
4.5 V
Voltage
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz
Frequency
D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range
D042 MCLR 0.8VDD - VDD V
D042A OSC1 (XT, HS and LP) 0.7VDD - VDD V Note1
D043 OSC1 (in RC mode) 0.9VDD - VDD V
Ports RC3 and RC4
D044 with Schmitt Trigger buffer 0.7VDD - VDD V For entire VDD range
D044A with SMBus 1.4 - 5.5 V for VDD = 4.5 to 5.5V
D070 PORTB weak pull-up current IPURB 50 250 400 µA VDD = 5V, VPIN = VSS
Input Leakage Current
(Notes 2, 3)
D060 I/O ports IIL - - ±1 µA Vss ≤ VPIN ≤ VDD, Pin at hi-imped-
ance
D061 MCLR, RA4/T0CKI - - ±5 µA Vss ≤ VPIN ≤ VDD
D063 OSC1 - - ±5 µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
Output Low Voltage
D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F87X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
VDD/2
RL
CL CL
Pin Pin
VSS VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on the 28-pin devices.
OSC1
1 3 3 4 4
2
CLKOUT
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 12
19 18
14 16
I/O Pin
(input)
17 15
20, 21
Note: Refer to Figure 15-4 for load conditions.
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
VDD VBOR
35
TABLE 15-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.
30 TmcL MCLR Pulse Width (low) 2 — — µs VDD = 5V, -40°C to +85°C
31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40°C to +85°C
(No Prescaler)
32 Tost Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period
33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C
34 TIOZ I/O Hi-impedance from MCLR Low — — 2.1 µs
or Watchdog Timer Reset
35 TBOR Brown-out Reset pulse width 100 — — µs VDD ≤ VBOR (D005)
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
RA4/T0CKI
40 41
42
RC0/T1OSO/T1CKI
45 46
47 48
TMR0 or
TMR1
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50 51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
53 54
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 15-4 for load conditions.
SS
70
SCK
(CKP = 0)
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76
SS
81
SCK
(CKP = 0)
71 72
79
73
SCK
(CKP = 1)
80
78
75, 76
74
Note: Refer to Figure 15-4 for load conditions.
SS
70
SCK
(CKP = 0) 83
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76 77
74
73
Note: Refer to Figure 15-4 for load conditions.
82
SS
70
SCK 83
(CKP = 0)
71 72
SCK
(CKP = 1)
80
75, 76 77
SDI
MSb IN BIT6 - - - -1 LSb IN
74
Note: Refer to Figure 15-4 for load conditions.
SCL
91 93
90 92
SDA
START STOP
Condition Condition
SDA
Out
Note: Refer to Figure 15-4 for load conditions.
RC6/TX/CK
Pin 121
121
RC7/RX/DT
Pin
120
122
Note: Refer to Figure 15-4 for load conditions.
RC6/TX/CK
pin 125
RC7/RX/DT
pin
126
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
XXXXXXXXXXXXXXXXXXXXXXXXX PIC16F876-04/SO
XXXXXXXXXXXXXXXXXXXXXXXXX
AABBCDE 9910SAA
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
XXXXXXXXXX PIC16F877
XXXXXXXXXX -04/PT
XXXXXXXXXX
AABBCDE 9911HAT
XXXXXXXXXX PIC16F877
XXXXXXXXXX -20/PQ
XXXXXXXXXX
AABBCDE 9904SAT
XXXXXXXXXX PIC16F877
XXXXXXXXXX -20/L
XXXXXXXXXX
AABBCDE 9903SAT
2
α
n 1
E1 A1
R L
c
β A2 B1
eB B p
E1
E
p
B
2
n 1
X
α
45 ° L
R2
c
A
A1
R1 φ
β L1 A2
2 α
n 1
E1 A1
A
R L
c
β B1
A2
eB B p
D D1
2
1
B
n
X x 45°
α
L A
R2
c
R1 φ A1
β L1 A2
D D1
2
1
B
n
X x 45°
α
L
R2
c A
R1
β φ A1
L1 A2
E1
E
# leads = n1
D D1
n12 α
CH2 x 45° CH1 x 45° A3
R1 L
35° A
A1
B1
c R2
B
β A2
p
E2 D2
Units INCHES* MILLIMETERS
Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 44 44
Pitch p 0.050 1.27
Overall Pack. Height A 0.165 0.173 0.180 4.19 4.38 4.57
Shoulder Height A1 0.095 0.103 0.110 2.41 2.60 2.79
Standoff A2 0.015 0.023 0.030 0.38 0.57 0.76
Side 1 Chamfer Dim. A3 0.024 0.029 0.034 0.61 0.74 0.86
Corner Chamfer (1) CH1 0.040 0.045 0.050 1.02 1.14 1.27
Corner Chamfer (other) CH2 0.000 0.005 0.010 0.00 0.13 0.25
Overall Pack. Width E1 0.685 0.690 0.695 17.40 17.53 17.65
Overall Pack. Length D1 0.685 0.690 0.695 17.40 17.53 17.65
Molded Pack. Width E‡ 0.650 0.653 0.656 16.51 16.59 16.66
Molded Pack. Length D‡ 0.650 0.653 0.656 16.51 16.59 16.66
Footprint Width E2 0.610 0.620 0.630 15.49 15.75 16.00
Footprint Length D2 0.610 0.620 0.630 15.49 15.75 16.00
Pins along Width n1 11 11
Lead Thickness c 0.008 0.010 0.012 0.20 0.25 0.30
Upper Lead Width B1† 0.026 0.029 0.032 0.66 0.74 0.81
Lower Lead Width B 0.015 0.018 0.021 0.38 0.46 0.53
Upper Lead Length L 0.050 0.058 0.065 1.27 1.46 1.65
Shoulder Inside Radius R1 0.003 0.005 0.010 0.08 0.13 0.25
J-Bend Inside Radius R2 0.015 0.025 0.035 0.38 0.64 0.89
Mold Draft Angle Top α 0 5 10 0 5 10
Mold Draft Angle Bottom β 0 5 10 0 5 10
* Controlling Parameter.
† Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent:MO-047 AC
Packages 28-pin PDIP, 28-pin windowed CERDIP, 40-pin PDIP, 44-pin TQFP,
28-pin SOIC 44-pin MQFP, 44-pin PLCC
Timers 3 3
Interrupts 11 or 12 13 or 14
Communication PSP, USART, SSP (SPI, I2C Slave) PSP, USART, SSP (SPI, I2C Master/Slave)
CCP 2 2
U
UA ...................................................................................... 64
Universal Synchronous Asynchronous Receiver
Transmitter (USART)
Asynchronous Receiver
Setting Up Reception ....................................... 103
Timing Diagram ................................................ 104
Update Address, UA .......................................................... 64
USART ............................................................................... 95
Asynchronous Mode .................................................. 99
Receive Block Diagram .................................... 103
Asynchronous Receiver ........................................... 101
Asynchronous Reception ......................................... 102
Asynchronous Transmitter ......................................... 99
Baud Rate Generator (BRG) ...................................... 97
Baud Rate Formula ............................................ 97
Baud Rates, Asynchronous Mode (BRGH=0) ... 98
High Baud Rate Select (BRGH Bit) .................... 95
Sampling ............................................................ 97
Clock Source Select (CSRC Bit) ................................ 95
Continuous Receive Enable (CREN Bit) .................... 96
Framing Error (FERR Bit) .......................................... 96
Mode Select (SYNC Bit) ............................................ 95
Overrun Error (OERR Bit) .......................................... 96
RC6/TX/CK Pin ........................................................ 7, 8
RC7/RX/DT Pin ........................................................ 7, 8
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N
Questions:
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
8. How would you improve our software, systems, and silicon products?
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type (including LC devices).
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99 Printed on recycled paper.
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by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
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1OUT
4OUT
1IN –
4IN –
A Versions . . . 15 nA Typ
NC
D Differential Input Voltage Range Equal to
Maximum-Rated Supply Voltage . . . 32 V
3 2 1 20 19
(26 V for LM2902 and LM2902Q) 1IN+ 4 18 4IN+
D Open-Loop Differential Voltage NC 5 17 NC
Amplification . . . 100 V/mV Typ VCC 6 16 GND
D Internal Frequency Compensation
NC 7 15 NC
3IN+
2IN+ 8 14
9 10 11 12 13
description
2IN –
3IN –
2OUT
NC
3OUT
These devices consist of four independent
high-gain frequency-compensated operational
amplifiers that are designed specifically to operate NC – No internal connection
from a single supply over a wide range of voltages.
Operation from split supplies is also possible symbol (each amplifier)
when the difference between the two supplies is
3 V to 30 V (for the LM2902 and LM2902Q, 3 V to
26 V) and VCC is at least 1.5 V more positive than IN –
–
PRODUCTION DATA information is current as of publication date. Copyright 1997, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
AVAILABLE OPTIONS
PACKAGED DEVICES
VERY CHIP
VIOmax SMALL CHIP CERAMIC PLASTIC FLAT
TA SMALL TSSOP FORM
AT 25°C OUTLINE CARRIER DIP DIP PACK
OUTLINE (PW)‡ (Y)
(D)† (FK) (J) (N) (W)
(DB)‡
0°C to 7 mV LM324D LM324DBLE — — LM324N LM324PWLE —
LM324Y
70°C 3 mV LM324AD — — — LM324AN LM324APWLE —
–25°C to 5 mV LM224D — — — LM224N — —
—
85°C 3 mV LM224AD — — — LM224AN — —
– 40°C to LM2902D — — LM2902N —
7 mV LM2902DBLE LM2902PWLE —
125°C LM2902QD — — LM2902QN —
– 55°C to 5 mV — — LM124FK LM124J — — LM124W
—
125°C 2 mV — — LM124AFK LM124AJ — —
† The D package is available taped and reeled. Add the suffix R to the device type (e.g., LM324DR).
‡ The DB and PW packages are only available left-end taped and reeled.
OUT
IN –
IN + ≈ 50-µA
Current
Regulator
GND
To Other
Amplifiers
COMPONENT COUNT
(total device)
Epi-FET 1
Transistors 95
Diodes 4
Resistors 11
Capacitors 4
VCC+
(1) (14)
(3) (4)
(2) (13) 1IN+ (1)
(2) 1OUT
1IN– (5)
(7) 2IN+
2OUT (6)
(10) 2IN–
3IN+ (8)
(3) (12) (9) 3OUT
3IN– (12)
(14) 4IN+
4OUT (13)
4IN–
62 (4) (11) (11)
GND
(5) (10)
CHIP THICKNESS: 15 TYPICAL
TJmax = 150°C
(6) (9)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
LM124, LM124A
LM2902,
LM224, LM224A UNIT
LM2902Q
LM324, LM324A
Supply voltage, VCC (see Note 1) 32 26 V
Differential input voltage, VID (see Note 2) ± 32 ± 26 V
Input voltage, VI (either input) – 0.3 to 32 – 0.3 to 26 V
Duration of output short circuit (one amplifier) to ground at (or below) TA = 25°C,
unlimited unlimited
VCC ≤ 15 V (see Note 3)
Continuous total dissipation See Dissipation Rating Table
LM124, LM124A – 55 to 125
LM224, LM224A – 25 to 85
free air temperature range,
Operating free-air range TA °C
LM324, LM324A 0 to 70
LM2902, LM2902Q – 40 to 125
Storage temperature range – 65 to 150 – 65 to 150 °C
Case temperature for 60 seconds FK package 260 °C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds J or W package 300 300 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds D, DB, N, or PW package 260 260 °C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values (except differential voltages and VCC specified for the measurement of IOS) are with respect to the network GND.
2. Differential voltages are at IN + with respect to IN –.
3. Short circuits from outputs to VCC can cause excessive heating and eventual destruction.
VCC – VCC –
RL = 2 kΩ 25°C
1.5 1.5
VCC – 1
VOH High-level output voltage RL = 10 kΩ 25°C V
.5
VCC = MAX, RL = 2 kΩ Full range 26 26 22
VCC = MAX, RL ≥ 10 kΩ Full range 27 28 27 28 23 24
VOL Low-level output voltage RL ≤ 10 kΩ Full range 5 20 5 20 5 20 mV
Large-signal
g g differential VCC = 15 V,, VO = 1 V to 11 V,, 25°C 50 100 25 100 100
† All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. MAX VCC for testing purposes is 26 V for LM2902
and LM2902Q, 30 V for the others.
‡ Full range is –55°C to 125°C for LM124, – 25°C to 85°C for LM224, 0°C to 70°C for LM324, and – 40°C to 125°C for LM2902 and LM2902Q.
§ All typical values are at TA = 25°C.
3–5
SLOS066E – SEPTEMBER 1975 – REVISED FEBRUARY 1997
QUADRUPLE OPERATIONAL AMPLIFIERS
LM324, LM324A, LM324Y, LM2902, LM2902Q
LM124, LM124A, LM224, LM224A
electrical characteristics at specified free-air temperature, VCC = 5 V (unless otherwise noted)
3–6
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
PACKAGE SCHEMATIC
DESCRIPTION
The MOC301XM and MOC302XM series are optically isolated triac driver devices. These devices contain a GaAs infrared
emitting diode and a light activated silicon bilateral switch, which functions like a triac. They are designed for interfacing between
electronic controls and power triacs to control resistive and inductive loads for 115 VAC operations.
FEATURES
• Excellent IFT stability—IR emitting diode has low degradation
• High isolation voltage—minimum 5300 VAC RMS
• Underwriters Laboratory (UL) recognized—File #E90700
• Peak blocking voltage
– 250V-MOC301XM
– 400V-MOC302XM
• VDE recognized (File #94766)
– Ordering option V (e.g. MOC3023VM)
APPLICATIONS
• Industrial controls • Solenoid/valve controls
• Traffic lights • Static AC power switch
• Vending machines • Incandescent lamp dimmers
• Solid state relay • Motor control
• Lamp ballasts
Note
1. Isolation surge voltage, VISO, is an internal device dielectric breakdown rating. For this test, Pins 1 and 2 are common, and
Pins 4, 5 and 6 are common.
Note
1. Test voltage must be applied within dv/dt rating.
2. This is static dv/dt. See Figure 5 for test circuit. Commutating dv/dt is a function of the load-driving thyristor(s) only.
3. All devices are guaranteed to trigger at an IF value less than or equal to max IFT. Therefore, recommended operating IF lies
between max IFT (30 mA for MOC3020M, 15 mA for MOC3010M and MOC3021M, 10 mA for MOC3011M and MOC3022M,
5 mA for MOC3012M and MOC3023M) and absolute max IF (60 mA).
Fig. 1 LED Forward Voltage vs. Forward Current Fig. 2 On-State Characteristics
1.8 800
1.7 600
200
1.5
0
1.4
TA = -55oC
-200
1.3
TA = 25oC
-400
1.2
TA = 100oC
-600
1.1
-800
1.0 -3 -2 -1 0 1 2 3
1 10 100
ON-STATE VOLTAGE - V TM (V)
IF - LED FORWARD CURRENT (mA)
Fig. 3 Trigger Current vs. Ambient Temperature Fig. 4 LED Current Required to Trigger vs. LED Pulse Width
1.4 25
TRIGGER CURRENT - I FT (NORMALIZED)
1.3
TRIGGER CURRENT - I FT (NORMALIZED)
20 NORMALIZED TO:
PWin ≥ 100 µs
1.2
15
1.1
1.0 10
0.9
5
0.8
0
0.7 1 2 5 10 20 50 100
NORMALIZED TO T A = 25∞C
LED TRIGGER WIDTH - PWin (µs)
0.6
-40 -20 0 20 40 60 80 100
10000
Fig. 5 dv/dt vs. Temperature
12
1000
STATIC dv/dt
10
IDRM, LEAKAGE CURRENT (nA)
CIRCUIT IN FIGURE 5
STATIC - dv/dt (V/µs)
8
100
4 10
0
25 30 40 50 60 70 80 90 100
RL
Rin 1 6 180
VCC 120 V
60 Hz
2 MOC3010M 5
MOC3011M
MOC3012M
3 4
ZL
ZL
LOAD GROUND
In this circuit the “hot” side of the line is switched and the load connected to the cold or ground side.
The 39 ohm resistor and 0.01µF capacitor are for snubbing of the triac, and the 470 ohm resistor and
0.05 µF capacitor are for snubbing the coupler. These components may or may not be necessary
depending upon the particular and load used.
0.390 (9.90)
0.332 (8.43)
0.260 (6.60) 0.260 (6.60)
0.240 (6.10) 0.240 (6.10)
0.200 (5.08)
0.115 (2.93) 0.200 (5.08) 0.012 (0.30)
0.115 (2.93) 0.008 (0.20)
0.100 (2.54)
0.015 (0.38) 0.025 (0.63)
0.020 (0.51)
0.020 (0.50) 15° 0.100 [2.54]
0.100 (2.54) 0.035 (0.88)
0.016 (0.41) 0.020 (0.50)
0.012 (0.30) 0.006 (0.16)
0.016 (0.41)
0.070 (1.78)
0.260 (6.60)
0.240 (6.10)
0.060 (1.52)
0.070 (1.77)
0.040 (1.02)
0.014 (0.36)
0.010 (0.25)
0.425 (10.79) 0.100 (2.54)
0.200 (5.08)
0.305 (7.75) 0.030 (0.76)
0.115 (2.93)
0.100 (2.54)
0.015 (0.38)
NOTE
All dimensions are in inches (millimeters)
ORDERING INFORMATION
MARKING INFORMATION
MOC3010 2
6
V X YY Q
3 4 5
Definitions
1 Fairchild logo
2 Device number
VDE mark (Note: Only appears on parts ordered with VDE
3
option – See order entry table)
4 One digit year code, e.g., ‘3’
5 Two digit work week ranging from ‘01’ to ‘53’
6 Assembly package code
*Note – Parts that do not have the ‘V’ option (see definition 3 above) that are marked with
date code ‘325’ or earlier are marked in portrait format.
11.5 ± 1.0
21.0 ± 0.1 24.0 ± 0.3
9.1 ± 0.20
NOTE
All dimensions are in inches (millimeters)
200
150
Time above 183°C, 120–180 sec
100
Ramp up = 2–10°C/sec • Peak reflow temperature: 245°C (package surface temperature)
50 • Time of temperature higher than 183°C for 120–180 seconds
• One time soldering reflow is recommended
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Time (Minute)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LM35
Precision Centigrade Temperature Sensors
General Description aged in hermetic TO-46 transistor packages, while the
LM35C, LM35CA, and LM35D are also available in the
The LM35 series are precision integrated-circuit temperature plastic TO-92 transistor package. The LM35D is also avail-
sensors, whose output voltage is linearly proportional to the able in an 8-lead surface mount small outline package and a
Celsius (Centigrade) temperature. The LM35 thus has an plastic TO-220 package.
advantage over linear temperature sensors calibrated in
˚ Kelvin, as the user is not required to subtract a large
constant voltage from its output to obtain convenient Centi- Features
grade scaling. The LM35 does not require any external n Calibrated directly in ˚ Celsius (Centigrade)
calibration or trimming to provide typical accuracies of ± 1⁄4˚C n Linear + 10.0 mV/˚C scale factor
at room temperature and ± 3⁄4˚C over a full −55 to +150˚C n 0.5˚C accuracy guaranteeable (at +25˚C)
temperature range. Low cost is assured by trimming and n Rated for full −55˚ to +150˚C range
calibration at the wafer level. The LM35’s low output imped- n Suitable for remote applications
ance, linear output, and precise inherent calibration make n Low cost due to wafer-level trimming
interfacing to readout or control circuitry especially easy. It
n Operates from 4 to 30 volts
can be used with single power supplies, or with plus and
minus supplies. As it draws only 60 µA from its supply, it has n Less than 60 µA current drain
very low self-heating, less than 0.1˚C in still air. The LM35 is n Low self-heating, 0.08˚C in still air
rated to operate over a −55˚ to +150˚C temperature range, n Nonlinearity only ± 1⁄4˚C typical
while the LM35C is rated for a −40˚ to +110˚C range (−10˚ n Low impedance output, 0.1 Ω for 1 mA load
with improved accuracy). The LM35 series is available pack-
Typical Applications
DS005516-4
TO-46 SO-8
Metal Can Package* Small Outline Molded Package
DS005516-1 DS005516-21
TO-92 TO-220
Plastic Package Plastic Package*
DS005516-2
DS005516-24
www.national.com 2
LM35
Absolute Maximum Ratings (Note 10) TO-92 and TO-220 Package,
(Soldering, 10 seconds) 260˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/ SO Package (Note 12)
Distributors for availability and specifications. Vapor Phase (60 seconds) 215˚C
Infrared (15 seconds) 220˚C
Supply Voltage +35V to −0.2V
ESD Susceptibility (Note 11) 2500V
Output Voltage +6V to −1.0V
Specified Operating Temperature Range: TMIN to T MAX
Output Current 10 mA (Note 2)
Storage Temp.; LM35, LM35A −55˚C to +150˚C
TO-46 Package, −60˚C to +180˚C LM35C, LM35CA −40˚C to +110˚C
TO-92 Package, −60˚C to +150˚C LM35D 0˚C to +100˚C
SO-8 Package, −65˚C to +150˚C
TO-220 Package, −65˚C to +150˚C
Lead Temp.:
TO-46 Package,
(Soldering, 10 seconds) 300˚C
Electrical Characteristics
(Notes 1, 6)
LM35A LM35CA
Parameter Conditions Tested Design Tested Design Units
Typical Limit Limit Typical Limit Limit (Max.)
(Note 4) (Note 5) (Note 4) (Note 5)
Accuracy T A =+25˚C ± 0.2 ± 0.5 ± 0.2 ± 0.5 ˚C
(Note 7) T A =−10˚C ± 0.3 ± 0.3 ± 1.0 ˚C
T A =TMAX ± 0.4 ± 1.0 ± 0.4 ± 1.0 ˚C
T A =TMIN ± 0.4 ± 1.0 ± 0.4 ± 1.5 ˚C
Nonlinearity T MIN≤TA≤TMAX ± 0.18 ± 0.35 ± 0.15 ± 0.3 ˚C
(Note 8)
Sensor Gain T MIN≤TA≤TMAX +10.0 +9.9, +10.0 +9.9, mV/˚C
(Average Slope) +10.1 +10.1
Load Regulation T A =+25˚C ± 0.4 ± 1.0 ± 0.4 ± 1.0 mV/mA
(Note 3) 0≤IL≤1 mA T MIN≤TA≤TMAX ± 0.5 ± 3.0 ± 0.5 ± 3.0 mV/mA
Line Regulation T A =+25˚C ± 0.01 ± 0.05 ± 0.01 ± 0.05 mV/V
(Note 3) 4V≤V S≤30V ± 0.02 ± 0.1 ± 0.02 ± 0.1 mV/V
Quiescent Current V S =+5V, +25˚C 56 67 56 67 µA
(Note 9) V S =+5V 105 131 91 114 µA
V S =+30V, +25˚C 56.2 68 56.2 68 µA
V S =+30V 105.5 133 91.5 116 µA
Change of 4V≤VS≤30V, +25˚C 0.2 1.0 0.2 1.0 µA
Quiescent Current 4V≤V S≤30V 0.5 2.0 0.5 2.0 µA
(Note 3)
Temperature +0.39 +0.5 +0.39 +0.5 µA/˚C
Coefficient of
Quiescent Current
Minimum Temperature In circuit of +1.5 +2.0 +1.5 +2.0 ˚C
for Rated Accuracy Figure 1, IL =0
Long Term Stability T J =TMAX, for ± 0.08 ± 0.08 ˚C
1000 hours
3 www.national.com
LM35
Electrical Characteristics
(Notes 1, 6)
LM35 LM35C, LM35D
Parameter Conditions Tested Design Tested Design Units
Typical Limit Limit Typical Limit Limit (Max.)
(Note 4) (Note 5) (Note 4) (Note 5)
Accuracy, T A =+25˚C ± 0.4 ± 1.0 ± 0.4 ± 1.0 ˚C
LM35, LM35C T A =−10˚C ± 0.5 ± 0.5 ± 1.5 ˚C
(Note 7) T A =TMAX ± 0.8 ± 1.5 ± 0.8 ± 1.5 ˚C
T A =TMIN ± 0.8 ± 1.5 ± 0.8 ± 2.0 ˚C
Accuracy, LM35D T A =+25˚C ± 0.6 ± 1.5 ˚C
(Note 7) TA =TMAX ± 0.9 ± 2.0 ˚C
TA =TMIN ± 0.9 ± 2.0 ˚C
Nonlinearity T MIN≤TA≤TMAX ± 0.3 ± 0.5 ± 0.2 ± 0.5 ˚C
(Note 8)
Sensor Gain T MIN≤TA≤TMAX +10.0 +9.8, +10.0 +9.8, mV/˚C
(Average Slope) +10.2 +10.2
Load Regulation T A =+25˚C ± 0.4 ± 2.0 ± 0.4 ± 2.0 mV/mA
(Note 3) 0≤IL≤1 mA T MIN≤TA≤TMAX ± 0.5 ± 5.0 ± 0.5 ± 5.0 mV/mA
Line Regulation T A =+25˚C ± 0.01 ± 0.1 ± 0.01 ± 0.1 mV/V
(Note 3) 4V≤V S≤30V ± 0.02 ± 0.2 ± 0.02 ± 0.2 mV/V
Quiescent Current V S =+5V, +25˚C 56 80 56 80 µA
(Note 9) V S =+5V 105 158 91 138 µA
V S =+30V, +25˚C 56.2 82 56.2 82 µA
V S =+30V 105.5 161 91.5 141 µA
Change of 4V≤VS≤30V, +25˚C 0.2 2.0 0.2 2.0 µA
Quiescent Current 4V≤V S≤30V 0.5 3.0 0.5 3.0 µA
(Note 3)
Temperature +0.39 +0.7 +0.39 +0.7 µA/˚C
Coefficient of
Quiescent Current
Minimum Temperature In circuit of +1.5 +2.0 +1.5 +2.0 ˚C
for Rated Accuracy Figure 1, IL =0
Long Term Stability T J =TMAX, for ± 0.08 ± 0.08 ˚C
1000 hours
Note 1: Unless otherwise noted, these specifications apply: −55˚C≤TJ≤+150˚C for the LM35 and LM35A; −40˚≤TJ≤+110˚C for the LM35C and LM35CA; and
0˚≤TJ≤+100˚C for the LM35D. VS =+5Vdc and ILOAD =50 µA, in the circuit of Figure 2. These specifications also apply from +2˚C to TMAX in the circuit of Figure 1.
Specifications in boldface apply over the full rated temperature range.
Note 2: Thermal resistance of the TO-46 package is 400˚C/W, junction to ambient, and 24˚C/W junction to case. Thermal resistance of the TO-92 package is
180˚C/W junction to ambient. Thermal resistance of the small outline molded package is 220˚C/W junction to ambient. Thermal resistance of the TO-220 package
is 90˚C/W junction to ambient. For additional thermal resistance information see table in the Applications section.
Note 3: Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output due to heating effects can be
computed by multiplying the internal dissipation by the thermal resistance.
Note 4: Tested Limits are guaranteed and 100% tested in production.
Note 5: Design Limits are guaranteed (but not 100% production tested) over the indicated temperature and supply voltage ranges. These limits are not used to
calculate outgoing quality levels.
Note 6: Specifications in boldface apply over the full rated temperature range.
Note 7: Accuracy is defined as the error between the output voltage and 10mv/˚C times the device’s case temperature, at specified conditions of voltage, current,
and temperature (expressed in ˚C).
Note 8: Nonlinearity is defined as the deviation of the output-voltage-versus-temperature curve from the best-fit straight line, over the device’s rated temperature
range.
Note 9: Quiescent current is defined in the circuit of Figure 1.
Note 10: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its rated operating conditions. See Note 1.
Note 11: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 12: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
www.national.com 4
LM35
Typical Performance Characteristics
Thermal Resistance Thermal Time Constant Thermal Response
Junction to Air in Still Air
DS005516-26
DS005516-25 DS005516-27
DS005516-29
DS005516-28
DS005516-30
DS005516-32 DS005516-33
DS005516-31
5 www.national.com
LM35
Typical Performance Characteristics (Continued)
DS005516-34 DS005516-35
*Wakefield type 201, or 1" disc of 0.020" sheet brass, soldered to case, or similar.
**TO-92 and SO-8 packages glued and leads soldered to 1" square of 1/16" printed circuit board with 2 oz. foil or similar.
www.national.com 6
LM35
Typical Applications
DS005516-19
DS005516-6
DS005516-20
CAPACITIVE LOADS
Like most micropower circuits, the LM35 has a limited ability
to drive heavy capacitive loads. The LM35 by itself is able to
drive 50 pf without special precautions. If heavier loads are
anticipated, it is easy to isolate or decouple the load with a
resistor; see Figure 3. Or you can improve the tolerance of
capacitance with a series R-C damper from output to
ground; see Figure 4.
When the LM35 is applied with a 200Ω load resistor as DS005516-7
shown in Figure 5, Figure 6 or Figure 8 it is relatively immune FIGURE 7. Temperature Sensor, Single Supply, −55˚ to
to wiring capacitance because the capacitance forms a by- +150˚C
pass from ground to input, not on the output. However, as
with any linear circuit connected to wires in a hostile envi-
ronment, its performance can be affected adversely by in-
tense electromagnetic sources such as relays, radio trans-
mitters, motors with arcing brushes, SCR transients, etc, as
its wiring can act as a receiving antenna and its internal
junctions can act as rectifiers. For best results in such cases,
a bypass capacitor from VIN to ground and a series R-C
damper such as 75Ω in series with 0.2 or 1 µF from output to
ground are often useful. These are shown in Figure 13,
Figure 14, and Figure 16.
DS005516-8
DS005516-5
DS005516-9
7 www.national.com
LM35
Typical Applications (Continued)
DS005516-11
DS005516-10
DS005516-12
DS005516-13
FIGURE 13. Temperature To Digital Converter (Serial Output) (+128˚C Full Scale)
DS005516-14
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LM35
Typical Applications (Continued)
DS005516-16
DS005516-15
9 www.national.com
LM35
Block Diagram
DS005516-23
www.national.com 10
LM35
Physical Dimensions inches (millimeters) unless otherwise noted
11 www.national.com
LM35
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
www.national.com 12
LM35 Precision Centigrade Temperature Sensors
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
2N3904 / MMBT3904 / PZT3904
2N3904 MMBT3904 PZT3904
C C
E E
C
C TO-92 B
B SOT-23 B
E SOT-223
Mark: 1A
OFF CHARACTERISTICS
V(BR)CEO Collector-Emitter Breakdown IC = 1.0 mA, IB = 0 40 V
Voltage
V(BR)CBO Collector-Base Breakdown Voltage IC = 10 µA, IE = 0 60 V
V(BR)EBO Emitter-Base Breakdown Voltage IE = 10 µA, IC = 0 6.0 V
IBL Base Cutoff Current VCE = 30 V, VEB = 3V 50 nA
ICEX Collector Cutoff Current VCE = 30 V, VEB = 3V 50 nA
ON CHARACTERISTICS*
hFE DC Current Gain IC = 0.1 mA, VCE = 1.0 V 40
IC = 1.0 mA, VCE = 1.0 V 70
IC = 10 mA, VCE = 1.0 V 100 300
IC = 50 mA, VCE = 1.0 V 60
IC = 100 mA, VCE = 1.0 V 30
VCE(sat) Collector-Emitter Saturation Voltage IC = 10 mA, IB = 1.0 mA 0.2 V
IC = 50 mA, IB = 5.0 mA 0.3 V
VBE(sat) Base-Emitter Saturation Voltage IC = 10 mA, IB = 1.0 mA 0.65 0.85 V
IC = 50 mA, IB = 5.0 mA 0.95 V
SWITCHING CHARACTERISTICS
td Delay Time VCC = 3.0 V, VBE = 0.5 V, 35 ns
tr Rise Time IC = 10 mA, IB1 = 1.0 mA 35 ns
ts Storage Time VCC = 3.0 V, IC = 10mA 200 ns
tf Fall Time IB1 = IB2 = 1.0 mA 50 ns
Spice Model
NPN (Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 Ne=1.259 Ise=6.734 Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2
Isc=0 Ikr=0 Rc=1 Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75 Tr=239.5n Tf=301.2p
Itf=.4 Vtf=4 Xtf=2 Rb=10)
2N3904 / MMBT3904 / PZT3904
NPN General Purpose Amplifier
(continued)
Typical Characteristics
500
V CE = 5V 0.15
400 β = 10
125 °C 125 °C
300
25 °C 0.1
200 25 °C
- 40 °C 0.05
100
- 40 °C
0
0.1 1 10 100 0.1 1 10 100
I C - COLLECTOR CURRENT (mA) I C - COLLECTOR CURRENT (mA)
1
1 β = 10 VCE = 5V
0.8 - 40 °C
0.8 - 40 °C 25 °C
25 °C 0.6
0.6 125 °C
125 °C 0.4
0.4
0.2
0.1 1 10 100 0.1 1 10 100
IC - COLLECTOR CURRENT (mA) I C - COLLECTOR CURRENT (mA)
500
f = 1.0 MHz
100 VCB = 30V
CAPACITANCE (pF)
5
10 4
C ibo
3
1
2
0.1 C obo
1
25 50 75 100 125 150 0.1 1 10 100
TA - AMBIENT TEMPERATURE ( °C) REVERSE BIAS VOLTAGE (V)
2N3904 / MMBT3904 / PZT3904
NPN General Purpose Amplifier
(continued)
4 4 I C = 100 µA
2 2
I C = 100 µA, R S = 500 Ω
0 0
0.1 1 10 100 0.1 1 10 100
f - FREQUENCY (kHz) R S - SOURCE RESISTANCE ( kΩ )
45 h fe 20
40 40 SOT-223
θ - DEGREES
0.75
35 60 TO-92
30 80
25 θ 100 0.5
20 120
SOT-23
15 140
V CE = 40V 160
10 0.25
fe
5 I C = 10 mA 180
h
0
1 10 100 1000 0
f - FREQUENCY (MHz) 0 25 50 75 100 125 150
TEMPERATURE (o C)
T J = 25°C
t r @ V CC = 3.0V
T J = 125°C
2.0V
10 10
t d @ VCB = 0V
5 5
1 10 100 1 10 100
I C - COLLECTOR CURRENT (mA) I C - COLLECTOR CURRENT (mA)
2N3904 / MMBT3904 / PZT3904
NPN General Purpose Amplifier
(continued)
T J = 25°C
T J = 125°C VCC = 40V
10 10
5 5
1 10 100 1 10 100
I C - COLLECTOR CURRENT (mA) I C - COLLECTOR CURRENT (mA)
V CE = 10 V V CE = 10 V
f = 1.0 kHz f = 1.0 kHz
T A = 25oC T A = 25oC
h fe - CURRENT GAIN
100
10
10 1
0.1 1 10 0.1 1 10
I C - COLLECTOR CURRENT (mA) I C - COLLECTOR CURRENT (mA)
100 10
V CE = 10 V
h re - VOLTAGE FEEDBACK RATIO (x10
V CE = 10 V
f = 1.0 kHz
h ie - INPUT IMPEDANCE (kΩ )
f = 1.0 kHz
T A = 25oC 7 T A = 25oC
10 5
4
1
2
0.1 1
0.1 1 10 0.1 1 10
I C - COLLECTOR CURRENT (mA) I C - COLLECTOR CURRENT (mA)
2N3904 / MMBT3904 / PZT3904
NPN General Purpose Amplifier
(continued)
Test Circuits
3.0 V
300 ns 275 Ω
10.6 V
Duty Cycle = 2%
Ω
10 KΩ
0
- 0.5 V C1 < 4.0 pF
< 1.0 ns
3.0 V
Duty Cycle = 2%
0 Ω
10 KΩ
C1 < 4.0 pF
- 9.1 V 1N916
< 1.0 ns
TO-92 Packaging
Configuration: Figure 1.0
5 Reels per
(FSCINT) Intermediate Box
Customized
F63TNR Label sample
Label
LOT: CBVK741B019 QTY: 2000 F63TNR
FSID: PN222N SPEC:
Label
FSCINT Label
10,000 units maximum
per intermediate box
for std option
Style “A”, D26Z, D70Z (s/h) Style “E”, D27Z, D71Z (s/h)
FIRST WIRE OFF IS EMITTER (ON PKG. 92) FIRST WIRE OFF IS COLLECTOR (ON PKG. 92)
ADHESIVE TAPE IS ON BOTTOM SIDE ADHESIVE TAPE IS ON BOTTOM SIDE
FLAT OF TRANSISTOR IS ON BOTTOM FLAT OF TRANSISTOR IS ON TOP
Hd
P Pd
Ha W1
d S
L
H1 HO
L1
WO t
W2
t1
P1 F1
P2 DO
ELECT ROSTATIC
SEN SITIVE D EVICES
D4 D1
D3
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
SOT-23 Packaging
Configuration: Figure 1.0
3P 3P 3P 3P
SOT-23 Packaging Information
Standard
Packaging Option D87Z
(no flow code)
Packaging type TNR TNR SOT-23 Unit Orientation
Qty per Reel/Tube/Bag 3,000 10,000
Reel Size 7" Dia 13"
Box Dimension (mm) 187x107x183 343x343x64
343mm x 342mm x 64mm Human Readable Label
Max qty per Box 24,000 30,000
0.0082 0.0082
Intermediate box for L87Z Option
Weight per unit (gm)
Weight per Reel (kg) 0.1175 0.4006
Note/Comments
H uman readable
Label
187mm x 107mm x 183mm
SOT-23 Tape Leader and Trailer Intermediate Box for Standard Option
Configuration: Figure 2.0
Carrier Tape
Cover Tape
Components
Trailer Tape Leader Tape
300mm minimum or 500mm minimum or
75 empt y poc kets 125 empty pockets
E1
F W
E2
B0 Wc
Tc A0
P1
K0
User Direction of Feed
Pkg type A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc
SOT-23 3.15 2.77 8.0 1.55 1.125 1.75 6.25 3.50 4.0 4.0 1.30 0.228 5.2 0.06
(8mm) +/-0.10 +/-0.10 +/-0.3 +/-0.05 +/-0.125 +/-0.10 min +/-0.05 +/-0.1 +/-0.1 +/-0.10 +/-0.013 +/-0.3 +/-0.02
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C). 0.5mm
20 deg maximum maximum
Typical
component
cavity 0.5mm
B0 center line maximum
Typical
Sketch A (Side or Front Sectional View) component Sketch C (Top View)
A0 center line
Component Rotation Component lateral movement
Sketch B (Top View)
SOT-23 Reel Configuration: Figure 4.0 Component Rotation
W1 Measured at Hub
Dim A
Max
Dim C
See detail AA
Dim D
W3 min
DETAIL AA
Reel
Tape Size Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)
Option
7.00 0.059 512 +0.020/-0.008 0.795 2.165 0.331 +0.059/-0.000 0.567 0.311 – 0.429
8mm 7" Dia
177.8 1.5 13 +0.5/-0.2 20.2 55 8.4 +1.5/0 14.4 7.9 – 10.9
13.00 0.059 512 +0.020/-0.008 0.795 4.00 0.331 +0.059/-0.000 0.567 0.311 – 0.429
8mm 13" Dia
330 1.5 13 +0.5/-0.2 20.2 100 8.4 +1.5/0 14.4 7.9 – 10.9
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
SOT-223 Packaging
Configuration: Figure 1.0
Customized Label
Packaging Description:
SOT-223 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
F63TNR Label resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
Antistatic Cover Tape These reeled parts in standard option are shipped with
2,500 units per 13" or 330cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (anti-
static coated). Other option comes in 500 units per 7" or
177cm diameter reel. This and some other options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
Static Dissipative comes in different sizes depending on the number of parts
shipped.
Embossed Carrier Tape
F63TNR Label
F63TNR Label sample
184mm x 184mm x 47mm
LOT: CBVK741B019 QTY: 3000
Pizza Box for D84Z Option
FSID: PN2222A SPEC:
SOT-223 Tape Leader and Trailer
D/C1: D9842 QTY1: SPEC REV:
Configuration: Figure 2.0 D/C2: QTY2: CPN:
N/F: F (F63TNR)3
Carrier Tape
Cover Tape
Components
Trailer Tape Leader Tape
300mm minimum or 500mm minimum or
38 empty pockets 62 empty pockets
K0 W
E2
Wc B0
Tc
A0 P1 D1
Pkg type A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc
0.292
SOT-223 6.83 7.42 12.0 1.55 1.50 1.75 10.25 5.50 8.0 4.0 1.88
+/-
9.5 0.06
(12mm) +/-0.10 +/-0.10 +/-0.3 +/-0.05 +/-0.10 +/-0.10 min +/-0.05 +/-0.1 +/-0.1 +/-0.10 +/-0.025 +/-0.02
0.0130
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C). 0.5mm
20 deg maximum maximum
Typical
component
cavity 0.5mm
B0 center line maximum
Typical
Sketch A (Side or Front Sectional View) component Sketch C (Top View)
A0 center line
Component Rotation Component lateral movement
Sketch B (Top View)
SOT-223 Reel Configuration: Figure 4.0 Component Rotation
W1 Measured at Hub
Dim A
Max
Dim C
See detail AA
Dim D
W3 min
DETAIL AA
Reel
Tape Size Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)
Option
7.00 0.059 512 +0.020/-0.008 0.795 5.906 0.488 +0.078/-0.000 0.724 0.469 – 0.606
12mm 7" Dia
177.8 1.5 13 +0.5/-0.2 20.2 150 12.4 +2/0 18.4 11.9 – 15.4
13.00 0.059 512 +0.020/-0.008 0.795 7.00 0.488 +0.078/-0.000 0.724 0.469 – 0.606
12mm 13" Dia
330 1.5 13 +0.5/-0.2 20.2 178 12.4 +2/0 18.4 11.9 – 15.4
1:1
DISCLAIMER
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.
Definition of Terms
Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Rev. G
BC547 / BC547A / BC547B / BC547C
BC547
BC547A
BC547B
BC547C
E TO-92
B
C
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150 degrees C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
OFF CHARACTERISTICS
V(BR)CEO Collector-Emitter Breakdown Voltage IC = 1.0 mA, IB = 0 45 V
V(BR)CBO Collector-Base Breakdown Voltage IC = 10 µA, IE = 0 50 V
V(BR)CES Collector-Base Breakdown Voltage IC = 10 µA, IE = 0 50 V
V(BR)EBO Emitter-Base Breakdown Voltage IE = 10 µA, IC = 0 6.0 V
ICBO Collector Cutoff Current VCB = 30 V, IE = 0 15 nA
VCB = 30 V, IE = 0, TA = +150 °C 5.0 µA
ON CHARACTERISTICS
hFE DC Current Gain VCE = 5.0 V, IC = 2.0 mA 547 110 800
547A 110 220
547B 200 450
547C 420 800
VCE(sat) Collector-Emitter Saturation Voltage IC = 10 mA, IB = 0.5 mA 0.25 V
IC = 100 mA, IB = 5.0 mA 0.60 V
VBE(on) Base-Emitter On Voltage VCE = 5.0 V, IC = 2.0 mA 0.58 0.70 V
VCE = 5.0 V, IC = 10 mA 0.77 V
DISCLAIMER
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.
Definition of Terms
Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Rev. G
SEMICONDUCTOR TECHNICAL DATA
*Motorola preferred devices
MT1
MT2
G
CASE 221A-06
(TO-220AB)
Style 4
THERMAL CHARACTERISTICS
RθJC Thermal Resistance — Junction to Case 2.0 °C/W
RθJA Thermal Resistance — Junction to Ambient 62.5
TL Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds 260 °C
(1) VDRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
OFF CHARACTERISTICS
IDRM Peak Repetitive Blocking Current mA
(VD = Rated VDRM, Gate Open) TJ = 25°C — — 0.01
TJ = 125°C — — 2.0
ON CHARACTERISTICS
VTM Peak On-State Voltage* Volts
(ITM = ± 21 A Peak) — 1.2 1.6
IGT Continuous Gate Trigger Current (VD = 12 V, RL = 100 Ω) mA
MT2(+), G(+) 5.0 13 35
MT2(+), G(–) 5.0 16 35
MT2(–), G(–) 5.0 18 35
IH Hold Current mA
(VD = 12 V, Gate Open, Initiating Current = ±150 mA) — 20 40
125 20 DC
180°
120 18
PAV, AVERAGE POWER (WATTS)
120°
TC, CASE TEMPERATURE (°C)
115 16
α = 30 and 60° 14
90°
110 60°
α = 90° 12
105
α = 180° α = 120° 10
100 α = 30°
8
95
DC 6
90 4
85 2
80 0
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
IT(RMS), RMS ON-STATE CURRENT (AMP) IT(RMS), ON-STATE CURRENT (AMP)
100 1
(NORMALIZED)
0.1
I T, INSTANTANEOUS ON-STATE CURRENT (AMP)
10
0.01
0.1 1 10 100 1000 1 · 104
t, TIME (ms)
MAXIMUM @ TJ = 25°C 40
1
I H, HOLD CURRENT (mA)
MT2 POSITIVE
MT2 NEGATIVE
0.1 5
0 0.5 1 1.5 2 2.5 3 3.5 4 – 40 – 10 20 50 80 110 125
VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C)
100 1
OFF-STATE VOLTAGE = 12 V
VGT, GATE TRIGGER VOLTAGE (VOLT)
IGT, GATE TRIGGER CURRENT (mA)
RL = 140 Ω
Q2
Q3
Q1 Q1
Q3
Q2
OFF-STATE VOLTAGE = 12 V
RL = 140 Ω
1 0.5
– 40 – 10 20 50 80 110 125 – 40 – 10 +20 50 80 110 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Gate Trigger Current Variation Figure 7. Gate Trigger Voltage Variation
10
2K
ITM
1
f=
tw 2 tw
1K
6f I
(di/dt)c = TM
VDRM 1000
0 1
10 100 1000 10000 10 20 30 40 50 60 70 80 90 100
RG, GATE TO MAIN TERMINAL 1 RESISTANCE (OHMS) (di/dt)c, RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
Figure 8. Critical Rate of Rise of Off-State Voltage Figure 9. Critical Rate of Rise of
(Exponential) Commutating Voltage
LL 1N4007
200 VRMS
ADJUST FOR MEASURE
ITM, 60 Hz VAC I
TRIGGER CONTROL
CHARGE
TRIGGER CONTROL –
CHARGE 400 V
+
2
1N914 51
NON-POLAR
G 1
CL
Note: Component values are for verification of rated (dv/dt)c. See AN1048 for additional information.
Figure 10. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Voltage