Ee 330 Finalprojectlabreport

EE 330 Final Project: A Temperature Sensor with Digital Output Joseph Kenkel, Jonah Stoffer, Marcus Kavars
Joseph Kenkel, Jonah Stoffer, Marcus Kavars
EE 330
Spring 2021
Dr. Chen
Mahmoud Gshash
Final Project: A Temperature Sensor with Digital Output
Introduction:
In this project we are going to create a temperature sensor with a digital output. This
temperature sensor sensor is going to run at two samples per second. We are going to start by
designing a temperature sensing circuit called a Proportional to Absolute Temperature (PTAT)
circuit. The output of this PTAT will feed into an amplifier to increase the slope caused by the
change in temperature. This will then feed into a single slope ADC. That will be the end of our
Cadence circuit. We will then design the 7 bit output of the ACD and use ModelSim Verilog
code to turn that input into something that will control a 7 segment display.
Op Amp:
Figure 1. PTAT build
The operational amplifier (op amp) that we will be using throughout the design of our
temperature sensor will provide a single output based on its two inputs, which will create a
differential input. This input is then amplified before being sent out of Vout.
We ended up using the TA’s op amp instead of designing one ourselves. This section is
going to be an in depth analysis of Mahmoud’s operational amplifier to better understand the
limitations of the amplifier and get a good understanding so we can build one in the future.
When designing the amplifier, you must designate how much current goes through each
of the sections. The majority should go to the far right output section that is made up of P3 and
N4. The rest of the power/ current is divided up between the other two sections.
In order to set the current, you need a current mirror. This design has a current sink
composed of N2, N3, and N4. This sink is powered by N3’s current. The PMOS, P0, above N3
acts as a resistor for this section. Mahmoud biased this section to have a current of around 9.75
uA.
Looking at the size comparisons to N2 and N3, they are approximately the exact same.
This means that they will have very similar currents. P1 and P2 in this section are set to insure
that N0 and N1 have the exact same current between them. Vip, when raised, causes the
resistance in N1 to go lower which results in P3 going lower and a larger Vout. When Vin is
raised, this causes the current through P2 to increase which results in a higher resistance for P3.
This higher resistance causes Vout to go lower. In summary, Vip makes vout larger and Vin
makes Vout smaller.
Figure 2. Geiger Excel Sheet
Using the Excel sheet that Geiger gave us, we started to fill out using parameters that
were given under Mahmoud’s op amp. Using this document, we found that the ideal max input
is between -1.19 volts and 2.21 volts and the ideal output is between -2.155 volts and 2.155 volts.
We then ran this through a stability analysis to insure that it would work.
PTAT:
As mentioned inside of the introduction, PTAT stands for Proportional to Absolute
Temperature. The other temperature sensing device is a CTAT. This stands for Complementary
to Absolute Temperature. The PTAT’s voltage will linearly rise as the temperature increases
while the CTAT’s voltage will linearly fall.
There are multiple devices that can measure temperature. One of the most obvious and
common is the thermistor and the diode. This will vary the resistance based on the temperature.
The problem with using these components is that they are exponentially functions. This is
demonstrated in the study conducted by Ken Wada and seen in Figure 3.
Figure 3. Resistance Vs Temperature

By using the PTAT, you will be able to get a linear output for your system. This system
utilizes the current source to hold diodes at a constant current. This means that the only change
in voltage is due to the temperature.
Figure 4. PTAT Schematic
The top 3 PMOSs are in the current source configuration. Since they all share a gate and
a source voltages, when these PMOS are in saturation, they have the same current. This is
𝑊
because the saturated PMOS equations is 𝐼𝑑 = − µ𝐶𝑜𝑥 * 2𝐿
(𝑉𝐺𝑆 − 𝑉𝑇). This means that
the voltage below it has next to zero effect on the current. This is only true when
𝑉𝐷𝑆 ≥ 𝑉𝐺𝑆 − 𝑉𝑇. If that condition is satisfied, then these are a current source.
Figure 5. Diode Configured PMOS
Figure 5 represents a PMOS in a diode configuration. Whenever there is a p-doped
region next to a n-doped region this creates a diode. The equation for a diode is given in
equation 1. Id is current going through the diode and Vd is the voltage across the diode. V T is
𝐾𝑇
equal to 𝑞
where these are all constants except for T which is the temperature in Kelvin.
𝑉𝑑
𝐼𝑑 = 𝐼𝑠 * 𝑒 𝑉𝑇 Equation 1
If equation 1 is rearranged to solve for Vd instead of Id, we get equation 2. We are doing
this because of the current source, we know that they all have the same current through it. We
𝑉𝑃𝑖𝑝 −𝑉𝑃1
also know that the current going through resistor R0 on Figure 4, is 𝑅0
.
𝐼
𝑉𝑑 = 𝑉𝑇 * 𝑙𝑛( 𝐼𝐷 ) Equation 2
𝑆
Next, if this is an ideal op amp, then Vin is equal to Vip. We also know that Vin is also
𝑉𝑃0 −𝑉𝑃1
equal to VP0. This means that we know that the current through R0 is 𝑅0
.
In order to fully understand what is happening, let us take a closer look at VP0 - VP1. To
find these, we must look back at equation 2. VT, and ID are going to be the exact same for both
of these. This is because the temperature and current will ideally be the same for both Mosfets.
This means that the only parameter that we can change is IS. You can do this by changing the size
of the PMOS. The easiest and most measurable way to do this is by adding a multiplier to one of
these. We started off by choosing to use a multiplier of “m” for P1. This multiplier increases the
size and linearly affects IS. You can rewrite V P0 - VP1 as equation 3.
𝐼 𝐼
𝑉𝑇 * 𝑙𝑛( 𝐼𝐷 ) − 𝑉𝑇 * 𝑙𝑛( 𝑚*𝐼𝐷 ) = 𝑉𝑇 * 𝑙𝑛(𝑚) Equation 3
𝑆 𝑆
𝐾𝑇
VT is linearly proportional to the temperature since it is equal to 𝑞
. Using equation 3,
𝑉𝑇*𝑙𝑛(𝑚)
we can say that the current throughout the system is 𝑅0
. Now that we know this, we can
start to look at Vout. The voltage at Vout is equal to the voltage of R1. The voltage of R1 is
IP4*R1. Since IP4= IP3=IP2 we can deduce equation 4.
𝐾𝑇*𝑙𝑛(𝑚)
𝐼𝑃4𝑅𝑅1 = 𝑞*𝑅𝑅0
* 𝑅𝑅1 Equation 4
Now we know that the two resistors and temperature increase the output linearly, while
𝑅𝑅1
the multiplier logarithmically increases it. We started off with a multiplier of of 10 and a 𝑅𝑅0
of
5. This produced the output of figure 6.

Figure 6. First PTAT
This was nice, but we wanted a larger gain. Since the resistors gave a larger gain, we
𝑅
switched the two. Now the multiplier is5 and 𝑅𝑅1 is 10. Plugging this in, this means that at -20
𝑅0
degree celsius Vout is 350mV and at 100 degrees celsius the output is 518 mV. Once this was
ran, we got an output that is shown in figure 7.
Figure 7. Linear PTAT Output

The two ends of PTAT are slightly different than the ideal PTAT. They are off by only a
little bit. 20mV at most. This is a result of the amplifier being non-idea. V Ip and VIn are not
exactly the same. They are slightly different which results in V out is slightly different than what
we expected.
𝑅𝑅1
After this, I got to greedy and chose to make the 𝑅𝑅0
50. This started to send the PMOS
into the triode region. Due to this, we got the output in figure 8. Knowing that we can run this
𝑅
through an amplifier, we left the PTAT with the multiplier of 5 and 𝑅𝑅1 of 10.
𝑅0
Figure 8. Nonlinear PTAT gain
Start up circuit
Because the current source is the output of the Op Amp, this means that when the system
is starting up as the voltage increases, it could get caught with all of the MOSFETs being stuck in
the cutoff position. The way that you get past this is by having an outside current source feed
into the system. This ensures that the MOSFETS get out of this cutoff position and into the
operating mode.
Once the PTAT is operating, you want this current source to shut off to save on power.
The way that you would implement this is expressed in figure 9.
Figure 9. Start up circuit
I would connect this to the VIn terminal. Because our PTAT worked just fine, Mahmoud
told us that we did not have to add this. This schematic must have the sizes manipulated to
ensure that current goes through when the system is off and shuts off when the system is running.
Increase the PTAT’s Gain

As you will learn in the ADC portion of this report, we want the range for the input of the
ADC to be from 0 volts to 1 volt. This means that we must both decrease the voltage at -20
degrees and increase it at 100 degrees. We were able to accomplish this using a non inverting
summing amplifier.
Figure 10. Non-inverting summing amplifier
There are two parts to this schetic. We will start with your basic non inverting amplifier
𝑅𝑅2
configuration. The equation for this portion is Gain = 𝑅𝑅3
+ 1.
The input portion is a little bit harder. We know that KCL must be true so the current
going through R0 is equal to the current going through R1. Another way to write it is using
equations 5 through 7.
𝑉𝑖𝑛1 − 𝑉+ 𝑉𝑖𝑛2 − 𝑉+
𝑅𝑅0
− 𝑅𝑅1
= 0 Equation 5
𝑉𝑖𝑛1 − 𝑉+ 𝑉𝑖𝑛2 − 𝑉+
𝑅𝑅0
= 𝑅𝑅1
Equation 6
𝑉𝑖𝑛1 𝑉𝑖𝑛2
𝑅𝑅0
+ 𝑅𝑅1
𝑉+ = 1 1 Equation 7
𝑅𝑅0
+𝑅
𝑅1
It is this last one that we are the most interested in. Vin2 is what is being multiplied with
the second stage of this amplifier. Inorder to make this math easier, we made R0 = R1. With this
little trick, we get equation 8.
𝑉𝑖𝑛1+ 𝑉𝑖𝑛2
𝑅𝑅 𝑉𝑖𝑛1+ 𝑉𝑖𝑛2
𝑉+ = 2 = 2
Equation 8
𝑅𝑅
Lastly, we know that we want the output to be zero at -20 degrees. Since the voltage of
the PTAT is 375 mV, this means that we want V in2 to be -375 mV to make the output zero. Next
524.668 − 375
comes setting up R2 and R3 or the actual gain. V+ at 100 degree is 2
or roughly 75
mV. Since we want the output to be 1 volt, you can find the gain by using equation 9.
1 𝑅2
𝐺𝑎𝑖𝑛 = 𝑃𝑇𝐴𝑇𝑀𝑎𝑥 − 𝑃𝑇𝐴𝑇𝑀𝑖𝑛
= 𝑅3
+1 Equation 9
𝑅2
Using this math, we need a gain of around 14, or an 𝑅3
of 13. Knowing this, we made the
schematic in figure 11.

Figure 11. PTAT Gain Schematic
We first choose to make R2 and R3 in the kiloohm range. Inorder to get a voltage of -375
mV, we must make a voltage divider. Since we know that the current going through R8 is equal
to R9 and we know what Vdd and Vss is, I choose the resistance accordingly. Normally, I set the
resistors in the MΩrange because the current going through this section is just waisted power.
The reason that all of our voltage dividers as only in the kΩis because the larger resistors are just
massive and there was not a power constraint, we decided it would be nicer to fit the smaller
resistors in our layout vs the larger ones.
The unity buffer was then installed to make sure that the current going through R0 and
R1 did not affect the output of this voltage divider. Speaking of current affecting the voltage, we
added some𝑀Ω resistors to limit the current so that the output of the PTAT is not affected. The
math that we calculated earlier would only work if we were using ideal voltage sources. In
hindsight while putting together the layout, just adding another unity buffer on the PTAT side
would have resulted in a smaller overall design than adding two𝑀Ωresistors.

Figure 12. PTAT Change
As you can see, there is a slight difference between a PTAT without a Vout load and a
PTAT that is hooked up to our op amp. Due to the absurdly large resistor, there is basically no
difference between the too. It was this thought that resulted in us not adding the unity buffer
afterwards. These two voltages are almost exactly the same.

Figure 13. Plot of PTAT with Gain
The output of the PTAT, V+, and final youtube all look identical except for their bound.
As we mentioned above, the PTAT has a range of 375 mV to 525 mV. Then you notice that Vip
is just PTAT_out + Vdiv divided by 2. This one's range is between 0 and 75mV as expected.
This part is then sent through a 14 gain amplifier to have a final bounds of 0 to 1V.
ADC
The next piece in the design was the ADC, or Analog-to-Digital Converter. Since a seven
segment display cannot take in an analog signal and figure out what temperature it corresponds
to, it was necessary to take our analog voltage signal from the PTAT and transform it into seven
wires to make up a binary number.
The ADC consists of two parts: an op-amp chain, and a seven-bit counter. The main idea
of the system is to have an op-amp chain that outputs a high signal, while the counter is being
incremented by a clock. The op-amp chain will act as an enable for the clock, turning it off and
stopping the counter when the correct(or near the correct) number has been reached. We decided
that the best way to implement this was with a single slope ADC, which would be put together
with the clock in an AND gate, and the output of that AND gate would feed into a counter
consisting of seven positive edge D-Flip-Flops.
A single slope ADC consists of two op-amps: the first being an integrator op-amp, and
the second being a comparator. The integrator op-amp would be fed the highest possible PTAT
output voltage as a constant source. This would create a line that starts at 0V, and rises at a
constant slope until it reaches the input voltage. This would be fed into a comparator op-amp,
along with the PTAT output. This creates a system that outputs a high voltage until the integrator
reaches a voltage that is equal to the PTAT output, in which case it switches to a low voltage.
This design will allow the system to shut off the clock, and create a number on the counter which
is proportional to the PTAT voltage. It would be challenging to explain each part of the ADC
without showing how it all comes together first. Our final design is shown below, and it will be
explained further after this:

Figure 14. Final ADC Build
The first part is the integrator. As stated before, it creates an output with a sloped line that
approaches the input voltage, starting from zero. It consists of a resistor and capacitor in parallel
for the design, which is what is creating this sloped line. The slope in this case would be equal to
the input voltage, called VREF, divided by the product of the resistor and capacitor values. Using
this, we chose values that would allow the ADC to be synchronized with a 10 MHz clock.
The second part is the comparator. This device is much simpler, and its purpose is to
compare the voltages of the PTAT output and the integrator to signal when to run the 10 MHz
clock. The only time the clock should be running is while the integrator voltage is lower than the
PTAT voltage. So, the comparator is configured to output a high voltage while the integrator is
smaller than the PTAT, and output a low voltage when it reaches the PTAT voltage. Below is an
example of the ADC working, with VREF = 1V and the PTAT voltage being 400 mV:
Figure 15. Integrator vs ADC Output
This output would be put into an AND gate with the clock, which would increment a
counter made up of D-Flip-Flops. These flip-flops were D-latches, arranged in master-slave
configuration. This created a system that would output a clock with half the frequency of the
input clock. These flip-flops can be chained together, with each of their D inputs hooked up to
the Qnot output, and with the clock hooked up to the Q output of the previous flip-flop in the
chain, as shown below:

Figure 16. D Flip Flop
Figure 17. Ripple Counter
When these are chained together like so, they create a ripple counter, where each
D-Flip-Flop acts as a clock for the next one, and with the outputs making up a binary number.
This in conjunction with the ADC would make a binary number that was proportional to the
PTAT output voltage, and create something to use with a seven segment display. Below is the
ripple counter shown with the ADC output:
Figure 18. Counter vs. ADC
This was, of course, what we had after a lot of testing and troubleshooting. The main
design challenges we encountered were the capacitor and resistor values, the implementation of a
switch, and creating an output that was perfectly accurate for at least on voltage, which would
allow us to fix errors in Verilog later.
The first big challenge was that we were limited in our choices for capacitor values.
Capacitors get very big very fast, especially on a layout, and so we needed it to be small. This
would create the problem of having very big resistor values, which isn’t ideal, but is more
acceptable than a massive capacitor. We balanced this by choosing a capacitor value of one pF,
and a resistor value of 106 MΩ.
The next challenge came with the switch. We ended up using an NMOS for the switch,
but this came with some problems. Mainly, the NMOS would have a very small current, even in
the cutoff region because it isn’t quite perfect. This slightly changed our VREF because the
current through the resistor in the integrator created a very small amount of voltage. We
overcame this by making the NMOS width very small, and make the length bigger, to make the
drain current very small, and minimize the effect. Of course, there would still be error, but with
this, it made it small enough to not make much of a difference.
The last big challenge we had to overcome was the fact that the ADC output could not
drop immediately. It took about a microsecond for the output to fall from high to low, which
would create slight errors in our counter. The way we overcame this problem was to slightly
adjust our resistor value until we had the fall time we wanted. While this would not be accurate
for every value, if it was accurate for one value, the rest could be adjusted in code later to
minimize error.
Piecing together
Figure 19. Final Build Schematic
The last step in this process is to piece all of the parts together. In order to create a final
layout with everything put together, we created this into a symbol without any voltage sources.
Now comes making sure that they all work together.

Figure 20. 40 degree sim
I will start off by showing you how everything works together at the 40 degree mark.
This is since 40 degrees is about the halfway point. At this temperature, we expect the PTAT to
be right around 500 mV. That is because this is halfway at the halfway point of the PTAT’s
output range. As you can tell, this is correct.
The next thing that I want to draw your attention to is the ANDout which is displayed in
blue. This is the output of the and gate. When this starts, the ADC is outputting a 2.5 volt
output. This will stay high until the comparator reaches the PTAT voltage. That means that the
AND gate will stay on for a varying amount of time. The and gain is hooked up to the 1 Mhz
clock and the output of the ADC. That means its signal is going to be the 1 Mhz clock until the
ADC goes low. It is at this point that the 7BitCounter saves its value and stops changing. Figure
# shows the output of this 7BitCounter.

Figure 21. 40 degrees bit output
The output is 0b1000110 or 70 in decimal. Because the ADC starts at -23 degrees, to get
the associated temperature, you must subtract 23 from this raw value. The output of the adc
thinks that this is actually 47 degrees. This is still off, but a lot less than 30 degrees off.
Figure 22. Temperature Off chart.

As you can tell, the chart is correct at 100 degrees and slowly becomes less accurate as
the temperature drops. This decrease in temperature looks pretty linear as the temperature goes
down. Seeing this linear trend and after some advice from Dr. Chen we have decided to correct
this code in verilog instead of in the circuit.
Figure 23, Actual Temperature vs Displayed Temperature
In figure 23, you can see the actual temperature graphed with the displayed temperature.
Using this chart, you can generate a couple of different equations for the line. In these equations,
x is the displayed raw temperature output, and y is the expected temperature which is the actual
temperature plus 23. If we plug our RAW output into the equation, we will get the correct
output. You can be more detailed and add more polynomials but 1 polynomial looks like enough
to correct the math.
This is just one way of correcting the output, but Dr. Chen gave us a second equation for
correcting our output which will be discussed in the verilog section.

Layout:
Once the entire schematic was finished and the components being used were finalized we
moved on to creating a layout for our temperature sensor. This was done by initially creating the
layout for the individual components (resistors, op amp, capacitors, etc), then using those to
create the layout for the larger blocks of our system (PTAT, ADC, and counter), and finally
putting everything together to form the complete layout. In general, for our layouts poly layer
was only used to connect directly to the gates of a PMOS or an NMOS, metal 1 was used for the
actual contacts; connecting to the sources and drains of the MOS devices; and simple traces, and
metal 2 and 3 were used to route more difficult sections of the layout to avoid extra connections
that would cause our layout to not match our schematic.
Figure 24: 1 kΩ Resistor Layout
Figure 25: 1 kΩ Resistor Extract

The first components that we created were the resistors. In Figure 24 it can be seen that
the resistor by implementing the serpentine method of resistor layout using the poly layer as the
body or the resistor and then metal 1 as the contacts. In order for Cadence to recognize the layout
as a resistor we used the res_id layer to cover the body of the resistor and excluded the contacts.
This informs Cadence on what area to the resistance of. To calculate the resistance of a specific
resistor Cadence most likely separates the layout into a number of squares and corner squares of
equal length and width. It would then multiply the number squares by the sheet resistance of the
material being used for the resistor, corner squares being worth 0.55 of a normal square. As seen
in Figure 25, the value of the created resistor is displayed once the layout has been extracted.
Figure 26: 106.6 MΩ Layout
Figure 27: 106.6 MΩ Resistor Extract Value
For the larger resistors, like in Figures 26 and 27, we stacked more layers vertically and
then used the stretching tool in Cadence to expand the resistor horizontally. This allowed us to
make adjustments (lengthen or shorten) to the layout to get a more exact value. The contacts of
the larger resistors were also put closer together to make it easier to route later on since they
were so much larger than all of the other components in the end. In total we needed layouts for a
1 kΩ resistor, 1.5 kΩ resistor, 2.125 kΩ resistor, 2.875 kΩ resistor, 3.5 kΩ resistor, 10 kΩ
resistor, 13 kΩ resistor, 1 MΩ resistor, and a 106.6 MΩ resistor. We are not including all of these
in the report since they were created in the same way as the two that were previously mentioned.
Figure 28: 1p Capacitor Layout

Figure 29: 1p Capacitor Extracted Value
After the nine resistors needed in the system were made, we moved on to the capacitor
layouts. By overlapping metal 1 and metal 2 layers we created the body of the capacitors. There
were two contacts for the capacitor, one was connected to the metal 1 layer and the other was
connected to the metal 2 layer. This can be seen in Figure 29. We made both layers identical
rectangles to minimize the fringe capacitance. Similarly to the resistor layouts, Cadence would
only recognize the capacitor if it was covered with the cap_id layer and the capacitance values
were displayed in the extracted views. To calculate capacitance Cadence multiplies the area of
the overlapping materials by the capacitance densities between the materials. We once again use
the stretch tool in Cadence to make adjustments to the layout in order to obtain reasonable
values. Along with the 1pF capacitor we created a 25 pF capacitor
When creating the op amp layout, we used the generic PMOS and NMOS models from
the NCSU_TechLib_ami06 library that is provided in Cadence. By generating connectivity from
all sources, the sizes of the MOSFETs were automatically updated and the necessary pins were
imported into the layout. This made it easier to create the layout seen in Figure 30. The only
problem with using the generic MOS devices was that they lacked the bulk pin that we needed
for our layout to actually match our schematic, Figure 31. This was a simple fix, by attaching an
NTAP via to the VDD of each PMOS and a metal 1 to poly via to the VSS of each NMOS we
formed the bulk pins required for our 4 pin MOS devices.
Figure 30: Connectivity Menu Options

Figure 31: Op Amp Layout
Figure 32: Op Amp Extracted View and LVS

Once we were done with the op amp layout we moved onto the unity gain buffer. This is
because we were only adding to the op amp’s layout by routing an additional trace from the
negative input of the op amp, Vin, to the output, Vout.
Figure 33: Unity Gain Buffer Layout
Figure 34: Unity Gain Buffer Extracted View and LVS

The 2 input NAND gate that we used in the D Flip Flop (DFF) was made in a very
similar way as the op amp. The pieces of the NAND were generated using connectivity to its
schematic. Then from there it needed the proper routing and vias for Cadence to consider it as
the correct NAND gate.
Figure 35: 2 Input NAND Layout

Figure 36: 2 Input NAND Extracted View and LVS
When creating the 3 input AND gate, we decided that it would be best to use the 3 input
in NAND gate and inverter that we created in Labs 3 and 4. Because the NAND and inverter
layouts were already sized to match each other, we were able to conserve space by overlapping
the VDD and VSS of each, as seen in Figure 37. This allowed for a much more simple layout
since we only needed to connect the output of the NAND into the input of the inverter.
Figure 37: 3 Input AND Layout
Figure 38: 3 Input AND Extracted View and LVS
When creating the DFF layout, we used both the 2 and 3 input NAND gates and the
inverter that have all been previously mentioned. While all of these gates were similarly sized,
we decided that the easiest way to construct this layout was to spread out the gates. This gave us
enough room to route effectively primarily using metals 2 and 3 to avoid causing unwanted
connections. At first the pins were placed wherever they had room, but we later came back to
replace all of the pins so that the input pins were on the left and the output pins were on the right.
This is the layout that can be seen in Figure 39.
Figure 39: D Flip Flop Layout
Figure 40: D Flip Flop Extracted View and LVS

After finishing the DFF layout, we were able to move onto the seven bit counter layout.
This was a quite simple layout that only used seven of the previously made DFFs. The layout is
almost identical to the schematic. Each DFF shares a common VDD, VSS, CLEAR, and
PRESENT input. The first Clock input is from a pin and the rest of the DFFs have their clock
connected to the Q output of the previous DFF. And finally the D input of each DFF is connected
to its own 𝑄 output.
Figure 41: Seven Bit Counter Layout
Figure 42: Seven Bit Counter Extracted View and LVS
The next piece that we created a layout for was the PTAT. To do this we needed the op
amp, 1 kΩ and 10 kΩ resistors, and 5 additional PMOS transistors. We then routed them to their
respective connections. This can be seen in Figure 43. To include the summing amplifier we
needed the unity gain op amp, a second op amp, two 1 MΩ resistors, a 1 kΩ resistor, a 13 kΩ
resistor, a 2.875 kΩ resistor, and a 2.125 kΩ resistor. Because the mega ohm resistors are so large
the rest of the layout is barely visible.
Figure 43: PTAT Layout
Figure 44: PTAT Extracted View and LVS

Figures 45 and 46: 1 MΩ Resistor Layout (left) and Extracted View/LVS (right)
The ADC and the final layout were done in the same way as the PTAT. We took the
previously created layouts and combined then into an appropriate layout with the correct
connections so that they matched their respective schematics. The ADC layout (Figure 47)
required three op amps, three 25 pF capacitors, an NMOS, a 1pF capacitor, a 1.5 kΩ resistor,3.5
kΩ resistor, and a 106.6 MΩ resistor. And the final layout (Figure 50) where the entire
temperature sensor was put together needed the PTAT with gain, the ADC, the three input AND
gate, three 25 pF capacitors, the seven bit counter. Both the ADC and the final layout are quite
large due to the Mego Ohm resistors needed so most of the smaller components are barely
visible.We were unable to get the LVS to work with any of the layouts that used the capacitors.
We suspect that it is due to the three capacitances that appeared when creating the capacitor
layouts, as seen in Figure 29.
Figures 47 and 48: ADC Layout (left) and Extracted View (right)
Figures 49: ADC Layout Close Up
Figure 50: Final Temperature Sensor Layout

Figure 51: Final Temperature Sensor Extracted
Figure 52: Final Temperature Sensor Layout Close Up

Seven Segment Decoder
The final part was the seven segment decoder. For this lab, since it was not required, we
created the base concept of the code that, in a working model, would be synthesized and be put
on the layout. The purpose of the code was to take the seven bit output from the counter and turn
it into output that would turn on the corresponding parts of four common cathode seven segment
displays.
For our proof of concept design, we used case statements, as it was a bit easier to
implement. However, because this would require massive multiplexers, this sort of code could
not be synthesized. The other main part of the code was to fix errors in the counter. While it
would not totally mend the mistakes, it would get a lot closer to what it should have been. Below
are some examples of the code, as well as a modelsim simulation of how the code would work:
Figure 53. Verilog SSD

Figure 54. SSD Simulation
The code itself is not too complex. The first part converts the input into a decimal
number, so that math can be used with it. Then, the second part puts the code through an error
correction formula given by Dr. Chen. This would take the output from our counter and correct it
slightly to be closer to what it should be. Finally, it gets converted back into a binary number and
the case statement finds the correct output.
The simulation above shows the code’s function. For this example, an input of 79 was
used, which corresponds to a temperature reading of 56 degrees. The seven segment decoder out
consists of the top bit, which only controls the negative sign bit on the first seven segment
display. The next 21 bits correspond to the 3 sets of 7 inputs of the 3 seven segment displays that
would show the numbers. This output shows a seven segment display output of 57, which is very
close to what the output should be.

The main part of the code that would have to change is the case statement. Because
Cadence cannot just make a huge multiplexer, boolean logic would replace the case statements.
There would be 22 logic statements, each corresponding to the 22 outputs for the seven segment
displays. Other than this, the code would be able to be implemented in Cadence.
Conclusion
Overall, this temperature sensor was pretty accurate. Leaving the ADC, the device was
off by a linear amount. This meant that we were able to fix it in the code that ran to the seven
segment display. With the correction code, this meant that the display timer was very accurate
within 2 degrees at its furthest. It was also able to reset twice a second and give us a result after
128µ𝑆after resetting.
Some things that we would change for the future is to first add overflow protection and
a reset pin. We have this built into the “7BitCounter” where we can force all the bits inside to
either a zero or a one. We would also create an output for the “7BitCounter” that when all of the
bits are full, it goes to the third input of the AND gate and shuts it off. These were both built into
the system, but we did not have time to implement them into our final design. Next, we would
create the resistors more square like to minimize the space that they require. Right now they are
popostruslly long. Doing this will help minimize the size of our device. We also need to figure
out the capacitor so we can get the LVS to pass for anything that has a capacitor. Lastly, we
would go in and add larger resistors or MOSFETS inside of the voltage dividers. This will limit
the power that is used throughout our system.

Overall, we are very happy with our temperature probe. This has exceeded our
expectations and has taught us so much in the process of building it. I also hope that you have
enjoyed this light novel that we have typed. I have printed it all off and framed it on my wall.
Silver lining, I no longer have to buy wallpaper.

Works Cited
Wada, Ken. “Getting a Handle on Thermistor Temperature Measurement.”
Embedded.com, 2 June 2015,
www.embedded.com/getting-a-handle-on-thermistor-temperature-measurement/.
“Analog to Digital Converter: Single Slope and Dual Slope ADC Explained.” YouTube,
All About Electronics, 1 June 2019,
www.youtube.com/watch?v=2gF_nfaBV_0.

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EE 330 Final Project: A Temperature Sensor with Digital Output Joseph Kenkel, Jonah Stoffer, Marcus Kavars

Joseph Kenkel, Jonah Stoffer, Marcus Kavars

Final Project: A Temperature Sensor with Digital Output

designing a temperature sensing circuit called a Proportional to Absolute Temperature (PTAT)

Figure 1. PTAT build

going to be an in depth analysis of Mahmoud’s operational amplifier to better understand the

makes Vout smaller.

Figure 2. Geiger Excel Sheet

As mentioned inside of the introduction, PTAT stands for Proportional to Absolute

while the CTAT’s voltage will linearly fall.

demonstrated in the study conducted by Ken Wada and seen in Figure 3.

Figure 3. Resistance Vs Temperature

in voltage is due to the temperature.

Figure 4. PTAT Schematic

Figure 5. Diode Configured PMOS

Figure 5 represents a PMOS in a diode configuration. Whenever there is a p-doped

IP4*R1. Since IP4= IP3=IP2 we can deduce equation 4.

5. This produced the output of figure 6.

Figure 6. First PTAT

ran, we got an output that is shown in figure 7.

Figure 7. Linear PTAT Output

Figure 8. Nonlinear PTAT gain

The way that you would implement this is expressed in figure 9.

Figure 9. Start up circuit

Increase the PTAT’s Gain

Figure 10. Non-inverting summing amplifier

little trick, we get equation 8.

schematic in figure 11.

Figure 11. PTAT Gain Schematic

resistors in our layout vs the larger ones.

would have resulted in a smaller overall design than adding two𝑀Ωresistors.

Figure 12. PTAT Change

afterwards. These two voltages are almost exactly the same.

Figure 13. Plot of PTAT with Gain

wires to make up a binary number.

consisting of seven positive edge D-Flip-Flops.

explained further after this:

Figure 14. Final ADC Build

Figure 15. Integrator vs ADC Output

counter made up of D-Flip-Flops. These flip-flops were D-latches, arranged in master-slave

chain, as shown below:

Figure 16. D Flip Flop

Figure 17. Ripple Counter

ripple counter shown with the ADC output:

Figure 18. Counter vs. ADC

allow us to fix errors in Verilog later.

and a resistor value of 106 MΩ.

this, it made it small enough to not make much of a difference.

Figure 19. Final Build Schematic

Now comes making sure that they all work together.

Figure 20. 40 degree sim

output range. As you can tell, this is correct.

# shows the output of this 7BitCounter.

Figure 21. 40 degrees bit output

Figure 22. Temperature Off chart.

this code in verilog instead of in the circuit.

Figure 23, Actual Temperature vs Displayed Temperature

to correct the math.

correcting our output which will be discussed in the verilog section.

that would cause our layout to not match our schematic.

Figure 24: 1 kΩ Resistor Layout

Figure 25: 1 kΩ Resistor Extract