RCC 

: Reset CLock Control

Sets all register to their serset value except the reset flogin the clock controller CSR register and the
registers in the Backup domain

Generated when one of the following events occurs

 Low level on the NRST pin (external reset)

 Window watchdog end of count condition WWGD reset
 (watchdog is a counter for reset until count condition)
 Automaticly reset for safty ( loop
 Software reset ( SW reset is a bit in register for reset sytem )
 Low-power reset

RCC : Reset CLock Control

RCC clock control and status register

Software reset

 Can force a system reset by setting the SYSRESETREQ bit in arm cortex and reset control
register
 CMSIS function NVIC_SystemReset() can be used to initialite a system reset request

Low power management reset

 Reset generated when entering the Standby mode

 nRST_STDBY in the user option bytes : whenever a standby mode entry sequence
is successfully executed, the device is reset instead of entering the standby mode
 Reset when entering the stop mode
 Enabled by resetting the nRST_STOP bit in the user option bytes ; whenever stop
mode entry sequence is successfully executed, the device is reset instead of
entering the stop mode

POWER REST

Power on /power down reset

(POR / PDR reset ) or broownout (BOR) reset

When existing the standb mode

BACKUP DOMAIN RESET

Sets all RTC registers and the RCC_BDCR register to their reset value the BKPSRAM is not affected
by this reset.

The only why of resetting the BKPSRAM is the through the flash interface by requesting a
protection level change from 1 to 0 ;
Generated when one of the following events occurs

 Software reset triggred by setting the BDRST bit in the RCC Bachup domain control
register (RCC_BDCR)
 VDD or Vbat power on , is both supplies have previously been powred of

Clocks
HSI oscillator clock

HSE oscillator clock

main PLL clock

And the following secondary clock source

32 kHz low speed internal RC (LSI RC) for watchdog and optionnally drives the RTC clock (RTCCLK)

HIGH SPEED EXTENAL CLOCK

External source (HSE bypass)

Extenal crystal/ceramic resonator (HSE crystal)

Select the external clock using HSEBYP and HSEON bits in the RCCclock control register (RCC_CR)

HSERDY indicates if the high-speed external oscillator is stable on not

High speed internal clock

 Internal 16Mhz RC oscillator and can be used directly as a system clock or used as PLL input
 Providing a clock source at low cost (no extenal components)
 Faster startup source time than the HSE crystal oscillator however even with calibration
the frequency is less acccurrate than an extenal crystal oscillator or ceramic resonator
 HSI calibration is done by ST at factory and calibration data loaded in the HSICAL[7 :0] bits
after reset
 Application can also trim the HSI frequency if the application using voltage or temperature
can affect the RC oscillator speed
 HSI signal can also be used as a backup source (Auxillary clock) if the HSE crystal oscillator
fails

PHASE LOCKED LOOP PLL

Main PLL clocked by the HSE or HSi oscillator with two different clock output. One for high speed
system clock (up to 180MHz) and clock for the USB OTG FS 48Mhz the random analog generator
<48Mhz and the SDIO < 48Mhz

Tow dedicated PLL (PLL2ISand PLLSAI) used to generate and accurate clock toarcheive hight quality
audio performance

Main PLLconfiguration is done by choosing the clock source HSI or HSE and configuration of division
factors M, N, P and Q