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Page No 0 4
Expt. No

CxPE RIHENNT LO- 0

BaSIC GATES USIN6 MAND 6ATE

AIN io_uuali Sedhi basic dogle qah aND 9ali OR qah ound NDI
NAMD qalL
qal mm

Dhm|1hi) EDA
APPARATUS DC RULpply (5V/1A),Caaben asutos 220
11aime kit.
14DD Cnd brmad boand. IC
(Ld And Grttn 1

qalns 0 Ccacuit Loth accept enL Or more iopuk

PRINC1PLE oqic
th a pal-dutnminid logic
pnducSDmlyBnl Dtput accoding
a callled u tu basu doqie qali
AND ,OR a n d NOT qat
be combinud
can in a sequonto ko Dbtain
DI4eut basie9aies calleda
combinational
Such a clrtult is
the olsid output cpmbinakion ban AND Qale
circuit wiich A a
Logic cinult.od NAND Qai USing thn NAND
NOT gal i callud as
ollo wed by a nuQliALd emptoying the
basic e logic Qatu can loe
gal tuo
4otlouwing ole-Morgan'slaw
if (A.B)=A+8
1 ( A +B ) A ' B '
u
Dulput onls uhtn all
a 1GH
d ciacuit p1Ddudng
AND 6ate Qalh
callud an AND
Inp Lulsa n e HIGH
HhL
Loben anu
circuit_produci ng H16H output
OR 6ateA gali
1aH Callbd au_OR
înpus
Teacher'sSignature
Pal1o elly He NAND
7
400
PIN Dlaqam ot I

SV
19 13

D
Te 7400

13

Tabe- 1
Logve Agmbel kor NAND
Touth table ok NAND
YEAB 5ate.
A y AB

1
 Date
Expt. No.
Page No. 1O

NOT Gcte-A ciYcui pynducd ng a n n Outp ut whtch L tta

Compliminl,
t

invoaseD t nput is Callud NoT qali

Hbweveythee aar otbe loQtc qali3 for 01ampli, a circul

whi chpYOdus HlGH_oulput wbenonly when onodd numbT
BInpuui is HLGH caulled an EXCLUSIVE 0YL0T EXOR) Galn.

PRoCEDURE
Pantr-1 To vertu the wAUD gaBes of iC400
Step1 Th pin diagam u 10 1A00 shoun in jiqu

Step-2 PINS 1 and

Jheouput_c
au poyidd with fdpuk_A-and
pbtaunLd at PIN 3.
B tipeuhvel

Step-3-Tulh tabl tor MANID Qalh indabl iis waikild

Thi weai kil_ emL o he NAND Qat m th tC

Step-4 The pp.cLd LAn be Lpeakd torte plhN tHhyee MAND

pcuts QL0, wlu compluEAh_clhuckin9 h Qivin1

NOTE
und PIN gmtundid
Aluays tho PIN 1H s Lonnidlid to_t5Y

AnyRlnahingpoînt ioput vupresuni a Jogical t1GH

LED ttDugh a Auitaba rezitb?

*DutpLlE COnDectidto a
Teacher's Signature
 TROH YIPND GATEE
Expt. No.
REnLIZF OT
R T 1o

TA LED in OkL
FLGuPE2
A y

y- A
4D

PART
tep 1
PART-3 T0 REAIZE
Step2
FIGURE-3

Step3
y = AB
AB
3 PART
B 2

Step1
TABLE-3

AB Step2
Y AB
o
Step3
1 0 0

SyHBOL oF AND
Jate
PaRT

Step
 Date

Page No. 1
Expt. No.

*LED Ln OAL CEate upekei a diaital HiGtH and LED inDEE gtate
LphLLn a diqital L o

10 9ut a Logical Low [or a digdtal 0) tlu Irput

i gondid th0u4h
O ui labli usiuto

PART 0 ealize NOT 90te pm AND 4aHe

Slep1 Th ciacuit is mad asAkoun n kigulz

C_
Step2 PINS 1 Ond au_povidud with ÎnpilE ATh Dutpuf_
iu bbBaind at th PIN 3

tabu drauwn in tahl 2 for NOT 40li l_veuhid..

Step912uLth

1allse the AND 0te om uaND gat

PARr-3 10
shown m gu -3
Step 1 Tho ireut l connicted aL

the piN 6
Step2 The output y ik ebtolnid at

k0T AND Q0l7m_ table8 4 h e d 1his

tep3; Tuth tahdi
f AND 40li {mm_ thu Us bNAND gatu
e a i h s a l i s ah

29ale usíng the NAD

aRT4 0 alie th
Connectecdas Shoan miguR A
Step-1 the cisouit s
Teacher's Signature
 NAND
PTE
PART-4:o REALlE THE OR GATE USIg THE

FIGURE-4

y-A+ B

A
A
BY
B
Y-A+3 1

SyHBOL OF OR GATE
1
TABLE-4
 Date

Expt. No. Page No. 12

Step-2A Iha ou put Y u Dbtainsd at HAe Pin .

Step-3i uh dable for OR gatz m table 4 veuhitd h

eauiisAalisah en ot_Oe qal rom the UAe o MAND 4aus.
RESULT Basiéungtc qates AND qate, DR qatt, AMDT 4ate have be
Lachoc using NAMD qalis Lsing BOolean laus