IET Generation, Transmission & Distribution

Special Issue: Challenges and New Solutions for Enhancing Ancillary

Services and Grid Resiliency in Low Inertia Power Systems

Voltage unbalance compensation using new ISSN 1751-8687

Received on 31st January 2020
Revised 27th March 2020
structure of decouple double synchronous Accepted on 30th April 2020
E-First on 9th June 2020
reference frame in stand-alone microgrids doi: 10.1049/iet-gtd.2020.0209
www.ietdl.org

Mojtaba Ahmadi1, Shahram Karimi1

1Department of Electrical Engineering, Razi University, Kermanshah, Iran
E-mail: shahramkarimi@razi.ac.ir

Abstract: In distribution networks, the voltage unbalance occurrence is inevitable. The voltage unbalance can have negative
impacts on the customer equipment and the network performance if it exceeds the permissible limit. This study proposes a
novel control strategy to compensate for the voltage unbalance in stand-alone microgrids. The proposed control method applies
to the inverter-interfaced distributed generation units. The suggested control strategy is based on the decouple double
synchronous reference frame (DDSRF) that is modified to improve its effectiveness. The modified DDSRF can effectively
decouple the positive and negative sequence components. The simulation results depict that the proposed control strategy
provides faster dynamic response and more effective voltage unbalance compensation comparing to the DSRF-based control
method.

+
 Nomenclature kdqI proportional–integral controller of the positive current
control loop
V sabc line-to-neutral voltages at the PCC −
kdqI proportional–integral controller of the negative current
Iabc line currents supplied by the VSC control loop
+∗
vsdq positive sequence d–q components of the reference τi time constant of the current controller
voltage
−∗
vsdq negative sequence d–q components of the reference
voltage 1 Introduction
+
vsdq positive sequence d–q components of the voltage at the Nowadays, the continuity of the electricity supply and the voltage
PCC quality with considering the environmental and economic aspects
−
vsdq negative sequence d–q components of the voltage at the are the important issues related to the power distribution operation.
PCC Adopting the distributed generations (DGs) in the distribution
+
vtdq positive sequence d–q components of the voltage at the networks is the main approach of the electrical engineers for
DG terminal guaranteeing the continuous supply of the local and sensitive loads,
−
vtdq negative sequence d–q components of the voltage at the improving the power quality, decreasing the emission of
DG terminal greenhouse gases, via utilising renewable energy resources, and
+
idq positive sequence d–q components of the DG current decreasing the power transmission losses.
−
idq negative sequence d–q components of the DG current The presence of DGs in the distribution systems has introduced
+ a new structure called microgrid (MG). MGs can either be
ildq positive sequence d–q components of the load current
−
connected to the main gird or be operated in the islanded (or stand-
ildq negative sequence d–q components of the load current alone) mode. The difference between the islanded and stand-alone
+
idq DC term of positive sequence d–q components of the mode is that: in the stand-alone mode, MG is isolated from the
current main grid (off-grid); while in the islanded mode, MG can be able to
−
idq DC term of negative sequence d–q components of the operate in the grid-connected mode [1]. Both grid-connected and
current stand-alone MGs require special control systems. When MGs are
+′ positive sequence d–q components of the current after
idq connected to the main grid, the DG control system is responsible
transformation for injecting a specified amount of the active and reactive power to
−′ negative sequence d–q components of the current after
idq the grid. In this case, the main grid controls the frequency. In the
transformation islanded and stand-alone mode of operation, the control system is
+∗
idq positive sequence d–q components of the reference responsible for keeping the voltage and frequency within a
current permitted limit and preserving the system stability [2, 3].
−∗
idq negative sequence d–q components of the reference frame In the distribution networks, unbalanced loads can cause the
+
idq estimated DC term of positive sequence d–q components voltage unbalance. The voltage unbalance has negative impacts on
of the current the equipment, such as induction motors, electronic converters, and
−
idq estimated DC term of negative sequence d–q components adjustable speed drives. Additionally, the voltage unbalance cause
of the current more losses in the power systems [4]. Due to these drawbacks, the
+
Δidq positive sequence d–q components of the current error IEC recommends that the voltage imbalance in electrical systems is
−
Δidq negative sequence d–q components of the current error limited to 2%.
The unbalanced voltage can be compensated via the injection of
K P, K Q droop controller coefficients
+
the negative sequence voltages by using series active power filters
kdqv proportional controller of the positive voltage control (APFs) or dynamic voltage restorers [5]. It is also possible to
loop balance the voltage of the point of common coupling (PCC) by
−
kdqv proportional controller of the negative voltage control injecting the negative sequence currents and compensating the
loop unbalanced loads using parallel APFs and static synchronous

IET Gener. Transm. Distrib., 2020, Vol. 14 Iss. 22, pp. 5093-5103 5093
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compensators (STATCOMs) [6]. However, all these solutions
impose additional costs. Therefore, researchers used the surplus
capacity of the inverter-interfaced DGs, recently, to improve the
voltage quality in order to reduce the additional costs. For example,
PV-STATCOM in which a photovoltaic (PV) inverter can be
controlled as a STATCOM is proposed in literatures for voltage
control [7, 8]. PVs contain valuable inverters that hardly operate at
their maximum rated power because of the variation of solar
radiation over the day. Therefore, it is more efficient to use the
excess capacity of the inverters for compensating the voltage
unbalance [9, 10]. Indeed, one can use an appropriate control
method in the control system of inverter-interfaced DGs to improve
the voltage quality at the consumer's side [11].
The proposed method in [7] supposes that the current of
unbalanced loads is accessible. However, the unbalanced currents
of the local loads are generally inaccessible for the inverter-
interfaced DGs.
A hierarchical control approach for voltage unbalance
compensation is suggested by sending appropriate control signals
from a central secondary controller to the primary level in [12]. In
[13], local distributed energy resource (DER) controllers are
divided into primary and secondary levels to compensate for the
voltage unbalance. The secondary layer collects information from
all DERs and provides control rules for controlling the primary
level using the averaging technique. In [14], a hierarchical control
structure is used to control the voltage unbalance factor (VUF) of
the PCC and shares the unbalanced currents among generators.
Although the proposed approaches in [12–14] are highly effective,
• Introducing a modified DDSRF to increase the accuracy of the
oscillatory component estimation.
• Proposing a control system based on the modified DDSRF to
compensate for the unbalanced voltage in the dq reference
frame.
The remaining of this paper is organised as follows: Section 2
describes the structure of modified DDSRF. In Section 3, the
proposed control strategy for unbalanced voltage compensation is
presented. The simulation results are provided in Section 4.
Eventually, the conclusion and discussion are presented in Section
5.
2 Structure of the proposed DDSRF
The injection of the positive and negative sequences of the current
is essential to compensate for the unbalanced networks. So the
positive and negative sequence currents must be separated, which
can perform using DSRF. In the DSRF, in order to extract the
positive sequence, the currents in the αβ reference frame must be
rotated, with the system angular frequency ω, in the
counterclockwise direction. Also, to extract the negative sequence,
the currents must be rotated in the clockwise direction. After
rotating, the positive and negative sequence currents in the dq
reference frame comprise two terms, a DC term, and an AC term as
follows [25]:
+ − −
+
idq = +
idq + e− j θ idq −θ

the need for a communication link makes these approaches less ← − − − → ← − − − − − − − − − − − − − →

DC term AC term
reliable. (1)
− + +
In [15–18], the MG unbalanced voltage is compensated by −
idq = −
idq + e− j θ −θ
idq
using the control system implemented in the αβ reference frame. ← − − − − → ← − − − − − − − − − − − − − →
DC term AC term
However, current limiting, in order to prevent DG overload,
especially during fault conditions, is a major problem because the ±
signals fed to the controllers must be sinusoidal [19]. where idq = id± + jiq±, and
The MG unbalanced voltage can be compensated by using a
double synchronous reference frame (DSRF) in the dq reference id+ = I +cos δ+ − φ+
frame [20]. However, the cross-coupling between the positive and
negative sequence components in the dq reference frame degrades iq+ = I +sin δ+ − φ+
(2)
the efficiency of the control system [21, 22]. In [23], low-pass id− = I −cos δ− − φ−
filters were directly used in the DSRF-based control system to
reduce this cross-coupling. But the use of low-pass filters does not iq− = I −sin δ− − φ−
completely eliminate the oscillatory components and even cause
undesirable effects such as slow transient response and limiting the Also
bandwidth of the control system. In [24], decouple DSRF
(DDSRF) has been introduced to improve the performance of θ+ = ωt + φ+, θ− = − ωt + φ− (3)
phase-locked loop (PLL) under unbalanced and distorted
conditions. An enhanced DDSRF has been proposed in [25] for In the above equations, φ+ and φ− are the initial phases of the
using in the current controller under unbalanced voltage conditions positive and negative sequences of the voltage, respectively. Also,
to eliminate the oscillatory components. In this DDSRF-based δ+ and δ− are the initial phases of the positive and negative
current controller, it is assumed that the positive and negative sequences of the current. In addition, the dashed line ‘―’ denotes
sequence components of reference currents in the dq reference the DC component.
frame are completely DC. However, under unbalanced conditions According to (1)–(3), the frequency of the AC term is twice the
due to the cross-coupling effect, the oscillatory components can frequency of the system
also be generated in these reference currents.
Although, DDSRF is extensively used in the synchronisation θ+ − θ− = ωt + φ+ − ( − ωt + φ−) = 2ωt + φ+ − φ−
algorithms based on PLL, which so-called DDSRF-PLL, under (4)
unbalanced conditions [26], to the best of the authors’ knowledge, θ− − θ+ = − ωt + φ− − (ωt + φ+) = − 2ωt + φ− − φ+
there are not yet scientific study addressing the use of DDSRF for
unbalanced voltage compensation. Generally, to eliminate the oscillatory term, a low-pass filter is
In this paper, the DDSRF has been modified to increase the used. However, the low-pass filter cannot completely eliminate the
accuracy of the oscillatory component estimation. In addition, this oscillatory component. In order to solve this problem, an enhanced
paper proposes that the modified DDSRF can be used in the control DDSRF has been suggested in [25]. Fig. 1 shows the structure of
system of inverter-interfaced DGs to compensate for the this DDSRF. This method for elimination of cross-coupling effect
unbalanced voltage. The simulation results show that the proposed (oscillatory component) takes advantage of the following equations
control approach can effectively compensate for the unbalanced [25]: (see (5)) . As one can see in Fig. 1, for obtaining the current
voltage in stand-alone MGs. In addition, using the proposed control error mean value a low-pass filter is used
strategy, the load power can be appropriately shared among DGs
despite the unbalanced load connection. Furthermore, the proposed + + ωf ωf
Δidq = Δidq = i+dq∗ − i+dq′
method does not require any communication link, which increases S + ωf S + ωf
the reliability. (6)
− − ωf ωf
The main contributions of this paper can be highlighted as Δidq = Δidq = i−dq∗ − idq
− ′

follows: S + ωf S + ωf

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 Fig. 3  Positive sequence component of the current in the d-axis

extracted according to the following equations: (see (7)) . In (7),

the estimated DC terms are obtained as follows:

+ +′ S2 + ωn2
idq = idq ×
S + 2ξωn + ωn2
2

(8)
− −′ S2 + ωn2
idq = idq ×
S + 2ξωn + ωn2
2

Fig. 1  DDSRF presented in [25] In (8), S2 + ωn2 /S2 + 2ξωn + ωn2 is the transfer function of the notch
filter, ωn and ξ are the natural frequency and the damping ratio,
respectively.
In order to compare the DDSRF presented in Fig. 1 (that is
named hereafter as the conventional DDSRF) and the proposed
DDSRF, a simulation is carried out in the condition that the
positive sequence component of the reference current in the d-axis
is changed at t = 1 s. In this simulation, the reference current is
id+ ∗ = 4 + 2sin(120πt) after t = 1 s. As shown in Fig. 3 when the
reference current is not DC and has an AC term, the conventional
DDSRF cannot appropriately extract the DC component. In
contrast, the proposed DDSRF can correctly eliminate the AC term
and extract the DC component.

3 Proposed control system

Fig. 2  Proposed DDSRF
+∗
In addition, it is assumed that the reference currents, idq −∗
and idq ,
are completely DC and non-oscillatory. Since in unbalanced
conditions, the reference currents can also comprise the oscillatory
component, so the estimation of the oscillatory terms using the
reference currents does not have the required efficiency. Therefore,
as shown in Fig. 2, in the proposed DDSRF, the measured currents
and two notch filters are used, to estimate the oscillatory terms.
The notch filters are tuned to suppress the second-order harmonic
component. To extract the DC terms from the positive and negative
currents, the estimated oscillatory terms must be subtracted from
the measured currents. By using the proposed DDSRF, the positive
and negative sequence components in the dq reference frame are
The main purpose of this paper is voltage balancing at the PCC in
stand-alone MGs. Fig. 4 shows the proposed control system. The
inverter-interfaced DG is connected to the PCC through an LCL
filter. In order to separate the positive and negative sequence
components of the line and DG currents, two modified DDSRFs
are used. In addition, one modified DDSRF is applied to separate
the positive and negative sequence components of the voltage.
Using the positive sequence component of the voltage and the line
current, delivered active and reactive powers to the PCC are
calculated. The voltage and frequency droop controllers are
responsible for controlling the voltage amplitude and the MG
frequency. The droop controllers produce the positive sequence
components of the reference voltage. Then, by means of two
voltage control loops, the positive and negative sequence
components of the reference current are generated. Two inner
current control loops are used to control the positive and negative

+′ + − − + −
idq = +
idq + e− j θ −θ
idq − e− j θ −θ
.
(idq − Δidq) − ∗
−

← − − − → ← − − − − − − − − − − → ← − − − − − − − − − →
DC term AC term DC term
← − − − − − − − − − − − − − − − − − − →
Cross − coupling term
− + + − +
(5)
−′
idq = −
idq + e− j θ −θ
idq − e− j θ −θ
. +
(i+dq∗ − Δidq)
← − − − → ← − − − − − − − − − − → ← − − − − − − − − − →
DC term AC term DC term
← − − − − − − − − − − − − − − − − − − →
Cross − coupling term

+′ + − − + − −
idq = +
idq + e− j θ − θ idq − e− j θ − θ idq
← − − − → ← − − − − − − − − − − → ← − − − − − − − − − − − →
DC term AC term Cross − coupling term
− + + − + +
(7)
−′
idq = −
idq + e− j θ −θ
idq − e− j θ −θ
idq
← − − − → ← − − − − − − − − − − → ← − − − − − − − − − − − →
DC term AC term Cross − coupling term

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Fig. 4  Proposed control system

sequence components of the DG current. Finally, the switching
signals are produced via a PWM block. In Fig. 4, the negative
sequence components of the reference voltage in the dq reference
−∗ −∗
frame, V sd and V sq are equal to zero. In the following subsections,
the design procedure of each control block is explained.
3.1 Droop controllers in the unbalanced conditions
problems, the virtual impedance is implemented in the control
system. The most important advantage of the virtual impedance is
the tuning of DG output impedance. This means that by employing
the virtual impedance, not only the output impedance of the
parallel DGs will be equal; the inductive property will be enhanced
as well. So, by adding the virtual impedance loop the required
+∗ +∗
reference voltage V sd and V sq are generated.

Based on the theory of the instantaneous powers, the delivered 3.3 Voltage controller design
active and reactive powers to the PCC caused by positive sequence
components are as follows: The dynamic model of the LCL filter can be achieved by using
KCL at the point of the capacitor connection. After transforming to
3 + + the dq reference frame, the following equations are obtained:
Ps+ t = +
V t i t + V sq t iq+ t (9)
2 sd d
+
dV sd t
3 Cf = id+ t − iLd
+ +
t + C f ω t V sq t (13)
+ +
Qs t = −V sd t iq+ t + V sq
+
t id+ t (10) dt
2
+
dV sq t
After calculating the active and reactive powers, using the voltage Cf = iq+ t − iLq
+ +
t − C f ω t V sd t (14)
dt
and frequency droop controllers, the PCC voltage and the
frequency are regulated as follows [27]: −
dV sd t
Cf = id− t − iLd
− −
t − C f ω t V sq t (15)
f − f 0 = − KP Ps+ − P0 (11) dt
−
dV sq t
V − V 0 = − KQ Qs+ − Q0 (12) Cf = iq− t − iLq
− −
t + C f ω t V sd t (16)
dt
where f0 and V0 are the rated frequency and voltage, respectively.
where ω t = dρ/dt .
Also P0 and Q0 are the tuned active and reactive powers, Equations (13)–(16) show that there is a coupling between V sd
respectively. and V sq for both positive and negative sequence components. To
Actually, droop control is an imitation of the steady-state
eliminate this coupling, the feed-forward compensator is used. In
treatment of synchronous generator, where by increasing demand
order to design the voltage controllers, the simplified block
for the active power, the frequency is reduced and vice versa. The
diagram of the closed-loop voltage control system for both positive
main advantage of the droop method is that it does not require a
and negative sequence components is considered as shown in
communication link for load sharing, which increases the reliability
of the system. Therefore, the droop controllers produce a sinusoidal Fig. 5. In this figure, kd±, qv denotes the voltage controller, and τi is
waveform as the positive component of the reference voltage. the desired time constant of the closed-loop current control system
which is explained in the next part.
3.2 Virtual impedance Since the transfer function of the open-looped voltage control
system has a pole in the coordinate origin, the steady-state error of
The voltage and frequency droop controllers can only perform the closed-loop system is zero. Therefore, one can consider the
correctly if the line reactance is much greater than the line kd±, qv as a proportional control with the value of k pv. Thus,
resistance. Also, the impedance between each DG and the PCC according to Fig. 5, the transfer function of the open-looped
(including transmission line impedance and the output impedance voltage control system can be attained as follows:
of DGs) is generally different. Therefore, resulting in unequal
power-sharing among DGs. In addition, the line impedance is not kpv 1
essentially inductive. Consequently, in this condition, the droop T olv s = (17)
C f s τis + 1
controllers are no longer effective. In order to overcome these

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Fig. 5  Simplified block diagram of the voltage control loop

Fig. 6  Simplified block diagram of the current control loop

3.4 Current controller design

The dynamic model of voltage source inverter (VSI) can be
obtained by applying KVL in the VSI output loop. After
transforming to the dq reference frame, one can deduce

did+ t
L + R + ron id+ t
dt (18)
+ + +
= V td t − V sd t + Lω0iq t

diq+ t
L + R + ron iq+ t
dt (19)
+ + +
= V tq t − V sq t − Lω0id t

did− t
L + R + ron id− t
dt (20)
− − −
= V td t − V sd t − Lω0iq t

diq− t
L + R + ron iq− t
dt (21)
− −
= V tq t − V sq t + Lω0id− t

where

± V dc ±
V td t = m (22)
2 d
Fig. 7  PCC voltage and VUF when DSRF-based method is used
± V dc ±
V tq t = m (23) (a) PCC voltage, (b) VUF
2 q
Fig. 6. To control of the VSI currents a proportional–integral (PI)
Equations (18)–(21) show that there is a coupling between Id and Iq controller is considered where
for both positive and negative sequence components. To eliminate
this coupling, the feed-forward compensator is used. Considering ki
the control variable as follows: kd±, qI = kp + (26)
s
udq(t) = V tdq t − V sdq t ± Lω0idq t (24) Based on Fig. 6, the transfer function of the open-loop system can
be written as follows:
The dynamic model of VSI can be represented in Laplace domain
as kp s + ki /kp
T ol s = (27)
± Ls s + R + ron /L
± udq
idq = (25)
Ls + R + ron Considering (27), it is clear that, the transfer function of the open-
loop system has a stable pole at p = − (R + ron)/L. Typically, this
The block diagram of the closed-loop current control system for pole is fairly close to the origin and corresponds to a slow system
both positive and negative sequence components are illustrated in

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Table 1 Parameters of the test system with one DG
Parameter Value
peak phase voltage, V 391
DC link voltage, V 1500
nominal frequency, Hz 60
switching frequency, kHz 3
inverter filter inductance, μH 100
inverter filter capacitance, μF 2500
line impedance, Ω 0.01 + j3.7
damping coefficient of notch filter (ξ) 0.707
kpv 1.6
kp 0.2
ki 4.14
KP 6 × 10−6
KQ 2 × 10−3

response. In order to improve the frequency response of the 3 + − + − − + − +

Psc = V i + V sqiq + V sd id + V sqiq (35)
system, this pole can be cancelled by the zero of PI controller. 2 sd d
Therefore, the PI controller parameters can be designed as
3 + − + − − + − +
ki R + ron Pss = V i − V sqid − V sd iq + V sqid (36)
2 sd q
= (28)
kp L
3 + − + − − + − +
Qsc = −V sd iq + V sqid − V sd iq + V sqid (37)
kp 1 2
= (29)
L τi
3 + − + − − + − +
Qss = V i + V sqiq − V sd id − V sqiq (38)
where τi is the desired time constant of the closed-loop current 2 sd d
control system and it can be obtained from the closed-loop transfer
function. The closed-loop transfer function is As can be seen from (35)–(38), the negative sequence components
cause the oscillatory component in the instantaneous active and
± reactive powers. Since, for compensating the unbalanced voltage,
i
d, q s 1
Gi s = = (30) the current that contains the negative sequence component must be
±
i
d , q ref s τis + 1 injected by the inverter-interfaced DG, the power oscillation is
inevitable, even if the voltage at the PCC becomes quite balanced.
To have a fast dynamic response, τi should be very small. On the
other hand, very small value of τi leads to the large bandwidth of 5 Simulation results
the closed-loop control system. Thus, the value of τi should be
In this section, in order to show the efficiency of the proposed
carefully chosen.
control strategy, two test systems are simulated using
SimPowerSystems/Simulink.
4 Instantaneous power under unbalanced
conditions 5.1 Test system with one DG
Considering the voltage and current sequence components in the dq The first test system is an inverter-interfaced DG that feeds the
reference frame, the complex instantaneous power delivered to the balanced and unbalanced loads connected to PCC (see Fig. 4). The
PCC is calculated as follows: parameters of this test system are listed in Table 1. The balanced
load is a balanced three-phase Y-connected load with the
3 jωt + ∗
ss = e V sdq + e− jωtV sdq
−
t e jωtidq
+
+ e− jωtidq
−
(31) impedance of 50 + j50 Ω per phase. At t = 0.4 s, a resistor with the
2 resistance of 50 Ω, as the unbalanced load, is connected between
phases a and b. The unbalanced load connection causes the voltage
By separating the real and imaginary parts, one can deduce unbalance at the PCC.
Fig. 7a depicts the PCC voltage while the unbalanced voltage
ps(t) = Ps + Psccos(2ωt) + Psssin(2ωt) compensation is performed using the control method based on
(32)
qs(t) = Qs + Qsccos(2ωt) + Qsssin(2ωt) DSRF. As one can see in Fig. 7a, this control method cannot
effectively compensate the unbalanced voltage. Fig. 7b presents the
where PS and QS are the average parts of the instantaneous active VUF for the PCC voltage in this case. This figure demonstrates
and reactive powers, respectively. According to (32), under that although the control method based on DSRF reduces the VUF,
unbalanced conditions, in addition to the average part, the its value remains unacceptable. In this case, the VUF is about 6%
instantaneous powers also contain the oscillatory parts with the at the steady-state. It is important to note that, according to the IEC
frequency equal to 2ω. The average parts of the instantaneous definition, the VUF is defined as the ratio of negative sequence
active and reactive powers are as follows: component to the positive sequence component, and this factor
must be limited under 2% in the steady-state conditions.
3 + + Fig. 8a shows the PCC voltage when compensation is
+ + − − − −
Ps = V i + V sqiq + V sd id + V sqiq (33) performed using the control method based on the conventional
2 sd d
DDSRF. In this control method, two conventional DDSRF is used.
The first conventional DDSRF is used in the voltage control loop
3 + + + + − − − −
Qs = −V sd iq + V sqid − V sd iq + V sqid (34) and the second one is used in the current control loop. As observed
2
in Fig. 8a, the unbalanced voltage compensation is carried out in
the steady-state conditions, but the voltage unbalance is still
and the oscillatory parts are deduced using the following equations:
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Fig. 8  PCC voltage and VUF when the conventional DDSRF-based Fig. 9  PCC voltage and VUF when the proposed method is used
method is used (a) PCC voltage, (b) VUF
(a) PCC voltage, (b) VUF

considerable at 0.1 s after connection of the unbalanced load to the

PCC. It is found in Fig. 8b that for the conventional DDSRF based
method, the VUF enters the allowable limits after 0.2 s, but again
at t = 0.8 s it exceeds allowed limit and at the steady-state the VUF
reaches 1.8%.
Fig. 9a illustrates the PCC voltage when the proposed control
strategy is used for compensating the unbalanced voltage. This
figure shows that the proposed control strategy effectively
compensates the unbalanced voltage. Fig. 9b indicates that with the
proposed method t = 0.532 s, the VUF is reduced to 2%, and in the
steady-state conditions its value remains less than 1%.
The positive and negative sequence components in the dq
reference frame for all control methods are shown in Figs. 10 and
11. As it can be seen, the positive sequence component in the d-
axis tracks its reference (391 V), and the positive sequence
component in the q-axis, and the negative sequence components in
the d- and q-axis are tracking zero, which is evidence of the proper
performance of the inverter control system. In addition, it is
observable that the amplitude of voltage oscillation in the negative
sequence component in the d- and q-axis in the DSRF-based
control method is so much and therefore, this method cannot Fig. 10  Positive sequence components
effectively compensate the unbalanced voltage. As shown in
Fig. 11, the conventional DDSRF based method, decreases the the oscillation of negative sequence components in the d- and q-
oscillation of negative sequence components. However, it can be axis, and as a result, the VUF in this case is much smaller than the
seen that the oscillations are not completely damped. As one can VUF in the cases that other methods are used for compensating the
see in Fig. 11, the proposed control method decreases effectively unbalanced voltage.

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Fig. 11  Negative sequence components
Fig. 12  DG active and reactive powers
Fig. 12 shows the output active and reactive power of the DG
unit. This figure depicts that the proposed control method and the
conventional DDSRF-based method provide faster dynamic
response compared to the DSRF based technique. Also, as can be
seen in Fig. 12, after the unbalanced load connection, the power
oscillation occurs due to the injection of negative sequence current
by the DG unit.
The output voltage and the output current of the DG unit, and
VUF at DG output terminal are presented in Fig. 13. As seen, after
connecting the unbalanced load, the negative sequence current,
which is injected to compensate the unbalanced PCC voltage,
causes the output current of the DG unit to become unbalanced.
Consequently, the flow of the unbalanced current through the line
impedance causes the output voltage of the DG unit to become
unbalanced. Therefore, VUF of the output voltage of the DG
increase to 7% in the steady-state conditions.
5.1.1 Severe unbalanced load connection: To compare the
efficiency of the conventional DDSRF-based method and the
proposed control method, instead of the previous unbalanced load,
a resistor with the resistance of 20 Ω is connected between phases
a and b, as a severe unbalance load, at t = 0.4 s. To avoid the
repetition of figures, only the negative sequence component in the
d-axis and VUF of the PCC voltage are presented. As one can see
in Fig. 14, when the proposed control strategy is used, the
amplitude of oscillation is much smaller than when using the
conventional DDSRF-based control method. Using the proposed
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Fig. 13  Voltage, current and VUF at the DG output when the proposed
method is used
(a) Voltage, (b) Current, (c) VUF
control method, the amplitude of negative sequence component is
1.12 V in the steady-state condition, while using the conventional
DDSRF-based control method, the amplitude of negative sequence
component is 21.6 V. It is also observed in Fig. 15, the VUF of
PCC voltage is 5.59% when the conventional DDSRF-based
control method is used.
However, as depicted in Fig. 15, using the proposed method the
VUF is <2%. It can be concluded that the proposed method is more
efficient compared to the conventional DDSRF-based control
method.
5.2 Test system with two DGs
The second test system consists of two inverter-interfaced DG
units. Fig. 16 depicts this test system. The parameters of this test
system are presented in Table 2. It is necessary to explain that the
structure and specifications of the second test system are similar to
those used in [28]. In this case, the balanced load is a balanced
three-phase Y-connected load with the impedance of 50 + j12.5 Ω
per phase. At t = 0.2 s, a resistor with the resistance of 100 Ω, as
the unbalanced load, is connected between phases a and b. To
avoid increasing the figures, in this case, only the figures
corresponding to the VUF, the output power of DG units, and the
frequency of the test stand-alone MG are presented when the
proposed control strategy is used.
Fig. 17a illustrates that after unbalanced load connection, the
VUF of the PCC voltage is reduced to 2% at t = 0.2836 s, and it is
<1% in the steady-state conditions. Figs. 17b and c show the VUF
of the output voltage of DG1 and DG2, respectively. These figures
depict that the contribution of the DG units for compensating the
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Fig. 14  Negative sequence component in the d-axis when sever
unbalanced load is connected

Fig. 15  VUF of the PCC voltage when sever unbalanced load is connected

Fig. 17  VUF of the voltage at

(a) PCC, (b) DG1 terminal, (c) DG2 terminal

Fig. 16  Structure of the second test system

Table 2 Parameters of the test system with two DGs

Parameter Value
peak phase voltage, V 311
DC link voltage, V 650
nominal frequency, Hz 50
switching frequency, kHz 10
inverter filter inductance, mH 1.8
inverter filter capacitance, μF 25
line inductance, mH 1.8
damping coefficient of notch filter (ξ) 0.707
kpv 12.7
kp 9
ki 15
KP 3 × 10−4
KQ 0.27 Fig. 18  Active and reactive powers of DG units

6 Conclusion and discussion

unbalanced voltage at the PCC causes the unbalanced voltage at
the terminal of both DGs.
Power sharing among DG units is shown in Fig. 18, as seen,
using the proposed control strategy, the active and reactive powers
are appropriately shared among DGs, despite the unbalanced load
connection. Also, as can be illustrated in Fig. 18, after the
unbalanced load connection, the power oscillation occurs due to
the injection of negative sequence current by both DG units.
The frequency of the test stand-alone MG is presented in
Fig. 19. This figure indicates that the frequency is also properly
regulated.
In this paper, the unbalanced voltage at PCC in stand-alone MGs is
compensated using inverter-based DGs. The unbalanced voltage
compensation is performed by using the proposed control strategy
that is based on the modified DDSRF. The design procedures of the
control parameters are described in detail. In order to evaluate the
effectiveness of the proposed control strategy, two test systems are
considered. The first test system is an inverter-interfaced DG that
feeds the balanced and unbalanced loads, and the second test
system is a stand-alone MG that consists of two inverter-interfaced
DG units. The simulation results depict that the proposed control
method provides a fast dynamic response, and the VUF at the PCC
is reduced to 2% less than 0.2 s after unbalanced load connection.

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Fig. 19  Frequency of the test stand-alone MG
In addition, the VUF in the steady-state conditions remains less
than 1%. Furthermore, the comparison between the DSRF-based
method, the conventional DDSRF-based method, and the proposed
control method is done for different loads in the first test system.
The simulation results show that the proposed control method can
effectively compensate the unbalanced voltage even under severe
unbalanced load connection, while other methods can not satisfy
the permissible limit and VUF exceeds 2%.
Since, in the proposed approach for compensating the
unbalanced voltage at PCC, the current, which contains the
negative sequence component is injected by the inverter-interfaced
DG, the DG's terminal voltage will be unbalanced. In addition, as
presented in Section 4, the negative sequence component causes
also the oscillatory component in the instantaneous active and
reactive powers. The power oscillation causes the issues that
should be taken into account. The oscillation in the DC-link
voltage (if the DC-link capacitor is used), and the possibility of
overloading the inverter are the issues that should be considered in
the control system. In order to prevent overloading of the inverter,
current limiter should be considered for the reference currents in
the current control loop.
As shown in Section 4, under unbalanced conditions, the
instantaneous active and reactive powers contain the oscillatory
components with the frequency equal to 2ω. In this paper, the
inverter-interfaced DG is a grid-forming inverter, and thus the
inverter is connected to a stiff DC source. However, in the grid-
following inverters, the oscillation components flow through the
DC-link capacitor and cause the oscillation with the same
frequency on the DC-link voltage. This oscillation component
degrades the converter functionality and imposes more stress on
the capacitor, and converter switches. In this case, as the power
increases or the DC-link capacitance decreases, the ripples on DC-
link increases. Then, the capacitance should be selected high
enough to mitigate the ripples. For grid-following inverters under
unbalanced conditions, to reduce the capacitor size while keeping
the level of ripples low, a proportional–integral–resonant (PIR)
DC-link controller can be used [29]. In this controller, the PI
compensator is responsible for regulating the DC component of the
DC-link voltage, while the PR compensator controls the 2ω
component and forces it to zero.
Regarding to the above descriptions, the limitations of the
proposed control strategy as well as the issue that need to be
considered in order to extend the proposed approach are
summarised as follows:
Limitations:
• It is assumed that there is no load connected to DG's terminal.
So, the unbalanced voltage at the DG's terminal does not
negative impact on the loads.
• It is assumed that the inverter has sufficient capacity for
unbalanced voltage compensation.
Requirement to extend the proposed method:
• In order to extend the proposed control strategy for grid-
following inverters, instead of the conventional DC-link
controller, a PIR controller should be used, or the DC-link
capacitance should be selected high enough to mitigate the
ripples with the frequency of 2ω.
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According to the aforementioned, finding the solutions for a trade-
off between unbalanced voltage compensation and power
oscillation reduction can be considered as a topic for future
researches.
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