Laboratory-Scaled STATCOM for Unbalanced
Voltage Sag Mitigation by Decoupled Double
Synchronous Reference Current Controllers
Carlos Roberto Amaya-Rodríguez and Chia-Chi Chu
Department of Electrical Engineering
National Tsing Hua University
HsinChu, Taiwan, R.O.C.
Email: carlos.amaya.hn@gmail.com; ccchu@ee.nthu.edu.tw.
Abstract—This paper presents implementations of a laboratory-
scaled static synchronous compensator (STATCOM) for reactive
power compensation for unbalanced voltage sags. In order to
attenuate the effects of coupling terms between sequence
components, double decoupled synchronous reference frame
(DDSRF) current controllers are implemented. Under this
framework, adequate decoupling between positive and negative
sequence components can be achieved. PSCAD/EMTDC
simulator is used to verify implementation results. A 2kVA, 220
V AC, 60 Hz laboratory-scaled STATCOM platform is
constructed for evaluating the dynamic performance of the
DDSRF-based STATCOM when unbalanced voltage sags occur
in a weak grid.
Keywords—Voltage Sag; Unbalanced Systems; Static
Synchronous Compensator (STATCOM); Double Decoupled
Synchronous Reference Frame (DDSRF);Weak Grid;
I. INTRODUCTION
T he voltage sag is one of the most common power quality
problems. Nowadays, minor voltage sags which once
would have been noticed only as a momentary flickering of
the illumination systems, may now completely interrupt large
automated factories due to the vast use of sensitive electronic
controllers, thus, resulting in substantial financial losses [1].
Common causes of over-currents leading to voltage sags are:
large induction motor starting, transformer energizing,
overloads, and short circuit faults [2]. Mitigations schemes
and strategies for improving system performance and
immunity to sags are presented in [3].
The Static synchronous compensator (STATCOM) has
shown to be a reliable shunt connected FACTS device capable
to provide reactive power compensation during voltage sags
[4-6]. The most common control strategy is based in the dq
synchronous reference frame, offering two major advantages:
a direct relationship of active and reactive power with the dq
current components, and it can be achieved through classical
PI controller, thus, it has been broadly accepted in industry.
The STATCOM offers an excellent dynamic performance,
small footprint, and high efficiency in controlling reactive
power, thus improving power system efficiency and stability
[7-9]. Furthermore, a number of studies have confirmed that
This work was supported in part by the National Science Council of Taiwan,
R.O.C., under Grant NSC 98-3114-E-007-004 and NSC 100-3113-E-007-006.
STATCOM is an appropriate solution to mitigate voltage
unbalances in the grid caused by fluctuating loads such as arc
furnaces [10,11]. In addition, fast and precise regulation of the
voltage at critical loads and fulfillment of the reactive currents
requirements of distributed generators connected to the grid
[12-14] stand out among the possibilities of the STATCOM.
Mitigation of unbalanced voltage sags is addressed in [16-
18] where voltage and current sequence components are
considered to produce an unbalanced set of compensating
currents based on the double synchronous reference frame
(DSRF) scheme. Filtering techniques were used to attenuate
the effects of coupling 2 ω terms between the sequence
components. The drawback of this approach is the inherent
reduction of controller bandwidth caused by direct influences
of filters in the control loop. To overcome this problem, recent
studies have confirmed that cancelation of the 2ω terms can be
achieved by the use of double decoupled synchronous
reference frame (DDSRF) current controller [18,19]. In this
paper, we will apply this technique for STATCOM
applications to ensure adequate decoupling between positive
and negative sequence components.
This paper is organized as follows. In section 2, the
electrical structure and control architecture of the STATCOM
are reviewed. Section 3 presents the development of the inner
loop current controller. Both DSRF and DDSRF schemes will
be examined. Section 4 introduces the outer voltage loop for
unbalanced sag compensation. The implementation of a
220VAC, 2.0 KVA laboratory-scaled STATCOM platform
evaluates the performance of the DDSRF current controller for
unbalanced voltage sag mitigation in section 5. These results
are also validated through PSCAD/EMTDC simulations.
II. STATCOM CONTROL
A. STATCOM Electrical Structure
Fig. 1 shows a STATCOM connected to the power grid.
The voltage-sourced converter (VSC) is connected to a
capacitor in the DC side (CDC) to provide energy storage. In
the other hand, the AC terminals of the VSC are interfaced
with the grid through an inductive filter and an isolation Δ-Y
transformer with 1:1 ratio (Lf=Lfilter+Ltr). The VSC AC
terminal voltages are denoted by Vta, Vtb, and Vtc. In Fig. 1, the sequence components of current controllers in the
resistance of the inductive filter (Rf) is combined with the synchronous reference frame (SRF), two new schemes will be
switching devices loss resistance (ron). In order to stabilize and examined: (i) double synchronous reference frame (DSRF)
filter the harmonic content at the PCC, a shunt capacitance scheme, and (ii) double decoupled synchronous reference
filter, Cf is added. The resistance Rf1 in series with Cf, provides frame (DDSRF) scheme.
damping at the resonance frequency. The point of common
A. Double Synchronous Reference Frame (DSRF) Control
coupling (PCC) voltages are labeled as Vsa, Vsb, and Vsc. In the
Fig. a load is also connected to the PCC. The grid voltages are
denoted by Vga, Vgb, and Vgc and the power line inductance is
represented by Lg.

Fig. 2. DSRF current controller.

Control of the positive sequence component of injected

Fig. 1. Schematic diagram of STATCOM.
current was achieved by the SRF current controller fed with
B. Control Architecture the positive sequence angle provided by the PLL. Similarly, it
The control architecture of the STATCOM is illustrated in is reasonable to extract the angle of the negative sequence
Fig. 1. The real power exchange between the STATCOM and component of the PCC voltage and use it to feed a second SRF
the power grid is governed by the phase difference between controller, therefore control a negative sequence current to
the PCC and STATCOM terminal voltages, regulating in this provide reactive power compensation under unbalanced
way the DC bus voltage. Meanwhile, the reactive power is voltage sags. A complete controller would have two
governed by the magnitude difference between these two synchronous reference frames rotating at fundamental
nodes, thus, controlling the PCC voltages. For the purpose of frequencies in opposite directions [15,23]. This structure,
reactive power compensation under unbalanced sags, an shown in Fig. 2, is referred as double synchronous reference
effective sequence component detection of the voltages and frame (DSRF) [18,19].
currents is required. Therefore, an appropriate phase-locked The current vector injected into the grid by this controller is
loop (PLL) structure is used to calculate the phase angle and given by
frequency of the system. The measured voltages and currents ⎡ ⎤ ⎡ ⎤
⎢ sin(ω t + δ + ) ⎥ ⎢ sin (ω t + δ − ) ⎥
are transformed into dq-synchronous reference frame, aided ⎢ ⎥ ⎢ ⎥ (1)
+ ⎢ 2π ⎥ − ⎢ 2π ⎥
by the Park transformation. As a result, DC values express the i = I sin(ω t + δ − +
) + I sin (ω t + δ + −
)
⎢ 3 ⎥ ⎢ 3 ⎥
measured signals, facilitating independent control of active ⎢ ⎥ ⎢ ⎥
⎢ sin(ω t + δ + + 2 π ) ⎥ ⎢ sin (ω t + δ − − 2 π ) ⎥
and reactive power by using PI controllers. ⎢⎣ 3 ⎥⎦ ⎢⎣ 3 ⎥⎦
For the purpose of voltage regulation at the PCC, two
control loops, namely, outer voltage control and inner current And its projection on the positive- and negative- SRF, rotating
control are employed. The voltage control loop generates the at +ω and –ω, respectively, can be expressed as
reference signals for the current controller in the inner loop ⎡ id + ⎤ ⎡ i d ⎤ ⎡ i d ⎤
+ +
⎡ cos(δ + ) ⎤
based on deviations of the PCC and DC bus voltages. The
+
idq = ⎢ + ⎥ = ⎢ + ⎥ + ⎢ + ⎥ = I+ ⎢ ⎥
⎢⎣ iq ⎥⎦ ⎢ i q ⎥ ⎢⎣ i q ⎥⎦ ⎢⎣ sin( δ ) ⎥⎦
+

current control loop produces the desired modulation signals ⎣ ⎦   

(2)
D C term s
that are sent to the space vector pulse width modulation
⎡ cos( 2 ω t ) ⎤ − ⎡ sin( 2 ω t ) ⎤
(SVPWM) module and generate the gate pulses for the VSC. + I − co s(δ − ) ⎢ ⎥ + I sin (δ ) ⎢
−
⎥
− sin(
⎣  2 ω t ) ⎦     ⎣  cos( 2 ω t ) ⎦
   

III. CURRENT CONTROL STRUCTURE FOR UNBALANCED A C term s

CURRENT INJECTION
Under unbalanced grid faults, the currents injected by a ⎡ id − ⎤ ⎡ i d ⎤ ⎡ i d ⎤
− −
⎡ cos(δ − ) ⎤
STATCOM might include negative-sequence components;
+
idq = ⎢ − ⎥ = ⎢ − ⎥ + ⎢ − ⎥ = I− ⎢ ⎥
⎢⎣ iq ⎥⎦ ⎢ i q ⎥ ⎢⎣ i q ⎥⎦ sin(δ − ) ⎦⎥
⎣⎢  (3)
therefore inject a set of unbalanced currents. In order to ⎣ ⎦ 

D Cterms
attenuate the effects of coupling 2 ω terms between the ⎡ cos(2ω t ) ⎤ + ⎡
− sin(2 ω t ) ⎤
+ I + cos(δ + ) ⎢ ⎥ + I sin(δ ) ⎢
+

⎣ sin(2 ω t ) ⎦ ⎣ cos(2 ω t ) ⎥⎦
  

AC term s
 In the above two equations (2)-(3), the appearance current errors ΔI+ and ΔI-, are free from oscillations, thus a
of 2 ω cross-coupling oscillations overlapping opposite low pass filter with cut-off frequency ω f = ω 2 can be used
sequence DC magnitudes is observed. PI controllers achieve to filter them, as proposed in [23] for PLL applications. Fig. 3
good tracking of the DC terms; however, the 2 ω oscillations shows the DDSRF current controller implementations.
produce steady state errors different from zero, thus causing
oscillations in the power delivered by the STATCOM. III. PCC AND DC VOLTAGE REGULATORS
B. Double Decoupled Synchronous Reference Frame The outer loop control of the STATCOM provides regulation
(DDSRF) Control of PCC and DC bus voltages, thus dictates the power
exchange dynamics. If the STATCOM guarantees balanced
The oscillations in the measured dq-currents under voltages at PCC, it is assumed that only the d-positive
unbalanced conditions must be avoided in order to provide sequence component of the voltage has a nonzero value, i.e.:
suitable compensating currents to regulate both, the PCC and Vd+=Vdref+, Vq+=0, Vd-=0, and Vq-=0. In the other hand, the
DC bus voltages of the STATCOM. The DDSRF current DC bus voltage, VDC, should remain constant at reference
controller minimizes the undesired oscillations by providing a value, VDC*. The convenience of controlling VDC2 instead of
decoupling structure based in the estimation of the amplitude VDC was presented in [22], given its direct relation with real
and phase of the coupling terms, maintaining the integrity of power.
the control loop [18,19] .
From (2) and (3), it is observed that the amplitude of
oscillations in the negative sequence is equal to the amplitude
of the DC term of the positive sequence injected current, and
vice versa. Therefore, it is feasible to use the DC current
references of opposite sequence components in the decoupling
structure. In addition, to minimize errors caused by sudden
perturbations at steady state, a measure of the error signal
feeding opposite sequence PI controllers is subtracted from the
current references.
The final expression of the DDSRF currents can be stated as
⎡cos(δ + ) ⎤
idq+ ' = I + ⎢ ⎥ Fig. 3. DDSRF current controller.
sin(δ + ) ⎦⎥
⎣⎢
 
Based in the deviation from the reference voltages, PI
DCterms

⎡cos(2ωt ) ⎤ ⎡sin(2ωt ) ⎤
compensators can be designed to produce the active and
+ I + cos(δ − ) ⎢ + I − sin(δ − ) ⎢ reactive power references of the STATCOM, P * and Q * ,
 
− sin(2ωt ) ⎥  
cos(2ωt ) ⎥
⎣ ⎦ ⎣ ⎦

DCterms
 
DCterms

respectively. Then this power references are properly
ACterms
processed to feed the reference of the current controllers. This
⎡cos(2ωt ) ⎤ − ⎡
− sin(2ωt ) ⎤
(
 
)
− I −* − ΔI − cos(δ − ) ⎢ −*

⎣ − sin(2ωt ) ⎦  
−
(
⎥ − I − ΔI sin(δ ) ⎢

⎣cos(2ωt ) ⎦
)
⎥ process is illustrated in Fig. 4.
 
DCterms DCterms

Cross − Couplingterms

for the positive- sequence current component, where I-* and

ΔI- are the reference and error signals in the negative sequence
component, respectively. Similarly,
⎡cos(δ − ) ⎤
idq− ' = I − ⎢ ⎥
⎢⎣sin(δ ) ⎥⎦
−

 

DCterms

⎡cos(2ωt ) ⎤ + ⎡ − sin(2ωt ) ⎤
+ I + cos(δ + ) ⎢ + I sin(δ + ) ⎢
 
sin(2ωt ) ⎥  
cos(2ωt ) ⎥
⎣ ⎦ ⎣ ⎦ Fig. 4. Outer voltage loop controller of the STATCOM.

DCterms
 
DCterms

ACterms

⎡cos(2ωt ) ⎤ + ⎡
− sin(2ωt ) ⎤ IV. SIMULATION AND EXPERIMENTAL RESULTS
(
 
)
− I +* − ΔI + cos(δ + ) ⎢ +*

⎣sin(2ωt ) ⎦  
+
(
⎥ − I − ΔI sin(δ ) ⎢

⎣cos(2ωt ) ⎦
⎥)
The STATCOM experimental platform schematic is

DCterms
 
DCterms

Cross − Couplingterms presented in Fig. 5. The proposed control strategy based in the
for the negative- sequence current component, where I+* and DDSRF current controller is performed using a TI F28335
ΔI+ are the reference and error signals in the positive sequence microcontroller. The parameters used in the experimental
component, respectively. Under steady state conditions, the platform and in the simulations are presented in Table 1. It is
worth mentioning that a large value for grid inductance, Lg, is
chosen in order to emulate a weak grid resembling the voltage
conditions at rural areas far away from main generators. The
purpose of this configuration is to request reactive power
compensation from the STATCOM to reach the steady state
voltage. Moreover, the parameters Kp and Ki of current and
voltage controllers are determined to achieve desired closed-
loop unit-step response [21].
pu and 0.035 pu, respectively. The voltage unbalance ratio
(VUR) during the fault is 7.5%.
The compensating effect of the STATCOM is shown in Fig.
7, where three phase voltages are regulated at rated 220V
RMS. The occurrence of the voltage sag at time 150 ms,
observes a decrease to 0.95 pu in Vd+. Given the fast response
of the controller, the steady state is recovered within 50 ms,
corresponding to 3 fundamental frequency periods.
The VUR during STATCOM compensation is depicted in
Fig. 7 (d). Since the outer loop control has a fast response, the
VUR reaches a maximum value of 2.1 % at the beginning and
end of the sag.
400
V Vbc V 1
ab ca
300

200 0.8
V+d
100

(p u )
(V )
0.6 0.85 pu
0

PC C

PCC
0.4

V
-100 0.75 pu

V
-200 0.2 +
Vq
-300
0
-400
Fig. 5. STATCOM experimental platform. 0 50 100 150 200 250
Time (ms)
300 350 400 450 500 0 50 100 150 200 250
Time (ms)
300 350 400 450 500

Table 1. PARAMETERS OF LABORATORY-SCALED STATCOM (a) (b)

System Ratings 0.08
Vq
-
10

Per Unit Bases Load Settings 0.06 8

S base 2.000 KVA Apparent power (S ) 2.000 KVA -

VUR
0.04 Vd 6
V PC C (p u )

V U R (% )
V base 220 V AC Power factor 0.8 Lagging
I base 5.25 A Load Resistance (R L, R L1 ) 19.36 Ω, 24Ω 0.02 4

Z base 24.2 Ω Load Inductance(L L ) 40 mH

0 2
Line frequency 60 Hz Line Inductance (L g ) 20 mH
-0.02 0
STATCOM Parameters 0 50 100 150 200 250
Time (ms)
300 350 400 450 500 0 50 100 150 200 250
Time (ms)
300 350 400 450 500

Physical Parameters Control Parameters (c) (d)

DC bus voltage (V DC ) 400 V Switching frequency (f sw ) 10 kHz
Fig. 6. Simulations results of PCC voltage before compensation: (a)
DC bus capacitance (C DC ) 2520 μF Sampling frequency (fsamp) 20 kHz
Inner Loop Current Controller
Line voltages; (b) Positive sequence components; (c) Negative
Filter Inductance (L f ) 5 mH
Filter resistance (R f ) 70 mΩ Proportional gain (Kp) 1.75 pu
sequence components; and (d) voltage unbalance ratio (VUR).
400
Filter capacitance (C f ) 10 μF Integral gain (Ki) 800 pu Vab V V
bc ca
Damping Resistance (R f1 ) 0.33 Ω Outer Loop Voltage Controller 300 1

VDC Proportional gain (KpVDC) 4 pu 200 +

Vd
0.8
VDC Integral gain (KiVDC) 16 pu 100
V PC C (V )

V PC C (p u )

+ 0.6
Vd Proportional gain (Kp Vd) 10 pu 0
+
Vd Integral gain (KiVd) 76 pu -100 0.4

Inner Loop Bandwidth 696 rad/sec Vd - , Vq- Proportional gain (Kp V2) 4 pu -200 0.2 Vq
+

Outer Loop PCC control Bandwi 162 rad/sec Vd - , Vq- Integral gain (KiV2) 24 pu -300
0
-400
0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500

A. PSCAD Simulation Verifications Time (ms) Time (ms)

In order to evaluate the dynamic performance of the (a) (b)

STATCOM, unbalanced voltage sag with 200 ms duration is 0.08 10

introduced by momentary insertion of RL1 in parallel with the 0.06 8

original loads RL for phase b, and phase c. 0.04 Vd- 6

V U R (% )

Fig. 6 shows the simulation results of PCC voltages before 0.02

Vq
-

the STATCOM is online. The three phase voltages are

V PC C (p u )

VUR

expressed in volts whereas; sequence components are

0 2

expressed in pu. Without compensation, the d-positive -0.02

0 50 100 150 200 250 300 350 400 450 500
0
0 50 100 150 200 250 300 350 400 450 500
Time (ms) Time (ms)
sequence voltage Vd+ at PCC only reaches 0.85 pu, and this
value dramatically decreases to 0.75 pu when the voltage sag (c) (d)
Fig. 7. Simulations results of PCC voltage after STATCOM
occurs at time 150 ms. The average value of the negative
compensation: (a) Line voltages; (b) Positive sequence components;
sequence Vd- and Vq- components during the faults are 0.053 (c) Negative sequence components; and (d) voltage unbalance ratio
(VUR).
 8
i
ib c
experimental results verified the efficacy of the proposed
6
ia control strategy.
4

2
(A)

0 Vabc (V)
abc
I

-2

-4

-6

-8
0 50 100 150 200 250 300 350 400 450 500
Time (ms)

Fig. 8. STATCOM compensating currents. Vd+ (pu)

B. Hardware Platform Verifications

In order to verify the performance of the STATCOM, the
need to setup a laboratory-scaled experimental platform arises.
The platform used in this work is shown in Fig. 9.
(a)
Vabc (V)

Vd- (pu)

(b)
Fig. 10. Experimental PCC voltages without compensation. (a) Three
Fig. 9. Experimental platform of STATCOM. phase voltages and Vd+; (b) Three phase voltages and Vd-

Vabc (V)
The uncompensated voltages measured from the
experimental platform are shown in Fig. 10. In addition to the
three phase voltages, the d-positive sequence component is
also shown in Fig. 10(a) and the homologous d-negative
sequence component in Fig 10(b).
Vd+ (pu)
The PCC voltages obtained when the STATCOM is online
are shown in Fig. 11. The steady state Vd+ voltage is boosted
to 1.0 pu in accordance with the simulation results. The
unbalanced sag is generated at time 150 ms, and the
STATCOM injects a set of unbalanced currents to the PCC
during the sag in order to maintain the PCC voltage at rated
conditions. The settling time to recover steady state voltage is Fig. 11. Experimental three phase and Vd+ PCC voltages when the
65 ms. At the end of the sag, a set of balanced compensating STATCOM is online.
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