PCS-985TE X Instruction Manual en Overseas General X R1.00

PCS-985TE
Transformer Relay
Instruction Manual
NR Electric Co., Ltd.

Preface
Preface
Introduction
This guide and the relevant operating or service manual documentation for the equipment provide
full information on safe handling, commissioning and testing of this equipment.
Documentation for equipment ordered from NR is dispatched separately from manufactured goods
and may not be received at the same time. Therefore, this guide is provided to ensure that printed
information normally present on equipment is fully understood by the recipient.
Before carrying out any work on the equipment, the user should be familiar with the contents of
this manual, and read relevant chapter carefully.
This chapter describes the safety precautions recommended when using the equipment. Before
installing and using the equipment, this chapter must be thoroughly read and understood.
Health and Safety

The information in this chapter of the equipment documentation is intended to ensure that
equipment is properly installed and handled in order to maintain it in a safe condition.
When electrical equipment is in operation, dangerous voltages will be present in certain parts of
the equipment. Failure to observe warning notices, incorrect use, or improper use may endanger
personnel and equipment and cause personal injury or physical damage.
Before working in the terminal strip area, the equipment must be isolated.
Proper and safe operation of the equipment depends on appropriate shipping and handling,
proper storage, installation and commissioning, and on careful operation, maintenance and
servicing. For this reason, only qualified personnel may work on or operate the equipment.
Qualified personnel are individuals who:
 Are familiar with the installation, commissioning, and operation of the equipment and of the
system to which it is being connected;
 Are able to safely perform switching operations in accordance with accepted safety
engineering practices and are authorized to energize and de-energize equipment and to
isolate, ground, and label it;
 Are trained in the care and use of safety apparatus in accordance with safety engineering
practices;
 Are trained in emergency procedures (first aid).
Instructions and Warnings

The following indicators and standard definitions are used:
PCS-985TE Transformer Relay i
Date: 2015-07-29
Preface
DANGER! means that death, severe personal injury and considerable equipment damage
will occur if safety precautions are disregarded.
WARNING! means that death, severe personal and considerable equipment damage
could occur if safety precautions are disregarded.
CAUTION! means that light personal injury or equipment damage may occur if safe ty
precautions are disregarded.
NOTICE! is particularly applies to damage to device and to resulting damage of the protected
equipment.
DANGER!
NEVER allow a open current transformer (CT) secondary circuit connected to this
device while the primary system is live. Open CT circuit will produce a dangerously high
voltage that cause death.
WARNING!
ONLY qualified personnel should work on or in the vicinity of this device. This personnel
MUST be familiar with all safety regulations and service procedures described in this
manual. During operating of electrical device, certain part of the device is under high
voltage. Severe personal injury and significant device damage could result from
improper behavior.
WARNING!
Do NOT touch the exposed terminals of this device while the power supply is on. The
generated high voltage causes death, injury, and device damage.
WARNING!
Thirty seconds is NECESSARY for discharging the voltage. Hazardous voltage can be
present in the DC circuit just after switching off the DC power supply.
CAUTION!
 Earthing
Securely earthed the earthing terminal of the device.
 Operating environment
ONLY use the device within the range of ambient environment and in an
environment free of abnormal vibration.
 Ratings
ii PCS-985TE Transformer Relay
Date: 2015-07-29
Preface
Check the input ratings BEFORE applying AC voltage/current and power supply to
the device.
 Printed circuit board
Do NOT attach or remove printed circuit board if the device is powered on.
 External circuit
Check the supply voltage used when connecting the device output contacts to
external circuits, in order to prevent overheating.
 Connection cable
Carefully handle connection cables without applying excessive force.
NOTICE!
The firmware may be upgraded to add new features or enhance/modify existing

features, please MAKE SURE that the version of this manual is compatible with the
product in your hand.
Copyright © 2015 NR. All rights reserved.
We reserve all rights to this document and to the information contained herein. Improper use in particular reproduction and dissemination
to third parties is strictly forbidden except where expressly authorized.
The information in this manual is carefully checked periodically, and necessary corrections will be included in future editions. If
nevertheless any errors are detected, suggestions for correction or improvement are greatly appreciated.
We reserve the rights to make technical improvements without notice.
NR ELECTRIC CO., LTD. Tel: +86-25-87178888

Headquarters: 69, Suyuan Avenue, Jiangning, Nanjing 211102, China Fax: +86-25-87178999
Manufactory: 18, Xinfeng Road, Jiangning, Nanjing 211111, China Website: www.nrelect.com, www.nrec.com
P/N: ZL_PCS-985TE_X_Instruction Manual_EN_Overseas General_X Version: R1.00
PCS-985TE Transformer Relay iii
Date: 2015-07-29
Preface
Documentation Structure
The manual provides a functional and technical description of this relay and a comprehensive set
of instructions for the relay’s use and application.
All contents provided by this manual are summarized as below:
1 Introduction
Briefly introduce the application, functions and features about this relay.
2 Technical Data
Introduce the technical data about this relay, such as electrical specifications, mechanical
specifications, ambient temperature and humidity range, communication port parameters, type
tests, setting ranges and accuracy limits and the certifications that our products have passed.
3 Operation Theory
Introduce a comprehensive and detailed functional description of all protective elements.
4 Supervision
Introduce the automatic self-supervision function of this relay.
5 Management
Introduce the management function (measurment and recording) of this relay.
6 Hardware
Introduce the main function carried out by each plug-in module of this relay and providing the
definition of pins of each plug-in module, typical wiring is provided.
7 Settings
List settings including system settings, communication settings and etc.
8 Human Machine Interface

Introduce the hardware of the human machine interface (HMI) module and a detailed guide for the
user how to use this relay through HMI. It also lists all the information which can be view through
HMI, such as settings, measurements, all kinds of reports etc.
9 Configurable Function
Brief introduction of configurable functions and configuration software.
10 Communication
Introduce the communication port and protocol which this relay can support, IEC60970 -5-103,
IEC61850 and DNP3.0 protocols are introduced in details.
11 Installation
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Date: 2015-07-29
Preface
Introduce the recommendations on unpacking, handling, inspection and storage of th is relay. A

guide to the mechanical and electrical installation of this relay is also provided, incorporating
earthing recommendations.
12 Commissioning
Introduce how to commission this relay, comprising checks on the calibration and functionality of
this relay.
13 Maintenance
A general maintenance policy for this relay is outlined.
14 Decommissioning and Disposal

A general decommissioning and disposal policy for this relay is outlined.
15 Manual Version History

List the instruction manual version and the modification history records.
Typographic and Graphical Conventions
Deviations may be permitted in drawings and tables when the type of designator can be obviously
derived from the illustration.
The following symbols are used in drawings:
&
AND gate
≥1
OR gate
Comparator
BI Binary signal via opto-coupler
SET I> Input signal from comparator with setting
EN Input signal of logic setting for function enabling
SIG Input of binary signal except those signals via opto-coupler
OTH Input of other signal
PCS-985TE Transformer Relay v
Date: 2015-07-29
Preface
XXX Output signal
Timer
t
Time (optional definite-time or inverse-time characteristic)
t
10ms 2ms
Timer [delay pickup (10ms), delay dropoff (2ms), non-settable]
[XXX] 0ms
Timer (delay pickup, settable)
0ms [XXX]
Timer (delay drop off, settable)
[XXX] [XXX]
Timer (delay pickup, delay drop off, settable)
IDMT
Timer (inverse-time characteristic)
---xxx is the symbol
Symbol Corresponding Relationship
Basic Example
A, B, C L1, L2, L3 Ia, Ib, Ic, I0 IL1, IL2, IL3, IN
AN, BN, CN L1N, L2N, L3N Ua, Ub, Uc VL1, VL2, VL3
ABC L123 Uab, Ubc, Uca VL12, VL23, VL31
U (voltage) V U0, U1, U2 VN, V1, V2
vi PCS-985TE Transformer Relay
Date: 2015-07-29
1 Introduction
1 Introduction
Table of Contents
1.1 Application.....................................................................................................................1-1
1.2 Functions .......................................................................................................................1-2
1.3 Features..........................................................................................................................1-5
List of Figures
Figure 1.1-1 Typical protection scheme 1 of PCS-985TE......................................................... 1-1
List of Tables
Table 1.2-1 Protective functions of PCS-985TE .................................................................... 1-3
Table 1.2-2 Miscellaneous functions of PCS-985TE ............................................................. 1-3
PCS-985TE Transformer Relay 1-a
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1 Introduction
1-b PCS-985TE Transformer Relay
Date: 2015-07-29
1 Introduction
1.1 Application
PCS-985TE is a kind of high performance numerical transformer protection device, which

integrates main and backup protection into one device. It provides complete protection of a
transformer in any voltage level, and is typically applied for startup/standby transformer or auxiliary
transformer of power plant with multiple branches, and main transformer, etc . It also provides
basic protection of a two-winding main transformer and one auxiliary transformer.
PCS-985TE provides up to 36 analog input channels including current and voltage inputs. The
transformer protections are configurable. Ancillary functions of fault diagnostic, disturbance
records, event records and communication function are integrated in the device.
Figure 1.1-1 ~ Figure 1.1-3 show typical protection schemes of PCS-985TE.
NOTICE!
Current transformers (CT) used for differential protection may be DIFFERENT from
those for backup protection.
Busbar 1
Busbar 2 50BF PCS-985TE
Busbar VT MR 49 62PD 21 27P,59P
50F
CB VT
Cal
3I0
l n abcn
*
Main 24 50P,51P 50G,51G 50Q,51Q 51PALM 59G 59GAlm
Transformer 87T 64REF
81
VT
abc
*
Conventional CT
*
Big-ratio CT
*
* *
* *
Step-down
Transformer
VT VT
abc
abc
Figure 1.1-1 Typical protection scheme 1 of PCS-985TE
PCS-985TE Transformer Relay 1-1
Date: 2015-07-29
1 Introduction
Busbar 1
Busbar 2
Busbar VT
CB VT
l n abcn
*
Main
Transformer
PCS-985TE
VT
abc
*
Conventional CT
*
Big-ratio CT
*
* * Cal
3I0
* *
Step-down
Transformer
MR 87T 64REF 64REF 50P, 51P 50G,51G 51PALM
VT VT
abc
abc
59G 59GAlm
Busbar 1
Busbar 2 50BF PCS-985TE
Busbar VT
62PD
MR
CB VT Cal
3I0
l n abcn
*
Start up/stand by *
Transformer
87T 64REF 24 50P, 51P 50G,51G 51PALM 59G 59GAlm
* *
* * * * 64REF 64REF
Branch A1 Branch A2 Branch B1 Branch B2
VT VT VT VT
abc abc abc abc
1.2 Functions
 Protective Functions
1-2 PCS-985TE Transformer Relay
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1 Introduction
The protective functions listed in following table are available for PCS-985TE; the functions can be
configured according to user’s requirement.
Table 1.2-1 Protective functions of PCS-985TE
No. Function ANSI

1 Transformer current differential protection 87T
2 Transformer restricted earth fault protection 64REF
3 Negative-sequence overcurrent protection 50/51Q
Definite-time overexcitation protection
4 24
Inverse-time overexcitation protection
Definite-time phase overcurrent protection
5 50/51P
Inverse-time phase overcurrent protection
6 Phase overcurrent alarm element 51PAlm
Definite-time ground overcurrent protection
7 50/51G
Inverse-time ground overcurrent protection
Definite-time phase overvoltage protection
8 59P
Inverse-time phase overvoltage protection
Definite-time phase undervoltage protection
9 27P
Inverse-time phase undervoltage protection
Definite-time residual overvoltage protection
10 59G
Inverse-time residual overvoltage protection
11 Overfrequency protection 81O
12 Underfrequency protection 81U
13 Rate-of-frequency-change protection 81R
14 Thermal overload protection 49
Phase-to-phase impedance protection
15 21
Phase-to-earth impedance protection
16 Circuit breaker failure protection 50BF
17 Pole disagreement protection 62PD
18 Breaker flashover protection 50F
19 Mechanical protection MR
20 Fault recorder FR
21 VT circuit supervision VTS
22 CT circuit supervision CTS
 Miscellaneous functions
Miscellaneous functions are listed in the following table, such as measurement, self-supervision
and oscillography, communication functions, and etc.
Table 1.2-2 Miscellaneous functions of PCS-985TE
Miscellaneous functions
Measurement 24 samples per cycle for current and voltage measurement
Configurable function Programmable binary inputs
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1 Introduction
Programmable binary outputs
Programmable LED indicators
Configurable protection functions
Self-supervision Relay hardware supervision and secondary circuit supervision
Disturbance 64 fault reports

recording 64 disturbance waveforms
Oscillography
(1) Protection picks up to trigger
function
Trigger mode (2) Manually trigger on keypad
(3) Remotely trigger through PCS-Explorer software
1024 supervision alarm events
Event recording 1024 binary input events
1024 device log events
Local HMI LCD and keypad
PCS-Explorer software or substation automation system

Remote HMI
software
Serial port
Ports type Electrical Ethernet port
Optical Ethernet port
Rear
IEC 60870-5-103 (Ethernet port or serial port)
communication
IEC 61850-8-1 (Ethernet port)
ports to host
Protocol type Modbus (Serial port)
DNP 3.0 (Ethernet port)
(Specified when ordering)
Rear communication port to printer One RS-232 port
Four kinds of clock synchronization methods :

1) Conventional
 PPS (RS-485): Pulse per second (PPS) via RS-485
differential level
 IRIG-B (RS-485): IRIG-B via RS-485 differential level
 PPM (DIN): Pulse per minute (PPM) via the optical
coupler
 PPS (DIN): Pulse per second (PPS) via the optical
Time synchronization
coupler
2) SAS
 SNTP (PTP): Unicast (point-to-point) SNTP mode via
Ethernet network
 SNTP (BC): Broadcast SNTP mode via Ethernet network
 Message (IEC103): Clock messages through IEC103
protocol
3) Ad vanced
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1 Introduction
 IEEE1588: Clock message via IEEE1588

 IRIG-B (Fiber): IRIG-B via optical-fibre interface
 PPS (Fiber) PPS: Pulse per second (PPS) via
optical-fibre interface
4) NoTimeSyn
Friendly HMI interface with LCD and 9-button keypad on the

front panel.
1 front multiplex RJ45 port for testing and setting
User Interface
1 RS-232 rear ports for printer
Language switchover—English+ selected language
Au xiliary software—PCS-Explorer
10 setting groups are available
Voltage and current drift auto-adjustment
1.3 Features
 Configurable Function
Modules of the device adopt intelligent design, amount of input and output modules and module
slot position are configurable. User can increase or decrease the amount of AC input module,
binary input module and binary output module, and terminals of those modules can be defined
according to actual requirement. Besides, configurability is also reflected in software design of
device, which means that user can hide the protective element not used or add new protective
module not in standard configuration.
 Parallel calculation of double DSP system
The hardware of the device comprises a 32-bit microprocessor and two 32-bit digital signal
processors (DSP). Those processors can operate in parallel companied by fast A/D converter. The
32-bit microprocessor performs logic calculation and the DSP performs the protection calculation.
High performance hardware ensures real time calculation of all protection relays within a sampling
interval.
On the premise of 24 samples per cycle, all data measurement, calculation and logic
discrimination could be done within one sampling period. The event recording and protection logic
calculation are completed simultaneously.
 Independent fault detector
Independent fault detectors in fault detector DSP module for connecting power supply of output
relays. The relay can drive a tripping output only when protection element on protection DSP
module operates with the fault detector in the fault detector DSP modu le operating simultaneously.
This kind of independent supervision of tripping outputs using fault detectors can avoid any
mal-operation possibly caused by any hardware component failure. This highly increases the
security. Please refer to Chapter 6 for details.
Date: 2015-07-29
1 Introduction
 Configurable tripping output
The tripping output contacts can be configured by tripping matrix and suitable to any mode of
tripping.
 Fault recording function
Event records include 1024 binary input events and 1024 alarm events. Disturbance records
including 64 fault reports, and 64 disturbance waveforms, and file format of waveform is
compatible with international COMTRADE91 and COMTRADE99 file. Analog inputs and binary
inputs can be recorded, and three oscillography triggering mode are supported, which are
protection pickup triggering, manual triggering on keypad of device, and remote triggering through
PCS-Explorer software.
 Powerful PC tool software
Powerful PC tool software (PCS-Explorer) can fulfill protection function configuration, modify
setting and waveform analysis.
 Integration of main and backup protection
Main and backup protection are integrated in one set of protection device. Protection information
is shared by all parts. The device can record all relevant waveforms of any fault.
 High sensitive and securable DPFC biased differential protection
DPFC (deviation of power frequency component) biased current differential protection element is
regardless of the load current and is sensitive to small internal fault current within the transformer.
Its performance against current transformer saturation is also good.
 Reliable CT Saturation Detection
Based on the operation sequence of DPFC restraint current element and DPFC differential current
element of differential protection, external fault with CT saturation or internal fault can be
distinguished correctly.
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2 Technical Data
2 Technical Data
Table of Contents
2.1 Electrical Specifications ............................................................................................2-1

2.1.1 AC Current Input .............................................................................................................. 2-1
2.1.2 AC Voltage Input .............................................................................................................. 2-1
2.1.3 Power Supply................................................................................................................... 2-1
2.1.4 Transducer Input .............................................................................................................. 2-1
2.1.5 Binary Input ..................................................................................................................... 2-2
2.1.6 Binary Output................................................................................................................... 2-2
2.2 Mechanical Specifications ........................................................................................2-3

2.3 Ambient Temperature and Humidity Range .........................................................2-3
2.4 Communication Port ...................................................................................................2-4
2.4.1 EIA-485 Port .................................................................................................................... 2-4
2.4.2 Ethernet Port ................................................................................................................... 2-4
2.4.3 Optical Fiber Port ............................................................................................................. 2-4
2.4.4 Print Port.......................................................................................................................... 2-4
2.4.5 Clock Synchronization Port .............................................................................................. 2-4
2.5 Type Tests ......................................................................................................................2-5

2.5.1 Environmental Tests......................................................................................................... 2-5
2.5.2 Mechanical Tests ............................................................................................................. 2-5
2.5.3 Electrical Tests................................................................................................................. 2-5
2.5.4 Electromagnetic Compatibility .......................................................................................... 2-5
2.6 Certifications.................................................................................................................2-6
2.7 Terminals........................................................................................................................2-6
2.8 Measurement Scope and Accuracy ........................................................................2-6

2.9 Management Function................................................................................................2-7
2.9.1 Control Performance........................................................................................................ 2-7
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2 Technical Data
2.9.2 Clock Performance .......................................................................................................... 2-7
2.9.3 Fault and Disturbance Recording ..................................................................................... 2-7
2.9.4 Binary Input Signal........................................................................................................... 2-7
2.10 Protective Functions ................................................................................................2-7

2.10.1 Main Transformer Current Differential Protection............................................................ 2-7
2.10.2 Restricted Earth Fault Protection.................................................................................... 2-8
2.10.3 Negative-sequence Overcurrent Protection .................................................................... 2-8
2.10.4 Overexcitation Protection ............................................................................................... 2-8
2.10.5 Phase Overcurrent Protection ........................................................................................ 2-9
2.10.6 Ground Overcurrent Protection ...................................................................................... 2-9
2.10.7 Overvoltage Protection................................................................................................. 2-10
2.10.8 Undervoltage Protection............................................................................................... 2-10
2.10.9 Residual Overvoltage Protection .................................................................................. 2-10
2.10.10 Overfrequency Protection........................................................................................... 2-10
2.10.11 Underfrequency Protection ......................................................................................... 2-10
2.10.12 Rate-of-Frequency-Change Protection........................................................................2-11
2.10.13 Thermal Overload Protection.......................................................................................2-11
2.10.14 Impedance Protection .................................................................................................2-11
2.10.15 Breaker Failure Protection...........................................................................................2-11
2.10.16 Pole Disagreement Protection.....................................................................................2-11
2.10.17 Breaker Flashover Protection ..................................................................................... 2-12
2.10.18 Mechanical Protection ................................................................................................ 2-12
2-2 PCS-985TETransformer Relay
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2 Technical Data
2.1 Electrical Specifications

2.1.1 AC Current Input
Phase rotation ABC

Nominal frequency 50Hz, 60Hz
Application object For protection For metering
Rated Current (In) 1A 5A 1A 5A
Linear to 0.05In~40In 0.05In~40In 0.05In~2In 0.05In~2In
Thermal withstand
-continuously 4In 2In
-for 10s 30In 12In
-for 1s 100In 30In
-for half a cycle 250In 75In
Burden <0.15VA/phase <0.25VA/phase <0.20VA/phase <0.40VA/phase
@In @In @In @In
Current input channel Ma ximum 51 Ma ximum 3
2.1.2 AC Voltage Input
Phase rotation ABC

Nominal frequency 50Hz, 60Hz
Rated Voltage (Un) 100V~130V 200V (residual voltage input)
Linear to 1~170V 2~233V
Thermal withstand
-continuously 200V 220
-10s 260V 380
-1s 300V 420
Burden at rated < 0.20VA/phase @Un < 0.80VA/phase @Un
Voltage input channel Ma ximum 24 Ma ximum 2
2.1.3 Power Supply
Standard IEC 60255-11:2008

Rated Voltage 110Vdc/125Vdc, 220Vdc/250Vdc
Variation 88~300Vdc
Permissible AC ripple voltage ≤15% of the nominal auxiliary voltage
Burden
Quiescent condition <35W
Operating condition <65W
2.1.4 Transducer Input
Standard IEC 60255-1: 2009

Input range 0-20mA 0-5V
Input resistance 235Ω 20kΩ
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2 Technical Data
Accuracy 0.5% 0.5%

Transducer input channel 6
2.1.5 Binary Input
Rated voltage 110Vdc 125Vdc 220Vdc 250Vdc

Rated current drain 1.1mA 1.25mA 2.2mA 2.5mA
On value 77-132Vdc 87.5-150Vdc 154-264Vdc 175-300Vdc
Off value <55Vdc <62.5Vdc <110Vdc <125Vdc
Ma ximum permissible voltage 300Vdc
Withstand voltage 2000Vac, 2800Vdc (continuously )
Response time for logic input ≤1ms
Up to 22 binary input (including 4 mechnical relays ) according to various
Number
hardware configurations
2.1.6 Binary Output
1. Tripping contact
Output mode Potential free contact

8A@380Vac
Continuous carry
8A@250Vdc
Pickup time (Typical) <8ms (typical 3ms)
Drop-off time <5ms
0.65A@48Vdc
0.35A@110Vdc
Breaking capacity (L/R=40ms) 0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
Burden 300mW
380Vac
Ma ximal system voltage
250Vdc
Test voltage across open contact 1000V RMS for 1min
12A@3s
18A@1s
Short duration current
24A@0.5s
40A@0.2s
Durability (Loaded contact) 10000 operations
Number Up to 33 trip output according to various hardware configurations
2. Signal contact
Output mode Potential free contact

8A@380Vac
Continuous carry
8A@250Vdc
Pickup time (Typical) <10 ms (typical 3ms)
Drop-off time <10 ms
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2 Technical Data
0.65A@48Vdc
0.35A@110Vdc
Breaking capacity (L/R=40ms) 0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
Burden 400mW
380Vac
Ma ximal system voltage
250Vdc
Test voltage across open contact 1200V RMS for 1min
12A@3s
15A@1s
Short duration current
20A@0.5s
30A@0.2s
Durability (Loaded contact) 10,000 operations minimum
Number Up to 33 signal output according to various hardware configurations
NOTICE!
Signal output contacts include watchdog contacts.
Tripping output contacts are not connected to trip circuit breakers directly. They are
connected to interposing relays or lockout relays contacts which are connected to trip
circuit breakers.
2.2 Mechanical Specifications

Mounting Way Flush mounted
Chassis color Silver grey
Weight per device Approx. 40kg
Chassis material Aluminum alloy
Location of terminal Rear panel of the device
Device structure Plug-in modular type @ rear side, integrated front plate
Protection class
Front side IP40
Other sides IP30
Rear side, connection terminals IP20
2.3 Ambient Temperature and Humidity Range

Standard IEC 60225-1: 2009
Operating temperature -40°C to +70°C (Readability of display may be impaired below -20°C)
Transport and storage temperature
-40°C to +70°C
range
Permissible humidity 5%-95%, without condensation
Pollution degree 2
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2 Technical Data
Altitude <3000m
2.4 Communication Port

2.4.1 EIA-485 Port
Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s , 57.6kbit/s, 115.2kbit/s

Protocol IEC 60870-5-103:1997
Ma ximal capacity 32
Transmission distance <500m
Safety le vel Isolation to ELV level
Twisted pair Screened twisted pair cable
2.4.2 Ethernet Port
Connector type RJ-45 ST, SC (Multi mode)

Transmission rate 100Mbits/s
Transmission standard 100Base-TX 100Base-FX
Transmission distance <100m <2km (1310nm)
Protocol IEC 60870-5-103:1997, DNP 3.0 or IEC 61850
2.4.3 Optical Fiber Port
2.4.3.1 For Station Level
Characteristic Glass optical fiber

Connector type ST
Fiber type Multi mode
Transmission distance <2km
Wave length 1310nm
Transmission power Min. -20.0dBm
Minimum receiving power Min. -30.0dBm
Margin Min +3.0dB
2.4.4 Print Port
Type RS-232
Baud Rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Printer type EPSON ® 300K printer
2.4.5 Clock Synchronization Port
Type RS-485
Transmission distance <500m
Ma ximal capacity 32
Timing standard PPS, IRIG-B
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2 Technical Data
2.5 Type Tests

2.5.1 Environmental Tests
Dry cold test IEC60068-2-1:2007
Dry heat test IEC60068-2-2:2007
Damp heat test, cyclic IEC60068-2-30:2005
2.5.2 Mechanical Tests

Vibration IEC 60255-21-1:1988 Class I
Shock and bump IEC 60255-21-2:1988 Class I
2.5.3 Electrical Tests

Dielectric tests Test voltage 2kV, 50Hz, 1min
Impulse voltage tests Test voltage 5kV
Overvoltage category III
Insulation resistance measurements Isolation resistance >100MΩ@500VDC
2.5.4 Electromagnetic Compatibility
IEC 60255-22-1:2007
1MHz burst disturbance test Common mode: class Ⅲ 2.5kV
Differential mode: class Ⅲ 1.0kV
IEC60255-22-2:2008 class Ⅳ
Electrostatic discharge test For contact discharge: 8kV
For air discharge: 15kV
IEC 60255-22-3:2007 class Ⅲ
Frequency sweep
Radiated amplitude-modulated
10V/m (rms), f=80~1000MHz
Radio frequency interference tests Spot frequency
Radiated amplitude-modulated
10V/m (rms), f=80MHz/160MH z/450MH z/900 MHz
Radiated pulse-modulated
10V/m (rms), f=900MHz
IEC 60255-22-4:2008
Fast transient disturbance tests Power supply, I/O, Earth: class Ⅳ, 4kV, 2.5kH z, 5/50ns
Communication terminals: class Ⅳ, 2kV, 5kHz, 5/50ns
IEC 60255-22-5:2008
Surge immunity test
Power supply, AC input, I/O port: class Ⅳ, 1.2/50us
Date: 2015-07-29
2 Technical Data
Common mode: 4kV

Differential mode: 2kV
IEC 60255-22-6:2001
Conducted RF Electromagnetic
Power supply, AC, I/O, Comm. Terminal: Class Ⅲ , 10Vrms, 150
Disturbance
kHz~80MH z
Power Frequency Magnetic Field IEC 61000-4-8:2001
Immunity Class Ⅴ, 100A/m for 1min, 1000A/m for 3s
IEC 61000-4-9:2001
Pulse Magnetic Field Immunity
Class Ⅴ, 6.4/16μs, 1000A/m for 3s
Damped oscillatory magnetic field IEC 61000-4-10:2001
immunity Class Ⅴ, 100kHz & 1 MHz–100A/m
Au xiliary power supply performance IEC60255-11: 2008

- Voltage dips Up to 200ms for dips to 40% of rated voltage without reset
-Voltage short interruptions 100ms for interruption without rebooting
2.6 Certifications
 ISO9001: 2008
 ISO14001:2004
 OHSAS18001: 2007
 ISO10012:2003
 CMMI L5
 EMC: 2004/108/EC, EN50263:1999
 Products safety(PS): 2006/95/EC, EN61010-1: 2001
2.7 Terminals
Connection Type Wire Size
2 2
Crimp terminals, 1.5mm ~4.0mm lead
AC current If using 4.0mm 2 lead, only dedicated terminal cable lug provided by NR
can be adopted.
AC voltage Crimp terminals, 1.0mm 2~2.5mm 2 lead
Power supply Crimp terminals, 1.0mm 2~2.5mm 2 lead
Contact I/O Crimp terminals, 1.0mm 2~2.5mm 2 lead
Grounding (Earthing) Connection BVR type, 2.5mm²~6.0mm 2 lead
2.8 Measurement Scope and Accuracy

Item Range Accuracy
Phase range 0°~ 360° ≤±3°
Frequency fn±3 Hz ≤ 0.02Hz
Currents from protection measurement current transformers
Date: 2015-07-29
2 Technical Data
≤ 2.0% of rating (0.05~1.00In)

Current 0.05~5.00 In
≤ 2.0% of applied quantities (1.00~5.00In)
≤ 1.0% of rating (0.05~1.00Un)
Voltage 0.05~1.50 Un
≤ 1.0% of applied quantities (1.00~1.50Un)
2.9 Management Function

2.9.1 Control Performance
Control mode Local or remote
Accuracy of local control ≤ 1s
Accuracy of remote control ≤ 3s
2.9.2 Clock Performance
Real time clock accuracy ≤ 3s/day

Accuracy of GPS synchronization ≤ 1ms
External time synchronization IRIG-B (200-98), PPS, IEEE1588 or SNTP protocol
2.9.3 Fault and Disturbance Recording
Ma ximum duration 2048 sampled points (24 sampled points per cycle)
Recording position 3 cycles before pickup of trigger element
2.9.4 Binary Input Signal
Resolution of binary input signal ≤ 1ms

Binary input mode Potential-free contact
Resolution of SOE ≤ 2ms
2.10 Protective Functions
There are some symbols mentioned in the following sections and the meaning of them is given
here.
Un – the secondary rated voltage of VT
In – the secondary rated current of CT
pu – per-unit value
Id – the differential current
U * / f* – the overexcitation multiples
2.10.1 Main Transformer Current Differential Protection
2.10.1.1 Biased Differential Element
Pickup up current setting 0.1~1.5 pu, steps 0.01 pu
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2 Technical Data
Drop-off current 0.95×Setting
Tolerance of operating current ≤5% of operating current or 0.02 pu, whichever is greater
Slope 1 setting 0.01~0.50, steps 0.01
Slope 2 setting 0.50~0.80, steps 0.01
2nd harmonic restraint coefficient setting 0.05~0.50, steps 0.01

th
5 harmonic setting for overexcitation 0.05~0.50, steps 0.01
50Hz: ≤ 30ms (Id>2xSetting)

Operating time (Without blocking criteria)
60Hz: ≤ 25ms (Id>2xSetting)
2.10.1.2 Instantaneous Differential Element
Current setting 2~14 pu, 0.01pu steps
Drop-off current 0.95×Setting
Tolerance of current setting ≤2.5%xSetting or 0.02 pu, whichever is greater
50Hz: ≤ 20ms (Id>1.5xSetting)

Operating time
60Hz: ≤20ms (Id>1.5xSetting)
2.10.2 Restricted Earth Fault Protection
Pickup up current setting 0.1~ 1.5In, steps 0.01In
Restraint slope setting 0.3~0.8, steps 0.01
Tolerance of operating current ≤5% or 0.02In, whichever is greater
Operating time 50Hz: ≤30ms (I0d>2×[64REF.I_Biased])

(Without time delay, without blocking criterion) 60Hz: ≤25ms (I0d>2×[64REF.I_Biased])
2.10.3 Negative-sequence Overcurrent Protection
Current setting 0.05~4In, steps 0.01A
Tolerance of current setting ≤2.5% of setting or 0.02In, whichever is greater
Drop-off to pickup ratio ≥95%
Definite-time time delay 0~3000.00s
Tolerance of definite-time time delay ≤1% of setting +40ms (at 2 times current s etting)
Operating time of inverse-time overcurrent ≤2.5% operating time or 40ms, whichever is greater(for current
element between 1.2 and 20 multiples of pickup)
2.10.4 Overexcitation Protection
Definite time U * / f * setting 1.00~2.00
Definite time delay for trip 0.1 ~3000.0s
Definite time delay for alarm 0.1~30.0s
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2 Technical Data
Inverse time U * / f * setting 1.00~2.00
Inverse-time time delay 1.0~3000.0s
Tolerance of U * / f * setting ≤2.5% of Setting or 0.01 whichever is greater
Tolerance of operating time of definite-time

≤1% of Setting +40ms (at 1.5 times U * / f * setting)
overexcitation protection
Tolerance of operating time of inverse-time

≤2.5% operating time or 40ms, whichever is greater
2.10.5 Phase Overcurrent Protection
Current setting 0.05~20.00In, steps 0.01 A
Tolerance of definite-time time delay ≤1% of setting +40ms (at 2 times current setting)
Phase-to-phase undervoltage setting of

2.00~120.00V, steps 0.01 V
voltage controlled element
Negative-sequence overvoltage setting of

1.00~120.00V, steps 0.01 V
voltage controlled element
Tolerance of voltage setting ≤2.5% of setting or 0.01Un, whichever is greater
Setting range of relay characteristic angle of

-90.00~90.00deg, steps 0.01 deg
direction element
Tolerance of relay characteristic angle ≤3 deg
2.10.6 Ground Overcurrent Protection
Current setting 0.05~20In, steps 0.01A
Tolerance of definite-time time delay ≤1% of setting +40ms (at 2 times current setting)
Setting range of relay characteristic angle of

90.00~270.00deg, steps 0.01 deg
direction element
Tolerance of relay characteristic angle ≤3 deg
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2 Technical Data
2.10.7 Overvoltage Protection
Voltage setting 0.10~200.00V, steps 0.01V

Tolerance of voltage setting ≤2.5% of setting or 0.1V, whichever is greater
Tolerance of definite-time time delay ≤1%Setting+40ms (at 1.2 times voltage setting)
Operating time of inverse-time overvoltage ≤2.5% operating time or 40ms, whichever is greater (for voltage
2.10.8 Undervoltage Protection

Drop-off to pickup ratio ≤105%
Tolerance of definite-time time delay ≤1%Setting+40ms (at 0.8 times voltage setting)
element between 0.5 and 0.8 multiples of pickup)
2.10.9 Residual Overvoltage Protection
Definite-time time delay 0.00~30.00 s
Tolerance of definite-time time delay ≤1% of setting +40ms (at 1.2 times voltage setting)
2.10.10 Overfrequency Protection
50.00 ~ 60.00Hz (for 50Hz system)

Overfrequency setting
60.00 ~ 70.00Hz (for 60Hz system)
Tolerance of frequency setting ≤ 0.02Hz
Time delay 0.10~300.00s
Tolerance of time setting ≤1%Setting+40ms (at 1.2 times frequency setting)
Time delay for overfrequency band
0.10~300.00min
accumulate protection
2.10.11 Underfrequency Protection
45.00 ~ 51.00Hz (for 50Hz system)

Underfrequency setting
55.00~ 61.00Hz (for 60Hz system)
Tolerance of frequency setting ≤ 0.02Hz
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2 Technical Data
Tolerance of time setting ≤1%Setting+40ms (at 0.8 times frequency setting)

Time delay for underfrequency band
0.10~300.00min
accumulate protection
2.10.12 Rate-of-Frequency-Change Protection
Rate-of-frequency-change setting 0.10~20.00 Hz/s, steps 0.01Hz/s

Tolerance of rate-of-frequency-change setting ≤0.10Hz/s
Time delay 0.1~100s
Tolerance of time setting ≤1%Setting+40ms
2.10.13 Thermal Overload Protection
Base current setting range 0.04In~20In, steps 0.01A
Thermal overload time constant 0.10~100.00 Min
Thermal accumulation coefficient 1.00~3.00
Drop-off to pickup ratio 95%
2.10.14 Impedance Protection
Impedance characteristic angle 0.00~ 90.00deg, steps 0.01deg

Impedance setting 0.05 ~ 200.00Ω, steps 0.01Ω
Tolerance of impedance setting ≤2.5% of setting or 0.1Ω, whichever is greater
Tolerance of time delay ≤1%Setting + 40ms (at 0.8 times impedance setting)
Current setting of PSBR element 0.05~20In, 0.01A steps
2.10.15 Breaker Failure Protection
Current setting of phase current criterion 0.05~10.00In, steps 0.01A
Current setting of negative-sequence current

0.05~4In, 0.01A steps
criterion
Current setting of residual current criterion 0.05~4In, 0.01A steps
Tolerance of time delay ≤1% of setting +40ms (at 2 times current setting)
2.10.16 Pole Disagreement Protection
Range of residual current setting 0.05~10In, steps 0.01A
Range of negative sequence current setting 0.05~10In, steps 0.01A
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2 Technical Data
Time delay 0.00~30.00 s
Tolerance of time setting ≤1% of setting +40ms (at 2 times current setting)
2.10.17 Breaker Flashover Protection
Negative-sequence current setting range 0.05~4In, steps 0.01A

Residual current setting range 0.05~4In, steps 0.01A
Phase current setting range 0.05~10In, steps 0.01A
Tolerance of current setting ≤2.5% or 0.02In whichever is greater
Tolerance of time setting ≤1%Setting + 40ms (at 2 times current setting)
2.10.18 Mechanical Protection
Delay pickup up time delay 0~6000.00s
Tolerance of time delay ≤1% of Setting +40ms
Date: 2015-07-29
3 Operation Theory
3 Operation Theory
Table of Contents
3.1 Overview ........................................................................................................................3-1

3.2 Transformer Current Differential Protection (87T)..............................................3-1
3.2.1 Application ....................................................................................................................... 3-1
3.2.2 Function Description ........................................................................................................ 3-1
3.2.3 Protection Principle .......................................................................................................... 3-2
3.2.4 Logic.............................................................................................................................. 3-17
3.2.5 Inputs and Outputs......................................................................................................... 3-21
3.2.6 Settings ......................................................................................................................... 3-23
3.3 Restricted Earth Fault Protection (64REF) ........................................................ 3-25

3.3.1 Application ..................................................................................................................... 3-26
3.3.2 Function......................................................................................................................... 3-26
3.3.3 Protection Principle ........................................................................................................ 3-26
3.3.4 Logic.............................................................................................................................. 3-32
3.3.6 Settings ......................................................................................................................... 3-36
3.4 Negative-Sequence Overcurrent Protection (50/51Q) .................................... 3-37

3.4.1 Application ..................................................................................................................... 3-37
3.4.2 Function......................................................................................................................... 3-37
3.4.4 Logic.............................................................................................................................. 3-39
3.4.6 Settings ......................................................................................................................... 3-41
3.5 Overexcitation Protection (24) .............................................................................. 3-43

3.5.1 Application ..................................................................................................................... 3-43
3.5.2 Function Description ...................................................................................................... 3-43
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3 Operation Theory
3.5.4 Logic.............................................................................................................................. 3-45
3.5.6 Settings ......................................................................................................................... 3-48
3.6 Main Transformer Phase Overcurrent Protection (50/51P) ........................... 3-49

3.6.1 Application ..................................................................................................................... 3-49
3.6.3 Protection Principle........................................................................................................ 3-50
3.6.4 Logic.............................................................................................................................. 3-56
3.6.6 Settings ......................................................................................................................... 3-61
3.7 Phase Overcurrent Alarm Elements (51PAlm) .................................................. 3-63

3.7.1 Application ..................................................................................................................... 3-63
3.7.2 Function......................................................................................................................... 3-64
3.7.4 Logic.............................................................................................................................. 3-64
3.7.6 Settings ......................................................................................................................... 3-66
3.8 Main Transformer Ground Overcurrent Protection (50/51G) ........................ 3-66

3.8.1 Application ..................................................................................................................... 3-66
3.8.2 Function......................................................................................................................... 3-66
3.8.4 Logic.............................................................................................................................. 3-71
3.8.6 Settings ......................................................................................................................... 3-75
3.9 Phase Overvoltage Protection (59P) ................................................................... 3-77

3.9.1 Application ..................................................................................................................... 3-77
3.9.4 Logic.............................................................................................................................. 3-79
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3 Operation Theory
3.9.6 Settings ......................................................................................................................... 3-81
3.10 Phase Undervoltage Protection (27P) ............................................................... 3-82

3.10.1 Application ................................................................................................................... 3-82
3.10.2 Function Description .................................................................................................... 3-82
3.10.3 Operation Principle ...................................................................................................... 3-83
3.10.4 Logic............................................................................................................................ 3-84
3.10.5 Inputs and Outputs....................................................................................................... 3-85
3.10.6 Settings........................................................................................................................ 3-86
3.11 Residual Overvoltage Protection (59G) ............................................................ 3-87

3.11.1 Application ................................................................................................................... 3-87
3.11.2 Function ....................................................................................................................... 3-87
3.11.3 Protection Principle ...................................................................................................... 3-87
3.11.4 Logic ............................................................................................................................ 3-88
3.11.5 Inputs and Outputs ....................................................................................................... 3-89
3.11.6 Settings........................................................................................................................ 3-90
3.12 Overfrequency Protection (81O) ........................................................................ 3-91

3.12.1 Application ................................................................................................................... 3-91
3.12.2 Function Description .................................................................................................... 3-92
3.12.3 Protection Principle ...................................................................................................... 3-92
3.12.4 Logic............................................................................................................................ 3-93
3.12.5 Inputs and Outputs....................................................................................................... 3-95
3.12.6 Settings........................................................................................................................ 3-97
3.13 Underfrequency Protection (81U) ...................................................................... 3-99

3.13.1 Application ................................................................................................................... 3-99
3.13.2 Function Description .................................................................................................. 3-100
3.13.3 Protection Principle .................................................................................................... 3-100
3.13.4 Logic.......................................................................................................................... 3-101
3.13.5 Inputs and Outputs..................................................................................................... 3-103
3.13.6 Settings...................................................................................................................... 3-105
PCS-985TE Transformer Relay 3-c
Date: 2015-07-29
3 Operation Theory
3.14 Rate-of-Frequency-Change Protection (81R)................................................ 3-107

3.14.1 Application ................................................................................................................. 3-107
3.14.2 Function..................................................................................................................... 3-108
3.14.4 Logic.......................................................................................................................... 3-109
3.14.5 Input and Output .........................................................................................................3-110
3.14.6 Settings.......................................................................................................................3-112
3.15 Thermal Overload Protection (49) .................................................................... 3-114

3.15.1 Application ..................................................................................................................3-114
3.15.2 Function......................................................................................................................3-114
3.15.3 Operation Principle .....................................................................................................3-114
3.15.4 Logic...........................................................................................................................3-115
3.15.5 Input and Output .........................................................................................................3-116
3.15.6 Settings.......................................................................................................................3-117
3.16 Impedance Protection (21) ................................................................................. 3-118

3.16.1 Application ..................................................................................................................3-118
3.16.2 Function Description ...................................................................................................3-118
3.16.3 Protection Principle .....................................................................................................3-118
3.16.4 Logic.......................................................................................................................... 3-124
3.16.6 Settings...................................................................................................................... 3-127
3.17 Breaker Failure Protection (50BF) ................................................................... 3-128

3.17.1 Application ................................................................................................................. 3-128
3.17.4 Logic.......................................................................................................................... 3-130
3.17.5 Input and Output ........................................................................................................ 3-131
3.17.6 Settings...................................................................................................................... 3-132
3.18 Pole Disagreement Protection (62PD) ............................................................ 3-132

3.18.1 Application ................................................................................................................. 3-133
3-d PCS-985TE Transformer Relay
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3 Operation Theory
3.18.2 Function..................................................................................................................... 3-133
3.18.4 Logic.......................................................................................................................... 3-134
3.18.5 Input and Output ........................................................................................................ 3-135
3.18.6 Settings...................................................................................................................... 3-136
3.19 Breaker Flashover Protection (50F) ................................................................ 3-136

3.19.1 Application ................................................................................................................. 3-136
3.19.2 Function..................................................................................................................... 3-137
3.19.4 Logic.......................................................................................................................... 3-138
3.19.5 Input and Output ........................................................................................................ 3-140
3.19.6 Settings...................................................................................................................... 3-141
3.20 Mechanical Protection (MR) .............................................................................. 3-141

3.20.1 Application ................................................................................................................. 3-141
3.20.4 Logic.......................................................................................................................... 3-142
3.20.6 Settings...................................................................................................................... 3-144
3.21 Interconnection Status Element (CBStatus).................................................. 3-145

3.21.1 Application ................................................................................................................. 3-145
3.21.4 Logic.......................................................................................................................... 3-146
3.21.5 Input and Output ........................................................................................................ 3-148
3.21.6 Settings...................................................................................................................... 3-149
3.22 Current Sum Element (CurrSum) ..................................................................... 3-149

3.22.1 Application ................................................................................................................. 3-149
3.22.3 Principle..................................................................................................................... 3-149
PCS-985TE Transformer Relay 3-e
Date: 2015-07-29
3 Operation Theory
3.22.4 Logic.......................................................................................................................... 3-149
3.22.6 Settings...................................................................................................................... 3-151
3.23 Three-Phase Current Element (Curr3P).......................................................... 3-151

3.23.1 Application ................................................................................................................. 3-151
3.23.3 Principle..................................................................................................................... 3-152
3.23.4 Logic.......................................................................................................................... 3-152
3.23.6 Settings...................................................................................................................... 3-155
3.24 Three-Phase Voltage Element (Volt3P) ........................................................... 3-156

3.24.1 Application ................................................................................................................. 3-156
3.24.3 Principle..................................................................................................................... 3-156
3.24.4 Logic.......................................................................................................................... 3-157
3.24.6 Settings...................................................................................................................... 3-160
3.25 Residual Current Element (Curr1P) ................................................................. 3-160

3.25.1 Application ................................................................................................................. 3-160
3.25.4 Settings...................................................................................................................... 3-161
3.26 Residual Voltage Element (Volt1P)................................................................... 3-161

3.26.1 Application ................................................................................................................. 3-162
3.26.4 Settings...................................................................................................................... 3-162
List of Figures
Figure 3.2-1 Transformer current compensation calculation process ................................ 3-7
3-f PCS-985TE Transformer Relay
Date: 2015-07-29
3 Operation Theory
Figure 3.2-2 Operation characteristic curve of steady-state differential element of

transformer ........................................................................................................................... 3-12
Figure 3.2-3 Operation characteristic curve of DPFC differential element of main

transformer ........................................................................................................................... 3-12
Figure 3.2-4 Logic diagram of startup of transformer current differential protection ...... 3-18
Figure 3.2-5 Logic diagram of steady-state current differential element of transformer.. 3-19
Figure 3.2-6 Logic diagram of DPFC current differential element of main transformer ... 3-20
Figure 3.2-7 Function block diagram of transformer current differential protection ........ 3-21
Figure 3.3-1 Operation characteristic curve of restricted earth fault protection .............. 3-29
Figure 3.3-2 Logic diagram of restricted earth fault protection ......................................... 3-33
Figure 3.3-3 Function block diagram of restricted earth fault protection.......................... 3-34
Figure 3.4-1 Logic diagram of negative -sequence overcurrent protection (x=1 or 2) ...... 3-40
Figure 3.4-2 Function block diagram of negative-sequence overcurrent protection ....... 3-40
Figure 3.5-1 Inverse-time overexcitation characteristic curve ........................................... 3-45
Figure 3.5-2 Logic diagram of overexcitation protection ................................................... 3-46
Figure 3.5-3 Function block diagram of overexcitation protection.................................... 3-46
Figure 3.6-1 Function diagram of main transformer phase overcurrent protection ......... 3-50
Figure 3.6-2 Connection of VT and CT of direction element .............................................. 3-54
Figure 3.6-3 Direction characteristic of main transformer phase overcurrent protection 3-54
Figure 3.6-4 Logic diagram of main transformer phase overcurrent protection (x=1,2,3) 3-57
Figure 3.6-5 Logic diagram of phase -to-phase VCE of main transformer phase overcurrent
protection .............................................................................................................................. 3-57
Figure 3.6-6 Logic diagram of negative-sequence VCE of main transformer phase

overcurrent protection ......................................................................................................... 3-58
Figure 3.6-7 Logic diagram of direction element of main transformer phase overcurrent
protection .............................................................................................................................. 3-58
Figure 3.6-8 Logic diagram of harmonic blocking element................................................ 3-59
Figure 3.6-9 Function block diagram of main transformer phase overcurrent protection 3-59
Figure 3.7-1 Logic diagram of phase overcurrent alarm elements (x=1, 2, 3) ................... 3-64
Figure 3.7-2 Function block diagram of phase overcurrent alarm elements .................... 3-65
Figure 3.8-1 Function diagram of ground overcurrent protection ..................................... 3-67
PCS-985TE Transformer Relay 3-g
Date: 2015-07-29
3 Operation Theory
Figure 3.8-2 Connection of VT and CT of directional element ........................................... 3-70
Figure 3.8-3 Directional characteristic of ground overcurrent protection......................... 3-70
Figure 3.8-4 Logic diagram of main transformer ground overcurrent protection (x=1,2,3)
............................................................................................................................................... 3-72
Figure 3.8-5 Logic diagram of direction element of main transformer ground overcurrent
protection .............................................................................................................................. 3-72
Figure 3.8-6 Logic diagram of harmonic blocking eleme nt................................................ 3-73
Figure 3.8-7 Function block diagram of main transformer ground overcurrent protection
............................................................................................................................................... 3-73
Figure 3.9-1 Logic diagram of phase overvoltage protection ............................................ 3-79
Figure 3.9-2 Function block diagram of phase overvoltage protection............................. 3-80
Figure 3.10-1 Logic diagram of undervoltage protection ................................................... 3-84
Figure 3.10-2 Function block diagram of undervoltage protection ................................... 3-85
Figure 3.11-1 Logic diagram of residual overvoltage protection ....................................... 3-89
Figure 3.11-2 Function block diagram of residual overvoltage protection ....................... 3-89
Figure 3.12-1 Logic diagram of stage x of overfrequency protection................................ 3-93
Figure 3.12-2 Logic diagram of stage 1 of overfrequency band accumulate protection .. 3-94
Figure 3.12-3 Logic diagram of stage 4 of overfrequency band accumulate protection .. 3-94
Figure 3.12-4 Function block diagram of overfrequency protection ................................. 3-95
Figure 3.13-1 Logic diagram of stage x of underfrequency protection (x=1~4) .............. 3-101
Figure 3.13-2 Logic diagram of stage 1 of underfrequency band accumulate protection

............................................................................................................................................. 3-102

............................................................................................................................................. 3-102
Figure 3.13-4 Function block diagram of underfrequency protection ............................. 3-103
Figure 3.14-1 Logic diagram of rate-of-frequency-change protection ............................. 3-110
Figure 3.14-2 Function block diagram of rate -of-frequency-change protection ............. 3-110
Figure 3.15-1 Logic diagram of thermal overload protection ........................................... 3-116
Figure 3.15-2 Function block diagram of thermal overload protection ........................... 3-116
Figure 3.16-1 Connection of VT and CT of direction element .......................................... 3-120
Figure 3.16-2 Operating characteristic of phase -to-phase impedance relay .................. 3-120
3-h PCS-985TE Transformer Relay
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3 Operation Theory
Figure 3.16-3 Operating characteristic of phase -to-earth impedance relay.................... 3-121
Figure 3.16-4 Logic diagram of FD PSBR (takes HV side as an example) ....................... 3-123
Figure 3.16-5 Logic diagram of stage 1 of phase-to-phase impedance protection......... 3-124
Figure 3.16-6 Function block diagram of impedance protection ..................................... 3-125
Figure 3.17-1 Logic diagram of breaker failure protection ............................................... 3-130
Figure 3.17-2 Function block diagram of breaker failure protection ............................... 3-131
Figure 3.18-1 Logical diagram of pole disagreement protection ..................................... 3-134
Figure 3.18-2 Function block diagram of pole disagreement protection......................... 3-135
Figure 3.19-1 Logic diagram of breaker flashover protection .......................................... 3-139
Figure 3.19-2 Function block diagram of breaker flashover protection .......................... 3-140
Figure 3.20-1 Logic diagram of channel 1 of mechanical protection 1............................ 3-142
Figure 3.20-2 Function block diagram of mechanical protection (x=1, 2) ....................... 3-143
Figure 3.21-1 Logic diagram of interconnection status element ..................................... 3-147
Figure 3.21-2 Function block diagram of interconnection status element ...................... 3-148
Figure 3.22-1 Logic diagram of current sum element....................................................... 3-149
Figure 3.22-2 Function block of current sum element...................................................... 3-150
Figure 3.23-1 Current pre-processing logic diagram........................................................ 3-152
Figure 3.23-2 Function block diagram of three-phase current element .......................... 3-153
Figure 3.24-1 Voltage pre-processing logic diagram........................................................ 3-157
Figure 3.24-2 Function block diagram of three-phase voltage element .......................... 3-157
Figure 3.25-1 Function block diagram of residual current element ................................. 3-161
Figure 3.26-1 Function block diagram of residual voltage element................................. 3-162
List of Tables
Table 3.2-1 Phase shift matrix for phase compensation ...................................................... 3-5
Table 3.2-2 Input signals of transformer current differential protection ........................... 3-21
Table 3.2-3 Output signals of transformer current differential protection ........................ 3-21
Table 3.2-4 Output signals of transformer current differential protection (event recorder)
............................................................................................................................................... 3-21
Table 3.2-5 Output signals of transformer current differential protection (measurements)

............................................................................................................................................... 3-22
PCS-985TE Transformer Relay 3-i
Date: 2015-07-29
3 Operation Theory
Table 3.2-6 Settings list of transformer current differential protection ............................. 3-23
Table 3.3-1 Input signals of restricted earth fault protection ............................................. 3-34
Table 3.3-2 Output signals of restricted earth fault protection .......................................... 3-34
Table 3.3-3 Output signals of restricted earth fault protection (event recorder) .............. 3-34
Table 3.3-4 Output signals of restricted earth fault protection (measurements) .............. 3-35
Table 3.3-5 Settings list of restricted earth fault protection ............................................... 3-36
Table 3.4-1 Inverse-time curve parameters of stage 2 of negative-sequence overcurrent

protection .............................................................................................................................. 3-39
Table 3.4-2 Input signals of negative-sequence overcurrent protection ........................... 3-40
Table 3.4-3 Output signals of negative-sequence overcurrent protection ........................ 3-41
Table 3.4-4 Output signals of negative-sequence overcurrent protection (event recorder)

............................................................................................................................................... 3-41
Table 3.4-5 Output signals of negative-sequence overcurrent protection (measurements)

............................................................................................................................................... 3-41
Table 3.4-6 Settings list of negative-sequence overcurrent protection............................. 3-41
Table 3.5-1 Input signals of overexcitation protection ....................................................... 3-46
Table 3.5-2 Output signals of overexcitation protection .................................................... 3-47
Table 3.5-3 Output signals of overexcitation protection (event recorder)......................... 3-47
Table 3.5-4 Output signals of overexcitation protection (measurements) ........................ 3-47
Table 3.5-5 Settings list of overexcitation protection ......................................................... 3-48
Table 3.6-1 Inverse-time curve parameters of stage 3 of main transformer phase

Table 3.6-2 Input signals of main transformer phase overcurrent protection................... 3-59
Table 3.6-3 Output signals of main transformer phase overcurrent protection................ 3-59
Table 3.6-4 Output signals of main transformer phase overcurrent protection (event
recorder)................................................................................................................................ 3-60
Table 3.6-5 Output signals of main transformer phase overcurrent protection

(measurements) .................................................................................................................... 3-60
Table 3.6-6 Settings list of main transformer phase overcurrent protection .................... 3-61
Table 3.7-1 Input signals of phase overcurrent alarm elements ........................................ 3-65
Table 3.7-2 Output signals of phase overcurrent alarm elements ..................................... 3-65
Table 3.7-3 Output signals of phase overcurrent alarm elements (event recorder) ......... 3-65
3-j PCS-985TE Transformer Relay
Date: 2015-07-29
3 Operation Theory
Table 3.7-4 Settings list of phase overcurrent alarm elements.......................................... 3-66
Table 3.8-1 Inverse-time curve parameters of stage 3 of main transformer ground

Table 3.8-2 Input signals of main transformer ground overcurrent protection................. 3-73
Table 3.8-3 Output signals of main transformer ground overcurrent protection.............. 3-74
Table 3.8-4 Output signals of main transformer ground overcurrent protection (event
recorder)................................................................................................................................ 3-74
Table 3.8-5 Output signals of main transformer ground overcurrent protection

(measurements) .................................................................................................................... 3-74
Table 3.8-6 Settings list of main transformer ground overcurrent protection .................. 3-75
Table 3.9-1 Input signals of phase overvoltage protection ................................................ 3-80
Table 3.9-2 Output signals of phase overvoltage protection ............................................. 3-80
Table 3.9-3 Output signals of phase overvoltage protection (event recorder).................. 3-80
Table 3.9-4 Output signals of phase overvoltage protection (measurements) ................. 3-81
Table 3.9-5 Settings list of phase overvoltage protection .................................................. 3-81
Table 3.10-1 Input signals of undervoltage protection ....................................................... 3-85
Table 3.10-2 Output signals of undervoltage protection .................................................... 3-85
Table 3.10-3 Output signals of phase undervoltage protection (event recorder) ............. 3-85
Table 3.10-4 Output signals of phase undervoltage protection (measurements) ............. 3-86
Table 3.10-5 Settings list of phase undervoltage protection.............................................. 3-86
Table 3.11-1 Input signals of residual overvoltage protection ........................................... 3-89
Table 3.11-2 Output signals of residual overvoltage protection ........................................ 3-90
Table 3.11-3 Output signals of residual overvoltage protection (event recorder) ............ 3-90
Table 3.11-4 Output signals of residual overvoltage protection (measurements) ............ 3-90
Table 3.11-5 Settings list of residual overvoltage protection............................................. 3-90
Table 3.12-1 Input signals of overfrequency protection ..................................................... 3-95
Table 3.12-2 Output signals of overfrequency protection .................................................. 3-95
Table 3.12-3 Output signals of overfrequency protection (event recorder) ...................... 3-96
Table 3.12-4 Output signals of overfrequency protection (measurements) ...................... 3-97
Table 3.12-5 Settings list of overfrequency protection....................................................... 3-97
Table 3.13-1 Input signals of underfrequency protection ................................................ 3-103
PCS-985TE Transformer Relay 3-k
Date: 2015-07-29
3 Operation Theory
Table 3.13-2 Output signals of underfrequency protection.............................................. 3-103
Table 3.13-3 Output signals of underfrequency protection (event recorder) .................. 3-104
Table 3.13-4 Output signals of underfrequency protection (measurements).................. 3-105
Table 3.13-5 Settings list of underfrequency protection .................................................. 3-105
Table 3.14-1 Input signals of rate -of-frequency-change protection................................. 3-111
Table 3.14-2 Output signals of rate-of-frequency-change protection .............................. 3-111
Table 3.14-3 Output signals of rate-of-frequency-change protection (event recorder) .. 3-111
Table 3.14-4 Settings list of rate -of-frequency-change protection .................................. 3-112
Table 3.15-1 Input signals of thermal overload protection............................................... 3-116
Table 3.15-2 Output signals of thermal overload protection ............................................ 3-116
Table 3.15-3 Output signals of thermal overload protection (event recorder) ................ 3-117
Table 3.15-4 Output signals of thermal overload protection (measurements) ................ 3-117
Table 3.15-5 Settings list of thermal overload protection ................................................ 3-117
Table 3.16-1 Input signals of impedance protection......................................................... 3-125
Table 3.16-2 Output signals of impedance protection...................................................... 3-125
Table 3.16-3 Output signals of impedance protection (event recorder) .......................... 3-125
Table 3.16-4 Output signals of impedance protection (measurements).......................... 3-126
Table 3.16-5 Settings list of impedance protection .......................................................... 3-127
Table 3.17-1 Input signals of breaker failure protection ................................................... 3-131
Table 3.17-2 Output signals of breaker failure protection ................................................ 3-131
Table 3.17-3 Output signals of breaker failure protection (event recorder) .................... 3-131
Table 3.17-4 Settings list of breaker failure protection..................................................... 3-132
Table 3.18-1 Input signals of pole disagreement protection ............................................ 3-135
Table 3.18-2 Output signals of pole disagreement protection ......................................... 3-135
Table 3.18-3 Output signals of pole disagreement protection (event recorder) ............. 3-135
Table 3.18-4 Settings list of pole disagreement protection.............................................. 3-136
Table 3.19-1 Input signals of breaker flashover protection.............................................. 3-140
Table 3.19-2 Output signals of breaker flashover protection ........................................... 3-140
Table 3.19-3 Output signals of breaker flashover protection (event recorder) ............... 3-140
Table 3.19-4 Settings list of breaker flashover protection ............................................... 3-141
3-l PCS-985TE Transformer Relay
Date: 2015-07-29
3 Operation Theory
Table 3.20-1 Input signals of mechanical protection (x=1, 2)........................................... 3-143
Table 3.20-2 Output signals of mechanical protection (x=1, 2) ........................................ 3-143
Table 3.20-3 Output signals of mechanical protection (event recorder) (x=1, 2) ............ 3-143
Table 3.20-4 Settings list of mechanical protection.......................................................... 3-144
Table 3.21-1 Input signals of interconnection status element ......................................... 3-148
Table 3.21-2 Output signals of interconnection status element ...................................... 3-148
Table 3.21-3 Output signals of interconnection status element (measurements) .......... 3-148
Table 3.21-4 Settings list of interconnection status element ........................................... 3-149
Table 3.22-1 Input signals of current sum eleme nt........................................................... 3-150
Table 3.22-2 Output signals of current sum element........................................................ 3-150
Table 3.22-3 Output signals of current sum element: measurements............................. 3-150
Table 3.22-4 Settings list of current sum element ............................................................ 3-151
Table 3.23-1 Input signals of three-phase current element .............................................. 3-153
Table 3.23-2 Output signals of three-phase current element ........................................... 3-153
Table 3.23-3 Output signals of three-phase current element (event recorder) ............... 3-153
Table 3.23-4 Output signals of three-phase current element (measurements) ............... 3-153
Table 3.23-5 Settings list of three-phase current element................................................ 3-155
Table 3.24-1 Input signals of three-phase voltage element.............................................. 3-157
Table 3.24-2 Output signals of three-phase voltage element ........................................... 3-158
Table 3.24-3 Output signals of three-phase voltage element (event recorder) ............... 3-158
Table 3.24-4 Output signals of three-phase voltage element (measurements) ............... 3-158
Table 3.24-5 Settings list of three-phase voltage element ............................................... 3-160
Table 3.25-1 Input signals of single current element with filter ....................................... 3-161
Table 3.25-2 Output signals of residual current element ................................................. 3-161
Table 3.25-3 Output signals of residual current element (measurements) ..................... 3-161
Table 3.25-4 Settings list of residual current element ...................................................... 3-161
Table 3.26-1 Input signals of residual voltage element .................................................... 3-162
Table 3.26-2 Output signals of residual voltage element ................................................. 3-162
Table 3.26-3 Output signals of residual voltage element (measurements) ..................... 3-162
Table 3.26-4 Settings list of residual voltage element ...................................................... 3-163
PCS-985TE Transformer Relay 3-m
Date: 2015-07-29
3 Operation Theory
3-n PCS-985TE Transformer Relay
Date: 2015-07-29
3 Operation Theory
3.1 Overview
The device has 2 plug-in modules (protection DSP module and fault detector DSP module) for
protection calculation. Protection DSP module is responsible for calculation of protection elements,
and fault detector DSP module is responsible for calculation of general fault detector element to
determine fault appearance on the protected power system. General fault detector picks up to
provide positive supply to output relays. The output relays can only operate when both a protection
element and the corresponding general fault detector operate simultaneously. Otherwise, the
output relays would not operate. An alarm message will be issued with blocking output if a
protection element operates while the corresponding general fault detector does not operate.
The fault detector of fault detector DSP module consists of several independent fault detector
elements, which can monitor corresponding protection elements without influence to other
protection elements. For example, biased current differential protection will not release tripping
command until both protection element of protection DSP module and the corresponding fault
detector of fault detector DSP module operate simultaneously. Furthermore, if there is a hardware
fault on one DSP module or the differential current is at the trip boundary, the inconsistent pickup
of fault detectors of biased current differential protection on two DSP modules will occur.
3.2 Transformer Current Differential Protection (87T)
NOTICE!
In Section 3.2, the prefix “Y” in settings (such as [Y.87T.I_Biased]) and input/output
signals (such as [Y.87T.Op_Biased]) can be Tr. Details of the prefix are:
Tr.87T Corresponds to main transformer current differential protection
3.2.1 Application
Transformer current differential protection is the main protection for the internal short -circuit fault of
transformer winding. Current differential protection can operate quickly to clear the internal fault to
avoid the transformer from damages or reduce the maintenance cost as low as possible.
3.2.2 Function Description
 Up to 6 group CT inputs for current differential protection.
 It is suitable for two-winding transformer and three-winding transformer.
 For Y-Y, △→△, △→Y and Y→△ connection, all possible vector combinations have been taken
into account, so it is very flexible.
 Optional inrush current distinguished principles and inrush current blocking method, which
can avoid the inrush current reliably, and it can also ensure the operation speed when a fault
happens during normal operation.
Date: 2015-07-29
3 Operation Theory
 Fifth harmonic blocking criterion applied continuously to detect overexcitation condition.
 Reliable biased differential element.
Biased current differential element with initial restraint slope is adopted, it consists of sensitive
and conventional biased differential elements as well as independent CT saturation criterion.
 High sensitive DPFC differential element.
DPFC current differential element can fully reflect the change of differential current and
restraint current, and it is not affected by the load current and is sensitive to small internal fault
current within the transformer. Its performance against CT saturation is also good.
 Unrestrained instantaneous differential element is equipped.
For internal serious fault, once the differential current is larger than the current setting of
instantaneous differential element, the current differential protection will operate to cut off the
fault quickly.
 Reliable differential CT circuit abnormality detection.
Voltage is also used to judge the abnormality of differential CT circuit, multi-phase CT circuit
failure, multi-side CT circuit failure and short-circuit condition can be detected.
3.2.3 Protection Principle
3.2.3.1 Overview
Current differential protection includes three operation elements: biased differential element,
unrestrained differential element and DPFC current differential element. When the differential
current is larger than the corresponding current threshold and no larger harmonic is detected,
current differential protection will operate, and it will drop off if the fault current disappears.
Sensitive biased differential element is variable slope differential element with initial restraint slope.
Conventional biased differential element is differential element with two broken lines. Unrestrained
differential element is used to cut off the serious fault quickly and there is no any blocking element
for it. Main transformer DPFC differential element adopts the current change to calculate, it is very
sensitive to slight fault under heavy loading condition. The three differential elements coordinate
with each other, so quick and high sensitive differential protection can be realized.
3.2.3.2 Amplitude Compensation
Generally, the magnitudes of secondary current of each side of transformer are different due to the
difference of voltage level and CT ratio. The current value difference between each side shall be
eliminated before calculation for current differential protection by amplitude compensation .
The nameplate parameters of the transformer (includes the rated apparent power and the rated
voltage of each side) and the primary and secondary data of CT of each side of the transformer
should be input to the device. The device will calculate the rated current of each side and the
differential adjust coefficient automatically according to the parameters.
 Calculate rated primary current of each side
Date: 2015-07-29
3 Operation Theory
Sn
I 1bBrm  Equation 3.2-1
3 U 1 nBrm
Where:
Brm=Side (branch) “m”.
Sn is the maximum rated capacity.
U 1 nBrm is rated primary voltage of side m.
I 1bBrm is rated primary current of side m.
 Calculate rated secondary current of each side
I 1bBrm
I 2 bBrm  Equation 3.2-2
CT Brm
Where:
I 2 bBrm is rated secondary current of side m.
CT Brm is the CT ratio of side m.
 Calculate differential adjust coefficient
k B a se  1
I 2 b B a se
k B rm 
I 2 b B rm Equation 3.2-3
( I 2 b B a se / I 2 n B a se )
 32
( I 2 b B rm / I 2 n B rm )
Where:
Brm=Branch (side) “m”.
I 2 bB rm I 2 b B a s e are rated secondary current of calculated side and referenced side of

,
transformer.
I 2 nB rm I 2 n B a s e are rated secondary current of CT of calculated side and referenced side of

,
transformer (1A or 5A).
Date: 2015-07-29
3 Operation Theory
k Base is adjust coefficient of referenced side of transformer.
k Brm is adjust coefficient of calculated side of transformer.
Via the setting [Y.87T.Opt_BaseSide], the referenced side for transformer current differential
protection can be selected, main transformer LV side (step-down transformer HV side) is the
default referenced side. If Equation 3.2-3 is not met, the setting error alarm signals
[Y.87T.Fail_Settings] will be issued and displayed on LCD and the protective device will be
blocked.
3.2.3.3 Phase Compensation
 Phase Compensation Principle
For the connection mode of transformer each side winding is different, different vector group will
be generated, the vector group will lead the phase shift of secondary currents of each side, which
should be adjusted via the phase compensation of the software.
The preconditions for current phase compensation calculation are:
1) Each side three-phase CT of transformer shall be connected in star type.
2) The secondary current channel of CT will be connected to the protection device directly.
3) The positive polarity of each side three-phase CT shall be at busbar side.
Phase compensation is carried out from each side to the referenced side. The referenced side is 0
or 12 o’clock. Other sides are n o’clock (n=0~11) relative to the referenced side. If the referenced
side is △ connection, then it does not need to be compensated, other sides need to shift for n
o’clock. If the referenced side is Y connection, then the referenced side is 1 o’clock to eliminate the
effects of zero-sequence current, other sides need to shift for n+1 o’clock.
For example:
The vector group of a transformer is Y0/Δ11, the setting [Tr_HVS.WdgConn] should be set as
“Wye”, the setting [Tr_LVS.WdgConn] should be set as “Delta”, and the setting
[Tr_LVS.Clk_WRT_HVS] should be set as “11”.
1) If LV side is set as the referenced side, it is 1 o'clock for HV side relative to LV side, so the
phase shift matrix corresponds to 1 o’clock is adopted to compensate HV side current. The LV
side is △ connection, so it does not need to be compensated.
2) If HV side is set as the referenced side, the HV side is Y connection, so the phase shift matrix
corresponds to 1 o’clock is adopted to compensate HV side current. It is 11 o'clock for LV side
relative to HV side, so the phase shift matrix corresponds to 12 (or 0, 11+1=12) o’clock is
adopted to compensate LV side current.
Date: 2015-07-29
3 Operation Theory
Table 3.2-1 Phase shift matrix for phase compensation
Relative o’clock Matrix
1 0 0
0  
0 1 0
(No phase shit)  
0 0 1 

 1 1 0 
1 1  
0 1 1
(Shift 30°leading)  
3 
 1 0 1 
 0 1 0
2  
0 0 1
(shift 60°leading)  
  1 0 0 
 0 1 1 
3 1  
1 0 1
(Shit 90°leading)  
3 
 1 1 0 
0 0 1
4  
1 0 0
(Shit 120°leading)  
0 1 0 

1 0 1 
5 1  
1 1 0
3 
 0 1  1 
 1 0 0
6  
0 1 0
 0 0  1 
 1 1 0 
7 1  
0 1 1
(Shift 150°lagging) 3  
 1 0  1 
0 1 0
8  
0 0 1
(Shift 120°lagging)  
1 0 0 

 0 1  1
S9 1  
1 0 1
3 
 1 1 0 
Date: 2015-07-29
3 Operation Theory
Relative o’clock Matrix
 0 0  1
10  
1 0 0
 0 1 0 

 1 0  1
11 1  
1 1 0
3 
 0 1 1 
NOTICE!
For Y-y and D-d connection the vector group can ONLY BE even number, (i.e. Y-y4,
D-d8), for Y-d and D-y connection the vector group can ONLY BE odd number, (i.e.
Y-d11, D-y5), if the two conditions can not be met, the setting error alarm signal
[Y.87T.Fail_Settings] will be issued and displayed on LCD and the protective device will
be blocked.
3.2.3.4 Calculations of Differential Current and Restraint Current
The calculation equation of differential current is:
 I dA   I A1  I A2  I A3 I A4

         
I   / I 2 bBr 1  M 2  I B 2 / I 2 bBr 2  M 3  I B 3 / I 2 bBr 3  M 4  I B 4 / I 2 bBr 4 
 dB  M 1  I B1      
 I dC   I C 1 

     
 I C 2 

   
 I C 3 

 
 I C 4 

   
1 2 3 4 Equation
 I A5   I A6  3.2-4
   
M 5   I B 5  / I 2 bBr 5  M 6   I B 6  / I 2 bBr 6
 I C 5   I C 6 
      
5 6
The above equation can be simplified to the following:
 I dA  I  A 1  I  A 2  I  A 3  I A 4  I A 5  I A 6

 I dB  I  B 1  I  B 2  I  B 3  I B 4  I B 5  I B 6 Equation 3.2-5

 I dC  I  C 1  I  C 2  I  C 3  I C 4  I C 5  I C 6
Where:
I Am , I Bm , I Cm in the equation are the secondary current vectors of side m (m=1, 2, 3, 4, 5, 6).
I  Am , I  Bm , I Cm are corrected secondary current vectors of side m (m=1, 2, 3, 4, 5, 6).
I dA , I dB , I dC are differential currents.
M 1, M 2 , M 3 , M 4 , M 5 , M 6 are phase shift matrixes of each side of transformer respectively. Its value is
Date: 2015-07-29
3 Operation Theory
decided according to the vector group of transformer and please refers to Section 3.2.3.3 for
details.
I 2 bBr 1 , I 2 bBr 2 , I 2 bBr 3 , I 2 bBr 4 , I 2 bBr 5 , I 2 bBr 6 are rated secondary values of each side of transformer
respectively.
The calculation equation of restraint current is:

 
1
 I rA  I  A1  I  A 2  I  A 3  I  A 4  I  A 5  I  A 6
2


 
1
 I rB  I B1  I B 2  I B 3  I B 4  I B 5  I B 6 Equation 3.2-6
 2

 
1
 I rC  I C 1  I C 2  I C 3  I C 4  I C 5  I C 6
 2
Where:
I rA , I rB , I rC are restraint currents.
Current compensation process is shown in the flowing figure (takes two-winding transformer as an
example). The symbol “*” represents the polarity of CT. If current flowing into the polarity side of CT,
the current direction is defined as positive direction. In an ideal situation, the differential current
（i.e. I d  I  _ H  I  _ L ）should be zero during the normal operation of the transformer or an
external fault occurring.
Ip_H Ip_L
* * *
* * *
HV side LV side
I_H I_L
PCS-985TI
Phase shift/zero sequence Phase shift/zero sequence
current elimination (*M1) current elimination (*M2)
Magnitude compensation Magnitude compensation

(/I2bBr1) (/I2bBr2)
I'_H I'_L
Calculate differential current and restraint current
Figure 3.2-1 Transformer current compensation calculation process
In above figure:
Ip_H, Ip_L are primary current vectors of HV and LV side respectively.
I_H, I_L are secondary current vectors of HV and LV side respectively.
I’_H, I’_L are secondary corrected current vectors of HV and LV side respectively.
M1, M2 are phase shift matrixes of HV and LV side respectively.
Date: 2015-07-29
3 Operation Theory
I 2 bBr 1 , I 2 bBr 2 are rated secondary currents of HV and LV side respectively.
To clarify the principle, in an ideal situation, three important operation conditions are considered.
1. Through-flowing current under undisturbed conditions or external fault:
The direction of I’_H is reverse to that of I’_L, but the amplitude of I’_H is equal to that of I’_L,
i.e. I’_H=–I’_L, |I’_H|=|I’_L|.
Id=|I’_H+I’_L|=|I’_H–I’_H|=0;
Ir=(|I’_H|+|I’_L|)/2=(|I’_H|+|I’_H|)/2=|I’_H|
No differential current (Id=0), restraint current (Ir) is one time of the through-flowing current,
and current differential protection will not operate.
2. Internal short-circuit fault, e.g. the fed currents of two sides are equal:
I’_L=I’_H, moreover |I’_L|=|I’_H|
Id=|I’_H+I’_L|=|I’_H+I’_H|=2|I’_H|;
Ir=(|I’_H|+|I’_L|)/2=(|I’_H|+|I’_H|)/2=|I’_H|
Differential current (Id) is two times of restraint current (Ir) and it corresponds to the total fault
current, current differential protection operates sensitively.
The above results show that Id = 2Ir during an internal fault. I.e. the operation characteristic of
current differential protection for internal fault is a straight line with a slope of 2.
3. Internal short-circuit fault, current is only fed from one side:
Assuming I’_L=0
Id=|I’_H+I’_L|=|I’_H+0|=|I’_H|;
Ir=(|I’_H|+|I’_L|)/2=(|I’_H|+|0|)/2=|I’_H|/2
Differential current (Id) is two times of restraint current (Ir) and it corresponds to fault current of
single side, current differential protection operates sensitively.
The above results show that Id = 2Ir during an internal fault. I.e. the operation characteristic of
current differential protection for internal fault is a straight line with a slope of 2.
3.2.3.5 Sensitive Biased Differential Element
The operation equation of sensitive biased differential element is:
Date: 2015-07-29
3 Operation Theory
 I d  K b l  I r  I D iff . P ic k u p (Ir  nIe )


 K b l  K b l 1  K b lr  ( I r / I e )

 I d  K b l 2  ( I r  n I e )  b  I D iff . P ic k u p (Ir  nIe )

K  ( K bl 2  K bl1 ) / ( 2  n )
 b lr
b  (K  K b lr  n )  n I e Equation 3.2-7
 bl1

m
1
 Ir   Ii
 2 i 1
 m
I 
 d
 Ii
 i 1
Where:
I i (i = 1, 2… m) are the corrected secondary currents of each side of transformer respectively.
Id is the differential current.
Ir is the restraint current.
I D iff . P ic k u p is the pickup current setting of biased differential element [Y.87T.I_Biased].
I e is the rated current of transformer.
K b1
is the restraint coefficient of biased differential element.
K b1r
is the restraint coefficient increment of biased differential element.
K bl1 is the initial slope setting of biased differential element, it takes 0.10 generally
[Y.87T.Slope1].
K bl 2 is the maximum slope setting of biased differential element, it takes 0.70 generally
[Y.87T.Slope2].
n is the restraint current multiple when the restraint coefficient reach to the maximum value. This
internal value is set as 6 fixedly.
3.2.3.6 Conventional Biased Differential Element
Conventional biased differential element with higher pickup current and higher restraint coefficient
comparing with sensitive biased differential element is equipped. Its biased restraint characteristic
can make the differential element not operate due to CT transient and steady-state saturation
Date: 2015-07-29
3 Operation Theory
during external fault, and it can operate reliably even the CT is seriously saturated during internal
fault. Operation criterion of conventional biased differential element is:
 I d  1 .2  I e

Id  Ir Equation 3.2-8
Where:
I d and I r have the same definitions as mentioned above.
NOTICE!
The related parameters of conventional biased differential element are set FIXEDLY in
the device. Therefore, the slope and the knee point with constant values do not need to
be set by user.
3.2.3.7 Unrestrained Instantaneous Differential Element
Unrestrained instantaneous differential element of transformer is used to accelerate the operation

speed for serious internal fault. The element has no blocking element and the current setting is
very high. If differential current of any phase is larger than the current setting of unrestrained
instantaneous differential element, the protection will operate to trip the circuit breaker of each side
instantaneously. Its operation criterion is:
I d  max  [Y.87T.I_Inst] Equation 3.2-9
Where:
I d  max is the maximum value of three phase differential currents.
[Y.87T.I_Inst] is the current setting of the unrestrained instantaneous differential element.
3.2.3.8 Main Transformer DPFC Differential Element
If internal slight fault occurs in main transformer, sensitive and conventional biased differential
element may not response sensitively due to the influence of load current. DPFC (Deviation of
Power Frequency Component) biased differential element of main transformer is equipped with
the device for that and it can significantly improve the sensitivity of the protection during small
current internal fault of main transformer. It can be enabled or disabled conveniently by the
corresponding logic setting.
The operation criteria of DPFC differential element are as follows:
  I d  1 . 25 *  I dt  I dth

  I d  0 .6 *  I r Ir  2 Ie Equation 3.2-10
  I  0 . 75 *  I  0 . 3 * I Ir  2Ie
 d r e
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3 Operation Theory
Ir    I m
i 1
Id    I m
i 1
Where:
 I dt is the floating threshold varied with the change of differential current. Take its multiple as
1.25 can ensure the threshold value always a bit higher than the unbalance current. So that
unwanted operation of the device can be avoided during power swing or frequency deviation
condition.
。。
 I 1 ,…  I m are the DPFC current of each side of main transformer respectively.
 I d is the DPFC differential current.
I dth is the fixed threshold.
 I r is the DPFC restraint current, the maximum value of three-phase DPFC current of all sides
are used as the restraint current.
NOTICE!
Calculation of restraint current of generator DPFC differential element is DIFFERENT

from steady-state biased differential element, all the settings about DPFC differential
element is FIXED in the program, it is difficult to test the characteristic at site.
If the above criteria are met, CT circuit failure detection (optional), inrush current detection and
overexcitation detection are also adopted to control transformer DPFC differential element.
For the restraint coefficient of transformer DPFC differential element can take a higher value, so it
has high ability to eliminate the effect of transient and steady-state CT saturation during an
external fault. Transformer DPFC differential element improves the sensitivity for detecting
transformer internal slight fault.
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3 Operation Theory
3.2.3.9 Operation Characteristic of Differential Protection
Id (Ie)
differential Tripping area of
current instantaneous diff.
2
K=
[Y.87T.I_Inst]
ff.
di
.0 ed f
K bia a o
l re
=1 s
na a
tio ing
of iff.
en pp
ea d
ar ed
nv ri
co T
ng a s
2]
pi e bi
pe
p
o
i
Sl
Tr itiv
T.
ns
7
.8
se
[Y
1.2Ie
pe1]
T.Slo
[Y.87
[Y.87T.I_Biased]
restraint current
0 1Ie 1.2Ie nIe Ir (Ie)
Figure 3.2-2 Operation characteristic curve of steady-state differential element of transformer
△ Id
m
K=
K=0.75
1.2Ie
K=0.6
[Tr.87T.I_Biased]
2Ie
△ Ir
Figure 3.2-3 Operation characteristic curve of DPFC differential element of main transformer
Current differential protection carries out the fault discrimination according to the current of each
phase. If the current criteria are met and no related blocking element(s) operate, differential
Date: 2015-07-29
3 Operation Theory
protection will operate to trip.
1) Sensitive biased differential element will send tripping signal monitored by CT saturation,
overexcitation, inrush current and CT circuit failure (optional). It can ensure the sensitivity of
differential protection and avoid the unwanted operation when CT is saturated during an
external fault. Its operation area is the tint shadow area in the figure above.
2) Conventional biased differential element will send tripping signal monitored by inrush current
and CT circuit failure (optional). It eliminates the influence of transient and steady -state
saturations of CT during an external fault and ensures differential protection can operate
reliably even if CT is saturated during an internal fault by means of its biased characteristic. Its
operation area is the deeper shadow area in the figure above.
3) Unrestrained instantaneous differential element will send tripping signal without any blocking
element if differential current of any phase is larger than corresponding current setting.
Unrestrained instantaneous differential element is used to cut off the internal serious fault
quickly. Its operation area is over the above two areas with the deepest dark shadow.
3.2.3.10 Inrush Current Detection
The logic setting [Y.87T.Opt_Inrush_Ident] is provided for users to select the inrush current
detection principle. If the logic setting is set as “Waveform”, discrimination by waveform distortion
is enabled, and if it is set as “Hm2”, discrimination by second harmonics is enabled .
The logic setting [Y.87T.Opt_BlkMode_Inrush] is provided for users to select the inrush current
blocking mode, synthetic blocking mode, cross blocking mode and phase blocking mode can be
selected.
3.2.3.10.1 Distinguishing by Harmonics
The ratio between second harmonic and fundamental component of three-phase differential
current is used to distinguish inrush current. Its criteria are:
I 2 nd  K 2 xb * I 1 st Equation 3.2-11
Where:
I 2 n d is the second harmonic of per-phase differential current.
I 1 s t is the fundamental component of the differential current of the corresponding phase.
K 2 xb is the restraint coefficient of second harmonics [Y.87T.K_Hm2_Inrush],
[Y.87T.K_Hm2_Inrush]=0.15 is recommended.
Users can select the second harmonic criterion or wave distortion criterion (see following section)
to distinguish inrush current.
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3 Operation Theory
3.2.3.10.2 Distinguishing by Wave Distortion
After the transmission of current transformer, the differential current is basically the fundamental
sinusoidal wave during an internal fault. When the transformer is energized, plentiful harmonics
will appear, the waveform will be distorted, the waveform is interrupted and unsymmetrical.
When an internal fault happens, the following expression is established:
S  K b * S
 Equation 3.2-12
S  St
Where:
S is the full-cycle integral value of differential current;
S  is the full-cycle integral value of (differential current instantaneous value+ differential current
instantaneous value a half cycle ago);
K b is a fixed coefficient.
S t is the threshold setting. The expression of S t is:
S t   * I d  0 .1 I e Equation 3.2-13
Where:
I d is the full-cycle integral value of differential current;
 is a ratio coefficient.
When inrush current appears, the above waveform distinguish expression is not met, current
differential protection will not mal-operate.
3.2.3.10.3 Inrush Current Blocking Mode
Users can select the inrush current blocking mode by the logic setting
[Y.87T.Opt_BlkMode_Inrush].
 Synthetic Blocking Mode
If the following criterion is met, the three-phase differential protection will be blocked.
M a x { I a 2 n d , I b 2 n d , I c 2 n d }  [ Y .8 7 T . K _ H m 2 _ In r u s h ]  M a x ( I a 1 n d , I b 1 n d , I c 1 n d ) Equation 3.2-14
 Cross Blocking Mode
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3 Operation Theory
 I a 2 n d  [ Y .8 7 T . K _ H m 2 _ In r u s h ]  I a 1 n d
 or
 I b 2 n d  [ Y .8 7 T . K _ H m 2 _ In r u s h ]  I b 1 n d
 or Equation 3.2-15
 I c 2 n d  [ Y .8 7 T . K _ H m 2 _ In r u s h ]  I c 1 n d
 I c 2 n d  [ Y .8 7 T . K _ H m 2 _ In r u s h ]  I c 1 n d

 I b 2 n d  [ Y .8 7 T . K _ H m 2 _ In r u s h ]  I b 1 n d
 Phase Blocking Mode
If one of the following criteria is met, only the corresponding phase differential protection will be
blocked.

 I b 2 n d  [ Y .8 7 T . K _ H m 2 _ In r u s h ]  I b 1 n d Equation 3.2-16

 I c 2 n d  [ Y .8 7 T . K _ H m 2 _ In r u s h ]  I c 1 n d
The synthetic blocking mode is strongly recommended to be selected in the actual application.
Operating experience indicating that the synthetic blocking mode can guarantee the differential
protection not operate under most inrush current situation, and ensure the differential protection
can operate sensitively when the excitation is no-load energized on to a fault.
3.2.3.11 CT Saturation Detection
When an transformer external fault happens, great through-fault current will flowing through the CT,
if the saturation degree of LV side CT is inconsistent with that of HV side CT, great unbalance
differential current will generate in the differential circuit, which will lead to the mal-operation of
differential protection. So the CT saturation detection function is required for transformer
differential protection.
There is a certain time before the CT falling into saturated state, so the changing characteristic of
differential current and restraint current within the initial time of the fault can be used to judge
whether it is an external fault. For an external fault, the deviation of power frequency component
(DPFC) of restraint current appears before the appearance of DPFC of differential current; for an
internal fault, DPFC of restraint current and differential current appear almost simultaneously. If
external fault is detected, CT saturation blocking criterion is enabled.
In order to prevent an unwanted operation of sensitive biased differential element caused by

transient state saturation of CT during an external fault, the second and third harmonics of current
are used for the protection device to discriminate saturation of three-phase CT.

I _ 2 nd  K  sat _ 2 xb  I _ 1 st
 Equation 3.2-17
 I  K  sat  I
  _ 3 rd _ 3 xb _ 1 st
Where:
I  _ 1 st is the fundamental component of one phase differential current.
Date: 2015-07-29
3 Operation Theory
I  _ 2 nd is the secondary harmonic of the corresponding phase differential current.
I  _ 3 rd is the third harmonic of the corresponding phase differential current.
K  sa t _ 2 x b and K  sa t _ 3 x b are fixed coefficients.
If any harmonic of one phase differential current meets the above equation, it will be considered
that it is CT saturation to cause this phase differential current and sensitive biased differential
element will be blocked. The criterion is only enabled when the transformer is in service.
3.2.3.12 Overexcitation Detection
When a transformer is overexcited, the exciting current will increase sharply which may result in
unwanted operation of differential protection. Therefore the overexcitation shall be discriminated to
block differential protection. If overexcitation is detected, then sensitive biased differential element
will be blocked.
I 5 th  k 5 xb * I 1 st Equation 3.2-18
Where:
I 1 s t is the fundamental component of differential current.
I 5 th is the fifth harmonic of differential current.
k 5 xb is the coefficient of fifth harmonic overexcitation detection [Y.87T.K_Hm5_OvExc]
3.2.3.13 Differential Circuit CT Supervision
3.2.3.13.1 Differential Circuit CT Abnormality Alarm
If the transformer differential current of any phase meets the following criteria and corresponding
differential element is enabled, the transformer differential current abnormality alarm
[Y.87T.Alm_Diff] with a time delay of 300ms, this alarm signal will not block the differential element.
The signal will reset if the differential current disappears with a time delay of 10s.
 I d  [Y . 8 7 T . I _ A l m ]
 Equation 3.2-19
 Id  k * Ir
Id is the differential current.
Ir is the restraint current.
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3 Operation Theory
k is the restraint coefficient of differential current abnormality alarm.
[Y.87T.I_Alm] is the current setting of differential current abnormality alarm.
3.2.3.13.2 Differential Circuit CT Circuit Failure Alarm
 Criteria
If any one of following four conditions is satisfied after the fault detector of biased differential
current picks up, it will be determined as fault and differential protection is released, otherwise it
will be determined that the fault detector of biased differential current picks up due to differential
CT circuit failure or short-circuit.
 Negative-sequence voltage of any side is larger than 1V.
 Any phase current of any side increases after the fault detector picks up.
 The maximum phase current is larger than 1.2Ie after the fault detector picks up.
 Among all the current channels, any three phases of the current decrease after fault
detector picks up.
If none of above four conditions is satisfied within 40ms after the fault detector of biased
differential current picks up, it will be determined as differential CT circuit failure and CT circuit
failure alarm will be issued. Then if the logic setting [Y.87T.En_CTS_Blk] is set as “1”, sensitive
and conventional biased differential element will be blocked, if the logic setting
[Y.87T.En_CTS_Blk] is set as “0”, sensitive and conventional biased differential element will not be
blocked. Transformer unrestrained instantaneous differential element will not be blocked during
CT circuit failure.
Before the transformer is connected to the power grid, CT circuit failure alarming and blocking
function will quit automatically.
The above conditions contain the voltage criteria and current criteria, which realizes the high
accuracy and sensitivity of the CT circuit failure detection.
The CT circuit failure alarm is latched once issued, it can be reset only after the failure is cleared
and the device is reset (i.e. the binary input [BI_RstTarg] is energized).
No matter whether the abnormality alarm signal makes the differential protection picks up, there
must be some problems in the differential circuit. For example, when the differential circuit fails,
the differential protection will not pick up for light-loaded condition, but the differential current
abnormality alarm signal will be issued. If the abnormality is treated in time, the mal-operation of
differential protection due to increase of load or external fau lt can be avoided (if the logic setting
[Y.87T.En_CTS_Blk] is set as “0”).
Once the differential CT circuit failure alarm is issued, the CT circuit should be check carefully, only
if the fault is cleared, the reset operation can be conducted.
3.2.4 Logic
For transformer current differential protection, if following three conditions are met, the protection
Date: 2015-07-29
3 Operation Theory
will be enabled.
(1) Logic setting [Y.87T.En] is set as “1”.
(2) The protection function enabling inputs [Y.87T.En1], [Y.87T.En2] are “1”
(3) The protection function blocking input [Y.87T.Blk] is “0”.
If transformer differential protection is disabled, all the related output signals will be reset. If no
external input is configured to [Y.87T.En1] ([Y.87T.En2]), the default initial value of [Y.87T.En1]
([Y.87T.En2]) is “1”; if no external input is configured to [Y.87T.Blk], the default initial value of
[Y.87T.Blk] is “0”.
SIG [Y.87T.En1] &

SIG [Y.87T.En2]
SIG [Y.87T.Blk]
En [Y.87T.En_Inst] & &

[Y.87T.St]
SIG Idmax>[Y.87T.I_Inst]
En [Y.87T.En_Biased] & ≥1
SIG Idmax>[Y.87T.I_Biased]
En [Tr.87T.En_DPFC] &
SIG ΔId>1.25ΔIdt+Idth
Figure 3.2-4 Logic diagram of startup of transformer current differential protection
Where:
Idmax is the maximum value of three phase differential currents.
 I d is the DPFC differential current.
 I dt is the floating threshold varied with the change of differential current.
I dth is the fixed threshold.
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3 Operation Theory
EN [Y.87T.En_Inst]
SIG [Y.87T.En1] &
&
SIG [Y.87T.En2]
[Y.87T.Op_Inst]
SIG [Y.87T.Blk]
SIG Idmax>[Y.87T.I_Inst]
0ms 500ms
SIG Y.87T.FD_Inst
EN [Y.87T.En_Biased]
SIG [Y.87T.En1] &
SIG &
[Y.87T.En2]
SIG [Y.87T.Blk]
SIG Flg_ConvBiasDiff &
SIG Flg_Inrush_ConvBiasDiff
SIG Flg_CTS &
SET [Y.87T.En_CTS_Blk] ≥1
[Y.87T.Op_Biased]
SIG Y.87T.FD_Biased 0ms 500ms
EN [Y.87T.En_Biased]
SIG [Y.87T.En1] &
SIG [Y.87T.En2]
SIG [Y.87T.Blk]
&
SIG Flg_SensBiasDiff
SIG Flg_CTSaturation
SIG Flg_Inrush_SensBiasDiff &
SIG Flg_CTS &
SET [Y.87T.En_CTS_Blk]
SIG Flg_OvExc_Hm5 &
SET [Y.87T.En_OvExc_Blk]
0ms 500ms
SIG Y.87T.FD_Biased
Figure 3.2-5 Logic diagram of steady-state current differential element of transformer
Where:
Idmax is the maximum value of three phase differential currents.
Flg_ConvBiasDiff is the internal flag indicating that the operation criteria of conventional biased
differential element are satisfied.
Flg_SensBiasDiff is the internal flag indicating that operation criteria of sensitive biased differential
element are satisfied.
Flg_CTS is the internal flag indicating that differential CT circuit failure is detected.
Flg_CTSaturation is the internal flag indicating that CT saturation is detected.
Flg_Inrush_ConvBiasDiff is the internal flag indicating that inrush current is detected for
conventional biased differential element.
Flg_Inrush_SensBiasDiff is the internal flag indicating inrush current is detected for sensitive
Date: 2015-07-29
3 Operation Theory
biased differential element.
Flg_OvExc_Hm5 is the internal flag indicating that overexcitation of transformer is distinguished by

fifth harmonic criterion.
Y.87T.FD_Inst is the signal indicating that the fault detector of unrestrained instantaneous
differential element picks up (the fault detector of fault detector DSP module).
Y.87T.FD_Biased is the signal indicating that the fault detector of biased differential element picks
up (the fault detector of fault detector DSP module).
EN [Tr.87T.En_DPFC]
SIG [Tr.87T.En1] &
SIG [Tr.87T.En2]
SIG [Tr.87T.Blk]
&
SIG Flg_DPFC_Diff [Tr.87T.Op_DPFC]
SIG Flg_Inrush_DPFC &
SIG Flg_CTS &
SET [Tr.87T.En_CTS_Blk]
SIG Flg_OvExc_Hm5 &
SET [Tr.87T.En_OvExc_Blk
SIG Tr.87T.FD_DPFC 0ms 500ms
Figure 3.2-6 Logic diagram of DPFC current differential element of main transformer
Where:
Flg_DPFC_Diff is the internal flag indicating that the operation criteria of DPFC differential element
are satisfied.
Flg_Inrush_DPFC is the internal flag indicating inrush current is detected for DPFC differential
element.
Flg_OvExc_Hm5 is the internal flag indicating that overexcitation of transformer is distinguished by

fifth harmonic criterion.
Flg_CTS is the internal flag indicating that differential CT circuit failure is detected.
Tr.87T.FD_DPFC is the signal indicating that the fault detector of DPFC differential element picks
up (the fault detector of fault detector DSP module).
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3 Operation Theory
3.2.5 Inputs and Outputs
87T
Y.87T.I3P1 Y.87T.St
Y.87T.I3P2 Y.87T.Op_Biased
Y.87T.I3P3 Y.87T.Op_Inst
Y.87T.I3P4 Tr.87T.Op_DPFC
Y.87T.I3P5 Y.87T.Alm_CTS
Y.87T.I3P6
Y.87T.Alm_Diff
Y.87T.En1
Y.87T.En2
Y.87T.Blk
Figure 3.2-7 Function block diagram of transformer current differential protection
Table 3.2-2 Input signals of transformer current differential protection
No. Signal Description

1 Y.87T.I3P1 Three-phase current data input 1
7 Y.87T.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings,
8 Y.87T.En2 such as function enabling binary inputs, logic links, etc.
9 Y.87T.Blk Protection function blocking input, such as function blocking binary input.
Table 3.2-3 Output signals of transformer current differential protection

1 Y.87T.St Transformer current differential protection starts.
2 Y.87T.Op_Inst Instantaneous differential element of transformer operates.
3 Y.87T.Op_Biased Biased differential element of transformer operates.
4 Tr.87T.Op_DPFC DPFC differential element of main transformer operates.
Alarm message indicating CT secondary circuit of transformer differential protection
5 Y.87T.Alm_Diff
is abnormal.
Alarm message indicating that CT secondary circuit of transformer differential
6 Y.87T.Alm_CTS
protection fails.
Above input and output signals can be used for programmable logic, and following output signals
are only for LCD display and waveform recording function of the device.
Table 3.2-4 Output signals of transformer current differential protection (event recorder)
Tripping reports
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3 Operation Theory
1 Y.87T.Op_Inst Instantaneous differential element of transformer operates.
2 Y.87T.Op_Biased Biased differential element of transformer operates.
3 Tr.87T.Op_DPFC DPFC differential element of main transformer operates.
Start signals
4 Y.87T.St Transformer current differential protection starts.
Alarm signals
Alarm message indicating CT secondary circuit of transformer differential

5 Y.87T.Alm_Diff
protection is abnormal.
Alarm message indicating that CT secondary circuit of transformer differential

6 Y.87T.Alm_CTS
protection fails.
Waveform recording
7 Y.87T.TrigDFR Transformer differential protection operates to trigger waveform recording.
Binary change report
8 Y.87T.St_Biased Transformer biased differential element starts.
9 Tr.87T.St_DPFC Main transformer DPFC differential element starts instantaneously.
Table 3.2-5 Output signals of transformer current differential protection (measurements)
No. Signal Description Unit
Tr.87T.Ida
Three-phase differential current amplitude of main
1 Tr.87T.Idb pu
transformer.
Tr.87T.Idc
Tr.87T.Ira
Three-phase restraint current amplitude of main
2 Tr.87T.Irb pu
transformer.
Tr.87T.Irc
Tr.87T.Ia_Cr_Brm
Three-phase corrected current of each side that used for
3 Tr.87T.Ib_Cr_Brm pu
main transformer differential protection (m=1~6).
Tr.87T.Ic_Cr_Brm
Access path:
Main menu -> Measurements -> Measurements1-> Tr Values-> Tr Diff Values
Main menu -> Measurements -> Measurements2-> Tr Values-> Tr Diff Values
Tr.87T.Ang(Ia_Br1-Brm) Phase angle between branch 1 corrected current and

4 Tr.87T.Ang(Ib_Br1-Brm) branch m corrected current of the same phase of main deg
Tr.87T.Ang(Ic_Br1-Brm) transformer (m=2,3,4,5,6).
Access path:
Main menu -> Measurements -> Measurements2-> Phase Angle-> Tr PhaseAngle Values
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3 Operation Theory
The secondary rated current of branch m of main

5 Tr.87T.I2b_Brm A
transformer (m=1,2,3,4,5,6).
Access path:
Main menu -> Measurements -> Measurements2-> Cal Param Display-> Sec Rated Curr Values
Adjust coefficient of branch m for main transformer

6 Tr.87T.K_Brm
differential protection (m=1,2,3,4,5,6).
Access path:
Main menu -> Measurements -> Measurements2-> Cal Param Display-> Diff Corr Coef Values
Y.87T.Ida
7 Y.87T.Idb Three-phase differential current amplitude of transformer. pu
Y.87T.Idc
Y.87T.Ida_HalfCycle Three-phase differential current half cycle amplitude of

8 Y.87T.Idb_HalfCycle transformer (only available for main transformer differential pu
Y.87T.Idc_HalfCycle protection).
Y.87T.Ira
9 Y.87T.Irb Three-phase restraint current amplitude of transformer. pu
Y.87T.Irc
Y.87T.Ia_Th_Biased_L
Three-phase current threshold of transformer sensitive
10 Y.87T.Ib_Th_Biased_L pu
biased differential current protection.
Y.87T.Ic_Th_Biased_L
Y.87T.Ia_Th_Biased_H
Three-phase current threshold of transformer conventional
11 Y.87T.Ib_Th_Biased_H pu
biased differential current protection.
Y.87T.Ic_Th_Biased_H
Y.87T.Ida_Hm2
Second harmonic amplitude of three-phase differential
12 Y.87T.Idb_Hm2 pu
current of transformer.
Y.87T.Idc_Hm2
Y.87T.Ida_Hm3
Third harmonic amplitude of three-phase differential current
13 Y.87T.Idb_Hm3 pu
of transformer.
Y.87T.Idc_Hm3
Y.87T.Ida_Hm5
Fifth harmonic amplitude of three-phase differential current
14 Y.87T.Idb_Hm5 pu
of transformer.
Y.87T.Idc_Hm5
Access path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Tr Diff Prot Values
3.2.6 Settings
Table 3.2-6 Settings list of transformer current differential protection
No. Setting Item Range Step Unit Description
1 Y.87T.En 0: disable 1 The logic setting of enabling/dis abling
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3 Operation Theory
1: enable transformer differential protection.
Pickup current setting of transformer biased

2 Y.87T.I_Biased 0.10~1.5 0.01 pu
differential element.
Current setting of transformer unrestrained

3 Y.87T.I_Inst 2~14 0.01 pu
instantaneous differential element
Differential current alarm setting of

4 Y.87T.I_Alm 0.05~1.0 0.01 pu
transformer.
Slope 1 of biased differential element of

5 Y.87T.Slope1 0.01~0.5 0.01
transformer.
Slope 2 of biased differential element of

6 Y.87T.Slope2 0.5~0.8 0.01
transformer.
Coefficient of 2 nd harmonic for transformer

7 Y.87T.K_Hm2_Inrush 0.05~0.5 0.01
inrush current detection.
Coefficient of 5 th harmonic for transformer

8 Y.87T.K_Hm5_OvExc 0.05~0.5 0.01
overexcitation detection
Tripping logic setting of transformer current

9 Y.87T.OutMap 0~3FFFFFFF
Logic setting of enabling/disabling

0: disable
10 Y.87T.En_Inst 1 transformer unrestrained instantaneous
1: enable
differential element.
0: disable Logic setting of enabling/disabling

11 Y.87T.En_Biased 1
1: enable transformer biased differential element.
Logic setting of enabling/disabling main

0: disable transformer DPFC differential element
12 Tr.87T.En_DPFC 1
1: enable (only a vailable for main transformer and
not available for step-down transformer).

0: disable
13 Y.87T.En_OvExc_Blk 1 overexcitation blocking element of
1: enable
transformer differential protection.

0: disable
14 Y.87T.En_CTS_Blk 1 transformer biased differential element
1: enable
being blocked by CT circuit failure.
Logic setting of selecting the inrush current

distinguishing method of transformer biased
Hm2
15 Y.87T.Opt_Inrush_Ident 1 differential element:
Waveform
0: Hm2
1: Waveform
SyntheticBlk Logic setting of selecting inrush current

16 Y.87T.Opt_BlkMode_Inrush 1
CrossBlk blocking mode for transformer biased
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3 Operation Theory
PhaseBlk differential element:

0: SyntheticBlk
1: CrossBlk
2: PhaseBlk
Access path: Settings-> Prot Settings -> Tr Diff Settings
NOTICE!
The logic setting [Y.87T.OutMap] is SHARED by the unrestrained instantaneous

differential element, biased differential element and DPFC differential element of
transformer.
[Y.87T.OutMap]
The tripping logic setting is used to specify which breaker(s) will be tripped when correspond ing
protection element operates. This logic setting comprises 32 binary bits as follows and is
expressed by a hexadecimal number of 8 digits from 0H to 3FFFFFFFH. The tripping logic setting
of the device is specified as follows:
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TrpOutput15
TrpOutput14
TrpOutput13
TrpOutput12
TrpOutput11
TrpOutput10
TrpOutput09
TrpOutput08
TrpOutput07
TrpOutput06
TrpOutput05
TrpOutput04
TrpOutput03
TrpOutput02
TrpOutput01
Enable trip
Function
matrix
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TrpOutput016
TrpOutput29
TrpOutput28
TrpOutput27
TrpOutput26
TrpOutput25
TrpOutput24
TrpOutput23
TrpOutput22
TrpOutput21
TrpOutput20
TrpOutput19
TrpOutput18
TrpOutput17
Function
Spare
Spare
“TrpOutput01” just means to drive tripping output channel 1. Set bit0 as “1” means this protection
element can operate to trip breaker(s). The bit corresponding to the breaker to be tripped shall be
set as “1” and other bits shall be “0”. For example, if transformer differential protection is defined to
trip breaker 3 (tripping output channel 3) and breaker 5 (tripping output channel 5), the bit0, bit3
and bit5 shall be set as “1” and other bits shall be set as “0”. Then a hexadecimal number
00000029H is formed as the tripping output logic setting of transformer differential protection.
Please note that tripping output logic settings of the equipment have to be set on basis of
application-specific drawings.
All the tripping logic settings mentioned below should be defined with the same method.
3.3 Restricted Earth Fault Protection (64REF)
NOTICE!
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3 Operation Theory
In Section 3.3, the prefix “Y” in settings (such as [Y.64REF.I_Biased]) and input/output
signals (such as [Y.64REF.Op_Biased]) can be Tr_HVS and Tr_MVS. Details of the
prefix are as:
Tr_HVS.64REF Corresponds to restricted earth fault protection of main transformer high voltage side.
Tr_MVS.64REF Corresponds to restricted earth fault protection of main transformer medium voltage side.
3.3.1 Application
Transformer restricted earth fault protection is the main protection for the internal earth fault of
transformer winding. Transformer restricted earth fault protection can operate quickly to clear the
internal earth fault to avoid the transformer from damages or reduce the maintenance cost as low
as possible.
3.3.2 Function
 Up to 4 group CT inputs for restricted earth fault protection.
 It is suitable for two-winding transformer and three-winding transformer
 Reliable biased differential element.
The biased differential element with restraint characteristic is adopted, it consists of sensitive and
conventional biased differential elements as well as independent CT saturation criterion .
3.3.3.1 Overview
Transformer restricted earth fault protection includes one operation element: biased differential
element. When the residual differential current is larger than the corresponding current threshold
and no larger harmonic is detected, restricted earth fault protection will operate, and it will drop off
if the fault current disappears.
3.3.3.2 Amplitude Compensation
Generally, the magnitudes of secondary current of each side of transformer are different due to the
difference of CT ratio. The current value difference between each side shall be adjusted before
calculation for restricted earth fault protection by amplitude compensation. The residual differential
adjust current of each side should be converted to In (In is the secondary rated current, 1A or 5A).
The primary and secondary data of CT of each side of transformer restricted earth fault protection
should be input to the device. The device will calculate the differential adjust coefficient of each
side automatically according to the parameters.
 Calculate differential adjust coefficient
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3 Operation Theory
k Base  1
I 1 n Brm
k Brm 
I 1 n Base Equation 3.3-1
( I 1 n Brm )
 16
( I 1 n Base )
Where:
Brm=Branch (side) “m”.
I 1 n Brm , I 1 n Base are primary rated current of calculated side and referenced side of transformer.
k Base is adjust coefficient of referenced side of transformer.
k Brm is adjust coefficient of calculated side of transformer.
Via the setting [Y.64REF.Opt_BaseSide], the referenced side for transformer current differential
protection can be selected, transformer neutral point measured CT is the default referenced side.
If Equation 3.3-1 is not met, the setting error alarm signals [Y.64REF.Fail_Settings] will be issued
and displayed on LCD and the protective device will be blocked.
3.3.3.3 Calculations of Differential Current and Restraint Current
The calculation equation of differential current is:
3 I 0 d  3 I 0 1  K B r1  3 I 0 2  K B r 2  3 I 0 3  K B r 3  3 I 0 4  K B a s e
Equation 3.3-2
3 I 0 d  3 I  0 1  3 I  0 2  3 I  0 3  3 I 0 4
Where:
3 I 0 1 , 3 I 0 2 , 3 I 0 3 in the equation are the residual current vectors of each side, and 3 I 0 4 is the
neutral point measured residual current vectors.
K B r1 ,K Br 2 ,K B r3 ,K B ase are the adjust coefficients of each side and neutral point side.
3 I ' 0 1 , 3 I ' 0 2 , 3 I ' 0 3 are the corrected residual current vectors of each side, and 3 I  0 4 is the
corrected neutral point measured residual current vectors.
3 I 0 d is the residual differential current.
The calculation equation of restraint current is:
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3 Operation Theory
3I 0r  m a x  3 I  0 1, 3 I  0 2 , 3 I  0 3 , 3 I  0 4  Equation 3.3-3
Where:
3 I 0 r is the residual restraint current.
3.3.3.4 Sensitive Biased Differential Element
The operation equation of sensitive biased differential element is:
 3 I 0 d  K b l  3 I 0 r

 3 I 0 d  I D iff . P ic k u p
Equation 3.3-4
 3 I 0 d  3 I  0 1  3 I  0 2  3 I  0 3  3 I 0 4

 3 I 0 r  m a x  3 I  0 1, 3 I  0 2 , 3 I  0 3 , 3 I  0 4 
Where:
3 I ' 0 1 , 3 I ' 0 2 , 3 I ' 0 3 are the corrected residual current vectors of each side, and 3 I  0 4 is the
corrected neutral point measured residual current vectors.
I D iff . P ic k u p is the pickup current setting of biased differential element [Y.64REF.I_Biased].
K b1 is the restraint coefficient of biased differential element.
3.3.3.5 Conventional Biased Differential Element
Conventional biased differential element with higher pickup current and higher restraint coefficient
comparing with sensitive biased differential element is equipped. Its biased restraint characteristic
can make the differential element not operate due to CT transient and steady-state saturation
during external fault, and it can operate reliably even the CT is seriously saturated during internal
fault. Operation criterion of conventional biased differential element is:
 3 I 0 d  1 .2  I n

3I0d  3I0r Equation 3.3-5
Where:
3 I 0 d and 3 I 0 r have the same definitions as mentioned above.
Date: 2015-07-29
3 Operation Theory
NOTICE!
The related parameters of conventional biased differential element are set FIXEDLY in
the device. Therefore, the slope and the knee point with constant values do not need to
be set by user.
3.3.3.6 Operation Characteristic of Restricted Earth Fault Protection
Operation characteristic of restricted earth fault protection is shown in following figure.
3I0d
Tripping area of
区
conventional biased diff. f .
作
a o diff
动
动
e
ar ed ]
差
率
.0
=1
ng ias lope
比
K
值
i
p b F.S
ip 低
Tr itive 4RE
ns [Y.6
se
1.2In
[Y.64REF.I_Biased]
0
1.2In 3I0r
Figure 3.3-1 Operation characteristic curve of restricted earth fault protection
Current differential protection carries out the fault discrimination according to the current of each
phase. If the current criteria are met and no related blocking element(s) operate, differential
protection will operate to trip.
1) Sensitive biased differential element will send tripping signal monitored by neutral point CT
saturation discrimination, differential current harmonic discrimination and three-phase
unbalance discrimination. It can ensure the sensitivity of differential protection and avoid the
unwanted operation when CT is saturated during an external fault. Its operation area is the tint
shadow area in the figure above.
2) Conventional biased differential element will send tripping signal monitored b y differential
current second harmonic. It eliminates the influence of CT saturation during an external fault
and ensures differential protection can operate reliably even if CT is saturated during an
internal fault by means of its biased characteristic. Its operation area is the deeper shadow
area in the figure above.
3.3.3.7 Neutral Point CT Saturation Detection
When an transformer external fault happens, great through -fault current will flowing through the
Date: 2015-07-29
3 Operation Theory
neutral point measuring residual CT, generally the CT ratio of the neutral point measuring residual
CT is small and it is easy to be saturated, great unbalance differential current will generate in the
differential circuit, which will lead to the mal-operation of differential protection. So the CT
saturation detection function is required for restricted earth fault protection.

transient state saturation of CT during an external fault, the second and third harmonics of neutral
point measured residual current are used for the protection device to discriminate saturation of the
neutral point measuring residual CT.

I _ 2 nd  K  sat _ 2 xb  I _ 1 st
 Equation 3.3-6
 I  K  sat  I
  _ 3 rd _ 3 xb _ 1 st
Where:
I  _ 1 st is the fundamental component of neutral point measured residual current.
I  _ 2 nd is the secondary harmonic of neutral point measured residual current.
I  _ 3 rd is the third harmonic of neutral point measured residual current.
K  sa t _ 2 x b and K  sa t _ 3 x b are fixed coefficients.
If neutral point measured residual current meets the above equation, it will be considered that it is
CT saturation to cause residual differential current and sensitive biased differential element will be
blocked. The criterion is only enabled when the transformer is in service and it will also be
controlled by the logic setting [Y.64REF.En_NPCurr].
3.3.3.8 Differential Current Harmonic Discrimination

transient state saturation of CT during an external fault, the second and third harmonics of residual
differential current are used for the protection device to discriminate CT saturation.
 3 I 0 d _ 2 n d  K 2 x b  3 I 0 d _ 1 s t
 Equation 3.3-7
 3 I 0 d _ 3 r d  K 3 x b  3 I 0 d _ 1 s t
Where:
3 I 0 d _ 1 s t is the fundamental component of residual differential current.
3 I 0 d _ 2 n d is the secondary harmonic of residual differential current.
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3 Operation Theory
3 I 0 d _ 3 r d is the third harmonic of residual differential current.
K 2 x b and K 3 x b are coefficients setting [Y.64REF.K_Hm2_Inrush] and [Y.64REF.K_Hm3_Inrush].
If residual differential current meets the above equation, it will be considered that it is CT
saturation to cause residual differential current and sensitive biased differential element will be
blocked. The criterion is only enabled when the transformer is in service.
3.3.3.9 Three-phase Unbalance Discrimination
Under some conditions such as a maximum three-phase short-circuit fault happens or inrush
current and etc., the wrong differential circuit residual current caused by CT transient state
characteristic difference and CT saturation etc. will affect the restricted earth fault protection, so
the device adopts the blocking criterion using positive-sequence current, i.e. when the residual
current of each side of restricted earth fault protection is greater than 0 times of positive
sequence current of corresponding side, it is identified that residual current is caused by a fault
and restricted earth fault protection will be released.
3 I 0   0  I1 Equation 3.3-8
Where:
3 I 0 is the calculated residual current of one side.
I1 is the positive sequence current of corresponding side.
0 is a proportional constant.
Once the neutral point measured residual current is larger than the threshold value, it is identified
that an earth fault happens, then positive-sequence current blocking criterion of each side will be
enabled fixedly.
3.3.3.10 Differential Current Alarm
If the differential current meets the following criteria and corresponding differential element is
enabled, the differential current abnormality alarm [Y.64REF.Alm_Diff] will be issued with a time
delay of 300ms, this alarm signal will not block the differential element. The signal will reset if the
differential current disappears with a time delay of 10s.
In order to consider both of sensitivity and reliability, percentage restraint differential current alarm
criteria is adopted:
 3 I 0 d  [ Y .6 4 R E F . I _ A lm ]
 Equation 3.3-9
3I0d  k * 3I0r
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3 Operation Theory
k is the differential current alarm percentage restraint coefficient.
[Y.64REF.I_Alm] is the differential current alarm setting.
No matter whether the abnormality alarm signal makes the restricted earth fault protection picks
up, there must be some problems in the differential circuit or the settings are wrong. For example,
when the differential circuit fails, the restricted earth fault protection will not pick up for light-loaded
condition, but the differential current abnormality alarm signal will be issued. If the abnormality is
treated in time, the mal-operation of differential protection due to increase of load or external fault
can be avoided.
3.3.4 Logic
For restricted earth fault protection, if following three conditions are met, the protection will be
enabled.
(1) Logic setting [Y.64REF.En] is set as “1”.
(2) The protection function enabling inputs [Y.64REF.En1], [Y.64REF.En2] are “1”.
(3) The protection function blocking input [Y.64REF.Blk] is “0”.
If restricted earth fault protection is disabled, all the related output signals will be reset. If no
external input is configured to [Y.64REF.En1] ([Y.64REF.En2]), the default initial value of
[Y.64REF.En1] ([Y.64REF.En2]) is “1”; if no external input is configured to [Y.64REF.Blk], the
default initial value of [Y.64REF.Blk] is “0”.
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3 Operation Theory
EN [Y.64REF.En_Biased]
SIG [Y.64REF.En1] &
SIG &
[Y.64REF.En2]
SIG [Y.64REF.Blk]
&
SIG Flg_ConvBiasedDiff
SIG Flg_2nd_Harm
≥1
SIG FD_BiasedDiff 0ms 500ms [Y.64REF.Op_Biased]
EN [Y.64REF.En_Biased]
SIG [Y.64REF.En1] &
SIG [Y.64REF.En2]
SIG [Y.64REF.Blk]
&
SIG Flg_SensBiasedDiff
SIG Flg_2nd_Harm
SIG Flg_3rd_Harm &
SIG Flg_Blk_PosSeq
SIG Flg_CTSaturation_Neu &
SET [Y.64REF.En_NPCurr]
0ms 500ms
SIG FD_BiasedDiff
SIG [Y.64REF.En1] &

SIG [Y.64REF.En2]
&
SIG [Y.64REF.Blk]
[Y.64REF.St]
En [Y.64REF.En_Biased] &
SIG 3I0d>[Y.64REF.I_Biased]
Figure 3.3-2 Logic diagram of restricted earth fault protection
Where:
Flg_ConvBiasedDiff is the internal flag indicating that operation criteria of conventional biased
differential element are met.
Flg_SensBiasedDiff is the internal flag indicating that operation criteria of sensitive biased
differential element are met.
Flg_2nd_Harm is the internal flag indicating that the second harmonic current blocking condition is
met.
Flg_3rd_Harm is the internal flag indicating that the third harmonic current blocking condition is
met.
FD_BiasedDiff is the signal indicating that the fault detector of restricted earth fault protection
picks up.
Flg_CTSaturation_Neu is the internal flag indicating that the neutral point CT is saturated.
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3 Operation Theory
64REF
Y.64REF.I3P1 Y.64REF.St
Y.64REF.I3P2 Y.64REF.Op_Biased
Y.64REF.I3P3 Y.64REF.Alm_Diff
Y.64REF.I1P
Y.64REF.En1
Y.64REF.En2
Y.64REF.Blk
Figure 3.3-3 Function block diagram of restricted earth fault protection
Table 3.3-1 Input signals of restricted earth fault protection

1 Y.64REF.I3P1 Three-phase current data input 1
Single-phase current data input, it is configured as neutral point measured residual
4 Y.64REF.I1P
current by default, and it can be changed by PCS-Explorer.
5 Y.64REF.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings,
6 Y.64REF.En2 such as function enabling binary inputs, logic links, etc.
7 Y.64REF.Blk Protection function blocking input, such as function blocking binary input.
Table 3.3-2 Output signals of restricted earth fault protection

1 Y.64REF.St Transformer restricted earth fault protection starts.
2 Y.64REF.Op_Biased Biased differential element of restricted earth fault protection operates.
3 Y.64REF.Alm_Diff Alarm message indicating residual differential current is abnormal.
Above input and output signals can be used for programmable logic, and f ollowing output signals
Table 3.3-3 Output signals of restricted earth fault protection (event recorder)
Tripping reports
1 Y.64REF.Op_Biased Biased differential element of restricted earth fault protection operates.
Start signals
2 Y.64REF.St Transformer restricted earth fault protection starts.
Alarm signals
3 Y.64REF.Alm_Diff Alarm message indicating residual differential current is abnormal.
Waveform recording
4 Y.64REF.TrigDFR Transformer restricted earth fault protection operates to trigger waveform
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3 Operation Theory
recording.
Table 3.3-4 Output signals of restricted earth fault protection (measurements)
Residual differential current of restricted earth fault

1 Tr_HVS.64REF.3I0d In
protection of main transformer HV side.
Residual restraint current of restricted earth fault

2 Tr_HVS.64REF.3I0r In
Corrected value of calculated residual current of branch m

3 Tr_HVS.64REF.3I0_Cr_Brm (m=1, 2, 3) for restricted earth fault protection of main In
transformer HV side.
Corrected value of neutral point measured residual current

4 Tr_HVS.64REF.3I0_Cr_NP for restricted earth fault protection of main transformer HV In
side.

5 Tr_MVS.64REF.3I0d In
protection of main transformer MV side.

6 Tr_MVS.64REF.3I0r In
Corrected value of calculated residual current of branch m

7 Tr_MVS.64REF.3I0_Cr_Brm (m=1, 2, 3) for restricted earth fault protection of main In
transformer MV side.
Corrected value of neutral point measured residual current

8 Tr_MVS.64REF.3I0_Cr_NP for restricted earth fault protection of main transformer MV In
side.
Access path:
Main menu -> Measurements -> Measurements1-> Tr Values-> Tr REF Values
Main menu -> Measurements -> Measurements2-> Tr Values-> Tr REF Values
Phase angle between branch 1 calculated residual current

9 Y.64REF.Ang(3I0_Br1-NP) deg
and neutral point measured residual current.


Access path:
Adjust coefficient of branch m for transformer restricted

12 Y.64REF.K_Brm
earth fault protection (m=1,2,3,4).
Access path:
Main menu -> Measurements -> Measurements2-> Cal Param Display-> Diff Corr Coef Values
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3 Operation Theory

13 Y.64REF.3I0d In
protection.

14 Y.64REF.3I0r In
protection.
Residual current threshold of sensitive biased differential

15 Y.64REF.3I0_Th_Biased_L In
element of restricted earth fault protection.
Residual current threshold of conventional biased

16 Y.64REF.3I0_Th_Biased_H In
differential element of restricted earth fault protection.
17 Y.64REF.3I0d_Hm2 Second harmonic amplitude of residual differential current. In
18 Y.64REF.3I0d_Hm3 Third harmonic amplitude of residual differential current. In
Second harmonic amplitude of neutral point measured

19 Y.64REF.3I0_NP_Hm2 In
residual current.
Third harmonic amplitude of neutral point measured

20 Y.64REF.3I0_NP_Hm3 In
residual current.
Access path:
Main menu -> Measurements -> Measurements2-> Prot Status-> Tr REF Prot Values
3.3.6 Settings
Table 3.3-5 Settings list of restricted earth fault protection
0: disable The logic setting of enabling/disabling

1 Y.64REF.En 1
1: enable transformer restricted earth fault protection.
Pickup current setting of biased differential

2 Y.64REF.I_Biased 0.10~1.50 0.01 In
element.
Residual differential current alarm setting of

3 Y.64REF.I_ Alm 0.05~1.00 0.01 In
transformer.
Percentage restraint coefficient of biased

4 Y.64REF.Slope 0.30~0.80 0.01 differential element of restricted earth fault
protection.
Coefficient of 2 nd harmonic for transformer

5 Y.64REF.K_Hm2_Inrush 0.05~0.50 0.01
rd
Coefficient of 3 harmonic for transformer
6 Y.64REF.K_Hm3_Inrush 0.05~0.50 0.01
Tripping logic setting of transformer

7 Y.64REF.OutMap 0~3FFFFFFF
restricted earth fault protection.
Logic setting of enabling/disabling biased

0: disable
8 Y.64REF.En_Biased 1 differential element of restricted earth fault
1: enable
protection.
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3 Operation Theory
Logic setting of enabling/disabling blocking

0: disable
9 Y.64REF.En_NPCurr 1 restricted earth fault protection if neutral
1: enable
point CT saturation is detected.
Access path:
Settings-> Prot Settings -> TrHVS REF Settings
Settings-> Prot Settings -> TrMVS REF Settings
3.4 Negative-Sequence Overcurrent Protection (50/51Q)
NOTICE!
In Section 3.4, the prefix “Y” in settings (such as [Y.50/51Q1.I2_Set]) and input/output
signals (such as [Y.50/51Q1.Op]) can be Tr_HVS and Tr_MVS. Details of the prefix are
as:
Corresponds to negative-sequence overcurrent protection of main transformer high

Tr_HVS.50/51Q
voltage side.
Corresponds to negative-sequence overcurrent protection of main transformer medium
Tr_MVS.50/51Q
voltage side.
3.4.1 Application
Negative-sequence overcurrent protection is applied as the backup protection for ge nerator. When
an unsymmetrical short-circuit fault happens or the three-phase loads are unbalance,
negative-sequence current will be generated. Negative-sequence current protection is mainly
used to detect the unbalanced load of three-phase induction motor (generator or electric motor),
negative-sequence current of stator winding will generate a magnetic field rotating in reverse
direction, the frequency of the magnetic field is twice relative to the frequency of the rotor. The
double-frequency magnetic field will generate eddy current on the surface of the rotor, which will
lead to the local over-heating of the end of the rotor, damping stripe and slot-wedge.
The negative-sequence overcurrent protection can also be applied to detect the single-phase and
two-phase fault when the fault current is low than the load current, the negative-sequence
overcurrent has higher sensitivity relative to phase overcurrent. Besides, the negative-sequence
overcurrent protection can also be applied to detect the open, fault or polarity error of the CT
circuit.
3.4.2 Function
Negative-sequence overcurrent protection has following functions:
 Two-stage negative-sequence overcurrent protection with independent logic, current and

time delay settings.
 Stage 1 is definite-time characteristic, stage 2 can be selected as definite-time or

inverse-time characteristic. The inverse-time characteristic is selectable among IEC and
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3 Operation Theory
ANSI/IEEE standard inverse-time characteristics and a user-defined inverse-time curve.
 Voltage controlled element can be selected to control each stage of negative-sequence

overcurrent protection.
3.4.3.1 Fault Detector
The operation criterion of negative-sequence overcurrent protection is:
I 2 >[50/51Qx.I2_Set] Equation 3.4-1
Where:
I 2 is the negative-sequence current of one side.
[50/51Qx.I2_Set] is the negative-sequence current setting of stage x (x=1 or 2) of

negative-sequence overcurrent protection.
If negative-sequence current is greater than the negative-sequence current setting of the enabled
stage of negative-sequence overcurrent protection, the stage of protection will operate after a time
delay. Each stage of negative-sequence overcurrent protection will drop off instantaneously after
fault current disappears.
3.4.3.2 Time Curve
Negative-sequence overcurrent protection stage 1 is definite-time characteristic and it can perform

instantaneous operation if the corresponding time delay setting is set as “0”. Stage 2 can be
selected as definite-time or inverse-time characteristic, and inverse-time operating time curve is as
follows.
 
 
K
t(I)    C   TP Equation 3.4-2
 I2  
( ) 1
 I 
 set 
Where:
I set is the base current setting, corresponds to the setting [Y.50/51Q2.Ib_Set].
T p is inverse-time time factor, corresponds to the setting [Y.50/51Q2.TMS].
, 
K ,C are inverse-time constants of inverse-time curve.
The user can select the operating characteristic from various inverse-time characteristic curves by
the setting [Y.50/51Q2.Opt_Curve], and parameters of available characteristics for selection are
shown in the following table.
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3 Operation Theory
Table 3.4-1 Inverse-time curve parameters of stage 2 of negative-sequence overcurrent protection
Y.50/51Q2.Opt_Curve Time Characteristic K α C
0 Definite time
1 IEC Normal inverse 0.14 0.02 0
2 IEC Very inverse 13.5 1.0 0
3 IEC Extremely inverse 80.0 2.0 0
4 IEC Short-time inverse 0.05 0.04 0
5 IEC Long-time inverse 120.0 1.0 0
6 ANSI Extremely inverse 28.2 2.0 0.1217
7 ANSI Very inverse 19.61 2.0 0.491
8 ANSI Inverse 0.0086 0.02 0.0185
9 ANSI Moderately inverse 0.0515 0.02 0.114
10 ANSI Long-time extremely inverse 64.07 2.0 0.25
11 ANSI Long-time very inverse 28.55 2.0 0.712
12 ANSI Long-time inverse 0.086 0.02 0.185
13 Programmable user-defined
If all available curves do not comply with user application, user can configure
[Y.50/51Q2.Opt_Curve] as “13” to customize the inverse-time curve characteristic (by configuring
the three inverse-time curve constants K ,  and C ).
3.4.3.3 Voltage Controlled Element
In order to improve the sensitivity of negative-sequence overcurrent protection, via the setting
[Y.50/51Qx.En_VCE], voltage controlled element of negative-sequence overcurrent protection can
be enabled or disabled. Please refer to Section 3.6.3.4 for details. Voltage controlled element of
negative-sequence overcurrent protection can be configured through the software PCS-Explorer.
3.4.4 Logic
For stage x of negative-sequence overcurrent protection, if following three conditions are met,
stage x of negative-sequence overcurrent protection is enabled.
(1) Logic setting [Y.50/51Qx.En] is set as “1”.
(2) The protection function enabling inputs [Y.50/51Qx.En1], [Y.50/51Qx.En2] are “1”
(3) The protection function blocking input [Y.50/51Qx.Blk] is “0”.
If negative-sequence overcurrent protection is disabled, all the related output signals will be reset.
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If no external input is configured to [Y.50/51Qx.En1] ([Y.50/51Qx.En2]), the default initial value of

[Y.50/51Qx.En1] ([Y.50/51Qx.En2]) is “1”; if no external input is configured to [Y.50/51Qx.Blk], the
default initial value of [Y.50/51Qx.Blk] is “0”.
EN [Y.50/51Qx.En]
SIG [Y.50/51Qx.En1] &
SIG [Y.50/51Qx.En2]
SIG [Y.50/51Qx.Blk]
SIG [Y.50/51Qx.I3P]
& &
[Y.50/51Qx.St]
SET [Y.50/51Qx.I2_Set]
SIG Y.50/51Q.VCE.Op ≥1
Timer
t
SET [Y.50/51Qx.En_VCE] [Y.50/51Qx.Op]
t
0ms 500ms
SIG Y.50/51Qx.FD Inverse-time only for
stage 2
Figure 3.4-1 Logic diagram of negative-sequence overcurrent protection (x=1 or 2)
Where:
[Y.50/51Q.VCE.Op] is the signal indicating that the voltage controlled element operates.
[Y.50/51Q.I3P] is the three-phase current input.
Y.50/51Qx.FD is the internal signal indicating that stage x of negative -sequence overcurrent
protection picks up (the fault detector of fault detector DSP module).
50/51Q
Y.50/51Qx.I3P Y.50/51Qx.St
Y.50/51Qx.VCE Y.50/51Qx.Op
Y.50/51Qx.En1
Y.50/51Qx.En2
Y.50/51Qx.Blk
Figure 3.4-2 Function block diagram of negative-sequence overcurrent protection
Table 3.4-2 Input signals of negative-sequence overcurrent protection

1 Y.50/51Qx.I3P Three-phase current data
2 Y.50/51Qx.VCE Voltage controlled element input
3 Y.50/51Qx.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
4 Y.50/51Qx.En2 as function enabling binary inputs, logic links, etc.
5 Y.50/51Qx.Blk Protection function blocking input, such as function blocking binary input.
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Table 3.4-3 Output signals of negative-sequence overcurrent protection

1 Y.50/51Q1.Op Stage 1 of negative-sequence overcurrent protection operates.
3 Y.50/51Q1.St Stage 1 of negative-sequence overcurrent protection starts.
Table 3.4-4 Output signals of negative-sequence overcurrent protection (event recorder)
Tripping reports
Start signals
Waveform recording
Stage 1 of negative-sequence overcurrent protection operates to trigger

5 Y.50/51Q1.TrigDFR
waveform recording.
Stage 2 of negative-sequence overcurrent protection operates to trigger

6 Y.50/51Q2.TrigDFR
waveform recording.
Table 3.4-5 Output signals of negative-sequence overcurrent protection (measurements)
Inverse-time accumulate value of stage 2 of

1 Y.50/51Q2.Accu %
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Status->Tr HVS PPF Prot Values
Main menu -> Measurements -> Measurements2-> Prot Status->Tr MVS PPF Prot Values
3.4.6 Settings
Table 3.4-6 Settings list of negative-sequence overcurrent protection

Logic setting of enabling/disabling stage 1
0: disable
1 Y.50/51Q1.En 1 of negative-sequence overcurrent
1: enable
protection.
Negative-sequence current setting of
2 Y.50/51Q1.I2_Set 0.05~4.00In 0.01 A
stage 1 of negative-sequence overcurrent
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protection.
Time delay of stage 1 of
3 Y.50/51Q1.t_Op 0~3000 0.01 s
Tripping logic setting of stage 1 of
4 Y.50/51Q1.OutMap 0~3FFFFFFF
Logic setting of enabling/disabling voltage
0: disable
5 Y.50/51Q1.En_VCE 1 controlled element of stage 1 of
1: enable
Logic setting of enabling/disabling stage 2
0: disable
6 Y.50/51Q2.En 1 of negative-sequence overcurrent
1: enable
protection.
7 Y.50/51Q2.I2_Set 0.05~4.00In 0.01 A stage 2 of negative-sequence overcurrent
protection.
Time delay of stage 2 of
8 Y.50/51Q2.t_Op 0~3000 0.01 s
Multiple of the maximum operating current
9 Y.50/51Q2.K_I2_Max 10~40 0.01 to the pickup setting of stage 2 of
The base current of transformer
10 Y.50/51Q2.Ib_Set 0.10~4.00In 0.01 A inverse-time negative-sequence
Time factor setting of stage 2 of
11 Y.50/51Q2.TMS 0.05~2.00In 0.01
Minimum time delay of stage 2 of
12 Y.50/51Q2.tmin 0~10 0.01 s
The constant K of stage 2 of
13 Y.50/51Q2.K 0~120 0.001
The constant C of stage 2 of
14 Y.50/51Q2.C 0~20 0.001 s
The exponent alpha of stage 2 of
15 Y.50/51Q2.Alpha 0.02~5 0.001
Logic setting for selecting operating
16 Y.50/51Q2.Opt_Curve 0~13 1 characteristic curve of stage 2 of
17 Y.50/51Q2.OutMap 0~3FFFFFFF
0: disable
18 Y.50/51Q2.En_VCE 1 controlled element of stage 2 of
1: enable
Access path:
Settings-> Prot Settings ->Tr HVS NegOC Settings
Settings-> Prot Settings ->TrMVS NegOC Settings
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3.5 Overexcitation Protection (24)
3.5.1 Application
Overexcitation protection is used to check the over-flux phenomenon during operation of the
transformer. Especially for the transformer of generator-transformer unit wiring, the over-flux
phenomenon will occur more easily. Abnormal voltage increase and abnormal frequency decline
will lead to the increase of flux density. When the flux density increase quickly over the rated flux
density, it will cause core saturation and resulting in great eddy current, then it will lead to severe
heating, the insulation of the equipment will be damaged.
Overexcitation protection has following functions:
 The ratio of voltage and frequency is adopted to check overexcitation, for the ratio is
proportional to the flux density (B) of the protected object
 RMS of three phase-to-phase voltages is used to calculate the overexcitation multiple, which
is not affected by frequency fluctuation.
 One stage definite-time overexcitation protection for tripping and one stage definite-time
overexcitation protection for alarm are equipped (with respective overexcitation multiple
setting and time delay).
 One-stage inverse-time overexcitation protection for tripping is equipped. The overexcitation

protection inverse-time stage is determined by eight groups of the per-unit value of
overexcitation multiple (U/f) and the tripping time (t), users can con figure it flexibly according
to the required over-excitation time characteristics.
3.5.3.1 Calculation of Overexcitation Multiple
Overexcitation multiples can be expressed by following equation:
n  U * / f* Equation 3.5-1
Where:
U * and f * are per unit value of voltage and frequency respectively.
The reference value for calculating per unit value of voltage is secondary rated voltage of some
side of transformer, and the reference value for calculating per unit value of frequency is rated
frequency. During normal operation, n = 1.
For example, if overexcitation protection is configured at HV side, HV side primary voltage is

525kV (i.e. [Tr_HVS.U1n_Plate]=525kV) and voltage transformer ratio is 500kV/100V (i.e.
[Tr_HVS.U1n] =500kV, [Tr_HVS.U2n]=100V). The reference value for calculating per unit value of
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voltage is:
[T r_ H V S .U 1 n _ P la te ]  [T r_ H V S .U 2 n ] 525 100
  6 0 .6 2 V
3  [T r_ H V S .U 1 n ] 3  500
The device will calculate the voltage reference value automatically according to the above settings,
so the primary voltage of the protected equipment, the primary and secondary voltage of the
voltage transformer should be set correctly.
3.5.3.2 Definite-time Overexcitation Protection
 Tripping stage
For Definite-time overexcitation protection tripping stage, the operation equation is:
U *
/ f * >[24.DT.K] Equation 3.5-2
Where:
U *
/ f * is the overexcitation multiples.
[24.DT.K] is overexcitation multiple setting of definite-time overexcitation protection tripping stage.
 Alarm stage
For Definite-time overexcitation protection alarm stage, the operation equation is:
U *
/ f * >[24.K_Alm] Equation 3.5-3
Where:
U *
/ f * is the overexcitation multiple.
[24.K_Alm] is overexcitation multiple setting of definite-time overexcitation protection alarm stage.
3.5.3.3 Inverse-time Overexcitation Protection
Inverse-time overexcitation protection realizes inverse-time characteristic by linear processing on

given inverse-time operation characteristic, after calculating the overexcitation multiple, by using
the method of piece-wise linear interpolation to get the corresponding operation time, then the
inverse-time characteristic can be realized. The heat accumulation and dissipation function is
equipped for inverse-time overexcitation protection.
Users can set eight groups of overexcitation multiple and tripping time to simulate the inverse-time
operation characteristics curve and it can satisfy the overexcitation requirement of various
transformer. For the overexcitation multiple between two overexcitation multiple settings, the
corresponding tripping time can be calculated via the internal piece-wise linear interpolation
method.
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Following figure shows inverse-time characteristic curve of overexcitation protection.
U*/f*
K0
K1
K2
K3
K4
K5
K6
K7
t0 t1 t2 t3 t4 t5 t6 t7 t(s)
Figure 3.5-1 Inverse-time overexcitation characteristic curve
The main harm of transformer overexcitation is overheat, inverse-time characteristic curve can
roughly simulate the heat accumulation and dissipation process for transformer overexcitation.
Once the transformer overexcitation multiple over the lower limit of inverse-time overexcitation
multiple [24.IDMT.K7], the time will be accumulated. When accumulated time delay is larger than
the tripping time of overexcitation protection, a tripping command will be issued by the device.
Once the transformer overexcitation multiple is less than the lower limit of inverse-time
overexcitation multiple [24.IDMT.K7], the inverse-time dissipation process starts. If the transformer
overexcitation multiple is always less than the lower limit of inverse-time overexcitation multiple,,
the accumulated value will decrease to “0” gradually.
The eight groups of settings of inverse-time characteristic curve must meet following conditions:
K0≥K1 ≥ K2 ≥ K3 ≥ K4 ≥ K5 ≥ K6 ≥ K7
t0 ≤t1 ≤ t2 ≤ t3 ≤ t4 ≤ t5 ≤ t6 ≤ t7
3.5.4 Logic
For each tripping stage of overexcitation protection, if following three conditions are met, the
protection will be enabled.
(1) Logic setting [24.En] is set as “1”.
(2) Protection function enabling inputs [24.En1], [24.En2] are “1”
(3) Protection function blocking input [24.Blk] is “0”.
If overexcitation protection is disabled, all the related output signals will be reset. If no external
input is configured to [24.En1] ([24.En2]), the default initial value of [24.En1] ([24.En2]) is “1”; if no
external input is configured to [24.Blk], the default initial value of [24.Blk] is “0”.
For the alarm stage of overexcitation protection, once the setting [ 24.En] is set as “1”, the alarm
function is enabled.
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SIG U*/f*>[24.K_Alm] &

[24.t_Alm] 0ms
[24.Alm]
EN [24.En]
SIG [24.En1] &
SIG [24.En2] &

[24.DT.t_Op] 0ms
[24.DT.Op]
SIG [24.Blk]
SIG U*/f*>[24.DT.K]
>=1
≥1
0ms 500ms
SIG 24.DT.FD
[24.St]
EN [24.En]
SIG [24.En1] &
SIG [24.En2] &

IDMT
[24.IDMT.Op]
SIG [24.Blk]
SIG U*/f*>[24.IDMT.K7]
0ms 500ms
SIG 24.IDMT.FD
Figure 3.5-2 Logic diagram of overexcitation protection
Where:
U *
/ f * is the overexcitation multiple.
24.DT.FD is the internal signal indicating that the definite-time overexcitation protection picks up
(the fault detector of fault detector DSP module).
24.IDMT.FD is the internal signal indicating that the inverse-time overexcitation protection picks up
24
24.U3P 24.St
f 24.DT.Op
24.En1 24.IDMT.Op
24.En2 24.Alm
24.Blk
Figure 3.5-3 Function block diagram of overexcitation protection
Table 3.5-1 Input signals of overexcitation protection

1 24.U3P Three-phase voltage input.
2 f Frequency input for the protection.
3 24.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
4 24.En2 as function enabling binary inputs, logic links, etc.
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5 24.Blk Protection function blocking input, such as function blocking binary input.
Table 3.5-2 Output signals of overexcitation protection

1 24.St Tripping stage of overexcitation protection starts.
2 24.DT.Op Definite-time overexcitation protection operates to trip.
3 24.IDMT.Op Inverse-time overexcitation protection operates to trip.
4 24.Alm The alarm stage of overexcitation protection operates to issue alarm signal
Table 3.5-3 Output signals of overexcitation protection (event recorder)
Tripping reports
1 24.DT.Op Definite-time overexcitation protection operates to trip.
2 24.IDMT.Op Inverse-time overexcitation protection operates to trip.
Start signals
3 24.St Tripping stage of overexcitation protection starts.
Alarm signals
4 24.Alm The alarm stage of overexcitation protection operates to issue alarm signal
Waveform recording
Tripping stage of overexcitation protection operates to trigger waveform

5 24.TrigDFR
recording.
6 24.DT.St Tripping stage of definite-time overexcitation protection starts.
7 24.IDMT.St Tripping stage of inverse-time overexcitation protection starts.
Table 3.5-4 Output signals of overexcitation protection (measurements)
1 f System frequency. Hz
2 24.U/f Overe xcitation multiple of overexcitation protection.
3 24.IDMT.ThermAccu Inverse-time accumulate value of overexcitation protection. %
Access path:
Main menu -> Measurements -> Measurements1-> Tr Values-> Tr Volt Values
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3.5.6 Settings
Table 3.5-5 Settings list of overexcitation protection

1 24.En 1
1: enable overexcitation protection.
Overe xcitation multiple setting of alarm stage
2 24.K_Alm 1.00~2.00 0.01
of definite-time overexcitation protection.
Time delay setting of alarm stage of
3 24.t_Alm 0.1~30 0.1 s
definite-time overexcitation protection.
Overe xcitation multiple setting of tripping stage
4 24.DT.K 1.00~2.00 0.01
of definite-time overexcitation protection.
Time delay setting of tripping stage of
5 24.DT.t_Op 0.1~3000 0.1 s
definite-time overexcitation protection.
Tripping logic setting of definite-time
6 24.DT.OutMap 0~3FFFFFFF
Upper-limit overexcitation multiple setting of
7 24.IDMT.K0 1.00~2.00 0.01
inverse-time overexcitation protection
Time delay setting corresponds to upper-limit
8 24.IDMT.t0_Op 1~3000 0.1 s
overexcitation multiple setting
Overe xcitation multiple setting 1 of
9 24.IDMT.K1 1.00~2.00 0.01
Time delay setting corresponds to
10 24.IDMT.t1_Op 1~3000 0.1 s
overexcitation multiple setting 1
11 24.IDMT.K2 1.00~2.00 0.01
12 24.IDMT.t2_Op 1~3000 0.1 s
13 24.IDMT.K3 1.00~2.00 0.01
14 24.IDMT.t3_Op 1~3000 0.1 s
15 24.IDMT.K4 1.00~2.00 0.01
16 24.IDMT.t4_Op 1~3000 0.1 s
17 24.IDMT.K5 1.00~2.00 0.01
18 24.IDMT.t5_Op 1~3000 0.1 s
19 24.IDMT.K6 1.00~2.00 0.01
20 24.IDMT.t6_Op 1~3000 0.1 s Time delay setting corresponds to
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21 24.IDMT.K7 1.00~2.00 0.01
22 24.IDMT.t7_Op 1~3000 0.1 s
Tripping logic setting of inverse-time
23 24.IDMT.OutMap 0~3FFFFFFF
Access path: Settings-> Prot Settings -> Tr OvExc Settings
3.6 Main Transformer Phase Overcurrent Protection (50/51P)
NOTICE!
In Section 3.6, the prefix “Y” in settings (such as [Y.50/51P1.I_Set]) and input/output
signals (such as [Y.50/51P1.Op]) can be Tr_HVS, Tr_MVS, and Tr_LVS. Details of the
prefix are as:
Tr_HVS.50/51P Corresponds to phase overcurrent protection of main transformer high voltage side.
Tr_MVS.50/51P Corresponds to phase overcurrent protection of main transformer medium voltage side.
Tr_LVS.50/51P Corresponds to phase overcurrent protection of main transformer low voltage side.
3.6.1 Application
When a fault occurs in power system, the current increases and phase overcurrent protection
operates to avoid damages to protected equipment. Voltage controlled element can be selected to
improve the sensitivity of phase overcurrent protection and direction element can be selected to
improve the selectivity of the protection. In order to prevent the phase overcurrent protection from
mal-operation when energizing a transformer without load, harmonic blocking element can be
applied to phase overcurrent protection (harmonic blocking element is not available for main
transformer low voltage side phase overcurrent protection).
An external fault will result in transformer overload, it will lead to damage of transformer if the fault
can not be cut off quickly, and in this case phase overcurrent protection can operate to trip
transformer circuit breaker to avoid physical damage. For small-scale transformer, phase
overcurrent protection can protect main transformer from internal fault, for large-scale transformer,
phase overcurrent protection is applied as the backup protection of transformer differential
protection.
Main transformer phase overcurrent protection has following functions:
 Three-stage phase overcurrent protection with independent logic, current and time delay
settings.
 Stage 1 and stage 2 are definite-time characteristic, stage 3 can be selected as definite-time
or inverse-time characteristic. The inverse-time characteristic is selectable among IEC and
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3 Operation Theory
ANSI/IEEE standard inverse-time characteristics and a user-defined inverse-time curve.
 Voltage controlled element can be selected to control each stage of phase overcurrent
protection.
 Direction element can be selected to control each stage of phase overcurrent protection with
three options: no direction, forward direction and reverse direction.
 Second harmonic blocking element can be enabled or disabled for each stage of phase
overcurrent protection (harmonic blocking element is not available for main transformer low
voltage side phase overcurrent protection).
3.6.3.1 Overview
Main transformer phase overcurrent protection consists of following elements:
 Phase overcurrent element: each stage is equipped with one independent overcurrent
element.
 Voltage controlled element: one voltage controlled element shared by all phase overcurrent
elements.
 Direction element: one direction element shared by all phase overcurrent elements.
 Harmonic blocking element: Second harmonic blocking function is available (harmonic

blocking element is not available for main transformer low voltage side phase overcurrent
protection).
U3P
Stage 1
[Alm_VTS] Direction Direction signal St
Element
Overcurrent Op
Element
voltage signal
Voltage Stage 2
Control St
Element Overcurrent Op
Element
I3P
Stage 3
Harmonic St
Blocking Overcurrent Op
Harmonic restraint
Element Element
signal
Figure 3.6-1 Function diagram of main transformer phase overcurrent protection
3.6.3.2 Current Element
The operation criterion of each stage of main transformer phase overcurrent protection is:
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I p > [Y.50/51Px.I_Set] Equation 3.6-1
Where:
I p is measured phase current.
[Y.50/51Px.I_Set] is the current setting of stage x (x=1, 2, or 3) of phase overcurrent protection.

For inverse-time overcurrent protection, it can be set as 1.1 times of base current of inverse-time
If any phase current is larger than the current setting of any enabled stage of phase overcurrent
protection, voltage controlled element operates (or voltage controlled element is disabled),
direction element operates (or direction element is disabled), and harmonic blocking element is
released (or harmonic blocking element is disabled), the stage of phase overcurrent protection will
operate after a time delay. The stage phase overcurrent protection will drop off instantaneously
after fault current disappears.
3.6.3.3 Time Curve
Main transformer phase overcurrent protection stage 1 and stage 2 are definite-time characteristic
and each stage can perform instantaneous operation if the corresponding time delay setting is set
as “0”. Stage 3 can be selected as definite-time or inverse-time characteristic, and inverse-time
operating time curve is as follows.
 
 
 K 
t(I)   C  TP Equation 3.6-2
 I  
 ( ) 1 
 I set 
Where:
I set is the base current setting, corresponds to the setting [Y.50/51P3.Ib_Set]. The maximum
operating current of the circuit should be taken into account, it should not pick up for overload.
T p is inverse-time time factor, corresponds to the setting [Y.50/51P3.TMS]. It should coordinate
to the time differential of the of the power grid.
, 
K ,C are inverse-time constants of inverse-time curve.
the setting [Y.50/51P3.Opt_Curve], and parameters of available characteristics for selection are
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Table 3.6-1 Inverse-time curve parameters of stage 3 of main transformer phase overcurrent protection
Y.50/51P3.Opt_Cur ve Time Characteristic K α C
0 Definite time
8 ANSI Inverse 0.0086 0.02 0.0185
[Y.50/51P3.Opt_Curve] as “13” to customize the inverse-time curve characteristic (by configuring
3.6.3.4 Voltage Controlled Element
Main transformer phase overcurrent protection is equipped as the backup protection of main
transformer and adjacent power equipment, and voltage element is usually used to control phase
overcurrent protection to improve sensitivity of the protection. Unsymmetrical fault will result in
unsymmetrical sequence voltages and symmetrical fault will lead to low three phase voltages at
relay location. If voltage element is enabled, phase overcurrent protection can operate if the
sequence voltage is larger than a setting or phase-to-phase voltage is lower than a setting, so
current settings of phase overcurrent protection can be set lower with high sensitivity.
 Operation criterion of voltage controlled element
The voltage controlled element picks up if phase-to-phase voltage is lower than its setting or
negative-sequence voltage is larger than its setting.
Criteria:
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U 
< [Y.50/51P.Upp_VCE] or U 2
 [Y.50/51P.U2_VCE] Equation 3.2-3
Where:
U  is the phase-to-phase voltage.
U 2
is the negative-sequence voltage.
[Y.50/51P.Upp_VCE] is the phase-to-phase undervoltage setting.
[Y.50/51P.U2_VCE] is the negative-sequence overvoltage setting.
Voltage of any side can be used as the input of voltage controlled element through the software
PCS-Explorer.
 Effect of VT Circuit
The logic setting [Y.50/51P.En_VTS_Blk] is used to control the voltage controlled element of phase
overcurrent protection during VT circuit failure. When VT circuit fails, if setting
[Y.50/51P.En_VTS_Blk] is set as “1”, the voltage controlled element will not pick up when VT circuit
fails; if the setting is set as “0”, and voltage controlled element meet the criterion, voltage
controlled element will pick up.
3.6.3.5 Direction Element
Direction element can be selected to control main transformer phase overcurrent protection to
coordinate with other protections of power grid. If the element is select ed for phase overcurrent
protection, then the protection becomes directional overcurrent protection.
Positive-sequence voltage (U1) is adopted as polarizing voltage, and pre-fault memory

positive-sequence voltage is used during three-phase close-up faults to ensure the direction
element working properly. Phase current (Ip) is adopted for calculation of direction element, and if
current is less than current threshold, both of forward direction and reverse direction are not met.

When a fault occurs at forward direction, the angle between polarizing voltage U ref and fault
current I dir is:
U ref
k  arg Equation 3.6-3
I dir
When a fault occurs at reverse direction, the angle is:
U ref 
 k  arg  180  Equation 3.6-4
I dir
k
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3 Operation Theory
Assuming that relay characteristic angle is  sen

(corresponds to the setting [Y.50/51P.RCA]), i.e.
the angle polarizing voltage leading fault current, in order to ensure the direction element can
operate reliably, the angle range of the forward direction is:
 U 
 sen  sen
ref
 90  arg   90 Equation 3.6-5
I dir
If VT and CT are connected as following figure, i.e. positive polarity of CT is at busbar side, points
to the protected object, then the operation zone of forward and reverse direction element are
shown in Figure 3.6-3 (Wherein the hatched portion is the operation zone of forward direction
element). Symbol” ” represents the positive polarity of current transformer.
Reverse Forward
CT
Protected
Object
VT
Direction
Element
Figure 3.6-2 Connection of VT and CT of direction element
Reverse
Uref(U1)
Φsen
Φsen+180°
Idir(Ip)
Forward
Figure 3.6-3 Direction characteristic of main transformer phase overcurrent protection
The logic setting [Y.50/51P.En_VTS_Blk] is used to control the direction element of phase
overcurrent protection during VT circuit failure. When VT circuit fails, if setting
[Y.50/51P.En_VTS_Blk] is set as “1”, the direction element will not pick up when VT circuit fails; if
the setting is set as “0”, and direction element meet the criterion, direction element will pick up.
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3.6.3.6 Harmonic Blocking Element
NOTICE!
This element is ONLY available for the main transformer HV side and MV side phase
overcurrent protection; it is not available for main transformer LV side phase
When phase overcurrent protection is used to protect main transformer during main transformer
energization, in order to prevent the mal-operation of phase overcurrent protection that caused by
inrush current, harmonic blocking function can be selected for each stage. Users can select the
harmonic blocking mode (synthetic blocking mode, synthetic blocking mode or phase blocking
mode) by the logic setting [Y.50/51P.Opt_Hm_Blk].
 Harmonic blocking principle
The device adopts the ratio between second harmonic and fundamental component of
three-phase current to realize inrush current blocking criterion, the equation is:
Operation criterion:
I p _ 2 n d  [5 0 / 5 1 P . K _ H m 2 ]  I p Equation 3.6-6
Where:
I p _ 2 nd is the second harmonic of any phase current.
I p is the fundamental component of corresponding phase current.
[50/51P.K_Hm2] is second harmonic restraint coefficient, the recommended value is 0.15.
Harmonic releasing
If any phase current is larger than the harmonic releasing current setting [Y.50/51P.I_Rls_HmBlk],
the harmonic blocking element will be released immediately even though the harmonic blocking
condition is met.
 Harmonic blocking mode
1) Synthetic blocking mode
M a x { I a 2 n d , I b 2 n d , I c 2 n d }  [ Y .5 0 / 5 1 P . K _ H m 2 ]  M a x ( I a 1 n d , I b 1 n d , I c 1 n d ) Equation 3.6-7
2) Cross blocking mode
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 I a 2 n d  [Y . 5 0 / 5 1 P . K _ H m 2 ]  I a 1 n d
 or
 I b 2 n d  [Y . 5 0 / 5 1 P . K _ H m 2 ]  I b 1 n d
 I a 2 n d  [Y . 5 0 / 5 1 P . K _ H m 2 ]  I a 1 n d
 or Equation 3.6-8
 I c 2 n d  [Y . 5 0 / 5 1 P . K _ H m 2 ]  I c 1 n d
 I c 2 n d  [Y . 5 0 / 5 1 P . K _ H m 2 ]  I c 1 n d

 I b 2 n d  [Y . 5 0 / 5 1 P . K _ H m 2 ]  I b 1 n d
3) Phase blocking mode
If one of the following criteria is met, only the corresponding phase differential protection will be
blocked.
 I a 2 n d  [Y . 5 0 / 5 1 P . K _ H m 2 ]  I a 1 n d

 I b 2 n d  [Y . 5 0 / 5 1 P . K _ H m 2 ]  I b 1 n d Equation 3.6-9

 I c 2 n d  [Y . 5 0 / 5 1 P . K _ H m 2 ]  I c 1 n d
3.6.4 Logic
Logic diagram of main transformer phase overcurrent is shown in the following figure, including
phase overcurrent element, voltage controlled element and direction element, harmonic blocking
element and enabling and blocking logic of the protection.
For stage x of phase overcurrent protection, if following three conditions are met, stage x of phase
overcurrent protection is enabled.
(1) Logic setting [Y.50/51Px.En] is set as “1”.
(2) The protection function enabling inputs [Y.50/51Px.En1], [Y.50/51Px.En2] are “1”
(3) The protection function blocking input [Y.50/51Px.Blk] is “0”.
If main transformer phase overcurrent protection is disabled, all the related output signals will be
reset. If no external input is configured to [Y.50/51Px.En1] ([Y.50/51Px.En2]), the default initial
value of [Y.50/51Px.En1] ([Y.50/51Px.En2]) is “1”; if no external input is configured to
[Y.50/51Px.Blk], the default initial value of [Y.50/51Px.Blk] is “0”.
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EN [Y.50/51Px.En]
SIG [Y.50/51Px.En1] &
SIG [Y.50/51Px.En2]
SIG [Y.50/51Px.Blk]
SIG [Y.50/51P.I3P]
& &
SET [Y.50/51Px.I_Set] [Y.50/51Px.St]
SIG [Y.50/51P.VCE.Op] ≥1
Timer
SET [Y.50/51Px.En_VCE] t
[Y.50/51Px.Op]
t
SIG [Y.50/51P.DIR.Op] ≥1
Inverse-time only for
SET [Y.50/51Px.En_Dir] stage 3
SIG [Y.50/51P.HMB.Op] ≥1
SET [Y.50/51Px.En_Hm2_Blk]
0ms 500ms
SIG Y.50/51Px.FD
Figure 3.6-4 Logic diagram of main transformer phase overcurrent protection (x=1,2,3)
Where:
[Y.50/51P.VCE.Op] is the signal indicating that the voltage controlled element operates.
[Y.50/51P.I3P] is the three-phase current input.
[Y.50/51P.DIR.Op] is the signal indicating that the direction element operates.
[Y.50/51P.HMB.Op] is the signal indicating that the harmonic blocking element is released.
Y.50/51Px.FD is the internal signal indicating that stage x of main transformer phase overcurrent
SIG [Y.50/51P.En] &

&
SIG [Y.50/51P.Blk] [Y.50/51P.VCE.Op_Upp]
SET U <[Y.50/51P.Upp_VCE] &

≥1
SIG VT circuit failure
&
EN [Y.50/51P.En_VTS_Blk]
Figure 3.6-5 Logic diagram of phase-to-phase VCE of main transformer phase overcurrent protection
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SIG [Y.50/51P.En] &

&
SIG [Y.50/51P.Blk] [Y.50/51P.VCE.Op_U2]
SET U 2>[Y.50/51P.U2_VCE] &

≥1
SIG VT circuit failure
&
Figure 3.6-6 Logic diagram of negative-sequence VCE of main transformer phase overcurrent protection
Where:
U  is the phase-to-phase voltage.
U 2 is the negative-sequence voltage.
[Y.50/51P.VCE.Op_Upp] is the internal operation signal of phase-to-phase undervoltage element.
[Y.50/51P.VCE.Op_U2] is the internal operation signal of negative-sequence voltage element.
EN [Y.50/51P.En] &
SIG [Y.50/51P.Blk] &

[Y.50/51P.DIR.Op]
SIG [Y.50/51P.I3P]
Direction
Check &
SIG [Y.50/51P.U3P]
Fwd/Rev
SET [Y.50/51P.Opt_Dir]
SIG VT circuit failure &
Figure 3.6-7 Logic diagram of direction element of main transformer phase overcurrent protection
Where:
[Y.50/51P.I3P] is the three-phase current input.
[Y.50/51P.U3P] is the three-phase voltage input.
[Y.50/51P.DIR.Op] is the internal signal indicating that the direction element operates.
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SIG Ip_2nd<[Y.50/51P.K_Hm2]*Ip &
SIG Ip>0.04In ≥1
&
SIG Ip>[Y.50/51P.I_Rls_HmBlk] [Y.50/51P.HMB.Op]
SIG [Y.50/51P.En] &
SIG [Y.50/51P.Blk]
Figure 3.6-8 Logic diagram of harmonic blocking element
I p _ 2 nd is second harmonic of phase current
I p is fundamental component of phase current.
[Y.50/51P.HMB.Op] is the signal indicating that the harmonic blocking element is released.
50/51P
Y.50/51Px.I3P Y.50/51Px.St
Y.50/51Px.U3P Y.50/51Px.Op
Y.50/51Px.En1
Y.50/51Px.En2
Y.50/51Px.Blk
Y.50/51Px.VCE
Figure 3.6-9 Function block diagram of main transformer phase overcurrent protection
Table 3.6-2 Input signals of main transformer phase overcurrent protection

1 Y.50/51Px.I3P Three-phase current data
2 Y.50/51Px.U3P Three-phase voltage data
3 Y.50/51Px.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
4 Y.50/51Px.En2 as function enabling binary inputs, logic links, etc.
5 Y.50/51Px.Blk Protection function blocking input, such as function blocking binary input.
6 Y.50/51Px.VCE Voltage controlled element input
Table 3.6-3 Output signals of main transformer phase overcurrent protection

1 Y.50/51P1.Op Stage 1 of phase overcurrent protection operates.
4 Y.50/51P1.St Stage 1 of phase overcurrent protection starts.
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Table 3.6-4 Output signals of main transformer phase overcurrent protection (event recorder)
Tripping reports
Start signals
Waveform recording
Stage 1 of phase overcurrent protection operates to trigger waveform

7 Y.50/51P1.TrigDFR
recording.

8 Y.50/51P2.TrigDFR
recording.

9 Y.50/51P3.TrigDFR
recording.
Table 3.6-5 Output signals of main transformer phase overcurrent protection (measurements)
Inverse-time accumulate value of phase A of stage 3 of

1 Y.50/51P3.Accu_A %
phase overcurrent protection.
Inverse-time accumulate value of phase B of stage 3 of

2 Y.50/51P3.Accu_B %
Inverse-time accumulate value of phase C of stage 3 of

3 Y.50/51P3.Accu_C %
The internal signal indicating that the direction element

4 Y.50/51P.DIR.Op
operates.
The signal indicating that the voltage controlled element

5 Y.50/51P.VCE.Op
operates.
The signal indicating that the harmonic blocking element is

6 Y.50/51P.HMB.Op
released (not available for main transformer LV side).
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Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Tr HVS PPF Prot Values
Main menu -> Measurements -> Measurements2-> Prot Values-> Tr MVS PPF Prot Values
Main menu -> Measurements -> Measurements2-> Prot Values-> Tr LVS Bak Prot Values
3.6.6 Settings
Table 3.6-6 Settings list of main transformer phase overcurrent protection

Phase-to-phase undervoltage setting of
1 Y.50/51P.Upp_VCE 2.00~120.00 0.01 V voltage controlled element of phase
Negative-sequence overvoltage setting of
2 Y.50/51P.U2_VCE 1.00~120.00 0.01 V voltage controlled element of phase
Relay characteristic angle of direction
3 Y.50/51P.RCA -90~90 0.01 deg
element of phase overcurrent protection.
Logic setting of selecting the pointing
direction of direction element of phase
0 Forward
4 Y.50/51P.Opt_Dir 1 overcurrent protection.
1: Reverse
0: Forward direction
1: Reverse direction
The second harmonic restraint coefficient
5 Y.50/51P.K_Hm2 0.05~0.5 0.01 deg for harmonic blocking element of phase
overcurrent protection
The phase current setting to release the
6 Y.50/51P.I_Rls_HmBlk 0.05~30 0.01 In
harmonic blocking element.
Logic setting of selecting harmonic
blocking mode for phase overcurrent
0: SyntheticBlk
protection:
7 Y.50/51P.Opt_Hm_Blk 1: CrossBlk 1
0: SyntheticBlk
2: PhaseBlk
1: CrossBlk
2: PhaseBlk
0: disable
8 Y.50/51P.En_VTS_Blk 1 controlled element or direction element
1: enable
being blocked during VT circuit failure.
0: disable Logic setting of enabling/disabling stage 1
9 Y.50/51P1.En 1
1: enable of phase overcurrent protection.
Current setting of stage 1 of phase
10 Y.50/51P1.I_Set 0.05~20.00In 0.01 A
Time delay of stage 1 of phase overcurrent
11 Y.50/51P1.t_Op 0~3000 0.01 s
protection.
12 Y.50/51P1.OutMap 0~3FFFFFFF Tripping logic setting of stage 1 of phase
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0: disable
13 Y.50/51P1.En_VCE 1 controlled element of stage 1 of phase
1: enable
Logic setting of enabling/disabling direction
0: disable
14 Y.50/51P1.En_Dir 1 element of stage 1 of phase overcurrent
1: enable
protection.
15 Y.50/51P1.En_Hm2_Blk 0, 1 1 harmonic blocking element of stage 1 of
0: disable Logic setting of enabling/dis abling stage 2
16 Y.50/51P2.En 1
17 Y.50/51P2.I_Set 0.05~20.00In 0.01 A
18 Y.50/51P2.t_Op 0~3000 0.01 s
protection.
Tripping logic setting of stage 2 of phase
19 Y.50/51P2.OutMap 0~3FFFFFFF
0: disable
1: enable
0: disable
1: enable
protection.
23 Y.50/51P3.En 1
24 Y.50/51P3.I_Set 0.05~20.00In 0.01 A
25 Y.50/51P3.t_Op 0~3000 0.01 s
protection.
26 Y.50/51P3.K_I_Max 10~40 0.01 to the pickup setting of stage 3 of phase
27 Y.50/51P3.Ib_Set 0.10~4.00In 0.01 A
inverse-time overcurrent protection.
Time factor setting of stage 3 of phase
28 Y.50/51P3.TMS 0.05~10.00 0.01
Minimum time delay of stage 3 of phase
29 Y.50/51P3.tmin 0~10 0.01 s
30 Y.50/51P3.K 0~120 0.01 The constant K of stage 3 of phase
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The constant C of stage 3 of phase
31 Y.50/51P3.C 0~20 0.01 s
The exponent alpha of stage 3 of phase
32 Y.50/51P3.Alpha 0.02~5 0.01
33 Y.50/51P3.Opt_Curve 0~13 1 characteristic curve of stage 3 of phase
34 Y.50/51P3.OutMap 0~3FFFFFFF
0: disable
1: enable
0: disable
1: enable
protection.
Access path:
Settings-> Prot Settings ->Tr HVS OC Settings
Settings-> Prot Settings ->TrMVS OC Settings
Settings-> Prot Settings ->Tr LVS OC Settings
3.7 Phase Overcurrent Alarm Elements (51PAlm)
NOTICE!
In Section 3.7, the prefix “Y” in settings (such as [Y.51PAlm1.I_Set]) and input/output
signals (such as [Y.51PAlm1.Alm]) can be Tr_HVS and Tr_MVS. Details of the prefix
are as:
Corresponds to phase overcurrent alarm elements of main transformer high voltage

Tr_HVS.51PAlm
side.
Corresponds to phase overcurrent alarm elements of main transformer medium voltage
Tr_MVS.51PAlm
side.
3.7.1 Application
During overload operation of a power transformer, great current results in greater heat will lead to
temperature increase of transformer, if the temperature reaches a too high value, the equipment
might be damaged, the insulation of the transformer will be forced ageing.
The phase overcurrent alarm elements are equipped to monitor the load of transformer winding,
and when load current exceeds the transformer limit load current, phase overcurrent alarm
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elements can be applied to issue alarm signals to remind field operators.
Besides, during overload of transformer, it is needed to initiate cooling system (such as cooling fan)
and blocking on-load-tap-changing (OLTC) function of the tap of transformer. Therefore phase
overcurrent alarm elements can also be applied to initiate cooling system and blocking OLTC
function.
3.7.2 Function
Phase overcurrent alarm elements has following functions:
 Three stages of definite-time phase overcurrent alarm elements with independent logic,
current and time delay settings are available.
 Phase overcurrent alarm elements is only applied for alarm signals.
 Drop off coefficient of each stage of phase overcurrent alarm element is settable.
Operation criterion:
I p > [Y.51PAlmx.I_Set] Equation 3.7-1
Where:
I p is phase current.
[Y.51PAlmx.I_Set] is the current setting of stage x (x=1~3) of phase overcurrent alarm element.
If any phase current is greater than the setting of any enabled stage of phase overcurrent alarm
element, the stage of phase overcurrent alarm element will operate after a settable time delay and
the stage protection will drop off if the overload current is lower than the drop off current value.
3.7.4 Logic
EN [Y.51PAlmx.En]
SIG [Y.51PAlmx.En1] &
SIG [Y.51PAlmx.En2]
SIG [Y.51PAlmx.Blk] &
[Y.51PAlmx.St]
SIG [Y.51PAlmx.I3P]
[Y.51PAlmx.t_Op] 0ms
SET [Y.51PAlmx.I_Set] [Y.51PAlmx.Alm]
Figure 3.7-1 Logic diagram of phase overcurrent alarm elements (x=1, 2, 3)
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3 Operation Theory
51PAlm
Y.51PAlmx.I3P Y.51PAlmx.St
Y.51PAlmx.En1 Y.51PAlmx.Op
Y.51PAlmx.En2
Y.51PAlmx.Blk
Figure 3.7-2 Function block diagram of phase overcurrent alarm elements
Table 3.7-1 Input signals of phase overcurrent alarm elements

1 Y.51PAlmx.I3P Three-phase current data.
2 Y.51PAlmx.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
3 Y.51PAlmx.En2 as function enabling binary inputs, logic links, etc.
4 Y.51PAlmx.Blk Protection function blocking input, such as function blocking binary input.
Table 3.7-2 Output signals of phase overcurrent alarm elements

1 Y.51PAlm1.Alm Stage 1 of phase overcurrent element operates to issue alarm signal.
4 Y.51PAlm1.St Stage 1 of phase overcurrent element starts.
Table 3.7-3 Output signals of phase overcurrent alarm elements (event recorder)
Alarm signal
Start signals
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3.7.6 Settings
Table 3.7-4 Settings list of phase overcurrent alarm elements
x=1, 2 and 3

0: disable Logic setting of enabling stage x of phase
1 Y.51PAlmx.En 1
1: enable overcurrent alarm element.
Current setting of stage x of phase
2 Y.51PAlmx.I_Set 0.05~20.00In 0.01 A
overcurrent alarm element.
Time delay of stage x of phase overcurrent
3 Y.51PAlmx.t_Op 0~3000 0.01 s
alarm element.
Drop off coefficient of stage x of phase
4 Y.51PAlmx.K_DropOut 0.75~0.99 0.01
overcurrent alarm element
Access path:
Settings-> Prot Settings ->Tr HVS OC Settings
Settings-> Prot Settings ->TrMVS OC Settings
3.8 Main Transformer Ground Overcurrent Protection (50/51G)
NOTICE!
In Section 3.8, the prefix “Y” in settings (such as [Y.50/51G1.3I0_Set]) and input/output
signals (such as [Y.50/51G1.Op]) can be Tr_HVS and Tr_MVS. Details of the prefix are
as:
Tr_HVS.50/51G Corresponds to ground overcurrent protection of main transformer high voltage side.
Tr_MVS.50/51G Corresponds to ground overcurrent protection of main transformer medium voltage side.
3.8.1 Application
If earth fault happens to a big-current earthing system, great residual current will generate,
whereas the great residual current is not exist during normal operation of the system, therefore
residual current is adopted for earth fault.
In order to improve the selectivity of ground overcurrent protection in power grid with two or
multiple power sources, directional element can be selected to control ground overcurrent
protection. In order to avoid the effect of transformer inrush current, second harmonic blocking
element can be applied to ground overcurrent protection.
3.8.2 Function
Ground overcurrent protection has following functions
 Three-stage ground overcurrent protection with independent logic, current and time delay
settings.
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 Stage 1 and stage 2 are definite-time characteristic, stage 3 can be selected as definite-time
or inverse-time characteristic. The inverse-time characteristic is selectable among IEC and
ANSI standard inverse-time characteristics and a user-defined inverse-time curve.
 Residual voltage can be selected to control each stage of ground overcurrent protection.
 Direction element can be selected to control each stage of ground overcurrent protection
with three options: no direction, forward direction and reverse direction.
 Second harmonic blocking element can be enabled or disabled for each stage of ground
 Measured residual current or calculated residual current can be selected for the calculation
of ground overcurrent protection.
3.8.3.1 Overview
Ground overcurrent protection consists of following elements:
 Residual overcurrent element: each stage is equipped with one independent residual
overcurrent element.
 Direction element: the direction of each stage can be set independently.
 Harmonic blocking element: Second harmonic blocking function is available.
3U0 from U3P

Stage1
[Alm_VTS] Direction Direction signal St
Element Ground
Op
Overcurrent
Element
Calculated or
measured 3I0
Stage2
St
Ground
Op
Overcurrent
Harmonic
Element
Blocking
Element Harmonic restraint
signal
Stage3
St
Ground
Op
Overcurrent
Element
Figure 3.8-1 Function diagram of ground overcurrent protection
3.8.3.2 Residual Current Element
The operation criterion of each stage of ground overcurrent protection is:
3I0 >[Y.50/51Gx.3I0_Set] Equation 3.8-1
Where:
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3 I 0 is measured residual current or calculated residual current, which is selected by user through
the setting [Y.50/51Gx.Opt_3I0] (x=1, 2 or 3).
[Y.50/51Gx.3I0_Set] is the residual current setting of stage x (x=1, 2 or 3) of ground overcurrent

protection.
If residual current is larger than the current setting of any enabled stage of ground overcurrent
protection, residual voltage controlled element operates (or voltage controlled element is disabled),
direction element operates (or direction element is disabled), and harmonic blocking element is
released (or harmonic blocking element is disabled), the stage of ground overcurrent protection
will operate after a time delay. The stage of ground overcurrent protection will drop off
instantaneously after fault current disappears.
3.8.3.3 Time Curve
Main transformer ground overcurrent protection stage 1 and stage 2 are definite-time
characteristic and each stage can perform instantaneous operation if the corresponding time delay
setting is set as “0”. Stage 3 can be selected as definite-time or inverse-time characteristic, and
inverse-time operating time curve is as follows.
 
 
K
t(I)    C   TP Equation 3.8-2
 3I0  
( ) 1
 I 
 set 
Where:
I set is the base current setting, corresponds to the setting [Y.50/51G3.Ib_Set].
T p is inverse-time time factor, corresponds to the setting [Y.50/51G3.TMS].
K ,  ,C are inverse-time constants of inverse-time curve.
the setting [Y.50/51G3.Opt_Curve], and parameters of available characteristics for selection are
Table 3.8-1 Inverse-time curve parameters of stage 3 of main transformer ground overcurrent protection
Y.50/51G3.Opt_Curve Time Characteristic K α C
0 Definite time
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3 Operation Theory
Y.50/51G3.Opt_Curve Time Characteristic K α C
8 ANSI Inverse 0.0086 0.02 0.0185
[Y.50/51G3.Opt_Curve] as “13” to customize the inverse-time curve characteristic (by configuring
3.8.3.4 Residual Voltage Controlled Element
Residual voltage controlled element is applied to ensure the reliability of the ground overcurrent
protection. Users can enable the element by setting [Y.50/51Gx.En_VCE]. If the setting is set as
“1”, the start signal or operation signal of residual overvoltage protection can be configured to
control ground overcurrent protection.
3.8.3.5 Residual Direction Element
The calculated residual voltage (3U0) is adopted as the polarizing quantity (i.e. polarizing voltage)
of residual directional element. When the measured residual current (IN) is selected for the
calculation of ground overcurrent, the measured residual current is the operating quantity (i.e. fault
current). When the calculated residual current (3I0) is selected for the calculation of ground
overcurrent, the calculated residual current is the operating quantity.

When a fault occurs at forward direction, the angle polarizing voltage U ref leading fault current
I dir is:
U ref
k  arg Equation 3.8-3
I dir
When a fault occurs at reverse direction, the angle is:
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3 Operation Theory
U ref 
 k  arg  180  Equation 3.8-4
I dir
k
Relay characteristic angle  sen (i.e. the setting [Y.50/51G.RCA]), in order to make sure the
residual direction element can operate reliably, the operating phase range for forward direction is:
 U 
 sen  sen
ref
 90  arg   90 Equation 3.8-5
I dir
If VT and CT are connected as following figure, i.e. positive polarity of CT is at busbar side, points
to the protected object, then the operation zone of forward and reverse direction element are
shown in Figure 3.8-3 (Wherein the hatched portion is the operation zone of forward direction
element). Symbol “*” represents the polarity of current transformer.
VT
Dir
Reverse
Direction
CT Element
Forward
Protected
Object
Figure 3.8-2 Connection of VT and CT of directional element
Forward
Idir(3I0 or IN)
Uref(3U0)
Φsen Φsen-180°
Reverse
Figure 3.8-3 Directional characteristic of ground overcurrent protection
The logic setting [Y.50/51G.En_VTS_Blk] is used to control the direction element of ground
overcurrent protection during VT circuit failure. When VT circuit fails, if the setting
[Y.50/51G.En_VTS_Blk] is set as “1”, the direction element will not pick up when VT circuit fails; if
the setting is set as “0”, and direction element meet the criterion, direction element will pick up.
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3.8.3.6 Harmonic Blocking Element
In order to prevent the mal-operation of ground overcurrent protection that caused by inrush
current, harmonic blocking function can be selected for each stage. If the setting
[Y.50/51Gx.En_Hm2_Blk] is set as “1” and the ratio between second harmonic and fundamental
component of residual current is larger than the second harmonic restraint coefficient, the
harmonic blocking element of ground overcurrent protection will operate. Via the setting
[Y.50/51Gx.En_Hm2_Blk], users can select which stage(s) of ground overcurrent protection will be
controlled by harmonic blocking element.
If the fundamental component of residual current is larger than the harmonic releasing residual
current setting [Y.50/51G.3I0_Rls_HmBlk], the harmonic blocking element will be released
immediately even though the harmonic blocking condition is met.
The operation equation of harmonic blocking element is:
3 I 0 _ 2 n d  [ Y .5 0 / 5 1G . K _ H m 2 ]  3 I 0 Equation 3.8-6
Where:
3 I 0 _ 2 n d is second harmonic of residual current
3 I 0 is fundamental component of residual current.
[51/51G.K_Hm2] is the second harmonic restraint coefficient of harmonic blocking element.
If the fundamental component of residual current is lower than the minimum operating current (the
typical value is 0.1In) of harmonic blocking element, the harmonic blocking element will out of
service.
3.8.4 Logic
Logic diagram of main transformer ground overcurrent is shown in the following figure, including
ground overcurrent element, residual voltage controlled element and direction element, harmonic
blocking element and enabling and blocking logic of the protection.
For stage x of ground overcurrent protection, if following three conditions are met, stage x of
ground overcurrent protection is enabled.
(1) Logic setting [Y.50/51Gx.En] is set as “1”.
(2) The protection function enabling inputs [Y.50/51Gx.En1], [Y.50/51Gx.En2] are “1”
(3) The protection function blocking input [Y.50/51Gx.Blk] is “0”.
If main transformer ground overcurrent protection is disabled, all the related output signals will be
reset. If no external input is configured to [Y.50/51Gx.En1] ([Y.50/51Gx.En2]), the default initial
value of [Y.50/51Gx.En1] ([Y.50/51Gx.En2]) is “1”; if no external input is configured to
[Y.50/51Gx.Blk], the default initial value of [Y.50/51Gx.Blk] is “0”.
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EN [Y.50/51Gx.En]
SIG [Y.50/51Gx.En1] &
SIG [Y.50/51Gx.En2]
SIG [Y.50/51Gx.Blk]
SIG 3I0 or IN
& &
SET [Y.50/51Gx.I_Set] [Y.50/51Gx.St]
SIG [Y.50/51G.VCE.Op] ≥1
Timer
SET [Y.50/51Gx.En_VCE] t
[Y.50/51Gx.Op]
t
SIG [Y.50/51Gx.DIR.Op] ≥1
Inverse-time only for
SET [Y.50/51Gx.En_Dir] stage 3
SIG [Y.50/51Gx.HMB.Op] ≥1
SET [Y.50/51Gx.En_Hm2_Blk]
0ms 500ms
SIG Y.50/51Gx.FD
Figure 3.8-4 Logic diagram of main transformer ground overcurrent protection (x=1,2,3)
Where:
[Y.50/51G.VCE.Op] is the signal indicating that the residual voltage controlled element operates.
3I0 or IN means calculated residual current (3I0) or measured residual current (IN).
[Y.50/51Gx.DIR.Op] is the signal indicating that the direction element operates.
[Y.50/51Gx.HMB.Op] is the signal indicating that the harmonic blocking element is released.
Y.50/51Gx.FD is the internal signal indicating that stage x of main transformer ground overcurrent
EN [Y.50/51Gx.En] &
SIG [Y.50/51Gx.Blk] &

[Y.50/51Gx.DIR.Op]
SIG [Y.50/51Gx.I3P/I1P]
Direction
Check &
SIG [Y.50/51Gx.U3P]
Fwd/Rev
SET [Y.50/51G.Opt_Dir]
EN [Y.50/51G.En_VTS_Blk]
Figure 3.8-5 Logic diagram of direction element of main transformer ground overcurrent protection
Where:
[Y.50/51Gx.I3P] is the three-phase current input.

[Y.50/51Gx.I1P] is single phase current input for ground overcurrent protection; generally it is the
measured residual current.
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[Y.50/51Gx.U3P] is the three-phase voltage input.

[Y.50/51Gx.DIR.Op] is the internal signal indicating that the direction element of stage x of ground
overcurrent protection operates.
SIG 3I0_2nd<[Y.50/51G.K_Hm2]*3I0_1 &
SIG 3I0_1>0.1In ≥1
&
SIG 3I0>[Y.50/51G.3I0_Rls_HmBlk] [Y.50/51Gx.HMB.Op]
SIG [Y.50/51Gx.En] &
SIG [Y.50/51Gx.Blk]
Figure 3.8-6 Logic diagram of harmonic blocking element
I p _ 2 nd is second harmonic of residual current
3 I 0 _ 1 is the fundamental component of residual current.
[Y.50/51Gx.HMB.Op] is the signal indicating that the harmonic blocking element of stage x of
ground overcurrent protection is released.
50/51G
Y.50/51Gx.I3P Y.50/51Gx.St
Y.50/51Gx.I1P Y.50/51Gx.Op
Y.50/51Gx.En1
Y.50/51Gx.En2
Y.50/51Gx.Blk
Y.50/51Gx.VCE
Figure 3.8-7 Function block diagram of main transformer ground overcurrent protection
Table 3.8-2 Input signals of main transformer ground overcurrent protection

1 Y.50/51Gx.I3P Three-phase current data
2 Y.50/51Gx.I1P Single phase current data, i.e. the measured residual current.
3 Y.50/51Gx.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings,
4 Y.50/51Gx.En2 such as function enabling binary inputs, logic links, etc.
5 Y.50/51Gx.Blk Protection function blocking input, such as function blocking binary input.
6 Y.50/51Gx.VCE Residual voltage control input for stage x of ground overcurrent protection.
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Table 3.8-3 Output signals of main transformer ground overcurrent protection

1 Y.50/51G1.Op Stage 1 of ground overcurrent protection operates.
4 Y.50/51G1.St Stage 1 of ground overcurrent protection starts.
Table 3.8-4 Output signals of main transformer ground overcurrent protection (e vent recorder)
Tripping reports
Start signals
Waveform recording
Stage 1 of ground overcurrent protection operates to trigger waveform

7 Y.50/51G1.TrigDFR
recording.

8 Y.50/51G2.TrigDFR
recording.

9 Y.50/51G3.TrigDFR
recording.
Table 3.8-5 Output signals of main transformer ground overcurrent protection (measurements)
Inverse-time accumulate value of stage 3 of ground

1 Y.50/51G3.Accu %
The internal signal indicating that the direction element of

2 Y.50/51Gx.DIR.Op
stage x (x=1, 2 or 3) operates.
The signal indicating that the harmonic blocking element of

3 Y.50/51Gx.HMB.Op
stage x (x=1, 2 or 3) is released.
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Access Path:
Main menu -> Measurements -> Measurements2-> Prot Status->Tr HVS EF Prot Values
Main menu -> Measurements -> Measurements2-> Prot Status->Tr MVS EF Prot Values
3.8.6 Settings
Table 3.8-6 Settings list of main transformer ground overcurrent protection

Relay characteristic angle of direction
1 Y.50/51G.RCA 90~270 0.01 deg
element of ground overcurrent protection.
Logic setting of selecting the pointing
direction of direction element of ground
0 Forward
2 Y.50/51G.Opt_Dir 1 overcurrent protection.
1: Reverse
0: Forward direction
1: Reverse direction
The second harmonic restraint coefficient
3 Y.50/51G.K_Hm2 0.05~0.5 0.01 deg for harmonic blocking element of ground
overcurrent protection
The phase current setting to release the
4 Y.50/51G.3I0_Rls_HmBlk 0.05~30 0.01 In
harmonic blocking element.
0: disable
5 Y.50/51G.En_VTS_Blk 1 element being blocked during VT circuit
1: enable
failure.
6 Y.50/51G1.En 1
1: enable of ground overcurrent protection.
Current setting of stage 1 of ground
7 Y.50/51G1.3I0_Set 0.05~20.00In 0.01 A
Time delay of stage 1 of ground
8 Y.50/51G1.t_Op 0~3000 0.01 s
Tripping logic setting of stage 1 of ground
9 Y.50/51G1.OutMap 0~3FFFFFFF
Logic setting of enabling/disabling residual
0: disable
10 Y.50/51G1.En_VCE 1 voltage controlled element of stage 1 of
1: enable
ground overcurrent protection.
0: disable
11 Y.50/51G1.En_Dir 1 element of stage 1 of ground overcurrent
1: enable
protection.
12 Y.50/51G1.En_Hm2_Blk 0, 1 1 harmonic blocking element of stage 1 of
Logic setting to select the current that
13 Y.50/51G1.Opt_3I0 0, 1 1 adopted by stage 1 of ground overcurrent
protection
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0: Measured residual current
1: Calculated residual current
14 Y.50/51G2.En 1
15 Y.50/51G2.3I0_Set 0.05~20.00In 0.01 A
16 Y.50/51G2.t_Op 0~3000 0.01 s
0: disable
1: enable
0: disable
1: enable
protection.
adopted by stage 2 of ground overcurrent
21 Y.50/51G2.Opt_3I0 0, 1 1 protection
22 Y.50/51G3.En 1
23 Y.50/51G3.3I0_Set 0.05~20.00In 0.01 A
24 Y.50/51G3.t_Op 0~3000 0.01 s
25 Y.50/51G3.K_3I0_Max 10~40 0.01 to the pickup setting of stage 3 of ground
26 Y.50/51G3.Ib_Set 0.10~4.00In 0.01 A
inverse-time overcurrent protection.
Time factor setting of stage 3 of ground
27 Y.50/51G3.TMS 0.05~10.00 0.01
Minimum time delay of stage 3 of ground
28 Y.50/51G3.tmin 0~10 0.01 s
The constant K of stage 3 of ground
29 Y.50/51G3.K 0~120 0.01
The constant C of stage 3 of ground
30 Y.50/51G3.C 0~20 0.01 s
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The exponent alpha of stage 3 of ground
31 Y.50/51G3.Alpha 0.02~5 0.01
32 Y.50/51G3.Opt_Curve 0~13 1 characteristic curve of stage 3 of ground
0: disable
1: enable
0: disable
1: enable
protection.
adopted by stage 3 of ground overcurrent
37 Y.50/51G3.Opt_3I0 0, 1 1 protection
Access path:
Settings-> Prot Settings ->Tr HVS EF Settings
Settings-> Prot Settings ->TrMVS EF Settings
3.9 Phase Overvoltage Protection (59P)
NOTICE!
In Section 3.9, the prefix “Y” in settings (such as [Y.59P1.Upp_Set]) and input/output
signals (such as [Y.59P1.Op]) can be Tr_HVS and Tr_MVS. Details of the prefix are as:
Tr_HVS.59P Corresponds to phase overvoltage protection of main transformer high voltage side.
Tr_MVS.59P Corresponds to phase overvoltage protection of main transformer medium voltage side.
3.9.1 Application
In the power system, there many causes will lead to overvoltage, such as mal-operation of the
excitation system, fault of voltage automatic adjustment device, load shedding due to full load of
generator, disconnection between generator and the system or isolated operation of the generator.
Overvoltage protection is provided to protect the operating equipment against the risk due to
abnormal rise of voltage.
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Phase overvoltage protection has following functions:
 Two-stage phase overvoltage protection for tripping and one-stage phase overvoltage
protection for alarm are available (with respective voltage setting, time delay and logic
setting).
 Stage 1 of phase overvoltage protection for tripping and the phase overvoltage protection for
alarm are definite-time overvoltage protection fixedly, stage 2 of phase overvoltage
protection for tripping can be configured as inverse-time overvoltage protection (IDMT) or
definite-time overvoltage protection by the setting [Y.59P2.Opt_Curve] (0: definite-time
characteristic, 1: inverse-time characteristic).
 Phase-to-phase voltage instead of phase-to-earth voltage is selected for overvoltage

protection calculation; it can prevent the overvoltage protection from mal-operation due to
single phase earthing for ungrounded system.
If phase-to-phase voltage is larger than corresponding voltage setting, corresponding stage of

overvoltage protection will pick up and operate with a settable time delay.
 Phase-to-phase voltage criterion
For each stage of overvoltage protection, the operation criterion is:
U   _ R M S > [Y.59Px.Upp_Set]
Equation 3.9-1
and U   _ m in >0.95* [Y.59Px.Upp_Set]
Where:
U   _ m in is the minimum value of amplitude of three phase-to-phase voltages.
U   _ R M S is the RMS value of amplitude of three phase-to-phase voltages.
[Y.59Px.Upp_Set] is the phase-to-phase voltage setting of stage x (x=1 or 2 or Alm) of overvoltage

protection.
3.9.3.2 Time Curve
Stage 1 of phase overvoltage protection for tripping and the phase overvoltage protection for alarm
are definite-time overvoltage protection fixedly.
Stage 2 of phase overvoltage protection for tripping can be configured as inverse-time overvoltage
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protection (IDMT) or definite-time overvoltage protection by the setting [Y.59P2.Opt_Curve] (0:

definite-time characteristic, 1: inverse-time characteristic), the equation of inverse-time
characteristic is:
TP
t 
U Equation 3.9-2
1
U set
Where:
U set
is inverse-time overvoltage pick-up setting, corresponds to the setting [Y.59P2.Upp_Set].
T p is inverse-time time factor, corresponds to the setting [Y.59P2.TMS].
3.9.4 Logic
For each stage of phase overvoltage protection, if following three conditions are met,
corresponding stage of phase overvoltage protection will be enabled.
(1) Logic setting [Y.59Px.En] is set as “1”.
(2) The protection function enabling inputs [Y.59Px.En1], [Y.59Px.En2] are “1”
(3) The protection function blocking input [Y.59Px.Blk] is “0”.
If overvoltage protection is disabled, all the related output signals will be reset. If no external input
is configured to [Y.59Px.En1] ([Y.59Px.En2]), the default initial value of [Y.59Px.En1] ([Y.59Px.En2])
is “1”; if no external input is configured to [Y.59Px.Blk], the default initial value of [Y.59Px.Blk] is “0”.
&
SIG [Y.59PAlm.U3P]
[Y.59PAlm.St]
SET [Y.59PAlm.Upp_Set]
Timer
EN [Y.59Pn.En] Y.59PAlm.t_Op
[Y.59PAlm.Alm]
SIG [Y.59Pn.En1] &
SIG [Y.59Pn.En2]
SIG [Y.59Pn.Blk]
SIG [Y.59Pn.U3P] &

[Y.59Pn.St]
SET [Y.59Pn.Upp_Set] Timer
t
0ms 500ms [Y.59Pn.Op]
SIG 59Pn.FD t
Inverse-time for stage 2 only
Figure 3.9-1 Logic diagram of phase overvoltage protection
Where:
[Y.59Px.U3P] is the three-phase voltage input for alarm or tripping stage of phase overvoltage
protection.
Y.59Px.FD is the signal to indicate that the fault detector of overvoltage protection picks up (the
fault detector of fault detector DSP module).
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59Pn (n=1 or 2) 59PAlm
Y.59Pn.U3P Y.59Pn.St Y.59PAlm.U3P Y.59PAlm.St
Y.59Pn.En1 Y.59Pn.Op Y.59PAlm.En1 Y.59PAlm.Alm
Y.59Pn.En2 Y.59PAlm.En2
Y.59Pn.Blk Y.59PAlm.Blk
Figure 3.9-2 Function block diagram of phase overvoltage protection
Table 3.9-1 Input signals of phase overvoltage protection

1 Y.59Px.U3P Three-phase voltage data. (x=1 or 2 or Alm)
2 Y.59Px.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings,
3 Y.59Px.En2 such as function enabling binary inputs, logic links, etc. (x=1 or 2 or Alm)
Protection function blocking input, such as function blocking binary input. (x=1 or 2 or
4 Y.59Px.Blk
Alm)
Table 3.9-2 Output signals of phase overvoltage protection

1 Y.59P1.St Phase overvoltage protection tripping stage 1 starts.
3 Y.59PAlm.St Phase overvoltage protection alarm stage starts.
4 Y.59P1.Op Phase overvoltage protection tripping stage 1 operates.
6 Y.59PAlm.Alm Phase overvoltage protection alarm stage operates to issue alarm signal.
Table 3.9-3 Output signals of phase overvoltage protection (event recorder)
Tripping reports
3 Y.59PAlm.Alm Phase overvoltage protection alarm stage operates to issue alarm signal.
Start signals
6 Y.59PAlm.St Phase overvoltage protection alarm stage starts.
Waveform recording
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3 Operation Theory
Phase overvoltage protection tripping stage 1 operates to trigger waveform

7 Y.59P1.TrigDFR
recording.
Phase overvoltage protection tripping stage 2 operates to trigger waveform

8 Y.59P2.TrigDFR
recording.
Table 3.9-4 Output signals of phase overvoltage protection (measurements)
1 Upp_Min The minimum value of three phase-to-phase voltages V
2 Upp_RMS The RMS value of three phase-to-phase voltages V
3 Upp_Peak The peak value of three phase-to-phase voltages V
Inverse-time accumulate value of stage 2 of phase overvoltage

4 Y.59P2.Accu %
protection.
Access Path:
3.9.6 Settings
Table 3.9-5 Settings list of phase overvoltage protection

0: disable Logic setting of enabling/disabling stage 1 of
1 Y.59P1.En 1
1: enable phase overvoltage protection.
Voltage setting of stage 1 of phase overvoltage
2 Y.59P1.Upp_Set 0.10~200 0.01 V
protection.
Time delay of stage 1 of phase overvoltage
3 Y.59P1.t_Op 0~30 0.01 s
protection.
4 Y.59P1.OutMap 0~3FFFFFFF
overvoltage protection.
Logic setting of enabling/disabling stage 2 of
0: disable
5 Y.59P2.En 1 phase overvoltage protection.
1: enable
0: disable; 1: enable
Voltage setting of stage 2 of phase overvoltage
6 Y.59P2.Upp_Set 0.10~200.00 0.01 V
protection.
Time delay of stage 2 of phase overvoltage
7 Y.59P2.t_Op 0~30 0.01 s
protection.
Time factor setting of stage 2 of inverse-time
8 Y.59P2.TMS 0.05~10.00 0.01 phase overvoltage protection. It is invalid if the
logic setting [59P2.Opt_Curve] is set as “0”.
Minimum time delay of stage 2 of inverse-time
9 Y.59P2.tmin 0~10 0.01 s phase overvoltage protection. It is invalid if the
logic setting [59P2.Opt_Curve] is set as “0”.
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3 Operation Theory

characteristic curve of stage 2 of phase
10 Y.59P2.Opt_Curve 0~1 1 overvoltage protection.
0: define-time
1: inverse-time
11 Y.59P2.OutMap 0~3FFFFFFF
0: disable Logic setting of enabling/disabling phase
12 Y.59PAlm.En 1
1: enable overvoltage protection alarm stage.
Voltage setting of phase overvoltage protection
13 Y.59PAlm.Upp_Set 0.10~200.00 0.01 V
alarm stage.
Time delay of phase overvoltage protection alarm
14 Y.59PAlm.t_Op 0~30 0.01 s
stage.
Access path:
Settings-> Prot Settings -> TrHVS VoltProt Settings
Settings-> Prot Settings -> TrMVS VoltProt Settings
3.10 Phase Undervoltage Protection (27P)
NOTICE!
In Section 3.10, the prefix “Y” in settings (such as [Y.27P1.Upp_Set]) and input/output
signals (such as [Y.27P1.Op]) can be Tr_HVS and Tr_MVS. Details of the prefix are as:
Tr_HVS.27P Corresponds to undervoltage protection of main transformer high voltage side.
Tr_MVS.27P Corresponds to undervoltage protection of main transformer medium voltage side.
3.10.1 Application
Undervoltage protection is used to detect the voltage decline of the operating motor, so to avoid
the impermissible operating conditions and the possible loss of stability. When the system voltage
decline to a certain degree so that the system stability will be affected, undervoltage protection can
be used as the operation criterion of load shedding.
Undervoltage protection has following functions:
 One-stage phase undervoltage protection for tripping and one-stage phase undervoltage
protection for alarm are available (with respective voltage setting, time delay and logic
setting).
 The phase undervoltage protection for alarm is definite-time undervoltage protection fixedly,
the phase undervoltage protection for tripping can be configured as inverse-time undervoltage
protection (IDMT) or definite-time undervoltage protection by the setting [Y.27P.Opt_Curve] (0:
definite-time characteristic, 1: inverse-time characteristic).
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3 Operation Theory
 Phase-to-phase voltage instead of phase-to-earth voltage is selected for undervoltage

protection calculation, it is insensitive to asymmetric voltage decline, but it is sensitive to
system stability problem.
3.10.3 Operation Principle
3.10.3.1 Operation Criterion
When phase-to-phase voltage is lower than corresponding voltage setting and the auxiliary
criterion is also met, corresponding stage of undervoltage protection will pick up and operate with
a settable time delay.
 Phase-to-phase voltage criterion
For each stage of undervoltage protection, the operation criterion is:
U  _ max > Up p_Set Equation 3.10-1
Where:
U  _ max is the maximum value of amplitude of three phase-to-phase voltages.
Up p_Set is the phase-to-phase voltage setting of undervoltage protection (tripping stage or alarm
stage).
3.10.3.2 Time Curve
The phase undervoltage protection for alarm is definite-time undervoltage protection fixedly.
The phase undervoltage protection for tripping can be configured as inverse-time undervoltage
protection (IDMT) or definite-time undervoltage protection by the setting [Y.27P.Opt_Curve] (0:
definite-time characteristic, 1: inverse-time characteristic), the equation of inverse-time
characteristic is:
TP
t 
U Equation 3.10-2
1
U set
Where:
U set
is inverse-time undervoltage pick-up setting, corresponds to the setting [Y.27P.Upp_Set].
T p is inverse-time time factor, corresponds to the setting [Y.27P.TMS].
3.10.3.3 Auxiliary Criterion
Undervoltage protection can be blocked by the normally open auxiliary contact of the circuit
breaker [Flg_52a]. If [Flg_52a] is “0”, undervoltage protection is blocked. Besides, the normally
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3 Operation Theory
open auxiliary contact of the circuit breaker can be replaced by the internal signal that indicating
the generator is connected with the system.
The undervoltage protection is also controlled by the load current, only if any phase current is
larger than 0.04In (the signal [Z.Flg_Onload]=1. Z=Y.27PAlm or Y.27P), the undervoltage
protection can be enabled.
When a fault happens at the secondary circuit of VT, the undervoltage protection tripping stage
can be blocked by a binary input signal (such as VT MCB auxiliary contact and etc.). The output
signal of VT circuit supervision function can also be adopted to block the undervoltage protection.
[Flg_52a], [Z.Flg_Onload] (Z=Y.27PAlm or Y.27P) and the VT abnormal binary input (or signal) can
be configured by the software PCS-Explorer.
3.10.4 Logic
For each stage of phase undervoltage protection, if following three conditions are met,
corresponding stage of phase undervoltage protection will be enabled.
(1) Logic setting [Z.En] (Z=Y.27PAlm or Y.27P) is set as “1”.
(2) The protection function enabling inputs [Z.En1], [Z.En2] are “1”.
(3) The protection function blocking input [Z.Blk] is “0”.
If undervoltage protection is disabled, all the related output signals will be reset. If no external input
is configured to [Z.En1] ([Z.En2]), the default initial value of [Z.En1] ([Z.En2]) is “1”; if no external
input is configured to [Z.Blk], the default initial value of [Z.Blk] is “0”.
Logic diagram of undervoltage protection is shown in the following figure.
EN [Y.27PAlm.En]
SIG [Y.27PAlm.En1] &
SIG [Y.27PAlm.En2]
&
SIG [Y.27PAlm.Blk]
[Y.27PAlm.St]
SET UΦΦ_max<[Y.27PAlm.Upp_Set]
Timer
Y.27PAlm.t_Op
[Y.27PAlm.Alm]
EN [Y.27P.En]
SIG [Y.27P.En1] &
SIG [Y.27P.En2] &
SIG [Y.27P.Blk] [Y.27P.St]
SET UΦΦ_max<[Y.27P.Upp_Set]
Timer
SIG Y.27P.FD 0ms 500ms t
[Y.27P.Op]
t
Figure 3.10-1 Logic diagram of undervoltage protection
Where:
Y.27P.FD is the internal signal to indicate that tripping stage of undervoltage protection picks up
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3 Operation Theory
27P 27PAlm
Y.27P.U3P Y.27P.St Y.27PAlm.U3P Y.27PAlm.St
Y.27P.En1 Y.27P.Op Y.27PAlm.En1 Y.27PAlm.Alm
Y.27P.En2 Y.27PAlm.En2
Y.27P.Blk Y.27PAlm.Blk
Flg_52a Flg_52a
Y.27P.Flg_Onload Y.27PAlm.Flg_Onload
Figure 3.10-2 Function block diagram of undervoltage protection
Table 3.10-1 Input signals of undervoltage protection

1 Flg_52a The signal indicating that the generator is connected with the system.
2 Z.U3P Three-phase voltage data (Z=Y.27PAlm or Y.27P).
3 Z.Flg_Onload The signal indicating that the load current is detected (Z=Y.27PAlm or Y.27P).
4 Z.En1 Protection function enabling input1 and input 2, it can be binary inputs or
settings, such as function enabling binary inputs, logic links, etc (Z=Y.27PAlm
5 Z.En2
or Y.27P).
Protection function blocking input, such as function blocking binary input
6 Z.Blk
(Z=Y.27PAlm or Y.27P).
Table 3.10-2 Output signals of undervoltage protection

1 Y.27P.St Phase undervoltage protection tripping stage starts.
2 Y.27PAlm.St Phase undervoltage protection alarm stage starts.
3 Y.27P.Op Phase undervoltage protection tripping stage operates.
4 Y.27PAlm.Alm Phase undervoltage protection alarm stage operates to issue alarm signal.
Table 3.10-3 Output signals of phase undervoltage protection (event recorder)
Tripping reports
1 Y.27P.Op Phase undervoltage protection tripping stage operates.
2 Y.27PAlm.Alm Phase undervoltage protection alarm stage operates to issue alarm signal.
Start signals
3 Y.27P.St Phase undervoltage protection tripping stage starts.
4 Y.27PAlm.St Phase undervoltage protection alarm stage starts.
Waveform recording
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3 Operation Theory
5 Y.27P.TrigDFR Phase undervoltage protection tripping stage operates to trigger waveform recording.
Table 3.10-4 Output signals of phase undervoltage protection (measurements)
1 Upp_Max The maximum value of three phase-to-phase voltages V
Inverse-time accumulate value of tripping stage of phase undervoltage

2 Y.27P.Accu %
protection.
Access Path:
3.10.6 Settings
Table 3.10-5 Settings list of phase undervoltage protection

0: disable Logic setting of enabling/disabling tripping stage
1 Y.27P.En 1
1: enable of phase undervoltage protection.
Voltage setting of tripping stage of phase
2 Y.27P.Upp_Set 0.10~120 0.01 V
undervoltage protection.
Time delay of tripping stage of phase
3 Y.27P.t_Op 0~30 0.01 s
Time factor setting of tripping stage of
inverse-time phase undervoltage protection. It is
4 Y.27P.TMS 0.05~10.00 0.01
invalid if the logic setting [Y.27P.Opt_Curve] is
set as “0”.
Minimum time delay of tripping stage of
inverse-time phase undervoltage protection. It is
5 Y.27P.tmin 0~10 0.01 s
invalid if the logic setting [Y.27P.Opt_Curve] is
set as “0”.
characteristic curve of tripping stage of phase
6 Y.27P.Opt_Curve 0~1 1 undervoltage protection.
0: define-time
1: inverse-time
Tripping logic setting of tripping stage of phase
7 Y.27P.OutMap 0~3FFFFFFF
0: disable Logic setting of enabling/disabling phase
8 Y.27PAlm.En 1
1: enable undervoltage protection alarm stage.
Voltage setting of phase undervoltage protection
9 Y.27PAlm.Upp_Set 0.10~120.00 0.01 V
alarm stage.
Time delay of phase undervoltage protection
10 Y.27PAlm.t_Op 0~30 0.01 s
alarm stage.
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Access path:
Settings-> Prot Settings -> TrHVS VoltProt Settings
Settings-> Prot Settings -> TrMVS VoltProt Settings
3.11 Residual Overvoltage Protection (59G)
NOTICE!
In Section 3.11, the prefix “Y” in settings (such as [Y.59G.3U0_Set]) and input/output
signals (such as [Y.59G.Op]) can be Tr_HVS, Tr_MVS and Tr_LVS. Details of the prefix
are as:
Tr_HVS.59G Corresponds to residual overvoltage protection of main transformer high voltage side.
Tr_MVS.59G Corresponds to residual overvoltage protection of main transformer medium voltage side.
Tr_LVS.59G Corresponds to residual overvoltage protection of main transformer low voltage side.
3.11.1 Application
Residual overvoltage protection is used to detect the earth fault of the system, generally it is used
for ungrounded system, high resistance grounded system or Peterson coil grounded system. For
directly grounded system or small resistance grounded system, generally ground overcurrent
protection is used to detect the earth fault.
3.11.2 Function
Residual overvoltage protection has following functions
 One-stage residual overvoltage protection for tripping and one-stage residual overvoltage
protection for alarm are available (with respective residual voltage setting, time delay and
logic setting).
 The residual overvoltage protection for alarm is definite-time residual overvoltage protection
fixedly, the residual overvoltage protection for tripping can be configured as inverse-time
residual overvoltage protection (IDMT) or definite-time residual overvoltage protection by the
setting [Y.59G.Opt_Curve] (0: definite-time characteristic, 1: inverse-time characteristic).
 The VT broken-delta residual voltage or the calculated residual voltage can be selected for
the calculation of residual overvoltage protection.
3.11.3.1 Operation Criterion
For any stage of residual overvoltage protection, the operation equation is:
3U 0
> [3U0_Set] Equation 3.11-1
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Where:
3U 0
is VT broken-delta residual voltage or calculated residual voltage, which is selected by user
through the setting [Y.59G.Opt_3U0]/[Y.59GAlm.Opt_3U0].
3U0_Set is the residual voltage setting of residual overvoltage protection (tripping stage or alarm
stage).
If residual voltage is greater than the setting of any enabled stage of residual overvoltage
protection, the stage of residual overvoltage protection will operate after a time delay and the
protection will drop off instantaneously after the fault disappears.
3.11.3.2 Time Curve
The residual overvoltage protection for alarm is definite-time residual overvoltage protection
fixedly.
The residual overvoltage protection for tripping can be configured as inverse-time residual
overvoltage protection (IDMT) or definite-time residual overvoltage protection by the setting
[Y.59G.Opt_Curve] (0: definite-time characteristic, 1: inverse-time characteristic), the equation of
inverse-time characteristic is:
TP
t 
U Equation 3.11-2
1
U set
Where:
U set
is inverse-time residual voltage pick-up setting, corresponds to the setting [Y.59G.3U0_Set].
T p is inverse-time time factor, corresponds to the setting [Y.59G.TMS].
3.11.4 Logic
For each stage of residual overvoltage protection, if following three conditions are met,
corresponding stage of residual overvoltage protection will be enabled.
(1) Logic setting [Z.En] (Z=Y.59GAlm or Y.59G)is set as “1”.
(2) The protection function enabling inputs [Z.En1], [Z.En2] are “1”.
(3) The protection function blocking input [Z.Blk] is “0”.
If residual overvoltage protection is disabled, all the related output signals will be reset. If no
external input is configured to [Z.En1] ([Z.En2]), the default initial value of [Z.En1] ([Z.En2]) is “1”; if
no external input is configured to [Z.Blk], the default initial value of [Z.Blk] is “0”.
Logic diagram of residual overvoltage protection is shown in the following figure.
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EN [Y.59GAlm.En]
SIG [Y.59GAlm.En1] &
SIG [Y.59GAlm.En2]
SIG [Y.59GAlm.Blk] &
SIG 3U0 [Y.59GAlm.St]
SET [Y.59GAlm.3U0_Set]
Timer
Y.59GAlm.t_Op
EN [Y.59G.En] [Y.59GAlm.Alm]
SIG [Y.59G.En1] &
SIG [Y.59G.En2]
SIG [Y.59G.Blk]
SIG 3U0 &

[Y.59G.St]
SET [Y.59G.3U0_Set]
SIG Y.59G.FD 0ms 500ms Timer

t
[Y.59G.Op]
t
Figure 3.11-1 Logic diagram of residual overvoltage protection
Where:
3U 0
is VT broken-delta residual voltage or calculated residual voltage.
Y.59G.FD is the internal signal to indicate that tripping stage of residual overvoltage protection
picks up (the fault detector of fault detector DSP module).
59G 59GAlm
Y.59G.U3P Y.59G.St Y.59GAlm.U3P Y.59GAlm.St
Y.59G.U1P Y.59G.Op Y.59GAlm.U1P Y.59GAlm.Alm
Y.59G.En1 Y.59GAlm.En1
Y.59G.En2 Y.59GAlm.En2
Y.59G.Blk Y.59GAlm.Blk
Figure 3.11-2 Function block diagram of residual overvoltage protection
Table 3.11-1 Input signals of residual overvoltage protection

1 Z.U3P Three-phase voltage data (Z=Y.59GAlm or Y.59G).
Single phase voltage data, i.e. VT broken-delta residual voltage (Z=Y.59GAlm
2 Z.U1P
or Y.59G).
3 Z.En1 Protection function enabling input1 and input 2, it can be binary inputs or
settings, such as function enabling binary inputs, logic links, etc (Z=Y.59GAlm
4 Z.En2
or Y.59G).
Protection function blocking input, such as function blocking binary input
5 Z.Blk
(Z=Y.59GAlm or Y.59G).
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Table 3.11-2 Output signals of residual overvoltage protection

1 Y.59G.St Residual overvoltage protection tripping stage starts.
2 Y.59GAlm.St Residual overvoltage protection alarm stage starts.
3 Y.59G.Op Residual overvoltage protection tripping stage operates .
4 Y.59GAlm.Alm Residual overvoltage protection alarm stage operates to issue alarm signal.
are only for LCD display and waveform recording function of the de vice.
Table 3.11-3 Output signals of residual overvoltage protection (e vent recorder)
Tripping reports
1 Y.59G.Op Residual overvoltage protection tripping stage operates.
2 Y.59GAlm.Alm Residual overvoltage protection alarm stage operates to issue alarm signal.
Start signals
3 Y.59G.St Residual overvoltage protection tripping stage starts.
4 Y.59GAlm.St Residual overvoltage protection alarm stage starts.
Waveform recording
5 Y.59G.TrigDFR Residual overvoltage protection tripping stage operates to trigger waveform recording.
Table 3.11-4 Output signals of residual overvoltage protection (measurements)
Inverse-time accumulate value of tripping stage of residual overvoltage

1 Y.59G.Accu %
protection.
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Status->Tr HVS EF Prot Values
Main menu -> Measurements -> Measurements2-> Prot Status->Tr MVS EF Prot Values
Main menu -> Measurements -> Measurements2-> Prot Status->Tr LVS Bak Prot Values
3.11.6 Settings
Table 3.11-5 Settings list of residual overvoltage protection

0: disable Logic setting of enabling/disabling tripping stage
1 Y.59G.En 1
1: enable of residual overvoltage protection.
Voltage setting of tripping stage of residual
2 Y.59G.3U0_Set 2.00~200 0.01 V
Time delay of tripping stage of residual
3 Y.59G.t_Op 0~30 0.01 s
4 Y.59G.TMS 0.05~10.00 0.01 Time factor setting of tripping stage of
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inverse-time residual overvoltage protection. It is
invalid if the logic setting [Y.59G.Opt_Curve] is
set as “0”.
Minimum time delay of tripping stage of
inverse-time residual overvoltage protection. It is
5 Y.59G.tmin 0~10 0.01 s
invalid if the logic setting [Y.59G.Opt_Curve] is
set as “0”.
characteristic curve of tripping stage of residual
6 Y.59G.Opt_Curve 0~1 1 overvoltage protection.
0: define-time
1: inverse-time
Tripping logic setting of tripping stage of residual
7 Y.59G.OutMap 0~3FFFFFFF
Logic setting to select the residual voltage that
adopted by tripping stage of residual overvoltage
8 Y.59G.Opt_3U0 0, 1 1 protection.
0: VT broken-delta residual voltage
0: disable Logic setting of enabling/disabling residual
9 Y.59GAlm.En 1
1: enable overvoltage protection alarm stage.
Voltage setting of residual overvoltage protection
10 Y.59GAlm.3U0_Set 2.00~200 0.01 V
alarm stage.
Time delay of residual overvoltage protection
11 Y.59GAlm.t_Op 0~30 0.01 s
alarm stage.
Logic setting to select the residual voltage that
adopted by alarm stage of residual overvoltage
12 Y.59GAlm.Opt_3U0 0, 1 1 protection.
0: VT broken-delta residual voltage
Access path:
Settings-> Prot Settings -> TrHVS EF Settings
Settings-> Prot Settings -> TrMVS EF Settings
Settings-> Prot Settings -> TrLVS EF Settings
3.12 Overfrequency Protection (81O)
3.12.1 Application
When active power surplus happens to the power system or the speed regulating system of
generator is in abnormal operation, the frequency of the power system will rise, so overfrequency
protection can be used to detect the above abnormal over-frequency conditions. If the frequency is
larger than the overfrequency protection setting, overfrequency protection will operate to issue
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3 Operation Theory
alarm signal or trip with a time delay.
Steam-turbine generator is able to withstand the frequency shifting, but this will leads to the
vibration of the turbine blade which will eventually cause the metal fatigue damage of the blade.
This kind of damage is a process of accumulation and it is irreversible, therefore, when t he
frequency protection is applied for steam-turbine generator, a feature of frequency accumulation is
required.
Overfrequency protection has following functions:
 Four stages of overfrequency protection (with respective frequency setting, time delay and
logic setting) are available. Each stage can be configured to issue alarm signal or trip.
 Four stages of overfrequency band accumulate protection are available and each stage has
respective frequency upper limit setting, lower limit frequency setting, accumulated time
setting and logic setting. Each stage can be configured to issue alarm signal or trip.
3.12.3.1 Overview
When the system frequency is larger than the overfrequency setting, the protection picks up, after
a time delay determined by the time delay setting, the overfrequency protection will operate to
issue alarm signal or trip. If the frequency accumulation function is enabled, i.e. the logic setting
[81O.OFx.En_Alm_Accu] or [81O.OFx.En_Trp_Accu] (x=1~4) is set as “1”, the relay will
accumulate the time that the system frequency falling into the corresponding overfrequency band,
if the accumulated time is larger than the corresponding time delay setting, the overfrequency
band accumulate protection will operate to issue alarm signal or trip.
The positive voltage is used to calculate the system frequency, after a filtering process, the
measurement of system frequency will not be affected by the harmonic component.
 Operation criterion of overfrequency protection
f >[81O.OFx.f_Set] Equation 3.12-1
Where:
f is system frequency.
[81O.OFx.f_Set] is the frequency setting of stage x (x=1~4) of overfrequency protection.
 Operation criterion of overfrequency band accumulate protection
[81O.OFx’.f_Set] > f >[81O.OFx.f_Set] Equation 3.12-2
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Where:
[81O.OFx.f_Set] is the lower limit frequency setting of stage x (x=1~4) of overfrequency band
accumulate protection.
[81U.UFx’.f_Set] is the upper limit frequency setting of stage x (x=1~4) of overfrequency band
If x=1~3, x’=x+1.
If x=4, the operation criterion of overfrequency band accumulate protection isL
f >[81O.OF4.f_Set] Equation 3.12-3
3.12.4 Logic
For overfrequency protection, when following three conditions are met, the protection is enabled.
(1) Logic setting [81O.En] is set as “1”.
(2) The protection function enabling binary inputs [81O.En1] and [81O.En2] are “1”
(3) The protection function blocking input [81O.Blk] is “0”.
If overfrequency protection is disabled, all the related output signals will be reset. If no external
input is configured to [81O.En1] ([81O.En2]), the default initial value of [81O.En1] ([81O.En2]) is
“1”; if no external input is configured to [81O.Blk], the default initial value of [81O.Blk] is “0”.
EN [81O.En] &
& [81O.OFx.t_Op] 0s
[81O.OFx.Alm]
EN [81O.OFx.En_Alm] &
SIG f > [81O.OFx.f_Set]
& [81O.St]
& [81O.OFx.t_Op] 0s
EN [81O.OFx.En_Trp] &
[81O.OFx.Op]
SIG f > [81O.OFx.f_Set]
SIG [81O.En1] &

SIG [81O.En2]
SIG [81O.Blk]
0 500ms
SIG 81O.FD
Figure 3.12-1 Logic diagram of stage x of overfrequency protection
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EN [81O.En]
SIG [Flg_52a] &
SIG [81O.Flg_OnLoad]
&
[81O.OF1.t_Accu] 0s
& [81O.OF1.Alm_Accu]
EN [81O.OF1.En_Alm_Accu] &
SIG [81O.OF2.f_Set]>f>[81O.OF1.f_Set]
& [81O.St]
& [81O.OF1.t_Accu] 0s
EN [81O.OF1.En_Trp_Accu] &
[81O.OF1.Op_Accu]
SIG [81O.OF2.f_Set]>f>[81O.OF1.f_Set]
SIG [81O.En1] &

SIG [81O.En2]
SIG [81O.Blk]
0 500ms
SIG 81O.FD
Figure 3.12-2 Logic diagram of stage 1 of overfrequency band accumulate protection
The stage 2 and stage 3 of overfrequency band accumulate protection are similar to stage 1 of
overfrequency band accumulate protection.
EN [81O.En]
SIG [Flg_52a] &
SIG [81O.Flg_OnLoad]
&
[81O.OF4.t_Accu] 0s
& [81O.OF4.Alm_Accu]
EN [81O.OF4.En_Alm_Accu] &
SIG f>[81O.OF4.f_Set]
& [81O.St]
& [81O.OF4.t_Accu] 0s
EN [81O.OF4.En_Trp_Accu] &
[81O.OF4.Op_Accu]
SIG f>[81O.OF4.f_Set]
SIG [81O.En1] &

SIG [81O.En2]
SIG [81O.Blk]
0 500ms
SIG 81O.FD
Figure 3.12-3 Logic diagram of stage 4 of overfrequency band accumulate protection
Where:
81O.FD is the internal signal to indicate that overfrequency protection picks up (the fault detector
of fault detector DSP module).
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81O
f 81O.St
81O.En1 81O.OF1.Op
81O.En2 81O.OF2.Op
81O.Blk 81O.OF3.Op
81O.Flg_OnLoad 81O.OF4.Op
Flg_52a 81O.OF1.Op_Accu
81O.OF2.Op_Accu
81O.OF3.Op_Accu
81O.OF4.Op_Accu
81O.OF1.Alm
81O.OF2.Alm
81O.OF3.Alm
81O.OF4.Alm
81O.OF1.Alm_Accu
81O.OF2.Alm_Accu
81O.OF3.Alm_Accu
81O.OF4.Alm_Accu
Figure 3.12-4 Function block diagram of overfrequency protection
Table 3.12-1 Input signals of overfrequency protection

2 81O.Flg_Onload The signal indicating that current is detected.
3 f Measured frequency data input.
4 81O.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
5 81O.En2 as function enabling binary inputs, logic links, etc.
6 81O.Blk Protection function blocking input, such as function blocking binary input.
Table 3.12-2 Output signals of overfrequency protection

1 81O.St Overfrequency protection starts.
2 81O.OF1.Op Stage 1 of overfrequency protection operates to trip.
6 81O.OF1.Op_Accu Stage 1 of overerfrequency band accumulate protection operates to trip.
10 81O.OF1.Alm Stage 1 of overfrequency protection operates to issue alarm signal.
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14 81O.OF1.Alm_Accu Stage 1 of overfrequency band accumulate protection operates to issue alarm signal.
Table 3.12-3 Output signals of overfrequency protection (e vent recorder)
Tripping reports
5 81O.OF1.Op_Accu Stage 1 of overfrequency band accumulate protection operates to trip.
Start signals
9 81O.St Overfrequency protection starts.
Alarm signals
Stage 1 of overfrequency band accumulate protection operates to issue alarm

14 81O.OF1.Alm_Accu
signal.

15 81O.OF2.Alm_Accu
signal.

16 81O.OF3.Alm_Accu
signal.

17 81O.OF4.Alm_Accu
signal.
Waveform recording
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3 Operation Theory
18 81O.TrigDFR Underfrequency protection operates to trigger waveform recording.
IO events
19 81O.OF1.St Stage 1 of overfrequency protection starts.
23 81O.OF1.St_ Accu Stage 1 of overfrequency band accumulate protection starts.
Table 3.12-4 Output signals of overfrequency protection (measurements)
1 81O.OF1.Dur_Accu The accumulate duration of stage 1 of overfrequency protection min
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Freq Prot Values
3.12.6 Settings
Table 3.12-5 Settings list of overfrequency protection

1 81O.En 1
1: enable overfrequency protection.
Frequency setting of stage 1 of overfrequency

2 81O.OF1.f_Set 50.00~70.00 0.01 Hz
protection.
Time delay of stage 1 of overfrequency band

3 81O.OF1.t_ Accu 0.10~300.00 0.01 min
Time delay of stage 1 of overfrequency

4 81O.OF1.t_Op 0.10~300.00 0.01 s
protection.

5 81O.OF1.OutMap 0~3FFFFFFF
overfrequency protection.

6 81O.OF2.f_Set 50.00~70.00 0.01 Hz
protection.

7 81O.OF2.t_ Accu 0.10~300.00 0.01 min
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8 81O.OF2.t_Op 0.10~300.00 0.01 s
protection.


10 81O.OF3.f_Set 50.00~70.00 0.01 Hz
protection.

11 81O.OF3.t_ Accu 0.10~300.00 0.01 min

12 81O.OF3.t_Op 0.10~300.00 0.01 s
protection.


14 81O.OF4.f_Set 50.00~70.00 0.01 Hz
protection.

15 81O.OF4.t_ Accu 0.10~300.00 0.01 min

16 81O.OF4.t_Op 0.10~300.00 0.01 s
protection.
Tripping logic s etting of stage 4 of


0: disable
18 81O.OF1.En_Alm 1 overfrequency protection operates to issue
1: enable
alarm signal.

19 81O.OF1.En_Trp 1
1: enable overfrequency protection operates to trip.

0: disable
20 81O.OF1.En_Alm_Accu 1 overfrequency band accumulate protection
1: enable
operates to issue alarm signal.

0: disable
21 81O.OF1.En_Trp_Accu 1 overfrequency band accumulate protection
1: enable
protection operates to trip.

0: disable
1: enable
alarm signal.

23 81O.OF2.En_Trp 1

0: disable
1: enable
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0: disable
1: enable
operates to trip.

0: disable
1: enable
alarm signal.

27 81O.OF3.En_Trp 1

0: disable
1: enable

0: disable
1: enable

0: disable
1: enable
alarm signal.

31 81O.OF4.En_Trp 1

0: disable
1: enable

0: disable
1: enable
Access path: Settings-> Prot Settings -> Over Freq Settings
3.13 Underfrequency Protection (81U)
3.13.1 Application
When the power system requires more active power or the speed regulating system of generator
is in abnormal operation, the frequency of the power system will decline, so underfrequency
protection can be used to detect the above abnormal low-frequency conditions. If the frequency is
lower than the underfrequency protection setting, underfrequency protection will operate to issue
alarm signal or trip with a time delay.
Steam-turbine generator is able to withstand the frequency shifting, but this will leads to the
vibration of the turbine blade which will eventually cause the metal fatigue damage of the blade.
This kind of damage is a process of accumulation and it is irreversible, therefore, when the
frequency protection is applied for steam-turbine generator, a feature of frequency accumulation is
Date: 2015-07-29
3 Operation Theory
required.
Underfrequency protection has following functions:
 Four stages of underfrequency protection (with respective frequency setting, time delay and
logic setting) are available. Each stage can be configured to issue alarm signal or trip.
 Four stages of underfrequency band accumulate protection are available and each stage has
respective frequency upper limit setting, lower limit frequency setting, accumulated time
setting and logic setting. Each stage can be configured to issue alarm signal or trip.
3.13.3.1 Overview
When the system frequency is smaller than the underfrequency setting, the protection picks up,
after a time delay determined by the time delay setting, the underfrequency protection will operate
to issue alarm signal or trip. If the frequency accumulation function is enabled, i.e. the logic setting
[81U.UFx.En_Alm_Accu] or [81U.UFx.En_Trp_Accu] (x=1~4) is set as “1”, the relay will
accumulate the time that the system frequency falling into the corresponding underfrequency band,
if the accumulated time is larger than the corresponding time delay setting, the underfrequency
band accumulate protection will operate to issue alarm signal or trip.
The positive voltage is used to calculate the system frequency, after a filtering process, the
measurement of system frequency will not be affected by the harmonic component.
 Operation criterion of underfrequency protection
f <[81U.UFx.f_Set] Equation 3.13-1
Where:
[81U.UFx.f_Set] is the frequency setting of stage x (x=1~4) of underfrequency protection.
 Operation criterion of underfrequency band accumulate protection
[81U.UFx’.f_Set] < f <[81U.UFx.f_Set] Equation 3.13-2
Where:
[81U.UFx.f_Set] is the upper limit frequency setting of stage x (x=1~4) of underfrequency band
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[81U.UFx’.f_Set] is the lower limit frequency setting of stage x (x=1~4) of underfrequency band
If x=4, [81U.UF x’.f_Set]=0; if x=1~3, x’=x+1.
3.13.4 Logic
For underfrequency protection, when following three conditions are met, the protection is enabled.
(1) Logic setting [81U.En] is set as “1”.
(2) The protection function enabling binary inputs [81U.En1] and [81U.En2] are “1”
(3) The protection function blocking input [81U.Blk] is “0”.
If underfrequency protection is disabled, all the related output signals will be reset. If no external
input is configured to [81U.En1] ([81U.En2]), the default initial value of [81U.En1] ([81U.En2]) is “1”;
if no external input is configured to [81U.Blk], the default initial value of [81U.Blk] is “0”.
EN [81U.En]
SIG [Flg_52a] &
SIG [81U.Flg_OnLoad]
&
& [81U.UFx.t_Op] 0s
EN [81U.UFx.En_Alm] & [81U.UFx.Alm]
SIG f < [81U.UFx.f_Set]
& [81U.St]
& [81U.UFx.t_Op] 0s
EN [81U.UFx.En_Trp] &
[81U.UFx.Op]
SIG f < [81U.UFx.f_Set]
SIG [81U.En1] &

SIG [81U.En2]
SIG [81U.Blk]
0 500ms
SIG 81U.FD
Figure 3.13-1 Logic diagram of stage x of underfrequency protection (x=1~4)
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3 Operation Theory
EN [81U.En]
SIG [Flg_52a] &
&
&
& [81U.UF1.t_Accu] 0s
EN [81U.UF1.En_Alm_Accu] [81U.UF1.Alm_Accu]
SIG [81U.UF2.f_Set]<f< [81U.UF1.f_Set]
& [81U.St]
EN [81U.UF1.En_Trp_Accu] &
[81U.UF1.Op_Accu]
SIG [81U.UF2.f_Set]<f< [81U.UF1.f_Set]
SIG [81U.En1] &

SIG [81U.En2]
SIG [81U.Blk]
0 500ms
SIG 81U.FD
The stage 2 and stage 3 of underfrequency band accumulate protection are similar to stage 1 of
underfrequency band accumulate protection.
EN [81U.En]
SIG [Flg_52a] &
&
EN [81U.UF4.En_Alm_Accu] & [81U.UF4.Alm_Accu]
SIG 0<f< [81U.UF4.f_Set]
& [81U.St]
EN [81U.UF4.En_Trp_Accu] &
[81U.UF4.Op_Accu]
SIG 0<f< [81U.UF4.f_Set]
SIG [81U.En1] &

SIG [81U.En2]
SIG [81U.Blk]
0 500ms
SIG 81U.FD
Where:
81U.FD is the internal signal to indicate that underfrequency protection picks up (the fault detector
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81U
f 81U.St
81U.En1 81U.UF1.Op
81U.En2 81U.UF2.Op
81U.Blk 81U.UF3.Op
81U.Flg_OnLoad 81U.UF4.Op
Flg_52a 81U.UF1.Op_Accu
81U.UF2.Op_Accu
81U.UF3.Op_Accu
81U.UF4.Op_Accu
81U.UF1.Alm
81U.UF2.Alm
81U.UF3.Alm
81U.UF4.Alm
81U.UF1.Alm_Accu
81U.UF2.Alm_Accu
81U.UF3.Alm_Accu
81U.UF4.Alm_Accu
Figure 3.13-4 Function block diagram of underfrequency protection
Table 3.13-1 Input signals of underfrequency protection

2 81U.Flg_Onload The signal indicating that current is detected.
4 81U.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
5 81U.En2 as function enabling binary inputs, logic links, etc.
6 81U.Blk Protection function blocking input, such as function blocking binary input.
Table 3.13-2 Output signals of underfrequency protection

1 81U.St Underfrequency protection starts.
2 81U.UF1.Op Stage 1 of underfrequency protection operates to trip.
6 81U.UF1.Op_Accu Stage 1 of underfrequency band accumulate protection operates to trip.
10 81U.UF1.Alm Stage 1 of underfrequency protection operates to issue alarm signal.
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Stage 1 of underfrequency band accumulate protection operates to issue alarm
14 81U.UF1.Alm_Accu
signal.
15 81U.UF2.Alm_Accu
signal.
16 81U.UF3.Alm_Accu
signal.
17 81U.UF4.Alm_Accu
signal.
Table 3.13-3 Output signals of underfrequency protection (e vent recorder)
Tripping reports
Start signals
9 81U.St Underfrequency protection starts.
Alarm signals

14 81U.UF1.Alm_Accu
signal.

15 81U.UF2.Alm_Accu
signal.

16 81U.UF3.Alm_Accu
signal.
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17 81U.UF4.Alm_Accu
signal.
Waveform recording
18 81U.TrigDFR Underfrequency protection operates to trigger waveform recording.
IO events
19 81U.UF1.St Stage 1 of underfrequency protection starts.
23 81U.UF1.St_Accu Stage 1 of underfrequency band accumulate protection starts.
Table 3.13-4 Output signals of underfrequency protection (measurements)
1 81U.UF1.Dur_Accu The accumulate duration of stage 1 of underfrequency protection min
Access Path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Freq Prot Values
3.13.6 Settings
Table 3.13-5 Settings list of underfrequency protection

1 81U.En 1
1: enable underfrequency protection.
Frequency setting of stage 1 of underfrequency

2 81U.UF1.f_Set 45.00~61.00 0.01 Hz
protection.
Time delay of stage 1 of underfrequency band

3 81U.UF1.t_Accu 0.10~300.00 0.01 min
Time delay of stage 1 of underfrequency

4 81U.UF1.t_Op 0.10~300.00 0.01 s
protection.

5 81U.UF1.OutMap 0~3FFFFFFF
underfrequency protection.
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6 81U.UF2.f_Set 45.00~61.00 0.01 Hz
protection.

7 81U.UF2.t_Accu 0.10~300.00 0.01 min

8 81U.UF2.t_Op 0.10~300.00 0.01 s
protection.


10 81U.UF3.f_Set 45.00~61.00 0.01 Hz
protection.

11 81U.UF3.t_Accu 0.10~300.00 0.01 min

12 81U.UF3.t_Op 0.10~300.00 0.01 s
protection.


14 81U.UF4.f_Set 45.00~61.00 0.01 Hz
protection.

15 81U.UF4.t_Accu 0.10~300.00 0.01 min

16 81U.UF4.t_Op 0.10~300.00 0.01 s
protection.


0: disable
18 81U.UF1.En_Alm 1 underfrequency protection operates to issue
1: enable
alarm signal.

19 81U.UF1.En_Trp 1
1: enable underfrequency protection operates to trip.

0: disable
20 81U.UF1.En_Alm_Accu 1 underfrequency band accumulate protection
1: enable

0: disable
21 81U.UF1.En_Trp_Accu 1 underfrequency band accumulate protection
1: enable
operates to trip.

0: disable
1: enable
alarm signal.
23 81U.UF2.En_Trp 0: disable 1 Logic setting of enabling/disabling stage 2 of
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0: disable
1: enable

0: disable
1: enable
operates to trip.

0: disable
1: enable
alarm signal.

27 81U.UF3.En_Trp 1

0: disable
1: enable

0: disable
1: enable
operates to trip.

0: disable
1: enable
alarm signal.

31 81U.UF4.En_Trp 1

0: disable
1: enable

0: disable
1: enable
operates to trip.
Access path: Settings-> Prot Settings -> Under Freq Settings
3.14 Rate-of-Frequency-Change Protection (81R)
3.14.1 Application
The rate-of-frequency-change protection is applied to quickly detect the frequency change of
system. If system frequency has a decreasing trend or an increasing trend, the protection can
detect it and operate to issue an alarm signal or a trip command. When active power demand and
active power supply can not keep the balance, the system frequency will change. The system
frequency decrease demands for loss of load of system, and the system frequency increase
demands for reduction of output and even generator shutdown.
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3.14.2 Function
Rate-of-frequency-change protection has following functions:
 Four stages of rate-of-frequency-change protection are available with separate

rate-of-frequency-change setting, time delay and logic setting.
 Each stage can be configured as frequency increase protection or decrease protection.
 Low voltage blocking function is available.
 A pick-up frequency setting is available.
3.14.3.1 Overview
The relay consistently monitoring the rate-of-frequency-change, if the rate-of-change for frequency
increase or decrease is greater than the pre-configured setting, a timer has been started, if the
duration exceeds the set time delay, the protection will operate to alarm or trip.
3.14.3.2 Measurement
The relay will use positive voltage to calculate the frequency value, the average value of the
frequency can be got via frequency smoothing calculation. The time period is configurable (the
default value is 5 cycles), within which the frequency change can be got. The ratio between the
frequency change and the time period is the corresponding rate-of-frequency-change. It can be a
positive value or a negative one.
To prevent the mal-operation of the protection, the low voltage blocking function is available for
rate-of-frequency-change protection, the low voltage blocking can be enabled or disabled, and the
low voltage blocking setting is settable. If the positive-sequence voltage is lower than the low
voltage blocking setting, the system frequency can not be accurately calculated from the voltage
signal, so the rate-of-frequency-change protection will be disabled automatically.
3.14.3.3 Frequency Increase or Decrease
Each stage of rate-of-frequency-change protection can be configured as frequency increase

protection or decrease protection. Each stage has independent logic setting and pick-up frequency
setting. Only if system frequency is lower than the corresponding pick-up frequency setting, the
stage of rate-of-frequency-decrease protection is enabled automatically. Only if system frequency
is higher than the corresponding pick-up frequency setting, the stage of rate-of-frequency-increase
protection is enabled automatically.
3.14.3.4 Criteria
Four stages of rate-of-frequency-change protection are available, the protection can operate to
alarm or trip.
 Operation criterion for rate-of-frequency-increase protection
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df
 [81R.RFx.df/dt_Set] Equation 3.14-1
dt
Where:
df
is the calculated rate-of-frequency-change.
dt
[81R.RFx.df/dt_Set] is the rate-of-frequency-change setting of stage x (x=1~4).
 Operation criterion for rate-of-frequency-decrease protection
df
 -[81R.RFx.df/dt_Set] Equation 3.14-2
dt
Where:
df
is the calculated rate-of-frequency-change.
dt
[81R.RFx.df/dt_Set] is the rate-of-frequency-change setting of stage x (x=1~4).
3.14.4 Logic
For rate-of-frequency-change protection, when following three conditions are met, the
rate-of-frequency-change protection is enabled.
(1) Logic setting [81R.En] is set as “1”.
(2) The protection function enabling inputs [81R.En1], [81R.En2] are “1”.
(3) The protection function blocking input [81R.Blk] is “0”.
If rate-of-frequency-change protection is disabled, all the related output signals will be reset. If no
external input is configured to [81R.En1] ([81R.En2]), the default initial value of [81R.En1]
([81R.En2]) is “1”; if no external input is configured to [81R.Blk], the default initial value of [81R.Blk]
is “0”.
Logics of rate-of-frequency-change protection is shown in following figure (takes the logic scheme
of stage 1 of rate-of-frequency-change protection as an example, the logic scheme of other stages
are the same).
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Set 81R.RF1.En_Alm
Set 81R.En_UV_Blk ≥1
Sig U1 > [81R.U_Set]
Sig f<[81R.RF1.f_Pkp]
&
Sig df/dt<-[81R.RF1.df/dt_Set]
≥1
Set [81R.RF1.Opt_Trend] 0/increase &
1/decrease [81R.RF1.t_Op] 0ms
& [81R.RF1.Alm]
Sig df/dt>[81R.RF1.df/dt_Set]
&
Sig f>[81R.RF1.f_Pkp]
Sig 81R.Flg_Onload & &

[81R.RF1.St]
Sig Flg_52a
[81R.RF1.t_Op] 0ms [81R.RF1.Op]
En 81R.En
SIG 81R.En1 &
SIG 81R.En2
SIG 81R.Blk
Set 81R.RF1.En_Trp
0 500ms
Sig 81R.FD
Figure 3.14-1 Logic diagram of rate-of-frequency-change protection
Where:
df
is the calculated system rate-of-frequency-change.
dt
81R.FD is the operation flag of the fault detector of rate-of-frequency-change protection (the fault
detector of fault detector DSP module).
3.14.5 Input and Output
81R
f 81R.St
81R.U3P 81R.RF1.Op
81R.En1 81R.RF2.Op
81R.En2 81R.RF3.Op
81R.Blk 81R.RF4.Op
Flg_52a 81R.RF1.Alm
81R.Flg_Onload 81R.RF2.Alm
81R.RF3.Alm
81R.RF4.Alm
Figure 3.14-2 Function block diagram of rate-of-frequency-change protection
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3 Operation Theory
Table 3.14-1 Input signals of rate-of-frequency-change protection

1 81R.U3P Three-phase voltage input.
4 81R.Flg_Onload The signal indicating that the load current is detected.
5 81R.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings,
6 81R.En2 such as function enabling binary inputs, logic links, etc.
7 81R.Blk Protection function blocking input, such as function blocking binary input.
Table 3.14-2 Output signals of rate-of-frequency-change protection

1 81R.St Rate-of-frequency-change protection starts.
2 81R.RF1.Op Stage 1 of rate-of-frequency-change protection operates to trip.
6 81R.RF1.Alm Stage 1 of rate-of-frequency-change protection operates to alarm.
Table 3.14-3 Output signals of rate-of-frequency-change protection (e vent recorder)
Tripping reports
Start signals
5 81R.St Rate-of-frequency-change protection starts.
Alarm signals
Waveform recording
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10 81R.TrigDFR Rate-of-frequency-change protection operates to trigger waveform recording.
11 81R.RF1.St Stage 1 of rate-of-frequency-change protection starts.
13 81R.RF3.St Stage 3 of rate-of-frequency-change protection starts .
3.14.6 Settings
Table 3.14-4 Settings list of rate-of-frequency-change protection

1 81R.En 1
1: enable rate-of-frequency-change protection.
The voltage setting for low voltage blocking element
2 81R.U_Set 6.00~100.00 0.01 V
of rate-of-frequency-change protection.
The pick-up frequency setting for stage 1 of
3 81R.RF1.f_Pkp 45.00~65.00 0.01 Hz
rate-of-frequency-change protection.
The frequency change trend for stage 1 of
4 81R.RF1.Opt_Trend 0, 1 1
0: Increase
1: Decrease
The rate-of-frequency-change setting of stage 1 of
5 81R.RF1.df/dt_Set 0.10~20 0.01 Hz/s
Time delay of stage 1 of rate-of-frequency-change
6 81R.RF1.t_Op 0.10~100.00 0.01 s
protection.
7 81R.RF1.OutMap 0~3xFFFFFFF
8 81R.RF2.f_Pkp 45.00~65.00 0.01 Hz
0: Increase
1: Decrease
10 81R.RF2.df/dt_Set 0.10~20 0.01 Hz/s
11 81R.RF2.t_Op 0.10~100.00 0.01 s
protection.
13 81R.RF3.f_Pkp 45.00~65.00 0.01 Hz
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0: Increase
1: Decrease
15 81R.RF3.df/dt_Set 0.10~20 0.01 Hz/s
16 81R.RF3.t_Op 0.10~100.00 0.01 s
protection.
18 81R.RF4.f_Pkp 45.00~65.00 0.01 Hz
0: Increase
1: Decrease
20 81R.RF4.df/dt_Set 0.10~20 0.01 Hz/s
21 81R.RF4.t_Op 0.10~100.00 0.01 s
protection.
0: disable
23 81R.RF1.En_Alm 1 rate-of-frequency-change protection operates to
1: enable
alarm.
0: disable
24 81R.RF1.En_Trp 1 rate-of-frequency-change protection operates to
1: enable
trip.
0: disable
1: enable
alarm.
0: disable
1: enable
trip.
0: disable
1: enable
alarm.
0: disable
1: enable
trip.
0: disable
1: enable
alarm.
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0: disable
1: enable
trip.
Logic setting of enabling/disabling low voltage
0: disable
31 81R.En_UV_Blk 1 blocking function for rate-of-frequency-change
1: enable
protection.
Access path:
Settings-> Prot Settings -> FreqRateChg Settings
3.15 Thermal Overload Protection (49)
NOTICE!
In Section 3.15, the prefix “Y” in settings (such as [Y.49.Ib_Set]) and input/output
signals (such as [Y.49.Op]) can be Tr_HVS and Tr_MVS. Details of the prefix are as:
Tr_HVS.49 Corresponds to thermal overload protection of main transformer high voltage side.
Tr_MVS.49 Corresponds to thermal overload protection of main transformer medium voltage side.
3.15.1 Application
Thermal overload protection can reflect the average heating condition of transformer winding, and
it can prevent the transformer from overheating caused by overload and asymmetric overload. The
thermal overload model is based on IEC 60255-8 standard, transformer load current is used to
calculate the thermal accumulation.
3.15.2 Function
Thermal overload protection has following functions:
 Thermal overload protection can operate to trip or alarm (with independent setting and logic
setting).
 One binary input signal can be used to clear the thermal accumulation.
 The thermal accumulation can be displayed according to each phase.
3.15.3 Operation Principle
3.15.3.1 Thermal Overload Element
Thermal overload protection reflects the overheating condition of transformer three-phase winding,
the thermal accumulation meets the demand of IEC 60255-8 standard. For any phase of
transformer winding, the operation time meets the following equation:
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2 2
I eq  I p
t    ln Equation 3.15-1
2 2
I eq  ( k  I B )
Where:
t is the operation time of thermal overload protection.
 is the thermal overload time constant, i.e. the setting [Y.49.Tau].
IB is the base current , i.e. the setting [Y.49.Ib_Set].
I eq is the root-mean-square value of equivalent current, it corresponds to transformer
three-phase currrent.
I p is the steady-state current before the thermal overload element pick-up, for cooling start
characteristic, I p is zero.
ln is natural logarithm.
k is thermal accumulation coefficient, corresponds to the setting [Y.49.K_Alm] or [Y.49.K_Trp].
If the thermal accumulation exceeds 100%, the device will operate to alarm or trip according to the
value of corresponding logic settings.
If the current disappears or is lower than the thermal overload base current, the heat dissipation
starts, the thermal accumulation will decline. One binary input signal can be used to clear the
thermal accumulation.
3.15.4 Logic
For thermal overload protection, when following three conditions are met, the thermal overload
protection is enabled.
(1) Logic setting [Y.49.En] is set as “1”.
(2) The protection function enabling inputs [Y.49.En1], [Y.49.En2] are “1”.
(3) The protection function blocking input [Y.49.Blk] is “0”.
If thermal overload protection is disabled, all the related output signals will be reset. If no external
input is configured to [Y.49.En1] ([Y.49.En2]), the default initial value of [Y.49.En1] ([Y.49.En2]) is
“1”; if no external input is configured to [Y.49.Blk], the default initial value of [Y.49.Blk] is “0”.
Logic of thermal overload protection is shown in following figure.
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3 Operation Theory
EN [Y.49.En]
SIG [Y.49.En1] &
SIG [Y.49.En2]
SIG [Y.49.Blk]
&
IDMT [Y.49.Alm]
EN [Y.49.En_Alm]
SIG I>[Y.49.Ib_Set]
EN [Y.49.En]
SIG [Y.49.En1] &
[Y.49.St]
SIG [Y.49.En2] &
SIG [Y.49.Blk] IDMT [Y.49.Op]
EN [Y.49.En_Trp]
SIG I>[Y.49.Ib_Set]
0ms 500ms
SIG Y.49.FD
Figure 3.15-1 Logic diagram of thermal overload protection
Where:
Y.49.FD is the operation flag of the fault detector of thermal overload protection (the fault detector
49
Y.49.I3P Y.49.St
Y.49.Clear Y.49.Op
Y.49.En1 Y.49.Alm
Y.49.En2
Y.49.Blk
Figure 3.15-2 Function block diagram of thermal overload protection
Table 3.15-1 Input signals of thermal overload protection

1 Y.49.I3P Three-phase current input.
2 Y.49.Clear Input signal to clear the thermal accumulation.
3 Y.49.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
4 Y.49.En2 as function enabling binary inputs, logic links, etc.
5 Y.49.Blk Protection function blocking input, such as function blocking binary input.
Table 3.15-2 Output signals of thermal overload protection

1 Y.49.St Thermal overload protection starts.
2 Y.49.Op Thermal overload protection operates to trip.
3 Y.49.Alm Thermal overload protection operates to alarm.
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3 Operation Theory
Table 3.15-3 Output signals of thermal overload protection (e vent recorder)
Tripping report
1 Y.49.Op Thermal overload protection operates to trip.
Start signal
2 Y.49.St Thermal overload protection starts.
Alarm signal
3 Y.49.Alm Thermal overload protection operates to alarm.
Waveform recording
4 Y.49.TrigDFR Thermal overload protection operates to trigger waveform recording.
Table 3.15-4 Output signals of thermal overload protection (measurements)
1 Y.49.Accu_ A Phase-A thermal accumulation for thermal overload protection %
2 Y.49.Accu_B Phase-B thermal accumulation for thermal overload protection %
3 Y.49.Accu_C Phase-C thermal accumulation for thermal overload protection %
Access path:
Main menu -> Measurements -> Measurements2-> Prot Status->Tr HVS PPF Prot Values
Main menu -> Measurements -> Measurements2-> Prot Status->Tr MVS PPF Prot Values
3.15.6 Settings
Table 3.15-5 Settings list of thermal overload protection

Logic setting of enabling/disabling thermal
1 Y.49.En 0/1
overload protection.
Base current setting of thermal overload
2 Y.49.Ib_Set 0.05-20In 0.01 A
protection.
Thermal overload time constant of thermal
3 Y.49.Tau 0.1-100.00 0.01 Min
overload protection.
Thermal accumulation coefficient for thermal
4 Y.49.K_Trp 1.00-3.00 0.01
overload protection operates to trip.
Thermal accumulation coefficient for thermal
5 Y.49.K_Alm 1.00-3.00 0.01
overload protection operates to alarm .
Tripping logic setting of thermal overload
6 Y.49.OutMap 0~3xFFFFFFF
protection.
Logic setting of enabling/disabling thermal
7 Y.49.En_Trp 0/1 1
overload protection operates to trip.
8 Y.49.En_Alm 0/1 1 Logic setting of enabling/disabling thermal
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3 Operation Theory

overload protection operates to alarm .
Access path:
Settings-> Prot Settings -> TrHVS ThOvLd Settings
Settings-> Prot Settings -> TrMVS ThOvLd Settings
3.16 Impedance Protection (21)
NOTICE!
In Section 3.16, the prefix “Y” in settings (such as [Y.21M1.I_PSBR]) and input/output
signals (such as [Y.21M1.ZP.Op]) can be Tr_HVS and Tr_MVS. Details of the prefix are
as:
Tr_HVS.21M Corresponds to impedance protection of main transformer high voltage side.
Tr_MVS.21 M Corresponds to impedance protection of main transformer medium voltage side.
3.16.1 Application
When phase overcurrent protection and ground overcurrent protection cannot meet the sensitivity
requirement of transformer backup protection, impedance protection can be configured. The
operation mode of power system has little effect on impedance protection, so impedance
protection can coordinate with protections of adjacent equipment easily.
 Two stage phase-to-phase impedance protection elements with respective impedance setting,
time delay setting and logic setting.
 Two stage phase-to-earth impedance protection elements with respective impedance setting,
time delay setting and logic setting.
 Power swing blocking releasing function.
3.16.3.1 Overview
Impedance protection includes phase-to-phase impedance protection and phase-to-earth

protection. Positive polarity of CT is at busbar side, and direction settings should be set according
to the principle.
The fault detector of impedance protection includes the DPFC phase-to-phase current fault
detector and the negative-sequence current fault detector. The fault detector output signal will last
for 500ms after the corresponding fault detector picks up, if phase-to-phase or phase-to-earth
impedance relay operates within the 500ms, the fault detector output signal will be kept.
 DPFC phase-to-phase current fault detector
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3 Operation Theory
Criteria of this fault detector:
 I  1 . 25  I t  I th Equation 3.16-1
Where:
 I t is the floating threshold value which will arise automatically and gradually according to
increasing of the current changing. The coefficient takes 1.25 in order to ensure the threshold
current is always slightly larger than the unbalance output, so the protection will not mal-operate
under power swing and frequency shifting condition.
I is the deviation value of phase-to-phase current.
I th is the fixed threshold 0.2In and it does not need to be set.
 Negative-sequence current fault detector
Criteria of this fault detector:
I 2  0.2In Equation 3.16-2
Where:
I 2 is the negative-sequence current of one side.
In is the secondary rated current of CT.
3.16.3.3 Direction Element
If VT and CT are connected as following figure, i.e. the positive polarity of CT is at busbar side,
points to the protected object, then the setting [Y.21Mx.ZP.Opt_Dir] and [Y.21Mx.ZG.Opt_Dir]
should be set as “1”. Otherwise [Y.21Mx.ZP.Opt_Dir] and [Y.21Mx.ZG.Opt_Dir] should be set as “0”.
Symbol “ ” represents the positive polarity of current transformer.
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3 Operation Theory
Reverse Forward
CT
Protected
Object
VT
Direction
Element
Figure 3.16-1 Connection of VT and CT of direction element
3.16.3.4 Phase-to-Phase Impedance Protection
Following figure shows operating characteristic of phase-to-phase impedance relay, the setting
[Y.21Mx.RCA] (x=1 or 2) is impedance characteristic angle (i.e.  m shown in the following figure,
it is also called reach angle). In the figure, if the setting [Y.21Mx.ZP.Opt_Dir] is “1”, Zn is the
reverse impedance setting [Y.21Mx.ZP.Z_Rev] and Zp is the forward impedance setting
[Y.21Mx.ZP.Z_Fwd]. If the setting [Y.21Mx.ZP.Opt_Dir] is “0”, Zn is the forward impedance setting
[Y.21Mx.ZP.Z_Fwd] and Zp is the reverse impedance setting [Y.21Mx.ZP.Z_Rev].
jx
IZp
U  IZp
U
m
R
IZn U  IZn
Figure 3.16-2 Operating characteristic of phase-to-phase impedance relay
The operation criterion of phase-to-phase impedance relay is as follows.

 
 (U  I Z P ) 
90  Arg  
 270 Equation 3.16-3
(U  I Z n )
Where:
U is phase-to-phase voltage vector.
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3 Operation Theory
I is phase-to-phase current vector.
NOTICE!
When [Y.21Mx.En_VTS_Blk] is “1”, if VT circuit failure signal [Y.Alm_VTS] is issued,

phase-to-phase impedance protection will be BLOCKED.
3.16.3.5 Phase-to-Earth Impedance Protection
Following figure shows operating characteristic of phase-to-earth impedance relay, the setting
[Y.21Mx.RCA] (x=1 or 2) is impedance characteristic angle (i.e.  m shown in the following figure,
it is also called reach angle). In the figure, If the setting [Y.21Mx.ZG.Opt_Dir] is “1”, Zn is the
reverse impedance setting [Y.21Mx.ZG.Z_Rev] and ZG is the forward impedance setting
[Y.21Mx.ZG.Z_Fwd]. If the setting [Y.21Mx.ZG.Opt_Dir] is “0”, Zn is the forward impedance setting
[Y.21Mx.ZG.Z_Fwd] and ZG is the reverse impedance setting [Y.21Mx.ZG.Z_Rev].
jx  
(I   k 3I 0 )ZG
  
U  (I   k 3I 0 )ZG
U
m
R
  
 
-(I   k 3 I 0 )Zn U  (I   k 3I 0 )Zn
Figure 3.16-3 Operating characteristic of phase-to-earth impedance relay
The operation criterion of phase-to-earth impedance relay is as follows.
  
U   (I   k  3 I 0 )Z G
90  A rg   
 270 Equation 3.16-4
U   (I   k  3 I 0 )Z n
Where:
U  is phase-to-earth voltage vector.
I  is phase-to-earth current vector.
3 I 0 is residual current vector.
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3 Operation Theory
z 0  z1
k  is the zero-sequence compensated coefficient of stage x of phase-to-earth
3 z1
impedance protection [Y.21Mx.K0], the setting range is 0~2. If the ground impedance points to the
busbar of local side, it takes 0.6 generally; If the ground impedance points to the transformer, it
takes 0~0.1 generally.
NOTICE!
When [Y.21Mx.En_VTS_Blk] is “1”, if VT circuit failure signal [Y.Alm_VTS] is issued,

phase-to-earth impedance protection will be BLOCKED.
3.16.3.6 Power Swing Blocking Releasing (PSBR)
PCS-985TE adopts power swing blocking releasing to avoid mal-operation of impedance

protection due to power swing. The protection is blocked all along under the normal condition and
power swing. Only if fault (internal fault or power swing with internal fault) is detected, power swing
blocking for impedance protection is released by PSBR element.
The logic setting [Y.21Mx.En_PSBR] is used to enable or disable PSBR function. If it is set as “1”,
the PSBR function is enabled. Otherwise, it is disabled.
If the time delay of impedance protection is more than 1.5s, PSBR function is not needed for the
impedance protection.
Power swing blocking for impedance relay will be released if any of the following PSBR elements
operate.
 Fault detector PSBR element (FD PSBR)
 Unsymmetrical fault PSBR element (UF PSBR)
 Symmetrical fault PSBR element (SF PSBR)
1. Fault detector PSBR element
At the moment that any impedance protection fault detector picks up, if positive-sequence
overcurrent element does not operate or the operating duration is less then 10ms, FD PSBR will
operate for 160ms.
Positive-sequence overcurrent element:
I1<[Y.21Mx.I_PSBR] Equation 3.16-5
I1 is positive-sequence current.
[Y.21Mx.I_PSBR] (x=1 or 2) is the current setting of FD PSBR, which is set larger than the
maximum load current of transformer.
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10ms 0
SIG I1>[Y.21Mx.I_PSBR] ≥1
&
0 160ms
SIG I1≤[Y.21Mx.I_PSBR] Flg_Pkp_FDPSBR
SIG Y.21M.FD
Figure 3.16-4 Logic diagram of FD PSBR (takes HV side as an example)
2. Unsymmetrical fault PSBR element
When an internal unsymmetrical fault happens, power swing blocking for impedance relay can be
released by following element:
I0  I2  m  I1 Equation 3.16-6
Where:
“m” is an internal fixed coefficient with a certain margin which can ensure UF PSBR operate during
power swing with internal unsymmetrical fault, while not operate during power swing or power
swing with external fault.
I 1， I 2 ， I 0 are positive-sequence current, negative-sequence current and zero-sequence current
respectively.
3. Symmetrical fault PSBR element
When fault detector operates and after 160ms, or during the power swing, if a three-phase fault
occurs, both of FD PSBR and UF PSBR can not operate to release the impedance protection.
Thus, SF PSBR is provided for this case specially. This detection is based on measuring the
voltage of power swing center:
U OS
 U 1  cos  Equation 3.16-7
Where:
 : the angle between positive-sequence voltage and positive-sequence current
U 1 : the positive-sequence voltage
The criterion of SF PSBR element comprises the following two parts:
1) When  0 . 03 U N
U OS
 0 . 08 U N , the SF PSBR element will operate with a time delay
150ms.
2) When  0 . 1U N
U OS
 0 . 25 U N , the SF PSBR element will operate with a time delay
500ms.
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3.16.4 Logic
The logic of phase-to-earth impedance protection is same to that of phase-to phase impedance
protection, and stage 1 of phase-to-phase impendence protection of HV side is taken as an
example as shown below.
For each stage of impedance protection, if following three conditions are met, the corresponding
stage of impedance protection is enabled.
(1) The logic setting [Tr_HVS.21M1.ZP.En] is set as “1”.
(2) The protection function enabling inputs [Tr_HVS.21M1.En1], [Tr_HVS.21M1.En2] are “1”.
(3) The protection function blocking input [Tr_HVS.21M1.Blk] is “0”.
If impedance protection is disabled, all the related output signals will be reset. If no external input
is configured to [Tr_HVS.21M1.En1] ([Tr_HVS.21M1.En2]), the default initial value of
[Tr_HVS.21M1.En1] ([Tr_HVS.21M1.En2]) is “1”; if no external input is configured to
[Tr_HVS.21M1.Blk], the default initial value of [Tr_HVS.21M1.Blk] is “0”.
EN Flg_Pkp_UFPSBR
≥1
EN Flg_Pkp_SFPSBR Flg_Pkp_PSBR
SIG Flg_Pkp_FDPSBR
SIG Flg_Pkp_PSBR ≥1
SIG [Tr_HVS.21M1.En_PSBR]
SIG Flg_Op_ZP1
&
SET [Tr_HVS.21M1.En]
&
SIG [Tr_HVS.21M1.En1] &
[Tr_HVS.21M1.ZP.St]
SIG [Tr_HVS.21M1.En2]
[Tr_HVS.21M1.ZP.t_Op] 0s [Tr_HVS.21M1.ZP.Op]
SIG [Tr_HVS.21M1.Blk]
SIG [Tr_HVS.21M1.En_VTS_Blk]
0ms 500ms
SIG Tr_HVS.21M1.FD
Figure 3.16-5 Logic diagram of stage 1 of phase-to-phase impedance protection
Where:
Flg_Pkp_UFPSBR is the internal flag indicating that unsymmetrical fault PSBR element picks up.
Flg_Pkp_SFPSBR is the internal flag indicating that symmetrical fault PSBR element picks up.
Flg_Pkp_FDPSBR is the internal flag indicating that fault detector PSBR element picks up.
Tr_HVS.21M1.FD is the operation flag of the fault detector of DPFC phase-to-phase current or
that of negative-sequence current (the fault detector of fault detector DSP module).
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Flg_Pkp_PSBR is the internal flag indicating that power swing blocking releasing element picks
up.
Flg_Op_ZP1 is the internal flag indicating that the operation criterion of stage 1 of phase-to-phase
impedance relay (i.e. Equation 3.16-3) is met.
[Tr_HVS.21M1.En_VTS_Blk] is the setting to enable the impedance protection being blocked by

VT circuit failure.
21
Y.21Mx.U3P Y.21Mx.St
Y.21Mx.I3P Y.21Mx.ZP.Op
Y.21Mx.En1 Y.21Mx.ZG.Op
Y.21Mx.En2
Y.21Mx.Blk
Figure 3.16-6 Function block diagram of impedance protection
x=1 and 2.
Table 3.16-1 Input signals of impedance protection

1 Y.21Mx.I3P Three-phase current data.
2 Y.21Mx.U3P Three-phase voltage data.
3 Y.21Mx.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
4 Y.21Mx.En2 as function enabling binary inputs, logic links, etc.
5 Y.21Mx.Blk Protection function blocking input, such as function blocking binary input.
Table 3.16-2 Output signals of impedance protection

1 Y.21Mx.St Stage x of impedance protection starts (x=1 or 2).
2 Y.21Mx.ZP.Op Stage x of phase-to-phase impedance protection operates (x=1 or 2).
3 Y.21Mx.ZG.Op Stage x of phase-to-earth impedance protection operates (x=1 or 2).
Table 3.16-3 Output signals of impedance protection (e vent recorder)
Tripping reports
1 Y.21M1.ZP.Op Stage 1 of phase-to-phase impedance protection operates.
2 Y.21M2.ZP.Op Stage 2 of phase-to-phase impedance protection operates.
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3 Y.21M1.ZG.Op Stage 1 of phase-to-earth impedance protection operates.
4 Y.21M2.ZG.Op Stage 2 of phase-to-earth impedance protection operates.
Start signals
5 Y.21M1.St Stage 1 of Impedance protection starts.
6 Y.21M2.St Stage 2 of Impedance protection starts.
Waveform recording
7 Y.21M1.TrigDFR Stage 1 of impedance protection operates to trigger waveform recording.
8 Y.21M2.TrigDFR Stage 2 of impedance protection operates to trigger waveform recording.
Table 3.16-4 Output signals of impedance protection (measurements)
1 Y.21Mx.Uab Phase-to-phase voltage of phase AB. V
2 Y.21Mx.Ubc Phase-to-phase voltage of phase BC. V
3 Y.21Mx.Uca Phase-to-phase voltage of phase CA. V
4 Y.21Mx.Iab Phase-to-phase current of phase AB. A
5 Y.21Mx.Ibc Phase-to-phase current of phase BC. A
6 Y.21Mx.Ica Phase-to-phase current of phase CA. A
7 Y.21Mx.Zab Phase-to-phase impedance of phase AB. Ohm
8 Y.21Mx.Zbc Phase-to-phase impedance of phase BC. Ohm
9 Y.21Mx.Zca Phase-to-phase impedance of phase CA. Ohm
10 Y.21Mx.Ua Phase-to-earth voltage of phase A. V
11 Y.21Mx.Ub Phase-to-earth voltage of phase B. V
12 Y.21Mx.Uc Phase-to-earth voltage of phase C. V
13 Y.21Mx.Ia Current of phase A. A
14 Y.21Mx.Ib Current of phase B. A
15 Y.21Mx.Ic Current of phase C. A
16 Y.21Mx.Za Phase-to-earth impedance of phase A. Ohm
17 Y.21Mx.Zb Phase-to-earth impedance of phase B. Ohm
18 Y.21Mx.Zc Phase-to-earth impedance of phase C. Ohm
19 Y.21Mx.Ang(Uab-Iab) Phase angle between phase-AB voltage and phase-AB current deg
20 Y.21Mx.Ang(Ubc-Ibc) Phase angle between phase-BC voltage and phase-BC current deg
21 Y.21Mx.Ang(Uca-Ica) Phase angle between phase-CA voltage and phase-CA current deg
22 Y.21Mx.Ang(Ua-Ia) Phase angle between phase-A voltage and phase-A current deg
23 Y.21Mx.Ang(Ub-Ib) Phase angle between phase-B voltage and phase-B current deg
24 Y.21Mx.Ang(Uc-Ic) Phase angle between phase-C voltage and phase-C current deg
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Access path:
Main menu -> Measurements -> Measurements2-> Prot Values->Tr HVS Impedance Prot Values
Main menu -> Measurements -> Measurements2-> Prot Values->Tr MVS Impedance Prot Values
3.16.6 Settings
Table 3.16-5 Settings list of impedance protection
x=1 or 2;
0: disable Logic setting of enabling/disabling stage x of

1 Y.21Mx.En 1
1: enable impedance protection.
Impedance characteristic angle (also called
2 Y.21Mx.RC A 0~90 0.01 deg reach angle) of stage x of impedance
protection.
Current setting of PSBR element of stage x of
3 Y.21Mx.I_PSBR 0.05~20In 0.01 A
The direction that the stage x of
phase-to-phase impedance point to.
4 Y.21Mx.ZP.Opt_Dir 0,1 1
0: system
1: transformer
Forward impedance setting of stage x of
5 Y.21Mx.ZP.Z_Fwd 0.05~200 0.01 ohm
phase-to-phase impedance protection.
Reverse impedance setting of stage x of
6 Y.21Mx.ZP.Z_Rev 0.05~200 0.01 ohm
Time delay of stage x of phase-to-phase
7 Y.21Mx.ZP.t_Op 0.05~30 0.01 s
Tripping logic setting of stage x of
8 Y.21Mx.ZP.OutMap 0~3FFFFFFF
9 Y.21Mx.ZP.En 1
1: enable phase-to-phase impedance protection.
Zero-sequence compensated coefficient of
10 Y.21Mx.K0 0.000~2.000 0.001 stage x of phase-to-earth impedance
protection.
The direction that the stage x of
phase-to-earth impedance point to.
11 Y.21Mx.ZG.Opt_Dir 0,1 1
0: system
1: transformer
Forward impedance setting of stage x of
12 Y.21Mx.ZG.Z_Fwd 0.05~200 0.01 ohm
phase-to-earth impedance protection
Reverse impedance setting of stage x of
13 Y.21Mx.ZG.Z_Rev 0.05~200 0.01 ohm
phase-to-earth impedance protection
14 Y.21Mx.ZG.t_Op 0.05~30 0.01 s Time delay of stage x of phase-to-earth
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Tripping logic setting of stage x of
15 Y.21Mx.ZG.OutMap 0~3FFFFFFF
phase-to-earth impedance protection.
16 Y.21Mx.ZG.En 1
1: enable phase-to-earth impedance protection.
Logic setting of enabling/disabling VT circuit
0: disable
17 Y.21Mx.En_ VTS_Blk 1 failure block element of stage x of impedance
1: enable
protection.
0: disable Logic setting of enabling/disabling the PSBR
18 Y.21Mx.En_PSBR 1
1: enable element of stage x of impedance protection.
Access path:
Settings-> Prot Settings -> TrHVS Impedance Settings
Settings-> Prot Settings -> TrMVS Impedance Settings
3.17 Breaker Failure Protection (50BF)
NOTICE!
In Section 3.17, the prefix “Y” in settings (such as [Y.50BF.I2_Set]) and input/output
signals (such as [Y.50BF.Op]) can be Tr_HVS and Tr_MVS. Details of the prefix are as:
Tr_HVS.50BF Corresponds to breaker failure protection of main transformer high voltage side.
Tr_MVS.50BF Corresponds to breaker failure protection of main transformer medium voltage side.
3.17.1 Application
Breaker failure protection is applied to monitor the circuit breaker state to ensure that the circuit
breaker is correctly opened. When a tripping command is issued from the protection device, but
the circuit breaker have not been tripped within a certain time delay, so that the fault can not be cut
off, then the circuit breaker of upper stream will be initiated to trip.

Breaker failure protection has following two criteria:
 After the tripping command been issued, the device will check whether the phase current and
negative-sequence current are larger than corresponding setting.
 The protection will use the auxiliary contact of the circuit breaker to judge whether the circuit
breaker is correctly tripped. As under certain circumstances, the criteria of current are not
applicable, like frequency protection, voltage protection and overexcitation protection etc.
The internal logic between above two criteria can be “And” or “Or”. If the setting
[Y.50BF.Opt_Mode] is set as “0”, the internal logic between current criterion and circuit breaker
auxiliary contact criterion is “Or”; if the setting [Y.50BF.Opt_Mode] is set as “1”, the internal logic
between current criterion and circuit breaker auxiliary contact criterion is “And”. Current criterion
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3 Operation Theory
and circuit breaker auxiliary contact criterion can be enabled or disabled separately, so that there
are four possible combinational logics for breaker failure protection:
1) Current criterion “And” circuit breaker auxiliary contact criterion;
2) Current criterion “or” circuit breaker auxiliary contact criterion;
3) Current criterion (circuit breaker auxiliary contact criterion is disabled);
4) Circuit breaker auxiliary contact criterion (current criterion is disabled);
3.17.3.1 Overview
The breaker failure protection has two independent tripping stages and is controlled by the input
signal [Y.50BF.Init], which can be an internal protection tripping signal or an external protection
operating binary input.
3.17.3.2 Current Criteria
Current criteria include phase current criterion and negative-sequence current criterion. If any
current criterion is satisfied, current element of breaker failure protection picks up.
1) Phase current criterion:
I  _ max >[Y.50BF.Ip_Set] Equation 3.17-1
Where:
I  _ max is the maximum value of three-phase current.
[Y.50BF.Ip_Set] is the phase current setting of breaker failure protection.
2) Negative-sequence current criterion:
I2> [Y.50BF.I2_Set] Equation 3.17-2
Where:
I2 is the calculated negative-sequence current.
[Y.50BF.I2_Set] is negative-sequence current setting of breaker failure protection.
3) Residual current criterion:
3I0> [Y.50BF.3I0_Set] Equation 3.17-3
Where:
3I0 is the calculated residual current.
[Y.50BF.3I0_Set] is residual current setting of breaker failure protection.
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3.17.4 Logic
For breaker failure protection, when following three conditions are met, the breaker failure
(1) Logic setting [Y.50BF.En] is set as “1”.
(2) The protection function enabling inputs [Y.50BF.En1], [Y.50BF.En2] are “1”.
(3) The protection function blocking input [Y.50BF.Blk] is “0”.
If breaker failure protection is disabled, all the related output signals will be reset. If no exte rnal
input is configured to [Y.50BF.En1] ([Y.50BF.En2]), the default initial value of [Y.50BF.En1]
([Y.50BF.En2]) is “1”; if no external input is configured to [Y.50BF.Blk], the default initial value of
[Y.50BF.Blk] is “0”.
Logics of breaker failure protection (with two time delays) is shown in following figure.
Set [Y.50BF.En_Ip] &
Sig IΦ_max>[Y.50BF.Ip_set]
Set [Y.50BF.En_I2] & 0 A OR B

A
Sig I2>[Y.50BF.I2_Set]
1 A AND B
Set [Y.50BF.En_3I0] & B
Sig 3I0>[Y.50BF.3I0_Set]
Sig [BI_52b]
OR/AND
&
Set [Y.50BF.Opt_Mode] [Y.50BF.St]
[Y.50BF.t1_Op] 0ms
En [Y.50BF.En] [Y.50BF.Op_t1]
&
SIG [Y.50BF.En1] [Y.50BF.t2_Op] 0ms
[Y.50BF.Op_t2]
SIG [Y.50BF.En2]
SIG [Y.50BF.Blk]
Sig [Y.50BF.Init]
0ms 500ms
Sig Y.50BF.FD
Figure 3.17-1 Logic diagram of breaker failure protection
Where:
[BI_52b] is the normally closed auxiliary contact of the circuit breaker.
I2 is the negative-sequence current.
3I0 is the calculated residual current.
50BF.FD is the operation flag of the fault detector of breaker failure protection (the fault detector of
fault detector DSP module).
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3 Operation Theory
50BF
Y.50BF.I3P Y.50BF.St
Y.50BF.Init Y.50BF.Op_t1
Y.50BF.En1 Y.50BF.Op_t2
Y.50BF.En2
Y.50BF.Blk
BI_52b
Figure 3.17-2 Function block diagram of breaker failure protection
Table 3.17-1 Input signals of breaker failure protection

1 Y.50BF.I3P Three-phase current input.
2 Y.50BF.Init Input signal of initiating breaker failure protection.
3 Y.50BF.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
4 Y.50BF.En2 as function enabling binary inputs, logic links, etc.
5 Y.50BF.Blk Protection function blocking input, such as function blocking binary input.
6 BI_52b The normally closed auxiliary contact of the circuit breaker.
Table 3.17-2 Output signals of breaker failure protection

1 Y.50BF.St Breaker failure protection starts.
2 Y.50BF.Op_t1 Breaker failure protection with time delay 1 operates.
Table 3.17-3 Output signals of breaker failure protection (event recorder)
Tripping reports
Start signals
3 Y.50BF.St Breaker failure protection starts.
Waveform recording
4 Y.50BF.TrigDFR Breaker failure protection operates to trigger waveform recording.
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3.17.6 Settings
Table 3.17-4 Settings list of breaker failure protection

0: disable Logic setting of enabling/disabling breaker failure
1 Y.50BF.En 1
1: enable protection.
Current setting of phase current criterion of breaker
2 Y.50BF.Ip_Set 0.05~10.00In 0.01 A
failure protection.
3 Y.50BF.I2_Set 0.05~4.00In 0.01 A
criterion of breaker failure protection.
Residual current setting of residual current criterion
4 Y.50BF.3I0_Set 0.05~4.00In 0.01 A
of breaker failure protection.
5 Y.50BF.t1_Op 0~10 0.01 s Time delay 1 of breaker failure protection.
Tripping logic setting of breaker failure protection
6 Y.50BF.OutMap_t1 0~3FFFFFFF
with time delay 1.
7 Y.50BF.t2_Op 0~10 0.01 s Time delay 2 of breaker failure protection.
Tripping logic setting of breaker failure protection
8 Y.50BF.OutMap_t2 0~3FFFFFFF 0.01
with time delay 2.
0: disable
9 Y.50BF.En_I2 negative-sequence current criterion of breaker
1: enable
failure protection.
0: disable Logic setting of enabling/disabling residual current
10 Y.50BF.En_3I0
1: enable criterion of breaker failure protection.
0: disable Logic setting of enabling/disabling phase current
11 Y.50BF.En_Ip
1: enable criterion of breaker failure protection.
Logic setting of enabling/disabling circuit breaker
0: disable
12 Y.50BF.En_CB_Ctrl auxiliary contact criterion of breaker failure
1: enable
protection.
The setting to select the internal logic between
0: Or
13 Y.50BF.Opt_ Mode current criterion and circuit breaker auxiliary
1: And
contact criterion.
Access path:
Settings-> Prot Settings -> TrHVS CBProt Settings
Settings-> Prot Settings -> TrMVS CBProt Settings
3.18 Pole Disagreement Protection (62PD)
NOTICE!
In Section 3.18, the prefix “Y” in settings (such as [Y.62PD.I2_Set]) and input/output
signals (such as [Y.62PD.Op]) can be Tr_HVS and Tr_MVS. Details of the prefix are as:
Tr_HVS.62PD Corresponds to pole disagreement protection of main transformer high voltage side.
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Tr_MVS.62PD Corresponds to pole disagreement protection of main transformer medium voltage side.
3.18.1 Application
If the voltage level of some side of transformer is high, usually phase -segregated circuit breaker is
equipped. If three-phase can not closing or tripping simultaneously due to mal-operation or
mechanical reason, or some phase trip suddenly (mal-trip) during normal operation, all of these
will lead to three-phase unbalance of the system and damage of power equipment. So that if a
pole disagreement fault is detected, after a settable time delay, pole disagreement protection will
issue a trip command to trip three-phase circuit breaker.
3.18.2 Function
Pole disagreement protection includes initiation condition and current criteria:
 Pole disagreement position input signal [Y.62PD.In_PD_CB] is used to initiate pole

disagreement protection.
 There are two current criteria for pole disagreement protection: residual current criterion and
negative-sequence current criterion. The two current criteria can be enabled or disabled
independently.
3.18.3.1 Overview
The device will detect the pole disagreement position input signal [Y.62PD.In_PD_CB], if the input
signal is “1”, pole disagreement protection is initiated. If the pole disagreement position input
signal is “1” for a long time, pole disagreement position contact abnormality alarm will be issued.
If any current criterion is enabled, the protection will also detect whether the residual current or
negative-sequence current is larger than the corresponding current setting.
Current criteria include residual current criterion and negative-sequence current criterion. If any
current criterion is met, current element of pole disagreement protection will pick up.
3I0 >[Y.62PD.3I0_Set] Equation 3.18-1
Where:
3I0 is the calculated residual current of some side.
[Y.62PD.3I0_Set] is residual current setting of pole disagreement protection of some side.
I2> [Y.62PD.I2_Set] Equation 3.18-2
Where:
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I2 is negative-sequence current of some side.
[Y.62PD.I2_Set] is negative-sequence current setting of pole disagreement protection of some

side.
3.18.4 Logic
For pole disagreement protection, when following three conditions are met, the pole disagreement
(1) Logic setting [Y.62PD.En] is set as “1”.
(2) The protection function enabling inputs [Y.62PD.En1], [Y.62PD.En2] are “1”.
(3) The protection function blocking input [Y.62PD.Blk] is “0”.
If pole disagreement protection is disabled, all the related output signals will be reset. If no
external input is configured to [Y.62PD.En1] ([Y.62PD.En2]), the default initial value of
[Y.62PD.En1] ([Y.62PD.En2]) is “1”; if no external input is configured to [Y.62PD.Blk], the default
initial value of [Y.62PD.Blk] is “0”.
Logic of pole disagreement protection is shown in following figure.
BI Y.62PD.In_PD_CB
Sig 3I0>[Y.62PD.3I0_set] &
Set Y.62PD.En_3I0
≥1 ≥1
&
[Y.62PD.St]
Set Y.62PD.En_I2 & [Y.62PD.t_Op] 0ms
[Y.62PD.Op]
Sig I2>[Y.62PD.I2_Set]
En Y.62PD.En
&
SIG Y.62PD.En1
SIG Y.62PD.En2
SIG Y.62PD.Blk
0ms 500ms
Sig Y.62PD.FD
[Y.62PD.t_Alm] 0ms
BI Y.62PD.In_PD_CB [Y.62PD.Alm]
Figure 3.18-1 Logical diagram of pole disagreement protection
Where:
I2 is negative-sequence current of some side.
Y.62PD.FD is the operation flag of the fault detector of pole disagreement protection (the fault
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62PD
Y.62PD.I3P Y.62PD.St
Y.62PD.In_PD_CB Y.62PD.Op
Y.62PD.En1 Y.62PD.Alm
Y.62PD.En2
Y.62PD.Blk
Figure 3.18-2 Function block diagram of pole disagreement protection
Table 3.18-1 Input signals of pole disagreement protection

1 Y.62PD.I3P Three-phase current input.
2 Y.62PD.In_PD_CB Pole disagreement position input signal
3 Y.62PD.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
4 Y.62PD.En2 as function enabling binary inputs, logic links, etc.
5 Y.62PD.Blk Protection function blocking input, such as function blocking binary input.
Table 3.18-2 Output signals of pole disagreement protection

1 Y.62PD.St Pole disagreement protection starts.
2 Y.62PD.Op Pole disagreement protection operates.
3 Y.62PD.Alm Pole disagreement position contact abnormality alarm
Table 3.18-3 Output signals of pole disagreement protection (event recorder)
Tripping reports
1 Y.62PD.Op Pole disagreement protection operates.
Start signals
2 Y.62PD.St Pole disagreement protection starts.
Alarm signals
3 Y.62PD.Alm Pole disagreement position contact abnormality alarm
Waveform recording
4 Y.62PD.TrigDFR Pole disagreement protection operates to trigger waveform recording.
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3.18.6 Settings
Table 3.18-4 Settings list of pole disagreement protection

0: disable Logic setting of enabling/disabling pole
1 Y.62PD.En 1
1: enable disagreement protection.
2 Y.62PD.I2_Set 0.05~10.00In 0.01 A negative-sequence current criterion of pole
Residual current setting of residual current criterion
3 Y.62PD.3I0_Set 0.05~10.00In 0.01 A
of pole disagreement protection.
4 Y.62PD.t_Op 0~30 0.01 s Time delay of pole disagreement protection.
Time delay of pole disagreement position contact
5 Y.62PD.t_Alm 0~30 0.01 s
abnormality alarm.
Tripping logic setting of pole disagreement
6 Y.62PD.OutMap 0~3FFFFFFF
protection.
0: disable
7 Y.62PD.En_I2 negative-sequence current criterion of pole
1: enable
8 Y.62PD.En_3I0
1: enable criterion of pole disagreement protection.
Access path:
3.19 Breaker Flashover Protection (50F)

NOTICE!
In Section 3.19, the prefix “Y” in settings (such as [Y.50F.I2_Set]) and input/output
signals (such as [Y.50F.Op_t1]) can be Tr_HVS and Tr_MVS. Details of the prefix are
as:
Tr_HVS.50F Corresponds to breaker flashover protection of main transformer high voltage side.
Tr_MVS.50F Corresponds to breaker flashover protection of main transformer medium voltage side.
3.19.1 Application
For the large-scale generator-transformer unit in higher voltage level system, during the process of
preparation synchronization or just out of operation, flashover in circuit breaker is possible when
phase angle difference between the voltages of two sides of the circuit breaker is around 180°.
Flashover in circuit breaker will damage the circuit breaker, and it also maybe cause the trouble to
extend, then the stable operation of the system will be destroyed. Usually flashover in circuit
breaker is one phase and two-phase flashover, it will generate torque which will act on the
generator, on the other hand it will generate negative-sequence current which will cause additional
loss to the rotor, and then the safety of the generator will be threatened. If the device detect the
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flashover fault, breaker flashover protection will operate to start de-excitation of the generator and
initiate the circuit breaker failure protection with a settable time delay.
3.19.2 Function
Breaker flashover protection includes following two criteria:
 Circuit breaker position auxiliary contact criterion. The circuit breaker is open when flashover
happens, users can select to only judge circuit breaker normally closed contact or judge both
of circuit breaker normally open contact and normally closed contact.
 Current criteria: negative-sequence current criterion, phase current criterion and residual
current criterion.
The internal logic between the above two criteria is “And”. Negative-sequence current criterion is
enabled fixedly; phase current criterion and residual current criterion can be enabled or disabled
independently.
3.19.3.1 Overview
When the circuit breaker is open, and the negative-sequence current or phase current or residual
current is larger than the corresponding setting, breaker flashover protection will operate to trip.
Two independent time delays are available for breaker flashover protection, breaker flashover
protection with time delay 1 can operate to trip generator circuit breaker or de-excitation circuit
breaker, breaker flashover protection with time delay 2 can operate to initiate the circuit breaker
failure protection.
3.19.3.2 Circuit Breaker Position Criterion
If the setting [Y.50F.Opt_Mode] is set as “0”, the protection will only judge the circuit breaker
normally closed auxiliary contact, if the normally closed auxiliary contact [BI_52b] is “1”, it means
the circuit breaker is open. If the setting [Y.50F.Opt_Mode] is set as “1”, the protection will judge
the circuit breaker normally closed auxiliary contact and normally open auxiliary contact, if the
normally closed auxiliary contact [BI_52b] is “1” and the normally open auxiliary contact [BI_52a] is
“0”, it means the circuit breaker is open.
When the setting [Y.50F.Opt_Mode] is set as “0”, if the normally closed auxiliary contact [BI_52b] is
“1” for a long time and current is detected, circuit breaker contact abnormality alarm [Y.50F.Alm]
will be issued. When the setting [Y.50F.Opt_Mode] is set as “1”, if the state of both of normally
closed auxiliary contact [BI_52b] and normally open auxiliary contact [BI_52a] are the same, circuit
breaker contact abnormality alarm [Y.50F.Alm] will also be issued.
Current criteria include negative-sequence current criterion, residual current criterion, and phase
current criterion. If any current criterion is met, current element of breaker flashover protection
picks up.
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I2> [Y.50F.I2_Set] Equation 3.19-1
Where:
I2 is the calculated negative-sequence current of some side.
[Y.50F.I2_Set] is negative-sequence current setting of breaker flashover protection of

corresponding side.
3I0 >[Y.50F.3I0_Set] Equation 3.19-2
Where:
[Y.50F.3I0_Set] is residual current setting of breaker flashover protection of corresponding side.
3) Phase current criterion:
I  _ max >[Y.50F.Ip_Set] Equation 3.19-3
Where:
I  _ max is the maximum value of three-phase current of some side.
[Y.50F.Ip_Set] is the phase current setting of breaker flashover protection of corresponding side.
3.19.4 Logic
For breaker flashover protection, when following three conditions are met, the breaker flashover
(1) Logic setting [Y.50F.En] is set as “1”.
(2) The protection function enabling inputs [Y.50F.En1], [Y.50F.En2] are “1”.
(3) The protection function blocking input [Y.50F.Blk] is “0”.
If breaker flashover protection is disabled, all the related outp ut signals will be reset. If no external
input is configured to [Y.50F.En1] ([Y.50F.En2]), the default initial value of [Y.50F.En1] ([Y.50F.En2])
is “1”; if no external input is configured to [Y.50F.Blk], the default initial value of [Y.50F.Blk] is “0”.
Logics of breaker flashover protection (with two time delays) is shown in following figure.
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Set Y.50F.En_IP &
Sig IΦ_max>[Y.50F.Ip_Set]
Set Y.50F.En_3I0 & ≥1
Sig 3I0>[Y.50F.3I0_Set]
Sig I2>[Y.50F.I2_Set]
&
Sig BI_52b
≥1
&
Set Y.50F.Opt_Mode &
&
[Y.50F.St]
Sig BI_52a
[Y.50F.t1_Op] 0ms [Y.50F.Op_t1]
Sig Y.50F.Alm
[Y.50F.t2_Op] 0ms [Y.50F.Op_t2]
En Y.50F.En
&
SIG Y.50F.En1
SIG Y.50F.En2
SIG Y.50F.Blk
0ms 500ms
Sig Y.50F.FD
Sig IΦ_max≥0.1In &
Set Y.50F.Opt_Mode
≥1
[Y.50F.t_Alm] 0ms [Y.50F.Alm]
Sig BI_52b =1
Sig BI_52a &
Set Y.50F.Opt_Mode
Figure 3.19-1 Logic diagram of breaker flashover protection
Where:
I2 is the calculated negative-sequence current of some side.
I  _ max is the maximum value of three-phase current of some side.
[BI_52b] is the normally closed auxiliary contact of the circuit breaker.
[BI_52a] is the normally open auxiliary contact of the circuit breaker.
Y.50F.FD is the operation flag of the fault detector of breaker flashover protection (the fault
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50F
Y.50F.I3P Y.50F.St
BI_52b Y.50F.Op_t1
BI_52a Y.50F.Op_t2
Y.50F.En1 Y.50F.Alm
Y.50F.En2
Y.50F.Blk
Figure 3.19-2 Function block diagram of breaker flashover protection
Table 3.19-1 Input signals of breaker flashover protection

1 Y.50F.I3P Three-phase current input.
2 BI_52b The normally closed auxiliary contact of the circuit breaker.
3 BI_52a The normally open auxiliary contact of the circuit breaker.
4 Y.50F.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
5 Y.50F.En2 as function enabling binary inputs, logic links, etc.
6 Y.50F.Blk Protection function blocking input, such as function blocking binary input.
Table 3.19-2 Output signals of breaker flashover protection

1 Y.50F.St Breaker flashover protection starts.
2 Y.50F.Op_t1 Breaker flashover protection with time delay 1 operates.
4 Y.50F.Alm Breaker flashover protection circuit breaker contact abnormality alarm.
Table 3.19-3 Output signals of breaker flashover protection (event recorder)
Tripping reports
Start signals
3 Y.50F.St Breaker flashover protection starts.
Alarm signals
4 Y.50F.Alm Breaker flashover protection circuit breaker contact abnormality alarm.
Waveform recording
5 Y.50F.TrigDFR Breaker flashover protection operates to trigger waveform recording.
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3.19.6 Settings
Table 3.19-4 Settings list of breaker flashover protection

0: disable Logic setting of enabling/disabling breaker
1 Y.50F.En 1
1: enable flashover protection.
2 Y.50F.I2_Set 0.05~4.00In 0.01 A
criterion of breaker flashover protection.
Current setting of residual current criterion of
3 Y.50F.3I0_Set 0.05~4.00In 0.01 A
breaker flashover protection.
Current setting of phase current criterion of breaker
4 Y.50F.Ip_Set 0.05~10.00In 0.01 A
flashover protection.
5 Y.50F.t1_Op 0.01~10.00 0.01 s Time delay 1 of breaker flashover protection.
Tripping logic setting of breaker flashover
6 Y.50F.OutMap_t1 0~3FFFFFFF
protection with time delay 1.
7 Y.50F.t2_Op 0.01~10.00 0.01 s Time delay 2 of breaker flashover protection.
Tripping logic setting of breaker flashover
8 Y.50F.OutMap_t2 0~3FFFFFFF 0.01
protection with time delay 2.
Time delay of breaker flashover protection circuit
9 Y.50F.t_ Alm 0.00~30.00 0.01 s
breaker contact abnormality alarm .
10 Y.50F.En_3I0
1: enable criterion of breaker flashover protection.
0: disable Logic setting of enabling/disabling phase current
11 Y.50F.En_Ip
1: enable criterion of breaker flashover protection.
The setting to select the logic for circuit breaker
position criterion of breaker flashover protection.
0: only judge the circuit breaker normally closed
12 Y.50F.Opt_ Mode 0, 1 auxiliary contact;
1: judge both of the circuit breaker normally closed
auxiliary contact and normally open auxiliary
contact.
Access path:
3.20 Mechanical Protection (MR)
3.20.1 Application
Any operation signal from the transformer body protection or other external device can be coupled
to the microprocessor-based protection device via the binary input signal. Transformer mechanical
protection can repeat these binary input signals to send alarm signals, tripping directly or tripping
with a time delay. By this way the output signal of some mechanical protection (such as gas
protection and etc.) can be coupled to the microprocessor-based protection device, and then
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these signals can be repeated through high-power relays to improve the anti-inference ability of
the protection.
Mechanical protection has following functions:
 High-power relays are adopted to improve the anti-interference ability of mechanical

protection.
 Each module provides 4 mechanical signal input channels for trip or alarm.

Transformer relay repeats external binary input signal through high-power relays and send them to
CPU through opto-coupler circuits. After CPU receiving those signals, the device will record them
as events, issue alarm signal and send tripping command with settable time delays. Because the
drop off time of mechanical input signals is usually too long, an internal time delay setting
[MR1(2).t_PW_n] (x=1, 2, 3, and 4) is used to control the drop off time (the default value is 9s), it
can prevent the relay from sending long-time tripping command.
3.20.4 Logic
For mechanical protection, if following three conditions are met, the protection will be enabled.
(1) Logic setting [MRx.En] (x=1, 2) is set as “1”.
(2) The protection function enabling inputs [MRx.En1], [MRx.En2] are “1”
(3) The protection function blocking input [MRx.Blk] is “0”.
If mechanical protection is disabled, all the related output signals will be reset. If no external input
is configured to [MRx.En1] ([MRx.En2]), the default initial value of [MRx.En1] ([MRx.En2]) is “1”; if
no external input is configured to [MRx.Blk], the default initial value of [MRx.Blk] is “0”.
Here takes channel 1 of mechanical protection 1 as an example. The logics of channel 2, 3 and 4
are similar with that of channel 1.
EN [MR1.En] &
EN [MR1.En_1] [MR1.Sig1]
SIG [MR1.Input1]
EN [MR1.En] & &

SIG [MR1.En1]
SIG [MR1.En2]
[MR1.t_DPU_1] [MR1.t_PW_1]
SIG [MR1.Blk] [MR1.Op1]
EN [MR1.En_1] &
SIG [MR1.Input1]
SET [MR1.OutMap_1] (bit0=1)
Figure 3.20-1 Logic diagram of channel 1 of mechanical protection 1
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MRx
MRx.Input1 MRx.St
MRx.Input2 MRx.Op1
MRx.Input3 MRx.Op2
MRx.Input4 MRx.Op3
MRx.En1 MRx.Op4
MRx.En2 MRx.Sig1
MRx.Blk MRx.Sig2
MRx.Sig3
MRx.Sig4
Figure 3.20-2 Function block diagram of mechanical protection (x=1, 2)
Table 3.20-1 Input signals of mechanical protection (x=1, 2)

1 MR x.Input1 Input signal of channel 1 of mechanical protection x.
5 MR x.En1 Protection function enabling input1 and input 2, it can be binary inputs or settings, such
6 MR x.En2 as function enabling binary inputs, logic links, etc.
7 MR x.Blk Protection function blocking input, such as function blocking binary input.
Table 3.20-2 Output signals of mechanical protection (x=1, 2)

1 MR x.St Mechanical protection x starts
2 MR x.Sig1 Output alarm signal of channel 1 of mechanical protection x.
6 MR x.Op1 Output tripping signal of channel 1 of mechanical protection x.
Table 3.20-3 Output signals of mechanical protection (event recorder) (x=1, 2)
Tripping reports
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Start signals
5 MR x.St Mechanical protection x starts.
Waveform recording
6 MR x.TrigDFR Mechanical protection x operates to trigger waveform recording.
IO events
11 MR x.St1 Channel 1 of mechanical protection x starts.
3.20.6 Settings
Table 3.20-4 Settings list of mechanical protection

0: disable Logic setting of enabling/disabling mechanical
1 MR1.En
1: enable protection 1.
Delay pickup time of tripping command of channel
2 MR1.t_DPU_1 0.00~6000.00 0.01 s
1 of mechanical protection 1.
Tripping logic setting of channel 1 of mechanical
3 MR1.OutMap_1 0~3FFFFFFF
protection 1.
0: disable Logic setting of enabling/disabling channel 1 of
4 MR1.En_1
1: enable mechanical protection 1.
5 MR1.t_DPU_2 0.00~6000.00 0.01 s
protection 1.
7 MR1.En_2
8 MR1.t_DPU_3 0.00~6000.00 0.01 s
protection 1.
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10 MR1.En_3
11 MR1.t_DPU_4 0.00~6000.00 0.01 s
protection 1.
13 MR1.En_4
0: disable Logic setting of enabling/disabling mechanical
14 MR2.En
1: enable protection 2.
15 MR2.t_DPU_1 0.00~6000.00 0.01 s
protection 2.
17 MR2.En_1
18 MR2.t_DPU_2 0.00~6000.00 0.01 s
protection 2.
20 MR2.En_2
21 MR2.t_DPU_3 0.00~6000.00 0.01 s
protection 2.
23 MR2.En_3
24 MR2.t_DPU_4 0.00~6000.00 0.01 s
protection 2.
26 MR2.En_4
Access path: Settings-> Prot Settings -> MechRly Settings
3.21 Interconnection Status Element (CBStatus)
3.21.1 Application
If a main transformer or a generator-transformer unit is connecting with the power network, it is

called “interconnection status”. Some protections should be enabled before the interconnection
status and disabled after the interconnection status, while some protections should be enabled
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after the interconnection status. The device will detect the position of main transformer HV side or
MV side circuit breaker and the current of the CT at the outlet of the circuit breaker, then
comprehensively judge whether the main transformer or the generator-transformer unit is during
interconnection status, the interconnection status flag can be output for the user to implement logic
programming.
Interconnection status element has following functions:
 Four circuit breaker auxiliary contact inputs, the auxiliary contact of main transformer HV
side or MV side circuit breaker can be connected to the device.
 Four groups of current inputs respectively correspond to the CTs at the outlet of the four
circuit breakers.

If the setting [Num_CB_HVS_Tr] is set as “1”, it means there is one circuit breaker on main
transformer HV side, then the auxiliary contact of main transformer HV side circuit breaker and the
current of the CT at the outlet of main transformer HV side circuit breaker should be input. If the
setting [Num_CB_HVS_Tr] is set as “2”, it means there are two circuit breakers on main
transformer HV side (it is also called 3/2 breakers wiring), then the auxiliary contacts of the two
circuit breakers of main transformer HV side and the currents of the CTs at the outlet of the two
circuit breakers should be input.
If the setting [Num_CB_MVS_Tr] is set as “0”, it means there is no circuit breaker on main
transformer MV side. If the setting [Num_CB_MVS_Tr] is set as “1”, it means there is one circuit
breaker on main transformer MV side, then the auxiliary contact of main transformer MV side
circuit breaker and the current of the CT at the outlet of main transformer MV side circuit breaker
should be input. If the setting [Num_CB_MVS_Tr] is set as “2”, it means there are two circuit
breakers on main transformer MV side (it is also called 3/2 breakers wiring), then the auxiliary
contacts of the two circuit breakers of main transformer MV side and the currents of the CTs at the
outlet of the two circuit breakers should be input.
The device will detect the position of main transformer HV side or MV side circuit breaker and the
current of the CT at the outlet of the circuit breaker, then comprehensively judge whether the main
transformer or the generator-transformer unit is during interconnection status, the interconnection
status flag can be output for the user to implement logic programming.
3.21.4 Logic
Logic of interconnection status element is shown in following figure.
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SIG [Num_CB_HVS_Tr]=1 &
SIG BI_52b_CB1 ≥1
&
SIG BI_52b_CB2 &
&
SIG [Num_CB_HVS_Tr]=2
[Flg_52a]
SIG [Num_CB_MVS_Tr]=0
SIG [Num_CB_MVS_Tr]=1 & ≥1
SIG BI_52b_CB3 &
SIG BI_52b_CB4 &
SIG [Num_CB_MVS_Tr]=2
SIG Imax1>0.04In
SIG Imax2>0.04In ≥1
[TrCBStatus.Flg_OnLoad]
SIG Imax3>0.04In
SIG Imax4>0.04In
SIG BI_52b_CB1 &

10s
[Alm_52_CB1]
SIG Imax1>0.10In
SIG BI_52b_CB2 &
10s
[Alm_52_CB2]
SIG Imax2>0.10In
SIG BI_52b_CB3 &

10s
[Alm_52_CB3]
SIG Imax3>0.10In
SIG BI_52b_CB4 &
10s
[Alm_52_CB4]
SIG Imax4>0.10In
Figure 3.21-1 Logic diagram of interconnection status element
Where:
Imax1 is the maximum phase current value of three-phase current 1.
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TrCBStatus
TrCBStatus.I3P1
TrCBStatus.I3P2
TrCBStatus.I3P3
TrCBStatus.I3P4 Flg_52a
BI_52b_CB1 TrCBStatus.Flg_OnLoad
BI_52b_CB2
BI_52b_CB3
BI_52b_CB4
Figure 3.21-2 Function block diagram of interconnection status element
Table 3.21-1 Input signals of interconnection status element

1 TrCBStatus.I3P1 Three-phase current input 1.
5 BI_52b_CB1 The normally closed auxiliary contact of circuit breaker 1.
Table 3.21-2 Output signals of interconnection status element

1 Flg_52a The signal indicating that the transformer is connected with the system.
The signal indicating that current of the CT at the outlet of the circuit breaker
2 TrCBStatus.Flg_OnLoad
is detected.
3 Alm_52_CB1 Circuit breaker 1 auxiliary contact abnormality alarm.
Table 3.21-3 Output signals of interconnection status element (measurements)
The signal indicating that the transformer is connected with the

1 Flg_52a
system.
The signal indicating that current of the CT at the outlet of the circuit
2 TrCBStatus.Flg_OnLoad
breaker is detected.
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Access path:
Main menu -> Measurements -> Measurements2-> Prot Values-> Misc Prot Values
3.21.6 Settings
Table 3.21-4 Settings list of interconnection status element

1 Num_CB_HVS_Tr 1~2 1 The circuit breaker number for main transformer HV side.
2 Num_CB_MVS_Tr 0~2 1 The circuit breaker number for main transformer MV side.
Access path: De vice Setup->Function Configuration
3.22 Current Sum Element (CurrSum)
3.22.1 Application
Current sum element is used to synthesize several channels of three-phase current as one
channel of three-phase current, so it can be convenient for protection logic calculation.
Up to three channels of three-phase current can be synthesized as one channel of three-phase

current.
3.22.3 Principle
If one side of the protected object has several branches, sometimes the current sum of the several
branches is needed. The CT ratio of the several branches can be different, the CT ratio of the first
channel of current is taken as the referenced CT ratio, the currents of other channel(s) will be
converted to the first channel firstly, and then the current sum is calculated.
3.22.4 Logic
EN [Y.CurrSum.En] &
[Y.CurrSum.I3P]
SIG [Y.CurrSum.I3P1]
SIG [Y.CurrSum.I3P2] 
SIG [Y.CurrSum.I3P3]
Figure 3.22-1 Logic diagram of current sum element
Y means one side of the protected object.
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Y.CurrSum
Y.CurrSum.I3P1 Y.CurrSum.I3P
Y.CurrSum.I3P2 Y.CurrSum.Ang(Ia)
Y.CurrSum.I3P3 Y.CurrSum.Ang(Ib)
Y.CurrSum.Ang(Ic)
Y.CurrSum.Flg_OnLoad
Figure 3.22-2 Function block of current sum element
Y means one side of the protected object.
Table 3.22-1 Input signals of current sum element

1 Y.CurrSum.I3P1 Three-phase current 1 data
Table 3.22-2 Output signals of current sum element

1 Y.CurrSum.I3P Three-phase current data set of x side
2 Y.CurrSum.Ia Phase A current of x side
3 Y.CurrSum.Ib Phase B current of x side
4 Y.CurrSum.Ic Phase C current of x side
5 Y.CurrSum.I_Avg The average value of three-phase current of x side
6 Y.CurrSum.Flg_OnLoad A flag indicating load current of x side is detected
Table 3.22-3 Output signals of current sum element: measurements
1 Y.CurrSum.Ia A
2 Y.CurrSum.Ib Phase current value of x side. A
3 Y.CurrSum.Ic A
4 Y.CurrSum.I_Avg The average value of three-phase current of x side. A
5 Y.CurrSum.Ang(Ia-Ib) Phase angle between phase A and phase B currents of x side. deg
6 Y.CurrSum.Ang(Ib-Ic) Phase angle between phase B and phase C currents of x side deg
7 Y.CurrSum.Ang(Ic-Ia) Phase angle between phase C and phase A currents of x side deg
8 Y.CurrSum.3I0_Cal Calculated residual current of x side. A
9 Y.CurrSum.I1 Positive-sequence current of x side. A
10 Y.CurrSum.I2 Negative-sequence current of x side. A
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3.22.6 Settings
Table 3.22-4 Settings list of current sum element

0: disable Logic setting of enabling/disabling current sum
1 Y.CurrSum.En 1
1: enable element (the default value is “1”).
Logic setting of enabling/disabling reverse polar
of current input 1 of x side, if it is set as “1”, the
0: disable
2 Y.CurrSum.En_RevCT1 1 negative value of current input 1 is used in the
1: enable
calculation of current sum element (the default
value is “0”).
of current input 2 of x side, if it is set as “1”, the
0: disable
1: enable
value is “0”).
of current input 3 of x side, if it is s et as “1”, the
0: disable
1: enable
value is “0”).
NOTICE!
The settings in above table CAN NOT be seen on LCD of equipment. These settings
are usually configured by field commission engineer according to the design drawing
and project requirement.
3.23 Three-Phase Current Element (Curr3P)
NOTICE!
In Section 3.23, the prefix “Y” in settings (such as [Y.I1n]) and input/output signals (such
as [Y.Ia]) can be Tr_HVS1, Tr_HVS2, Tr_MVS, Tr_LVS and ST_HVS#. Details of the
prefix are as:
Tr_HVS1 corresponds to the three-phase current of CT of main transformer HV side 1
Tr_HVS2 corresponds to the three-phase current of CT of main transformer HV side 2
Tr_MVS corresponds to the three-phase current of CT of main transformer MV side
Tr_LVS corresponds to the three-phase current of CT of main transformer LV side
corresponds to the three-phase current of big-ratio CT of H V side of step-down

ST_HVS#
transformer
3.23.1 Application
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Three-phase current element is responsible for pre-processing three phase currents and
calculating sequence components, amplitudes and phases of three phase currents, etc. All
calculated information of three-phase current element is for the protection logic calculation.

Three-phase current element has following functions:
 Pre-process three phase currents.
 Calculate information related to three-phase current.
 Monitor the secondary circuit of current including CT circuit abnormality.
3.23.3 Principle
 CT circuit abnormality supervision
If the calculated residual current is larger than 0.04In plus 25% of the maximum phase current, the
corresponding CT circuit abnormality alarm signal [Y.AlmL_CTS] will be issued with a time delay of
10s, and it will be reset with a time delay of 10s if the CT circuit returns to normal condition.
 Current detection
When any phase current is larger than 0.04In, it will be identified that current is detected for the
corresponding CT, CT having current signal can be used for programmable logic application.
3.23.4 Logic
10s 10s
SIG Y.3I0>0.04In+0.25Imax [Y.AlmL_CTS]
SIG Y.Ia>0.04In
≥1
SIG Y.Ib>0.04In [Y.Flg_OnLoad]
SIG Y.Ic>0.04In
Figure 3.23-1 Current pre-processing logic diagram
Where:
Y.Ia, Y.Ib, and Y.Ic are sampled three phase current values.
Y.3I0 is the calculated residual current.
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Curr3P
Y.ia Y.I3P
Y.ib Y.Ia
Y.ic Y.Ib
Y.Ic
Y.I_Avg
Y.AlmL_CTS
Y.Flg_OnLoad
Figure 3.23-2 Function block diagram of three-phase current element
Table 3.23-1 Input signals of three-phase current element

1 Y.ia Sampled value of phase-A current
2 Y.ib Sampled value of phase-B current
3 Y.ic Sampled value of phase-C current
Table 3.23-2 Output signals of three-phase current element

1 Y.I3P Three-phase current data set.
2 Y.Ia Phase-A current.
3 Y.Ib Phase-B current.
4 Y.Ic Phase-C current.
5 Y.I_ Avg The average amplitude of three-phase current.
6 Y.AlmL_CTS CT secondary circuit abnormality alarm.
7 Y.Flg_OnLoad A fla Tr_HVS g indicating that load current is detected
Above input signals and output signals can be used for programmable logic, and following output
signals are only for LCD display of equipment.
Table 3.23-3 Output signals of three-phase current element (event recorder)
Alarm signals
1 Y.AlmL_CTS CT secondary circuit abnormality alarm.
Table 3.23-4 Output signals of three-phase current element (measurements)
No. Output Signal Description
1 Tr_HVS1.Ia
2 Tr_HVS1.Ib Phase current amplitude of CT of main transformer HV side 1
3 Tr_HVS1.Ic
4 Tr_HVS1.I1 Positive-sequence current amplitude of CT of main transformer HV side 1
5 Tr_HVS1.I2 Negative-sequence current amplitude of CT of main transformer HV side 1
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The calculated residual current amplitude of CT of main transformer HV

6 Tr_HVS1.3I0_Cal
side 1
7 Tr_HVS2.Ia
8 Tr_HVS2.Ib Phase current amplitude of CT of main transformer HV side 2
9 Tr_HVS2.Ic
10 Tr_HVS2.I1 Positive-sequence current amplitude of CT of main transformer HV side 2
11 Tr_HVS2.I2 Negative-sequence current amplitude of CT of main transformer HV side 2
The calculated residual current amplitude CT of main transformer HV side

12 Tr_HVS2.3I0_Cal
2
13 Tr_MVS.Ia
14 Tr_MVS.Ib Phase current amplitude of CT of main transformer MV side
15 Tr_MVS.Ic
16 Tr_MVS.I1 Positive-sequence current amplitude of CT of main transformer MV side
17 Tr_MVS.I2 Negative-sequence current amplitude of CT of main transformer MV side
The calculated residual current amplitude of CT of main transformer MV

18 Tr_MVS.3I0_Cal
side
19 Tr_LVS.Ia
20 Tr_LVS.Ib Phase current amplitude of CT of main transformer LV side
21 Tr_LVS.Ic
22 Tr_LVS.I1 Positive-sequence current amplitude of CT of main transformer LV side
23 Tr_LVS.I2 Negative-sequence current amplitude of CT of main transformer LV side
The calculated residual current amplitude of CT of main transformer LV

24 Tr_LVS.3I0_Cal
side
Phase current amplitude of the big-ratio CT of HV side of step-down

25 ST_HVS#.Ia
transformer 1
26 ST_HVS#.Ib
27 ST_HVS#.Ic
Positive-sequence current amplitude of the big-ratio CT of HV side of
28 ST_HVS#.I1
step-down transformer 1
Negative-sequence current amplitude of the big-ratio CT of H V side of

29 ST_HVS#.I2
The calculated residual current amplitude of the big-ratio CT of HV side of

30 ST_HVS#.3I0_Cal
Access path:
Main menu -> Measurements -> Measurements1-> Tr Values-> Tr Curr Values
Main menu -> Measurements -> Measurements2->Tr Values-> Tr Curr Values
Date: 2015-07-29
3 Operation Theory
Phase angle between phase-A current and phase-B current of HV side 1 of

31 Tr_HVS1.Ang(Ia-Ib)
main transformer
Phase angle between phase-B current and phase-C current of HV side 1

32 Tr_HVS1.Ang(Ib-Ic)
of main transformer
Phase angle between phase-C current and phase-A current of HV side 1

33 Tr_HVS1.Ang(Ic-Ia)
of main transformer
Phase angle between phase-A current and phase-B current of HV side 2 of

34 Tr_HVS2.Ang(Ia-Ib)
main transformer
Phase angle between phase-B current and phase-C current of HV side 2

35 Tr_HVS2.Ang(Ib-Ic)
of main transformer
Phase angle between phase-C current and phase-A current of HV side 2

36 Tr_HVS2.Ang(Ic-Ia)
of main transformer
Phase angle between phase-A current and phase-B current of MV side of

37 Tr_MVS.Ang(Ia-Ib)
main transformer
Phase angle between phase-B current and phase-C current of MV side of

38 Tr_MVS.Ang(Ib-Ic)
main transformer
Phase angle between phase-C current and phase-A current of MV side of

39 Tr_MVS.Ang(Ic-Ia)
main transformer
Phase angle between phase-A current and phase-B current of LV side of

40 Tr_LVS.Ang(Ia-Ib)
main transformer
Phase angle between phase-B current and phase-C current of LV side of

41 Tr_LVS.Ang(Ib-Ic)
main transformer
Phase angle between phase-C current and phase-A current of LV side of

42 Tr_LVS.Ang(Ic-Ia)
main transformer
Phase angle between phase-A current and phase-B current of HV side of

43 ST_HVS#.Ang(Ia-Ib)
step-down transformer
Phase angle between phase-B current and phase-C current of H V side of

44 ST_HVS#.Ang(Ib-Ic)
Phase angle between phase-C current and phase-A current of HV side of

45 ST_HVS#.Ang(Ic-Ia)
Access path:
3.23.6 Settings
Table 3.23-5 Settings list of three-phase current element

1 Y.I1n 0~60000 1 A Primary rated current of corresponding CT
2 Y.I2n 1 or 5 A Secondary rated current of corresponding CT
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3 Operation Theory

Access path:
Settings->Tr Sys Settings
3.24 Three-Phase Voltage Element (Volt3P)
NOTICE!
In Section 3.24, the prefix “Y” in settings (such as [Y.U1n]) and input/output signals
(such as [Y.Ua]) can be Tr_HVS, Tr_MVS and Tr_LVS. Details of the prefix are as:
Tr_HVS corresponds to the three-phase voltage of main transformer HV side
Tr_MVS corresponds to the three-phase voltage of main transformer MV side
Tr_LVS corresponds to the three-phase voltage of main transformer LV side
3.24.1 Application
Three-phase voltage element is responsible for pre-processing three phase voltages and
calculating sequence components, amplitudes and phases of three phase voltages, etc. All
calculated information of three-phase voltage element is for the protection logic calculation.
 Pre-process three phase voltages.
 Calculate information related to three phase voltages.
 Monitor the secondary circuit of voltage including VT circuit abnormality.
 VT neutral line failure supervision.
3.24.3 Principle
 VT circuit failure supervision
If one of following two criteria is met and there is no operation of any fault detectors , VT circuit
failure alarm will be issued with a time delay of 10s. The abnormality alarm will be reset with a time
delay of 10s if the VT circuit returns to normal condition.
1) Positive sequence voltage is less than 18V and any phase current is larger than 0.04 In.
2) The three times of negative sequence voltage (3U2) is larger than 8V.
 VT neutral line failure supervision
If following two criteria are all met, VT neutral line failure alarm will be issued with a time delay of
20s. The abnormality alarm will be reset with a time delay of 20s if the VT neutral line returns to
normal condition. VT neutral line failure supervision function can be enabled or disabled
independently.
1) Positive sequence voltage is larger than 48V.
Date: 2015-07-29
3 Operation Theory
2) The third harmonic of calculated residual voltage (3U0_3ω) is larger than K*U1.
K is the VT neutral line failure judge coefficient [Y.K_VTNS], it takes 0.2~0.5 generally.
3.24.4 Logic
SIG 3U2>8V
≥1
10s 10s
SIG U1<18V & [Y.Alm_VTS]
SIG [Y.Flg_OnLoad]
EN Y.En_VTNS
&
20s 20s
SIG U1>48V & [Y.Alm_VTNS]
SIG 3U0_3ω>[Y.K_VTNS]*U1
Figure 3.24-1 Voltage pre-processing logic diagram
Where:
U2 and U1 are negative sequence voltage value and positive sequence voltage value respectively.
3U0_3ω is the third harmonic of calculated residual voltage.
Volt3P
Y.ua Y.Alm_VTS
Y.ub Y.Alm_VTNS
Y.uc Y.U3P
Y.Flg_OnLoad Y.Ua
Y.Ub
Y.Uc
Y.U_Avg
Figure 3.24-2 Function block diagram of three-phase voltage element
Table 3.24-1 Input signals of three-phase voltage element

1 Y.ua Sampled value of phase A voltage
2 Y.ub Sampled value of phase B voltage
3 Y.uc Sampled value of Phase C voltage
4 Y.Flg_OnLoad A flag indicating that load current is detected
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3 Operation Theory
Table 3.24-2 Output signals of three-phase voltage element

1 Y.U3P Three-phase voltage data set.
2 Y.Ua Phase-A voltage.
3 Y.Ub Phase-B voltage.
4 Y.Uc Phase-C voltage.
5 Y.U_Avg The average amplitude of three-phase voltage.
6 Y.Alm_VTS VT secondary circuit failure alarm.
7 Y.Alm_VTNS VT neutral line failure alarm.
Table 3.24-3 Output signals of three-phase voltage element (event recorder)
Alarm signals
1 Y.Alm_VTS VT secondary circuit failure alarm.
2 Y.Alm_VTNS VT neutral line failure alarm.
Table 3.24-4 Output signals of three-phase voltage element (measurements)
1 Tr_HVS.Ua
2 Tr_HVS.Ub Phase voltage amplitude of VT of main transformer HV side

3 Tr_HVS.Uc
Positive-sequence voltage amplitude of VT of main transformer HV

4 Tr_HVS.U1
side
Negative-sequence voltage amplitude of VT of main transformer HV

5 Tr_HVS.U2
side
The calculated residual voltage amplitude of VT of main transformer

6 Tr_HVS.3U0_Cal
HV side
7 Tr_HVS.Uab
Phase-to-phase voltage amplitude of the VT of H V side of main
8 Tr_HVS.Ubc
transformer
9 Tr_HVS.Uca
10 Tr_MVS.Ua
11 Tr_MVS.Ub Phase voltage amplitude of VT of main transformer MV side
12 Tr_MVS.Uc
Positive-sequence voltage amplitude of VT of main transformer MV

13 Tr_MVS.U1
side
Negative-sequence voltage amplitude of VT of main transformer MV

14 Tr_MVS.U2
side

15 Tr_MVS.3U0_Cal
MV side
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3 Operation Theory
16 Tr_MVS.Uab
Phase-to-phase voltage amplitude of the VT of MV side of main
17 Tr_MVS.Ubc
transformer
18 Tr_MVS.Uca
19 Tr_LVS.Ua
20 Tr_LVS.Ub Phase voltage amplitude of VT of main transformer LV side
21 Tr_LVS.Uc
Positive-sequence voltage amplitude of VT of main transformer LV

22 Tr_LVS.U1
side
Negative-sequence voltage amplitude of VT of main transformer LV

23 Tr_LVS.U2
side

24 Tr_LVS.3U0_Cal
LV side
25 Tr_LVS.Uab
Phase-to-phase voltage amplitude of the VT of LV side of main
26 Tr_LVS.Ubc
transformer
27 Tr_LVS.Uca
Access path:
Phase angle between phase-A voltage and phase-B voltage of HV

28 Tr_HVS.Ang(Ua-Ub)
side of main transformer
Phase angle between phase-B voltage and phase-C voltage of HV

29 Tr_HVS.Ang(Ub-Uc)
Phase angle between phase-C voltage and phase-A voltage of HV

30 Tr_HVS.Ang(Uc-Ua)
Phase angle between phase-A voltage and phase-B voltage of MV

31 Tr_MVS.Ang(Ua-Ub)
Phase angle between phase-B voltage and phase-C voltage of MV

32 Tr_MVS.Ang(Ub-Uc)
Phase angle between phase-C voltage and phase-A voltage of MV

33 Tr_MVS.Ang(Uc-Ua)
Phase angle between phase-A voltage and phase-B voltage of LV side

34 Tr_LVS.Ang(Ua-Ub)
of main transformer
Phase angle between phase-B voltage and phase-C voltage of LV side

35 Tr_LVS.Ang(Ub-Uc)
of main transformer
Phase angle between phase-C voltage and phase-A voltage of LV side

36 Tr_LVS.Ang(Uc-Ua)
of main transformer
Access path:
Date: 2015-07-29
3 Operation Theory
3.24.6 Settings
Table 3.24-5 Settings list of three-phase voltage element

1 Y.U1n 1~2000 0.01 kV Primary rated voltage of corresponding VT
Secondary rated phase-to-phase voltage of
2 Y.U2n 1~300 0.01 V
corresponding VT
Access path:
0: disable Logic setting of enabling/disabling VT neutral line
3 Y.En_VTNS
1: enable failure supervision function.
4 Y.K_VTNS 0.10~1.00 0.01 VT neutral line failure judge coefficient
Access path:
Settings->Config Settings
3.25 Residual Current Element (Curr1P)
NOTICE!
In Section 3.25, the prefix “Y” in input/output signals (such as [Y.I1P]) can be Tr_HVS,
and Tr_MVS. Details of the prefix are as:
Tr_HVS corresponds to the residual current of main transformer HV side
Tr_MVS corresponds to the residual current of main transformer MV side
3.25.1 Application
Residual current element is responsible for pre-processing measured residual current and
calculating the amplitude and the phase angle of residual current, etc. All calculated information of
residual current element is for the protection logic calculation.
 Pre-process measured residual current.
 Calculate information related to residual current.
Date: 2015-07-29
3 Operation Theory
Curr1P
Y.3i0 Y.I1P
Y.3I0_Ext
Figure 3.25-1 Function block diagram of residual current element
Table 3.25-1 Input signals of single current element with filter

1 Y.3i0 Measured residual current
Table 3.25-2 Output signals of residual current element

1 Y.I1P A current data set
2 Y.3I0_Ext The amplitude of external measured residual current
Table 3.25-3 Output signals of residual current element (measurements)
The external measured residual current amplitude of main transformer HV

1 Tr_HVS.3I0_Ext A
side
The external measured residual current amplitude of main transformer MV A

2 Tr_MVS.3I0_Ext
side
Access path:
Main menu -> Measurements -> Measurements1-> Tr Values-> Tr Curr Values
Main menu -> Measurements -> Measurements2->Tr Values-> Tr Curr Values
3.25.4 Settings
Table 3.25-4 Settings list of residual current element

1 Y.I1n_NP 0~60000 1 A Primary current value of neutral point CT,
2 Y.I2n_NP 1 or 5 A Secondary current value of neutral point CT.
Access path:
3.26 Residual Voltage Element (Volt1P)
NOTICE!
In Section 3.26, the prefix “Y” in input/output signals (such as [Y.U1P]) can be Tr_HVS,
Tr_MVS and Tr_LVS. Details of the prefix are as:
Tr_HVS corresponds to the residual voltage of main transformer HV side
Date: 2015-07-29
3 Operation Theory
Tr_MVS corresponds to the residual voltage of main transformer MV side
Tr_LVS corresponds to the residual voltage of main transformer LV side
3.26.1 Application
Residual voltage element is responsible for pre-processing residual voltage and calculating the
amplitude of residual voltage, etc. All calculated information of residual voltage element is for the
protection logic calculation
 Pre-process measured residual voltage.
 Calculate information related to residual voltage.
Volt1P
Y.3u0 Y.U1P
Y.3U0_Ext
Figure 3.26-1 Function block diagram of residual voltage element
Table 3.26-1 Input signals of residual voltage element

1 Y.3u0 Measured residual voltage
Table 3.26-2 Output signals of residual voltage element

1 Y.U1P A voltage data set
2 Y.3U0_Ext The amplitude of VT broken-delta residual voltage
Table 3.26-3 Output signals of residual voltage element (measurements)
The amplitude of VT broken-delta residual voltage of main transformer HV

1 Tr_HVS.3U0_Ext
side
The amplitude of VT broken-delta residual voltage of main transformer MV

2 Tr_MVS.3U0_Ext
side
The amplitude of VT broken-delta residual voltage of main transformer LV

3 Tr_LVS.3U0_Ext
side
Access path:
3.26.4 Settings
Date: 2015-07-29
3 Operation Theory
Table 3.26-4 Settings list of residual voltage element

1 Y.U1n 1~2000 0.01 kV Primary rated voltage of corresponding VT.
2 Y.U2n 1~300 0.01 V Secondary rated voltage of corresponding VT.
Secondary voltage value of corresponding
3 Y.U2n_Delt 1~300 0.01 V
broken-delta VT.
Access path:
Date: 2015-07-29
3 Operation Theory
Date: 2015-07-29
4 Supervi sion
4 Supervision
Table of Contents
4 Supervision.......................................................................................... 4-a
4.1 Overview........................................................................................................................ 4-1
4.2 Failure and Abnormality Alarms ............................................................................. 4-1

4.3 Relay Self-supervision.............................................................................................4-10
4.3.1 Relay Hardware Monitoring ............................................................................................4-10
4.3.2 Fault Detector Monitoring ...............................................................................................4-10
4.3.3 Setting Checking ............................................................................................................ 4-11
4.3.4 Memory Checking .......................................................................................................... 4-11
4.3.5 Opto-coupler Power Supervision .................................................................................... 4-11
4.3.6 Output Tripping Circuit Supervision ................................................................................ 4-11
4.3.7 Test Mode Supervision ................................................................................................... 4-11
4.3.8 Hardware Configuration Supervision .............................................................................. 4-11
List of Tables
Table 4.2-1 Alarm description ................................................................................................ 4-1
Table 4.2-2 Troubleshooting................................................................................................... 4-7
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4 Supervi sion
Date: 2015-07-29
4 Supervi sion
4.1 Overview
Protection system is in quiescent state under normal conditions, and it is required to respond
promptly for faults occurred on power system. When the device is in energizing process before the
LED “HEALTHY” is on, the device need to be checked to ensure no abnormality. Therefore, the
automatic supervision function, which checks the health of the protection system when startup and
during normal operation, plays an important role.
The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.
In case a defect is detected during initialization when DC power supply is provided to the device,
the device will be blocked with indication and alarm of relay out of service. It is suggested a trial
recovery of the device by re-energization. Please contact supplier if the device is still failure.
When a failure is detected by the automatic supervision, it is followed by a LCD message, LED
indication and alarm contact outputs. The failure alarm is also recorded in event recording report
and can be printed If required.
4.2 Failure and Abnormality Alarms

NOTICE!
If the protective device is blocked or alarm signal is sent during operation, please try to
find out its reason with the help of self-diagnostic record. If the failure reason can not be
found at site, please inform the manufacturer NR or the agent for maintenance. Please
DO NOT simply press button “TARGET RESET” on the protection panel or re-energize
on the device.
Hardware circuit and operation status of the device are self-supervised continuously. If any
abnormal condition is detected, information or report will be displayed and a corresponding alarm
will be issued.
A minor abnormality may block a certain number of protections functions while the other functions
can still work. However, if severe hardware failure or abnormality, such as PWR module failure,
DC converter failure and so on, are detected, all protection functions will be blocked and the LED
“HEALTHY” will be extinguished and blocking output contacts BO_FAIL will be given. The
protective device then can not work normally and maintenance is required to eliminate the failure.
All the alarm signals and the corresponding handling suggestions are listed below.
Table 4.2-1 Alarm description
Blocking
No. Item Description
Device
Fail Signals
The device fails.
1 Fail_Device This signal will be pick up if any fail signal picks up and it will Blocked
drop off when all fail signals drop off.
Date: 2015-07-29
4 Supervi sion
Blocking
Device
Set value of any setting is out of scope.
2 Fail_Setting_OvRange This signal will pick up instantaneously and will be latched Blocked
unless the recommended handling suggestion is adopted.
Mismatch between the configuration of plug-in modules and
3 Fail_BoardConfig Blocked
the designing drawing of an applied-specific project.
After config file is updated, settings of the file and settings
saved on the device are not matched.
4 Fail_SettingItem_Chgd Blocked
This signal will pick up instantaneously and will be latched
Error is found during checking memory data (fault detector
DSP module).
5 FDBrd.Fail_Memory Blocked
Error is found during checking settings (fault detector DSP
module).
6 FDBrd.Fail_Settings Blocked
DSP chip is damaged (fault detector DSP module).
7 FDBrd.Fail_DSP This signal will pick up instantaneously and will be latched Blocked
AC current and voltage samplings are abnormal (fault detector
DSP module).
8 FDBrd.Fail_Sample This signal will pick up with a time delay of 50ms and will be Blocked
latched unless the recommended handling suggestion is
adopted.
Error is found during checking memory data (protection DSP
module).
9 ProtBrd.Fail_Memory Blocked
Error is found during checking settings (protection DSP
module).
10 ProtBrd.Fail_Settings Blocked
DSP chip is damaged (protection DSP module).
11 ProtBrd.Fail_DSP This signal will pick up instantaneously and will be latched Blocked
AC current and voltage samplings are abnormal (protection
DSP module).
12 ProtBrd.Fail_Sample This signal will pick up with a time delay of 50ms and will be Blocked
latched unless the recommended handling suggestion is
adopted.
13 FDBrd.Fail_HTM The HTM bus for data exchange is abnormal (fault detector Blocked
Date: 2015-07-29
4 Supervi sion
Blocking
Device
DSP module).
The HTM bus for data exchange is blocked for a long time
14 ProtBrd.Fail_HTM Blocked
(protection DSP module).
The alarm indicating that the tripping output module located in
15 Bx.Fail_Board Blocked
slot No.x (x=12~15) is in abnormal status.
The alarm indicating that the output contactor of the tripping
16 Bx.Fail_Output output module located in slot No.x (x=12~15) is in abnormal Blocked
status.
Alarm Signals
The device is abnormal.
17 Alm_Device This signal will be pick up if any alarm signal picks up and it Unblocked
will drop off when all alarm signals drop off.
18 Alm_Insuf_Memory The memory of MON plug-in module is insufficient. Unblocked
The device is in the communication test mode.
19 Alm_CommTest This signal will pick up instantaneously and will drop off Unblocked
instantaneously.
The error is found during MON module checking settings of
device.
20 Alm_Settings_MON Unblocked
This signal will pick up with a time delay of 10s and will be
latched unless re-powering or rebooting the device.
The error is found during checking the version of software
downloaded to the device.
21 Alm_Version Unblocked
This signal will pick up instantaneously and will drop off
instantaneously.
The active group set by settings in device and that set by
binary input are not matched.
22 Alm_BI_SettingGrp Unblocked
This signal will pick up instantaneously and will drop off
instantaneously.
23 Alm_TimeSyn Time synchronization abnormality alarm. Unblocked
The alarm is to indicate that the IEC103 file in the devi ce is
24 Alm_CfgFile_IEC103 Unblocked
invalid.
The alarm is to indicate that the device is in testing mode for
25 Alm_TestMode Unblocked
signal/trip output.
The alarm is to indicate that the board at slot x (x=10,11) is in
26 Bx.Alm_Board Unblocked
abnormal status.
The power supply of BI plug-in module in slot 04 is abnormal.
27 B10.Alm_OptoDC This signal will pick up with a time delay of 10s and will drop off Unblocked
with a time delay of 10s.
The device is in the GOOSE test mode.
28 Alm_GOOSETest This signal will pick up instantaneously and will drop off Unblocked
instantaneously.
Date: 2015-07-29
4 Supervi sion
Blocking
Device
The “master” process is alarm.
29 Alm_master This signal will pick up instantaneously and will drop off Unblocked
instantaneously.
Current fault detector element operates for longer than 10s
(fault detector DSP module).
30 FDBrd.Alm_Pkp Unblocked
This signal will pick up with a time delay of 10s and will drop off
with a time delay of 10s.
Current fault detector element operates for longer than 10s
(protection DSP module).
31 ProtBrd.Alm_Pkp Unblocked
This signal will pick up with a time delay of 10s and will drop off
with a time delay of 10s .
Protection Element Alarm Signals
Main transformer HV side 1 CT secondary circuit abnormality
32 Tr_HVS1.AlmL_CTS Unblocked
alarm.
Main transformer HV side 2 CT secondary circuit abnormality
33 Tr_HVS2.AlmL_CTS Unblocked
alarm.
Main transformer MV side CT secondary circuit abnormality
34 Tr_MVS.AlmL_CTS Unblocked
alarm.
Main transformer LV side CT secondary circuit abnormality
35 Tr_LVS.AlmL_CTS Unblocked
alarm.
Step-down transformer HV side big-ratio CT secondary circuit
36 ST_HVS#.AlmL_CTS Unblocked
abnormality alarm.
37 Tr_HVS.Alm_VTS Main transformer HV side VT secondary circuit failure alarm. Unblocked
38 Tr_MVS.Alm_VTS Main transformer MV side VT secondary circuit failure alarm. Unblocked
39 Tr_LVS.Alm_VTS Main transformer LV side VT secondary circuit failure alarm. Unblocked
40 Tr_HVS.Alm_VTNS Main transformer HV side VT neutral line failure alarm. Unblocked
41 Tr_MVS.Alm_VTNS Main transformer MV side VT neutral line failure alarm. Unblocked
42 Tr_LVS.Alm_VTNS Main transformer LV side VT neutral line failure alarm. Unblocked
43 Alm_52_CB1 Circuit breaker 1 auxiliary contact abnormality alarm. Unblocked
Alarm message indicating CT secondary circuit of main
47 Tr.87T.Alm_Diff Unblocked
transformer differential protection is abnormal.
Alarm message indicating that CT secondary circuit of main
48 Tr.87T.Alm_CTS Unblocked
transformer differential protection fails.
Alarm message indicating residual differential current of HV
49 Tr_HVS.64REF.Alm_Diff Unblocked
side of main transformer is abnormal.
Alarm message indicating residual differential current of MV
50 Tr_MVS.64REF.Alm_Diff Unblocked
side of main transformer is abnormal.
51 24.Alm The alarm stage of overe xcitation protection operates to issue Unblocked
Date: 2015-07-29
4 Supervi sion
Blocking
Device
alarm signal
Stage 1 of underfrequency protection operates to issue alarm
52 81U.UF1.Alm Unblocked
signal.
signal.
signal.
signal.
Stage 1 of underfrequency band accumulate protection
56 81U.UF1.Alm_Accu Unblocked
Stage 1 of overfrequency protection operates to issue alarm
60 81O.OF1.Alm Unblocked
signal.
signal.
signal.
signal.
Stage 1 of overfrequency band accumulate protection
64 81O.OF1.Alm_Accu Unblocked
Stage 1 of rate-of-frequency-change protection operates to
68 81R.RF1.Alm Unblocked
alarm.
alarm.
alarm.
alarm.
Date: 2015-07-29
4 Supervi sion
Blocking
Device
Main transformer HV side pole disagreement position contact
72 Tr_HVS.62PD.Alm Unblocked
abnormality alarm
Main transformer HV side breaker flashover protection circuit
73 Tr_HVS.50F.Alm Unblocked
breaker contact abnormality alarm.
Stage 1 of phase overcurrent element of main transformer HV
74 Tr_HVS.51PAlm1.Alm Unblocked
side operates to issue alarm signal.
Thermal overload protection of main transformer HV side
77 Tr_HVS.49.Alm Unblocked
operates to alarm.
Phase overvoltage protection alarm stage of main transformer
78 Tr_HVS.59PAlm.Alm Unblocked
HV side operates to issue alarm signal.
Residual overvoltage protection alarm stage of main
79 Tr_HVS.59GAlm.Alm Unblocked
transformer HV side operates to issue alarm signal.
Phase undervoltage protection alarm stage of main
80 Tr_HVS.27PAlm.Alm Unblocked
transformer HV side operates to issue alarm signal.
Main transformer MV side pole disagreement position contact
81 Tr_MVS.62PD.Alm Unblocked
abnormality alarm
Main transformer MV side breaker flashover protection circuit
82 Tr_MVS.50F.Alm Unblocked
breaker contact abnormality alarm.
Stage 1 of phase overcurrent element of main transformer MV
83 Tr_MVS.51PAlm1.Alm Unblocked
Thermal overload protection of main transformer MV side
86 Tr_MVS.49.Alm Unblocked
operates to alarm.
Phase overvoltage protection alarm stage of main transformer
87 Tr_MVS.59PAlm.Alm Unblocked
MV side operates to issue alarm signal.
88 Tr_MVS.59GAlm.Alm Unblocked
transformer MV side operates to issue alarm signal.
Phase undervoltage protection alarm stage of main
89 Tr_MVS.27PAlm.Alm Unblocked
transformer MV side operates to issue alarm signal.
90 Tr_LVS.59GAlm.Alm Unblocked
transformer LV side operates to issue alarm signal.
91 MR1.Sig1 Output alarm signal of channel 1 of mechanical protection 1. Unblocked
Date: 2015-07-29
4 Supervi sion
Blocking
Device
95 MR1.Alm_PwrLoss Power supervision alarm signal of mechanical protection 1. Unblocked
Table 4.2-2 Troubleshooting
No. Item Handling suggestion

Fail Signals
The signal is issued with other specific fail signals, and please refer to the
1 Fail_Device
handling suggestion other specific alarm signals.
Please reset setting values according to the range described in the
2 Fail_Setting_OvRange instruction manual, then re-power or reboot the device and the device will
restore to normal operation state.
1. Go to the menu “Information→Borad Info”, check the abnormality
information.
3 Fail_BoardConfig 2. For the abnormality board, if the board is not used, then remove, and if
the board is used, then check whether the board is installed properly and
work normally.
Please check the settings mentioned in the prompt message on the LCD ,
4 Fail_SettingItem_Chgd and go to the menu “Settings” and select “Confirm_Settings” item to
comfirm settings. Then, the device will restore to normal operation stage.
5 FDBrd.Fail_Memory Please inform the manufacture or the agent for repair.
6 FDBrd.Fail_Settings Please inform the manufacture or the agent for repair.
Chips are damaged and please inform the manufacture or the agent
7 FDBrd.Fail_DSP
replacing the module.
1. Please make the device out of service.
2. Then check if the analog input modules and wiring connectors connected
8 FDBrd.Fail_Sample
to those modules are installed at the position.
3. Re-power the device and the device will restore to normal operation state.
9 ProtBrd.Fail_Memory Please inform the manufacture or the agent for repair.
10 ProtBrd.Fail_Settings Please inform the manufacture or the agent for repair.
Chips are damaged and please inform the manufacture or the agent
11 ProtBrd.Fail_DSP
replacing the module.
1. Please make the device out of service.
2. Then check if the analog input modules and wiring connectors connected
12 ProtBrd.Fail_Sample
to those modules are installed at the position.
3. Re-power the device and the device will restore to normal operation state.
13 FDBrd.Fail_HTM Please inform the manufacture or the agent for repair.
14 ProtBrd.Fail_HTM Please inform the manufacture or the agent for repair.
15 Bx.Fail_Board Please inform the manufacture or the agent for repair.
16 Bx.Fail_Output Please check the output contactor of the module located in slot No.x.
Alarm Signals
17 Alm_Device The signal is issued with other specific alarm signals, and please refer to the
Date: 2015-07-29
4 Supervi sion

handling suggestion other specific alarm signals.
18 Alm_Insuf_Memory Please replace MON plug-in module.
No special treatment is needed, and disable the communication test function
19 Alm_CommTest
after the completion of the test.
20 Alm_Settings_MON Please inform the manufacture or the agent for repair.
Users may pay no attention to the alarm signal in the project commissioning
stage, but it is needed to download the latest package file (including correct
version checksum file) provided by R&D engineer to make the alarm signal
21 Alm_Version disappear. Then users get the correct software version. It is not allowed that
the alarm signal is issued on the device already has been put into service.
the devices having being put into service so that the alarm signal
disappears.
Please check the value of setting [Acti ve_Grp] and binary input of indiating
active group, and make them matched. Then the “ALARM” LED will be
22 Alm_BI_SettingGrp
extinguished and the corresponding alarm message will disappear and the
device will restore to normal operation state.
1. check whether the selected clock synchronization mode matches the

clock synchronization source;
2. check whether the wiring connection between the device and the clock
synchronization source is correct
23 Alm_TimeSyn 3. check whether the setting for selecting clock synchronization (i.e.
[Opt_TimeSyn]) is set correctly. If there is no clock synchronization, please
set the setting [Opt_TimeSyn] as ”No TimeSync”.
4. After the abnormality is removed, the “ALARM” LED will be extinguished

and the corresponding alarm message will disappear and the device will
restore to normal operation state.
Please check IEC103 version of the device, or, redownload the new IEC103
24 Alm_CfgFile_IEC103
configuration file.
Please wait. The alarm will automatically disappear after the event test is
25 Alm_TestMode
finished.
26 Bx.Alm_Board Please check the module located in slot No.x.
1. check whether the binary input module is connected to the power supply.
2. check whether the voltage of power supply is in the required range.
27 B10.Alm_OptoDC 3. After the voltage for binary input module restores to normal range, the
“ALARM” LED will be extinguished and the corres ponding alarm message
will disappear and the device will restore to normal operation state.
Please wait. The alarm will automatically disappear after the GOOSE
28 Alm_GOOSETest
communication test is finished.
29 Alm_master Please inform the manufacture or the agent for repair.
30 FDBrd.Alm_Pkp Please check secondary values and protection settings. If settings are not
31 ProtBrd.Alm_Pkp set reasonable to make fault detectors pick up, please reset settings, and
Date: 2015-07-29
4 Supervi sion

then the alarm message will disappear and the device will restore to normal
operation state.
Protection Element Alarm Signals
32 Tr_HVS1.AlmL_CTS
33 Tr_HVS2.AlmL_CTS
Please check the corresponding CT secondary circuit. After the abnormality
34 Tr_MVS.AlmL_CTS
is eliminated, the device returns to normal operation state.
35 Tr_LVS.AlmL_CTS
36 ST_HVS#.AlmL_CTS
37 Tr_HVS.Alm_VTS
Please check the corresponding VT secondary circuit. After the abnormality
38 Tr_MVS.Alm_VTS
is eliminated, the device returns to normal operation state.
39 Tr_LVS.Alm_VTS
40 Tr_HVS.Alm_VTNS
Please check the corresponding VT secondary circuit of neutral line. After
41 Tr_MVS.Alm_VTNS
the abnormality is eliminated, the device returns to normal operation state.
42 Tr_LVS.Alm_VTNS
43 Alm_52_CB1
44 Alm_52_CB2 Please check the auxiliary contact of the corresponding circuit breaker. After
45 Alm_52_CB3 the abnormality is eliminated, the device returns to normal operation state.
46 Alm_52_CB4
47 Tr.87T.Alm_Diff
48 Tr.87T.Alm_CTS
49 Tr_HVS.64REF.Alm_Diff
50 Tr_MVS.64REF.Alm_Diff
51 24.Alm
52 81U.UF1.Alm
53 81U.UF2.Alm
54 81U.UF3.Alm
55 81U.UF4.Alm
56 81U.UF1.Alm_Accu
57 81U.UF2.Alm_Accu
58 81U.UF3.Alm_Accu
Please check the logic of corresponding protection element in Chapter 3.
59 81U.UF4.Alm_Accu
60 81O.OF1.Alm
61 81O.OF2.Alm
62 81O.OF3.Alm
63 81O.OF4.Alm
64 81O.OF1.Alm_Accu
65 81O.OF2.Alm_Accu
66 81O.OF3.Alm_Accu
67 81O.OF4.Alm_Accu
68 81R.RF1.Alm
69 81R.RF2.Alm
70 81R.RF3.Alm
Date: 2015-07-29
4 Supervi sion

71 81R.RF4.Alm
72 Tr_HVS.62PD.Alm
73 Tr_HVS.50F.Alm
74 Tr_HVS.51PAlm1.Alm
77 Tr_HVS.49.Alm
78 Tr_HVS.59PAlm.Alm
79 Tr_HVS.59GAlm.Alm
80 Tr_HVS.27PAlm.Alm
81 Tr_MVS.62PD.Alm
82 Tr_MVS.50F.Alm
83 Tr_MVS.51PAlm1.Alm
86 Tr_MVS.49.Alm
87 Tr_MVS.59PAlm.Alm
88 Tr_MVS.59GAlm.Alm
89 Tr_MVS.27PAlm.Alm
90 Tr_LVS.59GAlm.Alm
91 MR1.Sig1
92 MR1.Sig2
93 MR1.Sig3
94 MR1.Sig4
95 MR1.Alm_PwrLoss Check the power supply of mechanical relays.
4.3 Relay Self-supervision
4.3.1 Relay Hardware Monitoring

All chips on DSP module are monitored to ensure whether they are damaged o r having errors. If
any one of them is detected damaged or having error, the alarm signal [ProtBrd.Fail_DSP] or
[FDBrd.Fail_DSP] is issued with the device being blocked.
4.3.2 Fault Detector Monitoring
If any fault detector picks up to trigger oscillography function, the corresponding binary input
changing report will be recorded in “IO_Events” menu with tripping report [TrigDFR] being issued.
If a fault detector on protection or fault detector DSP module keeps picking up for 10s, the
corresponding alarm signal [ProtBrd.Alm_Pkp] or [FDBrd.Alm_Pkp] will be issued without the
device being blocked.
Date: 2015-07-29
4 Supervi sion
4.3.3 Setting Checking
This relay has 10 setting groups, only one setting group could be activiated (is active) at a time.
The settings of active setting group are checked to ensure they are reasonable. If settings are
checked to be unreasonable or out of setting scopes, a corresponding alarm signal will be issued,
and the device is also blocked.
4.3.4 Memory Checking
Data in non-volatile memory, which are not changed after device energized, are always checked
during device normal operation, such as settings, pointers, etc. If these data changed abnormally,
the corresponding alarm [ProtBrd.Fail_Memory] or [FDBrd.Fail_Memory] will be issued.
4.3.5 Opto-coupler Power Supervision
Positive power supply of opto-coupler on each BI module that located in slot No.x (No.x is the slot
number) is continuously monitored, and if a failure or damage on the module is detected, then the
alarm signal [Bx.Alm_OptoDC] will be issued.
4.3.6 Output Tripping Circuit Supervision
State of binary outputs on each BO module that located in slot No.x (No.x is the slot number) is
continuously monitored. If any abnormality is detected on the module, the corresponding alarm
signal [Bx.Alm_Output] will be issued with equipment being blocked.
4.3.7 Test Mode Supervision
When protection equipment is in communication test mode the alarm signal [Alm_CommTest] is
issued without blocking equipment.
4.3.8 Hardware Configuration Supervision
Module configuration is checked automatically during equipme nt initialization, if plug-in module

configuration is not consistent to the design drawing of an applied -specific, the alarm signal
[Fail_BoardConfig] is issued with the equipment being blocked.
Date: 2015-07-29
4 Supervi sion
Date: 2015-07-29
5 Management
5 Management
Table of Contents
5.1 Overview ........................................................................................................................5-1

5.2 Measurement ................................................................................................................5-1
5.3 Event & Fault Records................................................................................................5-1

5.3.1 Introduction ...................................................................................................................... 5-1
5.3.2 Event Recording .............................................................................................................. 5-2
5.3.3 Disturbance and Fault Recording ..................................................................................... 5-2
5.3.4 Present Recording ........................................................................................................... 5-3
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5 Management
Date: 2015-07-29
5 Management
5.1 Overview
The relay also provides some auxiliary functions, such as on-line data metering, binary input
status, event and disturbance recording. All these functions make the relay meet the demands of
the modern power grid requirements.
5.2 Measurement
The device can continuously display the measured analogue input quantities, some internal flags
and calculated value based on the analogue input quantities can also be displayed. The
measurement data are displayed on the LCD of the relay front panel or by the software interface
on the local or remote PC. The analog quantities will be displayed as RMS values of the
secondary side of CT and VT.
The device samples 24 points per cycle. The RMS value is calculated in each interval and the LCD
display will be updated in every 0.5 second.
Users can view the measured data on LCD by navigating the menu “Measurements”, or by
PCS-Explorer software or substation automatic system (SAS) software.
The device has two DSP modules that are protection DSP module and fault detector DSP module,
the displayed values of the menu “Measurements->Measurement1” corresponds to the
measurement data of protection DSP module, and the displayed values of the menu
“Measurements->Measurement2” corresponds to the measurement data of fault detector DSP
module.
Please refer to the output signal list (for measurements) of Section “Inputs and Outputs” of each
protection element in Chapter 3 for detailed description and the concrete access path of each
measurement data. For a certain application, some measurement data listed in Chapter 3 may be
eliminated due to the scheme user required, so please look up the device on site for actual
displayed measurement data.
5.3 Event & Fault Records
5.3.1 Introduction
The device provides the following recording functions:
 Event recording
 Fault and disturbance recording
 Present recording
All the recorded information except for waveform can be viewed on local LCD or by printing.
Waveform must be printed or be extracted using PCS-Explorer software and a waveform software.
Date: 2015-07-29
5 Management
5.3.2 Event Recording
The device can store up to 1024 abnormality alarm reports and 1024 binary input status changing
reports respectively. All the records are stored in non-volatile memory, and when the available
space is fully occupied, the oldest report is automatically overwritten by the latest one.
 Abnormality alarm reports
Abnormality detected during relay self-supervision, secondary circuit abnormality or protection

alarm element will be logged as individual events.
 Binary input status changing reports
When binary input status changes, the changed information will be displayed on LCD and logged
as binary input change report at the same time.
5.3.3 Disturbance and Fault Recording
5.3.3.1 Application
Users can use the disturbance recorder to achieve a better understanding of the behavior of the
power network and related primary and secondary device during and after a disturbance.
Analyzing on the recorded data can help to resolve practical problem.
5.3.3.2 Design
Disturbance recorder is consisted of tripping report and fault waveform and it is triggered by fault
detector. The device can store 64 pieces of trip reports and waveforms in non-volatile memory.
When protection operates, the operating information will be displayed on LCD and logged as trip
record at same time, which can be viewed in trip report. Here fault recording includes two kinds of
cases:
1) Only the fault detector element operates.
2) The fault detector element operates along with the operation of protective elements.
1. Trip record capacity and information
The device can store 64 pieces of trip reports in non-volatile memory. If a new fault occurs when
the spaces are fully occupied, the oldest will be overwritten by the latest one.
A complete trip record includes the following items:
1) Sequence number
Each operation will be recorded with a sequence number in the report and displayed on LCD
screen.
2) Date and time of fault occurrence
The time resolution is 1 ms using the relay internal clock. Initiating date and time is when a fault
detector picks up. The relative time is the time when protection element operates to send tripping
signal after fault detector picks up.
Date: 2015-07-29
5 Management
3) Operating time
It is the relative time when protection element operates to send tripping signal relative to fault
detector element operating, the operating time of output relay is not included.
4) Protection element
The protection element that issues the tripping command will be shown. If no protection element
operates to trip but only fault detector element operates, the fault report will record the title of fault
detector element.
2. Fault waveform record capacity and information
MON module of the relay can store 64 pieces of fault waveform in non-volatile memory. If a new
fault occurs when 64 fault waveform recorders have been stored, the oldest will be overwritten by
the latest one.
Each fault record consists of all analog and digital quantities related to protection, such as original
current and voltage, differential current, alarm elements, and binary inputs and etc.
1) Only the fault detector element operates.
Each time recording includes several-cycle pre-disturbance waveform (the waveform cycle
number before triggering is configured via the communication setting
[Num_Cyc_PreTrigDFR], the default value is 3-cycle) and 8-cycle after-disturbance
waveform.
2) The fault detector element operates along with the operation of protective element.
Each time recording includes several-cycle pre-fault waveform (the waveform cycle number
is configured via the communication setting [Num_Cyc_PreTrigDFR], the default value is
3-cycle), 8-cycle after-fault waveform, several-cycle pre-tripping waveform (the waveform
cycle number is configured via the communication setting [Num_Cyc_PreTrigDFR], the
default value is 3-cycle), 8-cycle after-tripping waveform and all the current and voltage
waveform with disturbance between the fault detector element and the protective element.
5.3.4 Present Recording
Present recording is used to record the waveform of present operating device which can be
triggered manually on LCD of device or remotely through PCS-Explorer software. Recording
content of present recording is same to that of disturbance recording. Each time recording
includes several-cycle pre-disturbance waveform (the waveform cycle number is configured via
the communication setting [Num_Cyc_PreTrigDFR], the default value is 3-cycle) and 8-cycle
after-disturbance waveform.
Date: 2015-07-29
5 Management
Date: 2015-07-29
6 Hardware Description
Table of Contents
6.1 Overview ........................................................................................................................6-1

6.2 Typical Wiring ...............................................................................................................6-4
6.3 CT Requirement ...........................................................................................................6-5

6.4 Plug-in Module Terminal Definition ........................................................................6-6
6.4.1 Plug-in Module Arrangement............................................................................................ 6-6
6.4.2 PWR Module (Power Supply)........................................................................................... 6-7
6.4.3 MON Plug-in Module (Monitor)......................................................................................... 6-8
6.4.4 DSP Module 1 (Protection Calculation) ...........................................................................6-11
6.4.5 DSP Module 2 (Fault Detector Calculation) .....................................................................6-11
6.4.6 BI Module (Binary Input) ................................................................................................ 6-12
6.4.7 BO Module (Binary Output) ............................................................................................ 6-16
6.4.8 Mechanical Signal Input and Output Module (MR module) ............................................. 6-21
6.4.9 AI Module (Analog Input)................................................................................................ 6-23
6.4.10 DC Analog Input Module .............................................................................................. 6-25
6.4.11 HMI Module.................................................................................................................. 6-25
List of Figures
Figure 6.1-1 Hardware diagram.............................................................................................. 6-1
Figure 6.1-2 Front view of the device .................................................................................... 6-3
Figure 6.1-3 Typical rear view of the device (typical) ........................................................... 6-3
Figure 6.2-1 Typical wiring of PCS-985TE ............................................................................. 6-4
Figure 6.4-1 The module arrangement of PCS-985TE from rear view (typical) ................... 6-6
Figure 6.4-2 View of PWR plug-in module............................................................................. 6-7
Figure 6.4-3 View of MON plug-in module............................................................................. 6-9
Figure 6.4-4 Wiring of communication interface................................................................. 6-11
Figure 6.4-5 Rear view of DSP module ................................................................................ 6-12
Date: 2015-07-29
Figure 6.4-6 Debouncing technique..................................................................................... 6-12
Figure 6.4-7 View of BI plug-in module (NR1503) ............................................................... 6-13
Figure 6.4-8 View of BI plug-in module (NR1504) ............................................................... 6-14
Figure 6.4-9 View of BO plug-in module (NR1521A) ........................................................... 6-16
Figure 6.4-10 View of BO plug-in module (NR1521H) ......................................................... 6-17
Figure 6.4-11 Pin definition of signal output module NR1523A ......................................... 6-18
Figure 6.4-12 Pin definition of signal output module NR1523B ......................................... 6-19
Figure 6.4-13 Pin definition of signal output module NR1523C ......................................... 6-20
Figure 6.4-14 Pin definition of signal output module NR1523D ......................................... 6-21
Figure 6.4-15 Pin definition of mechanical relay IO module (x=1, 2) ................................. 6-22
Figure 6.4-16 Schematic diagram of CT circuit automatically closed.................................... 6-24
Figure 6.4-17 Pin definition of AC analog output module .................................................. 6-25
List of Tables
Table 6.1-1 Module configuration PCS-985TE....................................................................... 6-2
Table 6.4-1 Terminal definition and description of PWR plug-in module ............................ 6-7
Date: 2015-07-29
6.1 Overview
Output Relay
Binary Input
External
Protection
CT/VT A/D Calculation
DSP
Fault
A/D Detector Pickup
DSP Relay
ETHERNET
LCD +E
Clock SYN
Power
Uaux LED CPU
Supply
RJ45
Keypad
PRINT
Figure 6.1-1 Hardware diagram
The device adopts 32-bit microchip processor CPU as control core for management and
monitoring function, meanwhile, adopts high-speed digital signal processor DSP to be in charge of
all the protection calculation. 24 points are sampled in every cycle and parallel processing of
sampled data can be realized in each sampling interval to ensure ultra-high reliability and safety of
protection equipment.
The working process of the device is as follows: firstly, the current and voltage is converted into
small voltage signal and sent to DSP module after being filtered and converted by AD for
protection calculation and fault detector respectively. When DSP module completes all the
protection calculation, the result will be sent to 32-bit CPU on MON module to be recorded.
Protection DSP module carries out protection logic calculation, tripping output, and MON module
completes SOE (sequence of event) record, waveform recording, printing, communication
between protection and SAS and communication between HMI and CPU. The work process of
fault detector DSP module is similar to that of protection DSP module, and the only difference is,
when fault detector DSP module decides a fault detector picks up, only positive power supply of
output relay will be switched on.
The device is comprised of intelligent modules, except that few particular modules’ position cannot
be changed in the whole device (please refer to Figure 6.4-1 for details), the others like AI (analog
input) module such as AC current, AC voltage, DC current, and etc., and IO (input and output)
module such as binary input, tripping output, signal output, and etc can be flexibly configured
according to the remained slot positions.
Date: 2015-07-29
Table 6.1-1 Module configuration PCS-985TE
No. ID Module description Remark

1 NR1101 Management and monitor module (MON module) Standard
2 NR1156 Protection calculation and fault detector module (DSP module) Standard
3 NR1503/NR1504 Binary input module (BI module) Standard

4 NR1536 Mechanical signal input module (MR module) Optional
5 NR1521/NR1523 Binary output module (BO module) Standard
6 NR1401 Analog input module (AI module) Standard

7 NR1301 Power supply module (PWR module) Standard
8 Human machine interface module (HMI module) Standard
 MON module provides functions like management function, completed event record, setting
management, and etc.
 DSP modules can carry out filtering, sampling, protection calculation and fault detector
calculation.
 AI module converts AC current and voltage to low voltage signals with current transfo rmers
and voltage transformers respectively.
 BI module provides binary inputs via opto-couplers with rating voltage among
110V/125V/220V/250V (configurable)
 MR module provides signal inputs and outputs for the mechanical protection.
 BO module provides all kinds of binary output contacts, including signal output contacts and
tripping output contacts.
 PWR module converts DC 250/220/125/110V into different DC voltage levels for various
modules of the device.
 HMI module is comprised of LCD, keypad, LED indicator and multiplex RJ45 ports for user as
human-machine interface.
Following figures show front and rear views of the device respectively. Programmable LED
indicators (No.4-No.20) can be defined by user through PCS-Explore software.
Date: 2015-07-29
1 11
HEALTHY
2 12 PCS-985
ALARM
3
TRIP
13
TRANSFORMER RELAY
4 14
5 15
C GRP
6 16
7 17 ENT
ES
8 18
9 19
10 20
Figure 6.1-2 Front view of the de vice
Slot No. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1
NR1101D NR1156D NR1156D NR1401 NR1401 NR1401 NR1504A NR1536A NR1521A NR1523A NR1523A NR1523C NR1301A
5V BJ
1 2 3 1 2 3
4 5 6 4 5 6 BJJ BSJ
ON
OFF
DANGER DANGER DANGER 1 BO_COM1
2 BO_FAIL
3 BO_ALM
4 BO_COM2
5 BO_FAIL
6 BO_ALM
7 OPTO+
8 OPTO-
10 PWR+
11 PWR-
12 GND
Figure 6.1-3 Typical rear view of the de vice (typical)
Date: 2015-07-29
6.2 Typical Wiring
Opto+ AI module 2 (NR1401) AI module 3 (NR1401)

1001 +
PCS-985TE 0601
Channel 7
Ia
Three-phase current
Voltage
BI_TimeSyn 0801
1002 + U
input channel 5
0602 Ian 0802
0603 Un
1003 + BI_Print Ib
0604 Ibn
Channel 8
BI_Maintenance
Voltage
1004 + 0605 0803
Ic U
AI module 1 (NR1401) 0804
BI_RstTarg 0606 Icn Un
1005 +
0401 Ia
Three-phase current
BI_05 0607
input channel 1
Channel 9
1006 + 0402
Three-phase current
Ian Ia
Voltage
0805
input channel 6
0403 0608 U
BI_06 Ib Ian 0806
1007 + Un
0404 0609 Ib
Ibn
1008 0405 0610 Ibn
Not used Ic
Channel
Voltage
0611 0807
0406 Icn Ic U
10
1009 + BI_07 0808
0612 Icn Un
BI module (NR1504)
0407
Three-phase current
1010 + BI_08 Ia
Channel 1
input channel 2
Voltage
0408 0613
Channel
Voltage
Ian U 0809
BI_09 U
11
1011 + 0409 0614
Ib Un 0810 Un
0410
1012 + BI_10 Ibn
Channel 2
0411
Voltage
Ic 0615
Channel
Voltage
BI_11 U 0811
1013 + 0412 U
12
Icn 0616
Un 0812 Un
1014 + BI_12
0413 Ia
Channel 3
Three-phase current
Voltage
0617
input channel 3
Channel
Voltage
1015 + Not used 0414 Ian U 0813
U
13
0618 Un
1016 + BI_13 0415 Ib 0814
Un
0416 Ibn
Channel 4
BI_14
Voltage
1017 + 0417 0619
Channel
Ic
Voltage
U 0815
U
14
0418 Icn 0620
1018 + BI_15 Un 0816
Un
BI_16
Channel 5
1019 +
Voltage
0419 0621
Three-phase current
Channel
Ia U
Voltage
0817
U
input channel 4
15
BI_17 0420 Ian 0622 Un
1020 + 0818 Un
0421 Ib
1021 + BI_18
Channel 6
0422
Voltage
Ibn 0623
Channel
Voltage
U 0819
0423 U
16
1022 - COM- Ic 0624 Un 0820
0424 Un
Icn
Channel
Voltage
0821 U
17
MR IO Module (NR1536A) 0822 Un
1101 Reset Signal ResetInput
Channel
Voltage
0823
1201 1102 MR1.Input1 U
18
BO_Trip_1-1 0824
High Voltage
1202 Un
1103 MR1.Input2
Binary Input Signals of
1203 Mechanical protection
1104 MR1.Input3
1204 BO_Trip_1-2
1105 MR1.Input4
1205
1206 BO_Trip_1-3 1106 BO_MR1.Sig1_1
P110 PWR+
1207 1107 BO_MR1.Sig2_1
Power External DC power
1208 BO_Trip_1-4 1108 BO_MR1.Sig3_1
Supply P111 supply
PWR-
BO module 2 for tripping (NR1521A)
1209 1109 BO_MR1.Sig4_1 P107 OPTO+

Power supply for
1210 BO_Trip_2-1
1110 Common1 P108 opto-coupler (24V)
OPTO-
1211
PWR module
1111 BO_MR1.Sig1_2
1212 BO_Trip_2-2 P102
BO_FAIL
1112 BO_MR1.Sig2_2
1213 BO_ALM P103
1214 BO_Trip_2-3 1113 BO_MR1.Sig3_2 P101

COM
1215 1114 BO_MR1.Sig4_2
BO_FAIL P105
1216 BO_Trip_2-4 Common2 P106
1115 BO_ALM
1217 COM P104
1116 BO_MR1.Sig1_3
1218 BO_Trip_3-1 P112
1117 BO_MR1.Sig2_3
Grounding
1219
1118 BO_MR1.Sig3_3
Screw
1220 BO_Trip_3-2
1119 BO_MR1.Sig4_3 Grounding
1221
Bus
1222 BO_Trip_3-3 1120 Common3
1121 Pwr+
Module Power Input
1122 Pwr - Multiplex
RJ45 (Front)
1301 1401 1501 Ethernet A

1302 BO_Signal_1-1 1402 BO_Signal_9-1 BO_Signal_17-1
1502 Ethernet B
1303 1403 1503 Electrical
BO_Signal_1-2 BO_Signal_9-2 Ethernet to
Optional
1304 1404 1504 BO_Signal_17-2 Ethernet C SCADA

1305 1405 1505 Ethernet D
1506
1307 1407 1507 Optical
Optional
BO module 3 for signal (NR1523C)
BO module 1 for signal (NR1523A)
BO module 2 for signal (NR1523A)
Ethernet C
BO_Signal_2-2 BO_Signal_10-2 BO_Signal_18-2 Ethernet to
1308 1408 1508
MON module (NR1101)
SCADA
Ethernet D
1309 1409 1509
BO_Signal_3-1 BO_Signal_11-1 BO_Signal_19-1
COM(optional)
1310 1410 1510 0101 485-1A

cable with single point earthing
To the screen of other coaxial
1311 1411 1511 0102 485-1B

1512 0103 SGND
1313 1413 1513 0104
1314 BO_Signal_4 1414 BO_Signal_12 BO_Signal_20
1514
0101 SYN+
1315 1415
Clock SYN
1515
BO_Signal_5 BO_Signal_13 BO_Signal_21 0102 SYN-
1316 1416 1516
0103 SGND
1317 1417 1517
BO_Signal_6 BO_Signal_14 BO_Signal_22 0104
1318 1418 1518
1319 1419 1519 0105 RTS
PRINT

1520 0106 TXD
1321 1421 1521 0107 SGND
1522
Figure 6.2-1 Typical wiring of PCS-985TE
Date: 2015-07-29
6.3 CT Requirement
-Rated primary current Ipn:
According to the rated current or maximum load current of primary apparatus.
-Rated continuous thermal current Icth:
According to the maximum load current.
-Rated short-time thermal current Ith and rated dynamic current Idyn:
According to the maximum fault current.
-Rated secondary current Isn
-Accuracy limit factor Kalf:
Ipn Rated primary current (amps)

Icth Rated continuous thermal current (amps)
Ith Rated short-time thermal current (amps)
Idyn Rated dynamic current (amps)
Isn Rated secondary current (amps)
Kalf Accuracy limit factor (Kalf=Ipal/Ipn)
IPal Rated accuracy limit primary current (amps)
Performance verification
Esl > Esl′
Rated secondary limiting e.m.f (volts)

Esl
Esl = kalf×Isn×(Rct+Rbn)
Kalf Accuracy limit factor (Kalf=Ipal/Ipn)
IPal Rated accuracy limit primary current (amps)
Rct Current transformer secondary winding resistance (ohms)
Rated resistance burden (ohms)
Rbn
Rbn=Sbn/Isn 2
Sbn Rated burden (VAs)
Required secondary limiting e.m.f (volts)

Esl′
Esl′ = k×Ipcf ×Isn×(Rct+Rb)/Ipn
k stability factor = 2
Protective checking factor current (amps)
Ipcf
Same as the maximum prospective fault current
Rct Current transformer secondary winding resistance (ohms)
Date: 2015-07-29
Real resistance burden (ohms)

Rb
Rb=Rr+2×RL+Rc
Rc Contact resistance, 0.05-0.1 ohm (ohms)
RL Resistance of a single lead from relay to current transformer (ohms)
Rr Impedance of relay phase current input (ohms)
For example:
1. Kalf=30, Isn=5A, Rct=1ohm, Sbn=60VA

2
Esl = kalf×Isn×(Rct+Rbn) = kalf×Isn×(Rct+ Sbn/ Isn )
= 30×5×(1+60/25)=510V
2. Ipcf=40000A, RL=0.5ohm, Rr=0.1ohm, Rc=0.1ohm, Ipn=2000A
Esl′ = 2×Ipcf×Isn×(Rct+Rb)/Ipn
= 2×Ipcf ×Isn×(Rct+(Rr+2×RL+Rc))/Ipn
= 2×40000×5×(1+(0.1+2×0.5+0.1))/2000=440V
Thus, Esl > Esl′
6.4 Plug-in Module Terminal Definition
The device consists of PWR plug-in module, MON plug-in module, DSP plug-in module, AI plug-in
module, BI plug-in module, BO plug-in module etc. Terminal definitions and application of each
plug-in module are introduced as follows.
Terminal definitions are represents with its slot position and pin number. For example, contact
1301-1302 means terminal 01-02 of the module located in slot 13, i.e. 13 represents the slot
position, 01 (02) represents the pin number on the module.
6.4.1 Plug-in Module Arrangement
The module arrangement of the device from rear view is shown in the following figure.
NR1101D NR1156D NR1156D NR1401 NR1401 NR1401 NR1504A NR1536A NR1521A NR1523A NR1523A NR1523C NR1301A
BO module 1 for tripping
BO module 2 for signals

AC AI module 1
AC AI module 2
AC AI module 3
DSP module 1
DSP module 2
MON module
PWR module
MR module
BI module
Slot No.
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 P1
Figure 6.4-1 The module arrangement of PCS-985TE from rear view (typical)
Date: 2015-07-29
6.4.2 PWR Module (Power Supply)
PWR module is a DC/DC converter with electrical insulation between input and output. It has an
input voltage range as described in Chapter 2. The standardized output voltages are +5V and
+24V DC. The tolerances of the output voltages are continuously mo nitored.
The +5V DC output provides power supply for all the electrical elements that need +5V DC power
supply in this device. The +24V DC output provides power supply for the static relays of this
device.
The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device is
in cold reserve.
A 12-pin connector is fixed on PWR module. The terminal definition of the connector is described
as below.
NR1301
5V OK ALM
BO_ALM BO_FAIL
1 BO_COM1 P101
BO_FAIL
2 BO_FAIL P102
BO_ALM
3 BO_ALM P103
4 BO_COM2 P104
BO_FAIL
5 BO_FAIL P105
BO_ALM
6 BO_ALM P106
7 OPTO+
8 OPTO-
9
10 PWR+
11 PWR-
12 GND
Figure 6.4-2 View of PWR plug-in module
Terminal definition and description is shown as follows:
Table 6.4-1 Terminal definition and description of PWR plug-in module
Terminal No. Symbol Description
01 BO_COM1 Common terminal 1
02 BO_FAIL Device failure output 1 (01-02, NC)
03 BO_AL M Device abnormality alarm output 1 (01-03, NO)
Date: 2015-07-29
04 BO_COM2 Common terminal 2
05 BO_FAIL Device failure output 2 (04-05, NC)
06 BO_AL M Device abnormality alarm output 2 (04-06, NO)
07 OPTO+ Positive power supply for BI module (24V)
08 OPTO- Negative power supply for BI module (24V)
09 Blank Not used
10 PWR+ Positive input of power supply for the device (250V/220V/125V/110V)
11 PWR- Negative input of power supply for the device (250V/220V/125V/110V)
12 GND Grounded connection of the power supply
The standard rated voltage of PWR module is self-adaptive to 88~300Vdc. If the input voltage is
out of the range, an alarm signal (Fail_Device) will be issued. For non-standard rated voltage
power supply module please specify when place order, and check whether the rated voltage of
power supply module is the same as the voltage of power source before the device being put into
service.
PWR module provides terminal 12 and grounding screw for device grounding. Terminal 12 shall be
connected to grounding screw and then connected to the earth copper bar of panel via dedicated
grounding wire.
Effective grounding is the most important measure for a device to prevent EMI, so effective
grounding must be ensured before the device is put into service.
Like almost all electronic relays, the device contains electrolytic capacitors. These capacitors are
well known to be subject to deterioration over time if voltage is not applied periodically.
Deterioration can be avoided by powering the relays up once a year.
6.4.3 MON Plug-in Module (Monitor)
CAUTION!
Do NOT look into the end of an optical fiber connected to an optical port.
Do NOT look into an optical port/connector.
A direct sight to laser light may cause temporary or permanent blindness.
MON module consists of high-performance built-in processor, FLASH, SRAM, SDRAM, Ethernet
controller and other peripherals. Its functions include management of the complete device, human
machine interface, communication and waveform recording etc.
MON module uses the internal bus to receive the data from other modules of the device. It
communicates with the LCD module by RS-485 bus. This module comprises 100BaseT Ethernet
interfaces, RS-485 communication interfaces, PPS/IRIG-B differential time synchronization
interface and RS-232 printing interface.
Date: 2015-07-29
Modules with various combinations of memory and interface are available as shown in the table
below.
NR1102G NR1102M NR1102N NR1101D
TX TX
ETHERNET ETHERNET
RX RX
TX TX
RX RX
ETHERNET
TX
RX
Figure 6.4-3 View of MON plug-in module
Module ID Memory Interface Terminal No. Usage Physical La yer

3 FO Ethernet To SCADA Optical fiber ST
01 SYN+
02 SYN- To clock
RS-485 Twisted pair wire
03 SGND synchronization
NR1102G 256M DDR
04
05 RTS
RS-232 06 TXD To printer Cable
07 SGND
4 RJ45 Ethernet To SCADA
01 SYN+
02 SYN- To clock Twisted pair wire
RS-485
NR1102M 256M DDR
04
05 RTS
07 SGND
NR1102N 256M DDR 2 FO Ethernet To SCADA Optical fiber ST
RS-485 01 SYN+ To clock Twisted pair wire
Date: 2015-07-29
02 SYN- synchronization
03 SGND
04
05 RTS
07 SGND
01 A
02 B
RS-485 To SCADA
03 SGND
04
05 A
06 B Twisted pair wire
RS-485 To SCADA
07 SGND
NR1101D 256M DDR 08
09 SYN+
10 SYN- To clock
RS-485
12
13 RTS
15 SGND
16
The correct method of connection is shown in Figure 6.4-4. Generally, the shielded cables with two
pairs of twisted pairs inside shall be applied. One pair of the twisted pairs is used to connect the “+”
and “–” terminals of difference signal; the other is used to connect the signal ground of the
interface, i.e. connect the signal groundings of all the devices to a bus through the twisted pair.
The module reserves a free terminal for all the communication ports; the free terminal does not
need to be connected.
Date: 2015-07-29
Twisted pair wire

A 01
B 02
COM
cable with single point earthing
To the screen of other coaxial
SGND 03
04
Twisted pair wire

SYN+ 01
CLOCK SYN
SYN- 02
SGND 03
04
Twisted pair wire

RTS 05
PRINT
TXD 06
SGND 07
Figure 6.4-4 Wiring of communication interface
6.4.4 DSP Module 1 (Protection Calculation)

The DSP Module 1 consists of high-performance digital signal processor and other peripherals.
The functions of this module include analog data acquisition, calculation of protection logic and
tripping output etc.
6.4.5 DSP Module 2 (Fault Detector Calculation)
The DSP Module 2 consists of high-performance digital signal processor and other peripherals.
The functions of this module include analog data acquisition, calculation of fault detector elements
and providing positive power supply to output relay.
DSP module 1 and DSP module 2 have the same hardware configuration and are located in slot
02 and slot 03 respectively. The following figure shows rear view and terminal definition for the
DSP module.
Date: 2015-07-29
NR1156D
1 2 3
4 5 6
Figure 6.4-5 Rear view of DSP module
6.4.6 BI Module (Binary Input)
There are two kinds of BI modules available, NR1503 and NR1504. Up to 2 BI modules can be
equipped with one device. The rated voltage can be selected to be 110V, 125V, 220V and 250V.
The well-designed debouncing technique is adopted in this device, and the state change of binary
input within “Debouncing time” will be ignored. As shown in Figure 6.4-6.
Figure 6.4-6 Debouncing technique
Each BI module is with a 22-pin connector for 11 binary inputs (NR1503) or 18 binary inputs
(NR1504).
Date: 2015-07-29
For NR1503, each binary input has independent negative power input of opto-coupler, and can be
configurable. The terminal definition of the connector of BI plug -in module is described as below.
[BI_n] (n=01, 02,…,11 can be configured as a specified binary input by PCS-Explorer software.)
BI_01 01
NR1503 Opto01- 02
BI_02 03
Opto02- 04
BI_03 05
Opto03- 06
BI_04 07
Opto04- 08
BI_05 09
Opto05- 10
BI_06 11
Opto06- 12
BI_07 13
Opto07- 14
BI_08 15
Opto08- 16
BI_09 17
Opto09- 18
BI_10 19
Opto10- 20
BI_11 21
Opto11- 22
Figure 6.4-7 View of BI plug-in module (NR1503)
Terminal description for NR 1503 is shown as follows.

01 BI_01 Configurable binary input 1
02 Opto01- Negative supply of configurable binary input 1
Date: 2015-07-29

For NR1504, all binary inputs share one common negative power input, and is configurable. The
terminal definition of the connector of BI plug-in module is described as below. [BI_n] (n=01,
02,…,18 can be configured as a specified binary input by PCS-Explorer software.)
BI_01 01
NR1504 BI_02 02
BI_03 03
BI_04 04
BI_05 05
BI_06 06
BI_07 07
08
BI_08 09
BI_09 10
BI_10 11
BI_11 12
BI_12 13
BI_13 14
15
BI_14 16
BI_15 17
BI_16 18
BI_17 19
BI_18 20
BI_19 21
COM- 22
Figure 6.4-8 View of BI plug-in module (NR1504)
Terminal description for NR1504 is shown as follows.

01 BI_01 Positive supply of power supply of the module
08 Blank Not used
Date: 2015-07-29

15 Blank Not used
22 COM- Common terminal of negative supply of binary inputs
A default configuration is given for first four binary signals (BI_ 02, BI_03, BI_04, BI_05) of the first
BI plug-in module (located in slot No.10), and they are, [BI_TimeSyn], [BI_Print], [BI_Maintenance]
and [BI_RstTarg] respectively. They can also be configured as other signals. Because the first
binary signal [BI_02] is set as [BI_TimeSyn] by default (the state change information of binary
signal [BI_TimeSyn] does not need be displayed), new binary signal should be added to state
change message if it is set as other signal.
1. Binary input: [BI_TimeSyn]
It is used to receive clock synchronization signal from clock synchronization device , the binary
input [BI_TimeSyn] will change from “0” to “1” once pulse signal is received. When the device
adopts “Conventional” mode as clock synchronization mode (refer to section “Communication
Settings”), the device can receives PPM (pulse per minute) and PPS (pulse per second). If the
setting [Opt_TimeSyn] is set as other values, this binary input is invalid.
2. Binary input: [BI_Print]
It is used to manually trigger printing latest report when the equipment is configured as manual
printing mode by logic setting [En_AutoPrint]=0. The printer button is located on the panel usually.
If the equipment is configured as automatic printing mode ([En_AutoPrint ] =1), report will be
printed automatically as soon as it is formed.
3. Binary input: [BI_Maintenance]
It is used to block communication export when this binary input is energized. During device
maintenance or testing, this binary input is then energized not to send reports via communication
port, local display and printing still work as usual. This binary input should be de-energized when
the device is restored back to normal.
4. Binary input: [BI_RstTarg]
It is used to reset latching signal relay and LCD displaying. The reset is done by pressing a button
on the panel.
Date: 2015-07-29
NOTICE!
The rated voltage of binary input is optional: 110V, 125V, 220V or 250V, which MUST be
specified when placing an order. It is necessary to CHECK whether the rated voltage of
BI module complies with site DC supply rating before put the relay in service.
6.4.7 BO Module (Binary Output)
6.4.7.1 Tripping Output Module (NR1521)
Two standard binary output modules, NR1521A, and NR1521H, can be selected. Output contact
can be configured as a specified tripping output contact by PCS-Explorer software according to
user requirement.
Up to four tripping output modules (located in slot 12) can be equipped with one device.
The details of the BO modules are as follows:
 NR1521A
NR1521A can provide 11 output contacts controlled by fault detector.
01
BO_Trip_01
NR1521A 02
03
BO_Trip_02
04
05
BO_Trip_03
06
07
BO_Trip_04
08
09
BO_Trip_05
10
11
BO_Trip_06
12
13
BO_Trip_07
14
15
BO_Trip_08
16
17
BO_Trip_09
18
19
BO_Trip_10
20
21
BO_Trip_11
22
Figure 6.4-9 View of BO plug-in module (NR1521A)
 NR1521H
NR1521H can provide 11 output contacts controlled by fault detector. The first four output contacts
are in parallel with instantaneous operating contacts which are recommend ed to be configured as
Date: 2015-07-29
fast signaling contacts.
01
BO_Trip_01
NR1521H 02
03
BO_Trip_02
04
05
BO_Trip_03
06
07
BO_Trip_04
08
09
BO_Trip_05
10
11
BO_Trip_06
12
13
BO_Trip_07
14
15
BO_Trip_08
16
17
BO_Trip_09
18
19
BO_Trip_10
20
21
BO_Trip_11
22
Figure 6.4-10 View of BO plug-in module (NR1521H)
6.4.7.2 Signal Output Module
Four standard binary output modules, NR1523A, NR1523B, NR1523C, and NR1523D, can be
selected to provide protection operation signal and abnormality alarm signal.
Up to four signal output modules (located in slot 08, 09, 10 and 15 respectively) can be equipped
with one device.
The details of the BO modules are as follows:
 NR1523A
The NR1523A module is a standard binary output module for signal, which can provide 8 signal
relays (11 signal output contacts, for the first three signal output relays, each relay includes two
contacts) without controlled by fault detector. All the contacts are normally open (NO) contacts,
and among which, [BO_Signal_6], [BO_Signal_7] and [BO_Siganl_8] are magnetic latched NO
contacts.
All contacts of the module can be configured as specified signal output conta cts of certain
protections by PCS-Explorer software according to users’ requirement. [BO_Signal_ 4] and
[BO_Siganl_5] are recommended to be configured as alarm signal output contacts, other contacts
are recommended to be configured as tripping signal output contacts.
A 22-pin connector is fixed on the front of this module. The pin definition of the connector is
Date: 2015-07-29
described as below.
NR1523A
NR1523A
01 01
BO_Signal_1-1 BO_Signal_1-1
02 02
03 03
04 04
05 05
06 06
07 07
08 08
09 09
10 10
11 11
12 12
13 13
BO_Signal_4 BO_Signal_4
14 14
15 15
16
16
17 17
18
18
19 19
20 20
21 21
22 22
Figure 6.4-11 Pin definition of signal output module NR1523A
 NR1523B
The NR1523B module is a standard binary output module for signal, which can provide 11 signal
output contacts without controlled by fault detector. Among those contacts, [BO_Signal_5] and
[BO_Siganl_6] are normally closed (NC) contacts, others are normally open (NO) contacts. All
contacts of the module can be configured as specified signal output contacts of some protection s
by PCS-Explorer software according to user requirement. Besides, only the contact [BO_Siganl_8]
is a magnetic latched NO contact.
described as below.
Date: 2015-07-29
NR1523B
NR1523B
01 01
02 02
03 03
04 04
05 05
06 06
07 07
08 08
09 09
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
21 21
22 22
Figure 6.4-12 Pin definition of signal output module NR1523B
 NR1523C
The NR1523C module is a standard binary output module for signal, which can provide 11 signal
output contacts without controlled by fault detector. Among those contacts, [BO_Signal_3-2],
[BO_Signal_5] and [BO_Siganl_7] are normally closed (NC) contacts, others are normally open
(NO) contacts. All contacts of the module can be configured as specified signal output contacts of
some protections by PCS-Explorer software according to user requirement.
described as below.
Date: 2015-07-29
NR1523C
NR1523C
01 01
02 02
03 03
04 04
05 05
06 06
07 07
08 08
09 09
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
21 21
22 22
Figure 6.4-13 Pin definition of signal output module NR1523C
 NR1523D
The NR1523D module is a standard binary output module for signal, which can provide 11 signal
output contacts without controlled by fault detector. All the contacts are normally open (NO), and
among which, only [BO_Siganl_8] is magnetic latched NO contact. All contacts of the module can
be configured as specified signal output contacts of certain protections by PCS-Explorer software
according to users’ requirement.
described as below.
Date: 2015-07-29
NR1523D
NR1523D
01 01
02 02
03 03
04 04
05 05
06 06
07 07
08 08
09 09
10 10
11 11
12 12
13 13
14 14
15 15
16
16
17 17
18
18
19 19
20 20
21 21
22 22
Figure 6.4-14 Pin definition of signal output module NR1523D
6.4.8 Mechanical Signal Input and Output Module (MR module)
NR1536A (220Vdc) and NR1536B (110Vdc/125V) are input and output modules (IO module) for
mechanical protection.
At most two MR modules can be equipped located in slot 11.
described as below.
Date: 2015-07-29
NR1536A NR1536B
MR IO Module x (NR1536A/B)
01 Reset Signal ResetInput
02 MRx.Input1
High Voltage
Binary Input
03 Signals of MRx.Input2
Mechanical MRx.Input3
04
protection
05 MRx.Input4
06 BO_MRx.Sig1_1
07 BO_MRx.Sig2_1
08 BO_MRx.Sig3_1
09 BO_MRx.Sig4_1
10 Common1
11 BO_MRx.Sig1_2
12 BO_MRx.Sig2_2
13 BO_MRx.Sig3_2
14 BO_MRx.Sig4_2
15 Common2
16 BO_MRx.Sig1_3
17 BO_MRx.Sig2_3
18 BO_MRx.Sig3_3
19 BO_MRx.Sig4_3
20 Common3
21 Pwr+
Module Power Input
22 Pwr -
Figure 6.4-15 Pin definition of mechanical relay IO module (x=1, 2)
Pin No. Symbol Description

Reset input, when a reset signal is issued, the corresponding magnetic latched
01 ResetInput
contacts of mechanical signals are reset.
Mechanical signal inputs
st
1 group output contacts (magnetic latched contact)
06-10 BO_MR x.Sig1_1 Output alarm signal contact 1 of channel 1 of mechanical protection x (NO contact).
2nd group output contacts
rd
3 group output contacts
Date: 2015-07-29
Pin No. Symbol Description

Power supply input of the module
21 Pwr+ Positive pole of power of the board connected to DC power supply

22 Pwr- Negative pole of power of the board connected to DC power supply
6.4.9 AI Module (Analog Input)
The analog input module is applicable for power plant with conventional VT and CT, the module is
not required if the device is used with ECT/EVT. The analog input module can transform these
high AC input values to relevant low AC output value for the DSP module. The transformers are
used both to step-down the currents and voltages to levels appropriate to the electronic circuitry of
this device and to provide effective isolation between this device and the power system. A low
pass filter circuit is connected to each transformer (CT or VT) secondary circuit for reducing the
noise of each analog AC input signal.
NOTICE!
The rated value of the input current transformer is optional: 1A or 5A. The rated value of
the CT MUST be definitely declared in the technical scheme and the contract.
Maximum linear range of the current converter is 40In.
Because the rated value of the input current transformer is optional, it is nece ssary to
CHECK whether the rated values of the current transformer inputs are accordant to the
demand of the engineering before putting the device into operation.
For AI module, if the plug is not put in the socket, external CT circuit is closed itself. It is shown as
below.
Plug
Socket
In
Out
plug is not put in the socket
Date: 2015-07-29
In
Out
Put the plug in the socket
Figure 6.4-16 Schematic diagram of CT circuit automatically closed
The analog input module NR1401 can provide 12-channel analog signal inputs and each channel
can be configured as a specified current or voltage channel by PCS-Explorer software according
to user requirements. Up to four NR1401 modules can be configured for the device. Three kinds of
AI modules can be used for the device:
1) 12-channel current AI module;
2) 12-channel voltage AI module;
3) 6-channel current and 6-channel voltage AI module.
4) 10-chanel current and 2-channel voltage AI module.
The rated values of current inputs are selected at order.
described as below.
Date: 2015-07-29
NR1401
NR1401 NR1401 NR1401 NR1401
I1 01 I1n 02 U1 01 U1n 02 I1 01 I1n 02 I1 01 I1n 02
I2 03 I2n 04 U2 03 U2n 04 I2 03 I2n 04 I2 03 I2n 04
Current input
I3 05 I3n 06 U3 05 U3n 06 I3 05 I3n 06 I3 05 I3n 06
I4 07 I4n 08 U4 07 U4n 08 I4 07 I4n 08 I4 07 I4n 08
Current input
I5 09 I5n 10 U5 09 U5n 10 I5 09 I5n 10 I5 09 I5n 10
Voltage input
Current input
I6 11 I6n 12 U6 11 U6n 12 I6 11 I6n 12 I6 11 I6n 12
I7 13 I7n 14 U7 13 U7n 14 U1 13 U1n 14 I7 13 I7n 14
I8 15 I8n 16 U8 15 U8n 16 U2 15 U2n 16 I8 15 I8n 16
Voltage input
I9 17 I9n 18 U9 17 U9n 18 U3 17 U3n 18 I9 17 I9n 18
I10 19 I10n 20 U10 19 U10n 20 U4 19 U4n 20 I10 19 I10n 20
Voltage
I11 21 I11n 22 U11 21 U11n 22 U5 21 U5n 22 U1 21 U1n 22
input
I12 23 I12n 24 U12 23 U12n 24 U6 23 U6n 24 U2 23 U2n 24
12I 12U 6I6U 10I2U
Figure 6.4-17 Pin definition of AC analog output module
In above figure, I1~I12 and U1~U12 are polarity terminals of corresponding relevant voltage and
current inputs respectively.
If user needs other analog input configuration, please declare in the technical scheme and the
contract.
6.4.10 DC Analog Input Module
The DC analog input module located in slot No.30 is reserved at present.
6.4.11 HMI Module
The display panel consists of liquid crystal display module, keyboard, LED and ARM processor.
The functions of ARM processor include display control of the liquid crystal display module,
keyboard processing, and exchanging data with the CPU through serial port etc. The liquid crystal
display module is a high-performance grand liquid crystal panel with soft back lighting, which has a
user-friendly interface and an extensive display range.
Date: 2015-07-29
Date: 2015-07-29
7 Settings
7 Settings
Table of Contents
7 Settings ................................................................................................ 7-a
7.1 Overview........................................................................................................................ 7-1
7.2 System Settings .......................................................................................................... 7-1

7.2.1 Setting List .......................................................................................................................7-1
7.2.2 Access Path .....................................................................................................................7-1
7.3 Main Transformer System Settings........................................................................ 7-1

7.3.1 Setting List .......................................................................................................................7-1
7.3.2 Access Path .....................................................................................................................7-3
7.4 Configuration Settings .............................................................................................. 7-3

7.4.1 Setting List .......................................................................................................................7-3
7.4.2 Access Path .....................................................................................................................7-4
7.5 Device Setup Settings ............................................................................................... 7-5

7.5.1 Device Settings ................................................................................................................7-5
7.5.2 Communication Settings ..................................................................................................7-6
7.5.3 Label Settings ................................................................................................................7-10
7.6 Protection Settings ...................................................................................................7-10
List of Tables
Table 7.2-1 List of system settings ........................................................................................ 7-1
Table 7.3-1 List of main transformer system settings .......................................................... 7-1
Table 7.4-1 List of configuration settings .............................................................................. 7-3
Table 7.5-1 List of device settings ......................................................................................... 7-5
Table 7.5-2 List of communication settings .......................................................................... 7-6
Table 7.5-3 List of label settings .......................................................................................... 7-10
PCS-985TE Transformer Protection 7-a
Date: 2015-07-29
7 Settings
7-b PCS-985TE Transformer Protection
Date: 2015-07-29
7 Settings
7.1 Overview
Settings are classified into two kinds, protection settings and common settings. Each protection
element has its independent setting menu which are given detailed description in Chapter 3. In this
chapter only common settings are introduced. Common settings consist of device settings,
communication settings, label settings, system settings and configuration settings.
The device has ten protection setting groups to coordinate with the different modes of power
system operation. One of these setting groups is assigned to be active. However, common
settings are shared by all protection setting groups, and settings of protection element are set
according to secondary values.
7.2 System Settings

7.2.1 Setting List
Table 7.2-1 List of system settings
No. Settings item Range Description
The number of active setting group, ten setting

1 Acti ve_Grp 1~31 groups can be configured for protection settings, and
only one is active at a time.
2 Opt_SysFreq 0: 50Hz; 1: 60Hz Select system working frequency.
Name of the protected primary equipment, such as

3 PrimaryEquip_Name Ma x 20 characters
generator, transformer, etc.
7.2.2 Access Path
MainMenuSettingsSystem Settings
7.3 Main Transformer System Settings

7.3.1 Setting List
Table 7.3-1 List of main transformer system settings

The power capacity of main transformer, it shall be
1 Tr.Sn_Plate 0.01~2000.00(MVA)
configured as the value stated in the name plate.
The rated primary voltage of main transformer HV side
2 Tr_HVS.U1n_Plate 0.01~2000.00 (kV)
that stated in the name plate.
The rated primary voltage of main transformer MV side
3 Tr_MVS.U1n_Plate 0.01~2000.00 (kV)
The rated primary voltage of main transformer LV side
4 Tr_LVS.U1n_Plate 0.01~2000.00 (kV)
0: Wye The winding connection mode of HV side of main
5 Tr_HVS.WdgConn
1: Delta transformer.
PCS-985TE Transformer Protection 7-1
Date: 2015-07-29
7 Settings
0: Wye The winding connection mode of MV side of main

6 Tr_MVS.WdgConn
0: Wye The winding connection mode of LV side of main
7 Tr_LVS.WdgConn
The relative o’clock for main transformer MV side
8 Tr_MVS.Clk_WRT_HVS 0~11(clk)
winding relative to main transformer HV side winding.
The relative o’clock for main transformer LV side
9 Tr_LVS.Clk_WRT_HVS 0~11(clk)
winding relative to main transformer HV side winding.
The primary rated voltage of VT of main transformer HV
10 Tr_HVS.U1n 0.01~2000.00(kV)
side.
The secondary rated voltage of VT of main transformer
11 Tr_HVS.U2n 0.01~300.00(V)
HV side.
The secondary rated broken-delta voltage of VT of
12 Tr_HVS.U2n_Delt 0.01~300.00(V)
main transformer HV s ide.
The primary rated voltage of VT of main transformer
13 Tr_MVS.U1n 0.01~2000.00(kV)
MV side.
The secondary rated voltage of VT of main transformer
14 Tr_MVS.U2n 0.01~300.00(V)
MV side.
15 Tr_MVS.U2n_Delt 0.01~300.00(V)
main transformer MV side.
The primary rated voltage of VT of main transformer LV
16 Tr_LVS.U1n 0.01~2000.00(kV)
side.
The secondary rated voltage of VT of main trans former
17 Tr_LVS.U2n 0.01~300.00(V)
LV side.
18 Tr_LVS.U2n_Delt 0.01~300.00(V)
main transformer LV side.
The primary rated current of CT of HV side 1 of main
19 Tr_HVS1.I1n 0~60000(A)
transformer.
The secondary rated current of CT of HV side 1 of main
20 Tr_HVS1.I2n 1A/5 A
transformer.
The primary rated current of CT of HV side 2 of main
21 Tr_HVS2.I1n 0~60000(A)
transformer.
The secondary rated current of CT of HV side 2 of main
22 Tr_HVS2.I2n 1A/5 A
transformer.
The primary rated current of CT of MV side of main
23 Tr_MVS.I1n 0~60000(A)
transformer.
The secondary rated current of CT of MV side of main
24 Tr_MVS.I2n 1A/5 A
transformer.
The primary rated current of CT of LV side of main
25 Tr_LVS.I1n 0~60000(A)
transformer.
The secondary rated current of CT of LV side of main
26 Tr_LVS.I2n 1A/5 A
transformer.
The primary rated current of the big-ratio CT of HV side
27 ST_HVS#.I1n 0~60000(A)
of step-down transformer.
7-2 PCS-985TE Transformer Protection
Date: 2015-07-29
7 Settings
The secondary rated current of the big-ratio CT of HV

28 ST_HVS#.I2n 1A/5 A
side of step-down transformer.
The primary rated current of neutral point residual CT of
29 Tr_HVS.I1n_NP 0~60000(A)
HV side of main transformer.
The secondary rated current of neutral point residual
30 Tr_HVS.I2n_NP 1A/5 A
CT of HV side of main transformer.
The primary rated current of neutral point residual CT of
31 Tr_MVS.I1n_NP 0~60000(A)
MV side of main transformer.
The secondary rated current of neutral point residual
32 Tr_MVS.I2n_NP 1A/5 A
CT of MV side of main transformer.
7.3.2 Access Path
MainMenuSettingsTr Sys Settings
7.4 Configuration Settings

Configuration settings are associated with application-specific primary layout of generator and
excitation transformer, tripping logics. Configuration settings are usually configured in factory or
configured by field commission engineer according to the design drawing and project requirement.
Modifying configuration settings need special warrant to input the special password.
7.4.1 Setting List
Table 7.4-1 List of configuration settings

Logic setting to configure which output relays
will delay drop-off since corresponding tripping
signal drop-off. If any bit is set as “1”, the
1 Cfg_Ext_TrpOut 0-3FFFFFFF corresponding output relay will delay drop-off
since corresponding tripping signal drop-off.
DDO (delay drop-off) time is decided by
[t_Ext_TrpOut].
DDO (delay drop-off) time of tripping output
2 t_Ext_TrpOut 0.00~0.45(s)
relays, its default value is 140ms.
Reverse the polarity direction of CT of main
transformer HV side 1. Its default value is “0”
and it should be set as “1” if the polarity direction
of CT of main transformer HV side 1 on site is
3 Tr_HVS1.En_RevCT 0/1 reversed due to incorrect wiring connecting,
then the program will reverse the main
transformer HV side 1 current polarity before
calculation. The following eight settings are
similar to it.
4 Tr_HVS2.En_RevCT 0/1 Reverse the polarity direction of CT of main
Date: 2015-07-29
7 Settings
transformer HV side 2.
5 Tr_MVS.En_RevCT 0/1
6 Tr_LVS.En_RevCT 0/1
transformer LV side.
Reverse the polarity direction of the big-ratio CT
7 ST_HVS#.En_RevCT 0/1
of HV side of step-down transformer 1.
The neutral line failure judge coefficient for VT of
8 Tr_HVS.K_VTNS 0.10~1.00 HV side of main transformer. The default value
is 0.2.
Logic setting of enabling/disabling VT neutral
0: disable
9 Tr_HVS.En_VTNS line failure supervision function for VT of HV side
1: enable
of main transformer.
10 Tr_MVS.K_ VTNS 0.10~1.00 MV side of main transformer. The default value
is 0.2.
0: disable
11 Tr_MVS.En_VTNS line failure supervision function for VT of MV
1: enable
side of main transformer.
12 Tr_LVS.K_VTNS 0.10~1.00 LV side of main transformer. The default value is
0.2.
0: disable
13 Tr_LVS.En_VTNS line failure supervision function for VT o f LV side
1: enable
of main transformer.
Logic setting of enabling non-volatile memory
for accumulate duration of underfrequency
14 81U.En_NVM_ Accu 0/1 protection. When it is set as “1”, the accumulate
duration of underfrequency protection will not be
cleared even when the device is not powered.
Logic setting of enabling non-volatile memory
for accumulate duration of o verfrequency
15 81O.En_NVM_ Accu 0/1 protection. When it is set as “1”, the accumulate
duration of overfrequency protection will not be
cleared even when the device is not powered.
The length of measuring window of
16 81R.MeasWindow 3~25
rate-of-frequency-change.
7.4.2 Access Path
MainMenuSettingsConfig Settings
Date: 2015-07-29
7 Settings
7.5 Device Setup Settings

7.5.1 Device Settings
7.5.1.1 Setting List
Table 7.5-1 List of device settings
No. Setting Item Range Description
Select encoding format of header (HDR) file

1 HDR_EncodedMode GB18030, UTF-8 COMTR ADE recording file. Default value is
“UTF-8”.
Select the caption language sent to SAS via

IEC103 protocol. Default value is 0.
2 Opt_Caption_103 0~2
0: Current language; 1: Fi xed Chinese; 2: Fixed
English
Enable/disable moveable disk to realize the

3 En_MDisk 0, 1 backup and recovery function.
Default value is 0, and the function is reserved.
Voltage level of binary input for the module that

located in slot No.x. For high-voltage BI
0:24V, 1:48V
modules, 110V, 125V or 220V can be set
4 Bx.Un_BinaryInput 2:110V, 3:220V, 4: 30V,
according to the actual requirement. For
5: 125V
low-voltage BI modules, 24V, 30V or 48V can be
set according to the actual requirement.
7.5.1.2 Setting Description
1. [HDR_EncodedMode]
Default value of [HDR_EncodedMode] is 1 (i.e. UTF-8 code) and please set it to 0 (i.e. GB18030)
according to the special requirement.
2. [Opt_Caption_103]
0: the group caption of IEC103 protocol is in current language
1: the group caption of IEC103 protocol is in Chinese
2: the group caption of IEC103 protocol is in English
It is recommended to be set as “1”, if the device communicates with SCADA in Chinese.
3. [En_MDisk]
1: Use moveable disk to realize the backup and recovery function.
0: Moveable disk will be disabled.
A moveable mdisk is implemented on the MON plug-in module to backup and restore programs,
settings and configurations.
Date: 2015-07-29
7 Settings
If MON plug-in module is broken, remove the mdisk and put it into a new MON plug -in module, use
the menu on HMI to restore the backup programs and configurations. If DSP plug-in module is
broken, after a new DSP plug-in module is installed, use the menu on HMI to restore the backup
programs and configurations. If the moveable mdisk is broken, after a new mdisk is installed on
the MON plug-in module, use the menu on HMI to back up the current programs and
configurations into the new mdisk.
The default setting is 0.
7.5.1.3 Access Path
MainMenuSettingsDevice SetupDevice Settings
7.5.2 Communication Settings
Table 7.5-2 List of communication settings
000.000.000.000~
1 IP_LAN1 IP address of Ethernet port 1.
255.255.255.255
000.000.000.000~
2 Mask_LAN1 Subnet mask of Ethernet port 1.
255.255.255.255
000.000.000.000~
255.255.255.255
000.000.000.000~
255.255.255.255
5 En_LAN2 0: disable, 1: enable Enable/disable the IP address of port 2.
000.000.000.000~
255.255.255.255
000.000.000.000~
255.255.255.255
000.000.000.000~
255.255.255.255
000.000.000.000~
255.255.255.255
000.000.000.000~
12 Gateway Gateway of router.
255.255.255.255
Enable/disable sending message in broadcast mode via

13 En_Broadcast1 0: disable, 1: enable
network 1. (IEC103).
Date: 2015-07-29
7 Settings



Communication address between the protective device

17 Addr_RS485A 0~255
with the SCADA or RTU via RS-485 serial port 1.
4800,9600,19200,
18 Baud_RS485A 38400,57600,115200 Baud rate of rear RS-485 serial port 1.
(bps)
0: IEC103;
1: MODBUS;
19 Protocol_RS485A Communication protocol of rear RS-485 serial port 1.
2: DNP;
3: DLT645.
Communication address between the protective device

20 Addr_RS485B 0~255
with the SCADA or RTU via RS-485 serial port 2.
4800,9600,19200,
21 Baud_RS485B 38400,57600,115200 Baud rate of rear RS-485 serial port 2.
(bps)
0: IEC103;
1: MODBUS;
22 Protocol_RS485B Communication protocol of rear RS-485 serial port 2.
2: DNP;
3: DLT645.
Threshold value of sending measurement values to

23 Threshold_Measmt_Net 0.00~100.00(%) SCAD A through IEC103 or IEC61850 protocol.
Default value: “1%”.
The time period when the equipment sends

24 Period_Measmt_Net 0~65535s measurement data to SCADA through IEC103 protocol.
Default value:”60”.
Select the format of measurement data sent to SCADA

25 Format_Measmt 0, 1
through IEC103 protocol.
4800,9600,19200,
26 Baud_Printer 38400,57600,115200 Baud rate of printer port.
(bps)
0: disable
27 En_AutoPrint Enable/disable automatic printing function.
1: enable
Date: 2015-07-29
7 Settings
Conventional
SAS
28 Opt_TimeSyn Select the mode of time synchronization of equipment.
Ad vanced
NoTimeSyn
000.000.000.000~ The address of the external SNTP clock synchronization

29 IP_Server_SNTP
255.255.255.255 server sending SNTP message to the equipment.
The local time zone also refered to as the hour offset

30 OffsetHour_UTC -12~12hrs
hour from UTC .
31 OffsetMinute_UTC 0~60 The offset minute of local time from UTC.
32 IEDNAME The IED name defined in 61850 protocol.
The recorded waveform cycle number before triggering,

33 Num_Cyc_PreTrigDFR 0~140(cycle)
the default value is 3-cycle.
7.5.2.2 Setting Description
1. [En_LANx] (x= 2, 3, 4)
These setting are used to enable/disable IP addresses of Ethernet 2, 3 and 4 respectively. IP

address of Ethernet 1 is enabled fixedly.
“1”: enable the IP address of Ethernet port and the corresponding IP address setting is need to be
set.
“0”: disable the IP address of Ethernet port and the corresponding IP address setting is not need to
be set.
2. [En_Broadcast]
This setting is only used for IEC 103 protocol. If NR network IEC103 protocol is used, the setting
must be set as “1”.
0: the device does not send UDP messages through network;
1: the device sends UDP messages through network.
3. [Protocol_RS485x] (x=A, B)
The setting is used to select the communication protocol of rear RS-485 serial port x.
0: IEC 60870-5-103 protocol
1: Modbus protocol
2: DNP protocol
3: DLT645
4. [Format_Measmt]
The setting is used to select the format of measurement data sent to SCADA through IEC103
Date: 2015-07-29
7 Settings
protocol.
0: GDD data type through IEC103 protocol is 12;
1: GDD data type through IEC103 protocol is 7, i.e. 754 short real number of IEEE standard.
5. [En_AutoPrint]
If automatic print is required for disturbance report after protection operating, the setting should be
set as “1”.
6. [Opt_TimeSyn]
There are four selections for clock synchronization of device, each selection includes different time
clock synchronization signals shown in following table.
Item Description
PPS(RS-485): Pulse per second (PPS) via RS-485 differential level.
IRIG-B(RS-485): IRIG-B via RS-485 differential level.
Conventional
PPM(DIN): Pulse per minute (PPM) via the binary input [BI_TimeSyn].
PPS(DIN): Pulse per second (PPS) via the binary input [BI_TimeSyn].
SNTP(PTP): Unicast (point to point) SNTP mode via Ethernet network.
SAS SNTP(BC): Broadcast SNTP mode via Ethernet network.
Message (IEC103): Clock messages through IEC103 protocol.
IEEE1588: Clock message via IEEE1588.
Ad vanced IRIG-B(Fiber): IRIG-B via optical-fibre interface.
PPS(Fiber) PPS: Pulse per second (PPS) via optical-fibre interface.
When no time synchronization signal is connected to the equipment, please select
NoTimeSyn
this option and the alarm message [Alm_TimeSyn] will not be issued anymore.
“Conventional” mode and “SAS” mode are always be supported by device, but “Advanced” mode
is only supported when NET-DSP module is equipped. The alarm signal [Alm_TimeSyn] may be
issued to remind user loss of time synchronization signals.
1) When “SAS” is selected, if there is no conventional clock synchronization signal, the device
will not send the alarm signal [Alm_TimeSyn]. When “Conventional” mode is selected, if there
is no conventional clock synchronization signal, “SAS” mode will be enabled automatically
with the alarm signal [Alm_TimeSyn] being issued simultaneously.
2) When “Advanced” mode is selected, if there is no conventional clock synchronization signal

connected to NET-DSP module，“SAS” mode is enabled automatically with the alarm signal
[Alm_TimeSyn] being issued simultaneously.
3) When “NoTimeSyn” mode is selected, the device will not send alarm signals without time
synchronization signal. But the device can be still synchronized if receiving time
synchronization signal.
The clock message via IEC103 protocol is invalid when the device receives the IRIG-B signal
through RS-485 port.
7. [IP_Server_SNTP]
Date: 2015-07-29
7 Settings
It is the address of the SNTP time synchronization server which send s SNTP timing messages to
the relay or BCU.
8. OffsetHour_UTC, OffsetMinute_UTC
If the IEC61850 protocol is adopted in substations, the time tags of communication messages are
required according to UTC (Universal Time Coordinated) time.
The setting [OffsetHour_UTC] is used to set the hour offset of the current time zone to the GMT
(Greenwich Mean Time) zone; for example, if a relay is applied in China, the time zone of China is
east 8th time zone, so this setting is set as “8”. The setting [OffsetMinute_UTC] is used to set the
minute offset of the current time zone to the GMT zone.
Time zone GMT zone East 1 st East 2 nd East 3 rd East 4 th East 5 th

Setting 0 1 2 3 4 5
th th th th th
Time zone East 6 East 7 East 8 East 9 East 10 East 11 th
Setting 6 7 8 9 10 11
th st nd rd th th
Time zone East/West 12 West 1 West 2 West 3 West 4 West 5
Setting -12/12 -1 -2 -3 -4 -5
th th th th th
Time zone West 6 West 7 West 8 West 9 West 10 West 11 th
Setting -6 -7 -8 -9 -10 -11
7.5.2.3 Access Path
MainMenuSettingsDevice SetupComm Settings
7.5.3 Label Settings

Label settings are used to definite the label of each tripping output. Label settings will not affect
protection logics and it will only affect the displayed names of corresponding tripping output on
LCD, PCS-Explorer software etc.
Table 7.5-3 List of label settings
No. Setting Item Description
1 Name_TrpOutpx (x=1~29) Label settings of tripping output x
7.5.3.2 Access Path
MainMenuSettingsDevice SetupLabel Settings
7.6 Protection Settings

All the protection settings have be given in Section “Settings” of each protection element in
Chapter 3.
Date: 2015-07-29
Table of Contents
8.1 Overview............................................................................................ 8-1
8.1.1 Keypad Operation ............................................................................................................ 8-2
8.1.2 LED Indications................................................................................................................ 8-3
8.1.3 Front Communication Port ............................................................................................... 8-3
8.1.4 Ethernet Port Setup ......................................................................................................... 8-4
8.2 Understand the HMI Menu Tree...................................................... 8-5
8.2.1 Overview.......................................................................................................................... 8-5
8.2.2 Measurements ................................................................................................................. 8-8
8.2.3 Status ............................................................................................................................ 8-10
8.2.4 Records ......................................................................................................................... 8-10
8.2.5 Settings ..........................................................................................................................8-11
8.2.6 Print............................................................................................................................... 8-12
8.2.7 Local Cmd ..................................................................................................................... 8-15
8.2.8 Information..................................................................................................................... 8-15
8.2.9 Test................................................................................................................................ 8-15
8.2.10 Clock ........................................................................................................................... 8-16
8.2.11 Language ..................................................................................................................... 8-16
8.3 Understand the LCD Display ........................................................ 8-17
8.3.1 Overview........................................................................................................................ 8-17
8.3.2 Display during Normal Operation ................................................................................... 8-17
8.3.3 Display When Tripping ................................................................................................... 8-17
8.3.4 Display under Abnormal Condition ................................................................................. 8-19
8.3.5 Display When Binary State Changes.............................................................................. 8-20
Date: 2015-07-29
8.3.6 Display Device Logs ...................................................................................................... 8-22
8.4 Keypad Operation .......................................................................... 8-23
8.4.1 View Device Analog ....................................................................................................... 8-23
8.4.2 View Device Status ........................................................................................................ 8-23
8.4.3 View Device Records..................................................................................................... 8-24
8.4.4 View Device Setting ....................................................................................................... 8-24
8.4.5 Print Device Records ..................................................................................................... 8-24
8.4.6 Modify Device Setting .................................................................................................... 8-25
8.4.7 Copy Device Setting ...................................................................................................... 8-28
8.4.8 Switch Setting Group ..................................................................................................... 8-29
8.4.9 Delete Records.............................................................................................................. 8-30
8.4.10 Modify Device Clock .................................................................................................... 8-30
8.4.11 Check Software Version ............................................................................................... 8-31
8.4.12 View Module Information.............................................................................................. 8-31
8.4.13 Select Language .......................................................................................................... 8-32
List of Figures
Figure 8.1-1 Front panel of the device ................................................................................... 8-1
Figure 8.1-2 Keypad mounted on the front panel ................................................................. 8-2
Figure 8.1-3 LED indications .................................................................................................. 8-3
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel ................................ 8-4
Figure 8.1-5 Rear view and terminal definition of NR1102M ................................................ 8-5
Figure 8.2-1 Tree diagram of total command menu .............................................................. 8-7
Figure 8.3-1 LCD display of single line diagram ................................................................. 8-17
Figure 8.3-2 LCD display 1 of trip report ............................................................................. 8-18
Figure 8.3-3 LCD display 2 of trip report and alarm report................................................. 8-19
Figure 8.3-4 LCD display of alarm report ............................................................................ 8-19
Figure 8.3-5 Display of binary change report...................................................................... 8-20
Figure 8.3-6 Display of control report.................................................................................. 8-22
Date: 2015-07-29
Figure 8.4-1 Display of inputting password ........................................................................ 8-27
Figure 8.4-2 Display 1 of modifying settings ...................................................................... 8-27
Figure 8.4-3 Display 2 of modifying settings ...................................................................... 8-28
Figure 8.4-4 Display of copy settings .................................................................................. 8-29
Figure 8.4-5 Display of switching setting group ................................................................. 8-29
Figure 8.4-6 Display of deleting report ................................................................................ 8-30
Figure 8.4-7 Display of modifying clock .............................................................................. 8-31
Figure 8.4-8 Display of selecting language ......................................................................... 8-32
List of Tables
Table 8.1-1 Definition of the 8-core cable.............................................................................. 8-4
Table 8.3-1 Tripping reports related to oscillography ........................................................ 8-18
Table 8.3-2 Contact inputs list ............................................................................................. 8-21
Table 8.3-3 Contact outputs list ........................................................................................... 8-21
Table 8.3-4 User Operating event list .................................................................................. 8-23
PCS-985TE Transformer Relay 8-c
Date: 2015-07-29
8-d PCS-985TE Transformer Relay
Date: 2015-07-29
The operator can access the protective device from the front panel. Local communication with the
protective device is possible using a computer via a multiplex RJ45 port on the front panel.
Furthermore, remote communication is also possible using a PC with the substation automation
system via rear RS485 port or rear Ethernet port. The operator is able to check the protective
device status at any time.
This chapter describes human machine interface (HMI), and give operator an instruction about
how to display or print event report, setting and so on through HMI menu tree and display metering
value, including RMS current, voltage and frequency etc. through LCD. Procedures to change
active setting group or a settable parameter value through keypad are also described in details.
8.1 Overview
NOTICE!
The LCD interface in this chapter is ONLY a reference and available for explaining
specific definition of LCD. The displayed interface of the actual protection device may
be some DIFFERENT from it.
The human-machine interface consists of a human-machine interface (HMI) module which allows
a communication to be as simple as possible for the user. The HMI module helps to draw your
attention to something that has occurred which may activate a LED or a report displayed on the
LCD. Operator can locate the data of interest by navigating the keypad.
1 11
5
HEALTHY
2 12 PCS-985
ALARM
3
TRIP
13
TRANSFORMER RELAY
4 14
5 15
C GRP
6 16
7 17 ENT
ES
8 18
9 19 1
4
10 20
3
2
Figure 8.1-1 Front panel of the de vice
The function of HMI module:

A 320×240 dot matrix backlight LCD display is visible in dim lighting
1 LCD conditions. The corresponding messages are displayed when there is
operation implemented.
20 status indication LEDs, first three LEDs are fixed as the signals of
2 LED
“HEALTHY” , “ALARM” and “TRIP”, others are configurable.
3 Keypad Navigation keypad and command keys for full access to device
Date: 2015-07-29

4 Communication port a multiplex RJ45 port for local communication with a PC
5 Logo Type and designation and manufacturer of device
8.1.1 Keypad Operation
NOTICE!
Press “+”, “”, “”, “-“, “ENT” IN SEQUENCE to confirm the setting change and press
“+”, “-“, “+”, “-“, “ENT” IN SEQUENCE to execute the report deletion.
+
GR
ENT
ESC
Figure 8.1-2 Ke ypad mounted on the front panel
1. “ESC”:
 Cancel the operation
 Quit the current menu
2. “ENT”:
 Execute the operation
 Confirm the interface
3. “GRP”
 Activate the switching interface of setting group
4. leftward and rightward direction keys (“◄” and “►”):
 Move the cursor horizontally
 Enter the next menu or return to the previous menu
5. upward and downward direction keys (“▲” and “▼”)
 Move the cursor vertically
 Select command menu within the same level of menu
6. plus and minus sign keys (“＋” and “－”)
 Modify the value
 Modify and display the message number
Date: 2015-07-29
 Page up/down
8.1.2 LED Indications
01 HEALTHY 11
01 HEALTHY
02 ALARM 12
03 13 02 ALARM
Recommended
04 14
05 15 03 TRIP
06 16
LED_03 is configured as shown in the right
07 17
side, and other LEDs (LED_04~LED_20)
08 18 are configured according to the practical
09 19 requirement through the PCS-Explorer
10 20 software.
LED_03 ~ LED_ 20 are configurable
Figure 8.1-3 LED indications
A brief explanation has been made as bellow.
LED Displa y Description
When the device is out of service or any hardware error is defected during
Off
HEALTHY self-check.
Steady Green Lit when the device is in service and ready for operation.
Off When the device in normal operating condition.

ALARM
Steady Yellow Lit when VT circuit failure, CT circuit failure or other abnormal alarm is issued.
Off When the device in normal operating condition.

TRIP
Red Lit when any protection element trips.
“HEALTHY” LED can only be turned on by energizing the device and no abnormality detected.
“ALARM ” LED is turned on when abnormalities of device occurs like above mentioned and can be
turned off after abnormalities are removed except CT circuit failure alarm signal which can only be
reset when the failure is removed and the device is rebooted or re-energized.
“TRIP” LED is turned on and latched once any protection element operates and can be turned off
by pressing the signal RESET button on the front panel.
Other LED indicators with no labels are configurable and user can configure them to be lit by
signals of operation element, alarm element and binary output contact according to requirement
through PCS-Explorer software, and there are three colors (green, yellow and red) for user
selection.
8.1.3 Front Communication Port
There is a multiplex RJ45 port on the front panel. This port can be used as an RS-232 serial port
as well as a twisted-pair Ethernet port. As shown in the following figure, a customized cable is
applied for debugging via this multiplex RJ45 port.
Date: 2015-07-29
P2
P1
P3
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel
In the above figure and the following table:
P1: To connect the multiplex RJ45 port. An 8-core cable is applied here.
P2: To connect the twisted-pair Ethernet port of the computer.
P3: To connect the RS-232 serial port of the computer.
The definition of the 8-core cable in the above figure is introduced in the following table.
Table 8.1-1 Definition of the 8-core cable
Terminal Device side Computer side

Core color Function
No. (Left) (Right)
1 Orange & white TX+ of the Ethernet port P1-1 P2-1
2 Orange TX- of the Ethernet port P1-2 P2-2
3 Green & white RX+ of the Ethernet port P1-3 P2-3
4 Blue TXD of the RS-232 serial port P1-4 P3-2
5 Brown & white RXD of the RS-232 serial port P1-5 P3-3
6 Green RX- for the Ethernet port P1-6 P2-6
7 Blue & white P1-7
The ground connection of the RS-232 port. P3-5
8 Brown P1-8
8.1.4 Ethernet Port Setup

MON plug-in module is equipped with two or four 100Base-TX Ethernet interface, takes NR1102M
as an example, its rear view and the definition of terminals is shown in Figure 8.1-5.
The Ethernet port can be used to communication with PC via auxiliary software (PCS-Explorer)
after connecting the protection device with PC, so as to fulfill on-line function (please refer to the
instruction manual of PCS-Explorer). At first, the connection between the protection device and PC
must be established. Through setting the IP address and subnet mask of corresponding Ethernet
interface in the menu “Settings→Device Setup→Comm Settings”, it should be ensured that the
protection device and PC are in the same network segment. For example, setting the IP address
and subnet mask of network A. (using network A to connect with PC)
PC: IP address is set as “198.87.96.102”, subnet mask is set as “255.255.255.0”
Date: 2015-07-29
The IP address and subnet mask of protection device should be [IP_LAN1]= 198.87.96.XXX,
[Mask_LAN1]=255.255.255.0, [En_LAN1]=1. (XXX can be any value from 0 to 255 except 102)
If the logic setting [En_LAN1] is non-available, it means that network A is always enabled. If using
other Ethernet port, for example, Ethernet port B, the logic setting [En_LAN2] must be set as “1”.
NR1102M
ETHERNET
Network A
Network B
ETHERNET
Network C
Network D
SYN+
SYN-
SGND
RTS
TXD
SGND
Figure 8.1-5 Rear view and terminal definition of NR1102M
8.2 Understand the HMI Menu Tree
8.2.1 Overview
Pressing “▲” at any running interface can return to the main menu. Select different submenu by
“▲” and “▼”. Enter the selected submenu by pressing “ENT” or “►”. Press “◄” and return to the
previous menu. Press “ESC” and exit the main menu directly. For fast return to the command
menu, one command menu will be recorded in the quick menu after its first execution. Up to five
latest menu commands can be recorded in the quick menu by “first in first out” principle. It is
arranged from top to bottom and in accordance with the execution order of command menus.
Press “▲” to enter the main menu, the interface is shown in the following diagram:
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Quick Menu
Language
Clock
Device Settings
Mainmenu
If the protective device is powered for the first time, there is no recorded shortcut menu. Press “▲”
to enter the main menu with the interface as shown in the following diagram:
Measurements
Status
Records
Settings
Print
Local Cmd
Information
Test
Clock
Language
NOTICE!
The menu shown in following figure is NOT the specific-application menu. For each
project, the menu VARIES with the protection configuration.
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MAIN MENU
Measurements Records Print
Measurements 1 Disturb Records Device Info

Superv Events Settings
Tr Values
IO Events
System Settings
Tr Diff Values Device Logs
Tr Sys Settings
Tr REF Values
Settings Config Settings
Tr Curr Values
Prot Settings
Tr Volt Values System Settings
Tr Sys Settings Submenus same to those in the
Measurements 2 menu“Settings->Prot Settings”
Config Settings
Tr Values2 Prot Settings Device Setup
Tr Diff Values Tr Diff Settings Submenus same to those in the
Tr REF Values TrHVS REF Settings
menu“Settings->Device Setup”
Tr Curr Values TrMVS REF Setting All Settings

Tr Volt Values Tr OvExc Settings Latest Chgd Settings
Phase Angle UnderFreq Settings

Disturb Records
OverFreq Settings
Tr PhaseAngle Values Superv Events
FreqRateChg Settings
IO Events
Cal Param Display MechRly Settings
Device Logs
Sec Rated Curr Values TrHVS OC Settings Device Status
Diff Corr Coef Values TrHVS NegOC Settings Waveforms
TrHVS EF Settings
Prot Values Tr Diff Wave
TrHVS VoltProt Settings
Misc Prot Values Tr Curr Wave
TrHVS Impedance Settings
Tr Diff Prot Values Tr Volt Wave
TrHVS OvLd Settings
Tr REF Prot Values TrHVS BFP Settings IEC103 Info
Freq Prot Values TrMVS OC Settings Cancel Print
Tr HVS PPF Prot Values TrMVS NegOC Settings
Local Cmd
Tr HVS EF Prot Values TrMVS EF Settings
Tr HVS Impedance Prot Values TrMVS VoltProt Settings Reset Target
Tr MVS PPF Prot Values TrMVS Impedance Settings Trig Oscillograph
Tr MVS EF Prot Values TrMVS OvLd Settings Download
Tr MVS Impedance Prot Values TrMVS BFP Settings Information
Tr LVS Bak Prot Values TrLVS OC Settings
Version Info
TrLVS EF Settings
Status Board Info
Copy Settings
Inputs Test
Device Setup
Contact Inputs Device Test
Device Settings
Disturb Events
Outputs Comm Settings
Contact Outputs Label Settings All Test
FD Status Select Test
Superv Events
All Test
Select Test
IO Events
All Test
Select Test
Contact Outputs
Internal Signal
Disturb Item
HMI Setup
Clock
BackLitDur
Contrast
Language SupervLCD
SupervLED
Figure 8.2-1 Tree diagram of total command menu
Under the main interface, press “▲” to enter the main menu, and select submenu by pressing “▲”,
“▼” and “ENT”. The command menu adopts a tree shaped content structure. The above diagram
provides the integral structure and all the submenus under menu tree o f the protection device.
Date: 2015-07-29
8.2.2 Measurements
This menu is mainly used to display the real time sampling value of current, voltage and phase
angle. This menu and “Status” menu can fully reflects of the running environment of the protection
device. As long as the displayed values consist with the actual running situation, basically, the
protection device can work normally. This menu is set to greatly facilitate the debugging and
maintenance of people on site. Please refer to Section “Inputs and Outputs” of each protection
element about the detailed description of each sampled values.
The menu “Measurements” has following submenus.

1 Measurements 1 Display sampled and calculated values on protection DSP module.
2 Measurements 2 Display sampled and calculated values on fault detector DSP module.
8.2.2.1 Measurements1
The menu “Measurement1” has following submenus.

1 Tr Values Display the value of main transformer on protection DSP module.
2 ST Values Display the value of step-down transformer on protection DSP module.
(1) The submenu “Tr Values” includes the following command menus.
Display magnitude of differential current and restraint current of current

1 Tr Diff Values
differential protection of main transformer on protection DSP module.
Display magnitude of differential current and restraint current of restricted

2 Tr REF Values
earth fault protection of main transformer on protection DSP module.
Display magnitude of AC current of main transformer on protection DSP

3 Tr Curr Values
module.
Display magnitude of AC voltage of main transformer on protection DSP

4 Tr Volt Values
module.
8.2.2.2 Measurements2
The menu “Measurements2” has following lower submenus.

1 Tr Values Display the value of main transformer on fault detector DSP module.
2 ST Values Display the value of step-down transformer on fault detector DSP module.
3 Phase Angle Display the value of phase angle on fault detector DSP module.
4 Cal Param Display Display the calculated values on fault detector DSP module.
5 Prot Values Display the values related with protection element.
(1) The submenu “Tr Values” includes the following command menus.
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Display magnitude of differential current and restraint current of current

1 Tr Diff Values
differential protection of main transformer on fault detector DSP module.
Display magnitude of differential current and restraint current of restricted

2 Tr REF Values
earth fault protection of main transformer on fault detector DSP module.
Display magnitude of AC current of main transformer on fault detector

3 Tr Curr Values
DSP module.
Display magnitude of AC voltage of main transformer on fault detector

4 Tr Volt Values
DSP module.
(2) The submenu “Phase Angle” includes the following command menus.
Display the phase angle values of main transformer protection on fault

1 Tr PhaseAngle Values
detector DSP module.
(3) The submenu “Cal Param Display” includes the following command menus.
Display the secondary current value for differential protection of main

1 Sec Rated Curr Values
transformer and step-down transformer.
Display the coefficients for current differential protection and restricted

2 Diff Corr Coef Values
earth fault protection of main transformer and step-down transformer.
(4) The submenu “Prot Values” includes the following command menus.
Display status values related to interconnection status element on fault

1 Misc Prot Values
detector DSP module.
Display status values related to main transformer current differential

2 Tr Diff Prot Values
protection on fault detector DSP module.
Display status values related to main transformer restricted earth fault

3 Tr REF Prot Values
protection on fault detector DSP module.
Display status values related to frequency protection on fault detector

4 Freq Prot Values
DSP module.
Display status values related to phase-to-phase backup protection of

5 Tr HVS PPF Prot Values
main transformer HV side on fault detector DSP module.
Display status values related to earth fault protection of main transformer

6 Tr HVS EF Prot Values
HV side on fault detector DSP module.
Tr HVS Impedance Prot Display status values related to impedance protection of main transformer
7
Values HV side on fault detector DSP module.
Display status values related to phase-to-phase backup protection of

8 Tr MVS PPF Prot Values
main transformer MV side on fault detector DSP module.
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Display status values related to earth fault protection of main transformer

9 Tr MVS EF Prot Values
MV side on fault detector DSP module.
Tr MVS Impedance Prot Display status values related to impedance protection of main transformer
10
Values MV side on fault detector DSP module.
Display status values related to backup protection of main transformer LV

11 Tr LVS Bak Prot Values
side on fault detector DSP module.
8.2.3 Status
This menu is mainly used to display the real time input signals and output signals of the device.
This menu and “Measurements” menu fully reflects the running environment of the protection
device. As long as the displayed signals are in accordance with the actual running situation,
basically, the protection device can work normally. This menu is set to greatly facilitate the
debugging and maintenance of people on site.
The menu “Status” has following submenus.

1 Inputs Display all input signal states
2 Outputs Display all output signal states
8.2.3.1 Inputs
The menu “Inputs” has following submenus.

1 Contact Inputs Display states of binary inputs derived from opto-isolated channels
8.2.3.2 Outputs
The menu “Outputs” has following submenus.

1 Contact Outputs Display states of tripping output contacts
2 FD Status The operating flag of fault detector element of each protection element
8.2.4 Records
This menu is used to display all kinds of records, including the disturbance records, supervision
events, binary events and device logs, so that the operator can load to view and use as the
reference of analyzing accidents and repairing the device. All records are stored in non-volatile
memory, it can still record them even if it loses its power.
This menu includes the following command menus.
No. Item Function description

1 Disturb Records Display disturbance records of the device
2 Superv Events Display supervision events of the device
Date: 2015-07-29

3 IO Events Display binary events of the device
4 Device Logs Display device logs of the device
8.2.5 Settings
This menu is used to browse, modify and set all settings including device setup parameters,
protection settings and system parameters etc. Moreover, it can also execute the setting copy
between different setting groups.
1 System Settings To display and modify the system settings
2 Tr Sys Settings To display and modify the system settings of main transformer protection.
3 Config Settings To display and modify the configuration settings.
4 Prot Settings To display and modify the settings of each protection elements.
5 Device Setup To display and modify the settings related to device setup
8.2.5.1 Prot Settings
The submenu “Prot Settings” includes the following command menus.
To display and modify the settings of main transformer differential

1 Tr Diff Settings
protection.
To display and modify the settings of restricted earth fault protection of main
2 TrHVS REF Settings
To display and modify the settings of restricted earth fault protection of main
3 TrMVS REF Settings
To display and modify the settings of main transformer overexcitation

4 Tr OvExc Settings
protection.
5 UnderFreq Settings To display and modify the settings of underfrequency protection.
6 OverFreq Settings To display and modify the settings of overfrequency protection.
7 FreqRateChg Settings To display and modify the settings of rate-of-frequency-change protection.
8 MechRly Settings To display and modify the settings of mechanical protection.
To display and modify the settings of phase overcurrent protection of main

9 TrHVS OC Settings
To display and modify the settings of negative-sequence overcurrent

10 TrHVS NegOC Settings
To display and modify the settings of earth fault protection of main

11 TrHVS EF Settings
12 TrHVS VoltProt Settings To display and modify the settings of phase overvoltage and undervoltage
Date: 2015-07-29
To display and modify the settings of impedance protection of main

13 TrHVS Impedance Settings
To display and modify the settings of thermal overload protection of main

14 TrHVS OvLd Settings
To display and modify the settings of breaker failure protection of main

15 TrHVS BFP Settings

16 TrMVS OC Settings
To display and modify the settings of negative-sequence overcurrent

17 TrMVS NegOC Settings
To display and modify the settings of earth fault protection of main

18 TrMVS EF Settings
To display and modify the settings of phase overvoltage and undervoltage

19 TrMVS VoltProt Settings
To display and modify the settings of impedance protection of main

20 TrMVS Impedance Settings
To display and modify the settings of thermal overload protection of main

21 TrMVS OvLd Settings
To display and modify the settings of breaker failure protection of main

22 TrMVS BFP Settings

23 TrLVS OC Settings
To display and modify the settings of earth fault prote ction of main
24 TrLVS EF Settings
25 Copy Settings Copy setting between different setting groups.
8.2.5.2 Device Setup
The menu “Device Setup” has following submenus.
1 Device Settings To display and modify the device settings.
2 Comm Settings To display and modify the communication settings .
3 Label Settings To display and modify the label settings of the output signals.
8.2.6 Print
This menu is used for printing device description, setting, all kinds of records, waveform and
information related with 103 Protocol.
This menu includes the following command menus and submenus.
Date: 2015-07-29
To print the description information of protective device including software

1 Device Info
version.
To print settings. It can print by different classifications as well as printing all

2 Settings settings of the de vice. Besides, it can also print out the latest modified
setting item.
3 Disturb Records To print tripping reports.
4 Superv Events To print self-check alarm and device operation abnormal alarm reports.
5 IO Events To print status change of binary signal.
6 Device Logs To print operation logs of the device.
To print present status of device, including measurement, signal status,

7 Device Status
settings, etc.
8 Waveforms To print recorded waveforms .
To print 103 protocol information, including function type (FUN), information

9 IEC103 Info serial number (INF), general classification service group number and
channel number (ACC).
10 Cancel Print To cancel the undergoing printing task.
8.2.6.1 Settings
The menu “Settings” has following submenus.
1 System Settings To print the system settings
2 Tr Sys Settings To print the system settings of main transformer protection.
3 Config Settings To print the configuration settings.
4 Prot Settings To print the settings of each protection elements.
5 Device Setup To print the settings related to device setup
6 All Settings Print all settings included in “Settings” submenu
7 Latest Chgd Settings Print the latest modified settings
(1) The submenu “Prot Settings” includes the following command menus.
1 Tr Diff Settings To print the settings of main transformer differential protection.
To print the settings of restricted earth fault protection of main transformer

2 TrHVS REF Settings
HV side.
To print the settings of restricted earth fault protection of main transformer

3 TrMVS REF Settings
MV side.
4 Tr OvExc Settings To print the settings of main transformer overexcitation protection.
5 UnderFreq Settings To print the settings of underfrequency protection.
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6 OverFreq Settings To print the settings of overfrequency protection.
7 FreqRateChg Settings To print the settings of rate-of-frequency-change protection.
8 MechRly Settings To print the settings of mechanical protection.
To print the settings of phase overcurrent protection of main transformer HV

9 TrHVS OC Settings
side.
To print the settings of negative-sequence overcurrent protection of main

10 TrHVS NegOC Settings
11 TrHVS EF Settings To print the settings of earth fault protection of main transformer HV side.
To print the settings of phase overvoltage and undervoltage protection of

12 TrHVS VoltProt Settings
main transformer HV side.
13 TrHVS Impedance Settings To print the settings of impedance protection of main transformer HV side.
To print the settings of thermal overload protection of main transformer HV

14 TrHVS OvLd Settings
side.
To print the settings of breaker failure protection of main transformer H V

15 TrHVS BFP Settings
side.
To print the settings of phase overcurrent protection of main transformer MV

16 TrMVS OC Settings
side.
To print the settings of negative-sequence overcurrent protection of main

17 TrMVS NegOC Settings
18 TrMVS EF Settings To print the settings of earth fault protection of main transformer MV side.
To print the settings of phase overvoltage and undervoltage protection of

19 TrMVS VoltProt Settings
main transformer MV side.
20 TrMVS Impedance Settings To print the settings of impedance protection of main transformer MV side.
To print the settings of thermal overload protection of main transformer MV

21 TrMVS OvLd Settings
side.
To print the settings of breaker failure protection of main transformer MV

22 TrMVS BFP Settings
side.
To print the settings of phase overcurrent protection of main transformer LV

23 TrLVS OC Settings
side.
24 TrLVS EF Settings To print the settings of earth fault protection of main transformer LV side.
25 All Settings Print all settings included in “Prot Settings” submenu
(2) The submenu “Device Setup” includes the following command menus.
1 Device Settings To print the device settings
2 Comm Settings To print the communication settings
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3 Label Settings To print the label settings
(3) The menu “Waveforms” has following submenus.
To print the recorded current waveforms of main transformer current

1 Tr Diff Wave
2 Tr Curr Wave To print the recorded current waveforms of main transformer protection.
3 Tr Volt Wave To print the recorded voltage waveforms of main transformer protection.
8.2.7 Local Cmd

This menu is used for resetting the tripping relay with latch, protection device signal lamp, LCD
display, as the same as the resetting function of binary input. Record the currently acquired
waveform data of the protection device under normal condition for printing and uploading SAS.
Besides, it can send out the request of program download.
1 Reset Target Reset the local signal, the signal indicator lamp and the LCD display
2 Trig Oscillograph Trigger waveform recording
3 Download Send out the download request
8.2.8 Information
In this menu the LCD displays software information of DSP module, MON module and HMI module,
which consists of version, creating time of software, CRC codes and management sequence
number. Besides, hardware board information can also be viewed.
Display software information of DSP module, MON module and HMI

1 Version Info module, which consists of version, creating time of software, CRC codes
and management sequence number.
Monitor the current working state of each intelligent module of the

2 Board Info
equipment
8.2.9 Test
This menu is used for developers to debug the program and for engineers to maintain the device.
It can be used to check item fault message, and fulfill the communication test function. It is also
used to generate all kinds of report or event to transmit to the SAS without any external input, so
as to debug the communication on site.
Date: 2015-07-29
This menu includes the following command menu.
Automatically generate all kinds of reports or events to transmit to SCAD A,

including disturbance records , self-supervision events and binary events. It
1 Device Test
can realize the report uploading by different classification, as well as the
uploading of all kinds of reports
2 Internal Signal Display some internal alarm or tripping signals
3 Disturb Item Check the fault report one by one.
4 HMI Setup Test the LED and the LCD display
(1) The menu “Device Test” has following submenus.
Generate protection element operation messages to transmit to SCAD A

(only used for debugging persons). Users can respectively e xecute the test
1 Disturb Events
automatically or manually by selecting sub-commands “All Test” or “Select
Test”.
Generate alarm messages to transmit to SCADA (only used for debugging

2 Superv Events persons). Users can respectively execute the test automatically or manually
by selecting sub-commands “All Test” or “Select Test”.
Generate BI and BO events to transmit to SCAD A (only used for debugging

3 IO Events persons). Users can respectively execute the test automatically or manually
by selecting sub-commands “All Test” or “Select Test”.
4 Contact Output To test the output contacts of the BO intelligent module.
(2) The menu “HMI Setup” has following submenus.
1 BacklitDur To set the backlighting duration of the LCD screen
2 Contrast To set the contrast of the LCD screen
3 SupervLCD To test the LCD screen.
4 SupervLED To test the LED indicators.
8.2.10 Clock
The current time of internal clock can be viewed here. The time is displayed in the form
YY-MM-DD and hh:mm:ss. All values are presented with digits and can be modified.
8.2.11 Language
This menu is mainly used for set LCD display language.
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8.3 Understand the LCD Display
8.3.1 Overview
There are five kinds of LCD display: SLD (single line diagram) display, tripping reports, alarm
reports, binary input changing reports and device logs. Tripping reports and alarm reports will not
disappear until these reports are acknowledged by pressing the “RESET” button in the protection
panel (i.e. energizing the binary input [BI_RstTarg]). User can press “ESC” first then “ENT”
simultaneously to switch the display among trip reports, alarm reports and the SLD display. Binary
change reports will be displayed for 5s and then it’ll return to the previous d isplay interface
automatically. Device logs will not pop up and can only be viewed by navigating the corresponding
menu.
8.3.2 Display during Normal Operation
After the protection device is powered and turns into the initiating interface, it takes 45 seconds to
complete the initialization of protection device. During the initialization, the “ HEALTHY” indicator of
the protection device goes out.
Under normal condition, the LCD will display the interface similar as Figure 8.3-1. The LCD adopts
white color as its backlight that is activated if once there is any keyboard operation, and is
extinguished automatically after 60 seconds of no operation.
When the device is powered on, the LCD will display single line diagram as following:
Date and time
Communication address Addr:102 2014-10-28 10:10:00 Group 01 Active setting group number
IdTr: 0.00pu Main transformer differential current
Main transformer current 0.00A
0.00A f: 0.00Hz Frequency
Figure 8.3-1 LCD display of single line diagram
breaker open. breaker closed.
The displayed content of the interface contains: the current date and time of the protection device
(with a format of yy-mm-dd hh:mm:ss:), the currently valid setting group number, the three -phase
current sampled values, differential current etc.
8.3.3 Display When Tripping

This protection device can store 64 fault reports and 64 fault waveforms. When there is protection
Date: 2015-07-29
element operating, the LCD will automatically display the latest fault report, and two kinds of LCD
display will be available depending on whether there is self-check report at present.
If the device has no self-check report, the display interface will only show the fault report.
Disturb Records NO.2

2014-11-28 07:10:00:200
0000ms TrigDFR
0024ms Tr.87T.Op_Biased
Figure 8.3-2 LCD display 1 of trip report
Disturb Records NO.2 shows the title and SOE number of the report.
2014-11-28 07:10:00:200 shows the time when fault detector picks up, the format is
year–month-date and hour: minute:second:millisecond.
0000ms TrigDFR shows fault detector of protection element and operation time of fault detector is
fixed as 0ms.
0024ms Tr.87T.Op_Biased shows the relative operation time and operation element of protection
element
All the protection elements have been listed in Chapter 3 “Operation Theory”, and please refer to
Section “Inputs and Outputs” of each protection element for details. Operation reports of fault
detector and the reports related to oscillography function are shown in the following table.
Table 8.3-1 Tripping reports related to oscillography
No. Message Description

1 TrigDFR_Man Oscillography function is triggered manually.
2 TrigDFR_Rmt Oscillography function is triggered remotely.

3 TrigDFR Fault detector operates to trigger oscillography.
Oscillography function is triggered by alarm signals on
4 ProtBrd.TrigDFR_Alm
protection board.
Oscillography function is triggered by failure signals on
5 ProtBrd.TrigDFR_Fail
protection board.
For the situation that the fault report and the self-check alarm report occur simultaneously in the
following figure, the upper half part is fault report, and the lower half part is self-check report. As to
Date: 2015-07-29
the upper half part, it displays separately the record number of fault report, fault name, generating
time of fault report (with a format of yy-mm-dd hh:mm:ss:), protection element and tripping element.
If there is protection element, there is relative time on the basis of fault detector element. At the
same time, if the total lines of protection element and tripping element are more than 3, a scroll bar
will appear at the right. The height of the black part of the scroll bar basically indicates the total
lines of protection element and tripping element, and its position suggests the position of the
currently displayed line in the total lines. The scroll bar of protection element and tripping element
will roll up at the speed of one line per time. When it rolls to the last three lines, it’ll roll from the
earliest protection element and tripping element again. The displayed content of the lower half pa rt
is similar to that of the upper half part.
NO.010 2014-11-28 10:10:00:083 Disturb
0000ms TrigDFR
0024ms Tr.87T.Op_Biased
Superv Events
24.Alm
Figure 8.3-3 LCD display 2 of trip report and a larm report
8.3.4 Display under Abnormal Condition

This protection device can store 1024 self-check reports. During the running of protection device,
the self-check report of hardware errors or system running abnormity will be displayed
immediately.
Superv Events NO.4

2014-11-29 9:18:47:500ms
Settings_Chgd 0 1
Figure 8.3-4 LCD display of alarm report
Date: 2015-07-29
Superv Events NO.4 shows the SOE number and title of the report
2014-11-29 09:18:47:500 shows the data and time of the report occurred: year–month-date
and hour:minute:second:millisecond
Settings_Chgd 0->1 shows the content of abnormality alarm
All the alarm elements have been listed in Chapter 4 “Supervision”.
8.3.5 Display When Binary State Changes

When a binary input is energized or de-energized, output contacts operate, the corresponding IO
event report will be automatically displayed on LCD as follows. This protective equipment can
store 1024 events of binary signals. During the running of the equipment, the binary signals will be
displayed once the input signal state changes.
IO Events NO.4
2014-11-29 09:18:47:500ms
BI_Maintenance 0 1
Figure 8.3-5 Display of binary change report
IO Events NO.4 shows the number and title of the report
2014-11-29 09:18:47:500 shows the date and time of the report occurred, the format is
year–month-date and hour:minute:second:millisecond
BI_Maintenance 0->1 shows the state change of binary input, including binary input name,
original state and final state
Contact inputs and contact outputs are listed in the following two tables, and user can define
undefined binary inputs as the specific binary inputs via PCS-Explorer software.
NOTICE!
The binary input number of BI intelligent module of different type may be DIFFERENT
and signals list in following table are just for reference, please refer to Chapter
“Hardware” for details.
Date: 2015-07-29
Table 8.3-2 Contact inputs list
No. Binary input Description

1 BI_TimeSyn Binary input of time synchronization pulse
2 BI_Print Binary input of triggering printing
3 BI_Maintenance Binary input of indicating the protection device is under maintenance state
4 BI_RstTarg Binary input of resetting signal of protective device
5 Bxx.BI_01 Binary input 01 of the binary input module located in slot No.xx.
Table 8.3-3 Contact outputs list

1 TrpOut01 The 1 st group of tripping output contacts.
2 TrpOut02 The 2 nd group of tripping output contacts.
rd
3 TrpOut03 The 3 group of tripping output contacts.
4 TrpOut04 The 4 th group of tripping output contacts.


th
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th
17 TrpOut17 The 17 th group of tripping outputs contacts.

th
19 TrpOut19 The 19 group of tripping outputs contacts.


th
27 TrpOut27 The 27 group of tripping outputs contacts.
8.3.6 Display Device Logs

This protection device can store 1024 pieces of equipment logs. During the running of the
protection device, equipment logs will be displayed after user operations.
Device Logs NO.4

2008-11-28 10:18:47:569ms
Device_Reboot
Figure 8.3-6 Display of control report
Device Logs NO. 4 shows the title and the number of the report
2008-11-28 10:18:47:569 shows the date and time when the report occurred, the format is
year–month-date and hour:minute:second:millisecond
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Device_Reboot shows the state content of the user operation report.
User operating information listed below may be displayed.
Table 8.3-4 User Operating event list
No. Message Description

1 Reboot The device has been reboot.
2 Settings_Chgd The device′s settings have been changed.
3 Acti veGrp_Chgd Active setting group has been changed.
4 Report_Cleared All reports have been deleted. (Device logs cannot be deleted)
5 Waveform_Cleared All waveforms have been deleted.
6 Process_Exit A process has exited.
8.4 Keypad Operation

8.4.1 View Device Analog
The operation is as follows:
1. Press the key “▲” to enter the main menu.
2. Press the key “▲” or “▼” to move the cursor to the “Measurements” menu, and then
press the “ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to any command menu item, and then press
the key “ENT” to enter the submenu.
4. Press the “▲” or “▼” to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most).
5. Press the key “◄” or “►” to select pervious or next command menu.
6. Press the key “ENT” or “ESC” to exit this menu (returning to the “Measurements” menu).
8.4.2 View Device Status

2. Press the key “▲” or “▼” to move the cursor to the “Status” menu, and then press the
“ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to any command menu item, and then press
the key “ENT” to enter the submenu.
4. Press the “▲” or “▼” to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most).
6. Press the key “ENT” or “ESC” to exit this menu (returning to the “Status” menu).
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8.4.3 View Device Records

2. Press the key “▲” or “▼” to move the cursor to the “Records” menu, and then press the
key “ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to any command menu, and then press the
key “ENT” to enter the submenu.
4. Press the key “▲” or “▼” to page up/down.
5. Press the key “＋” or “－” to select pervious or next record.
7. Press the key “ENT” or “ESC” to exit this menu (returning to the “Records” menu).
8.4.4 View Device Setting

2. Press the key “▲” or “▼” to move the cursor to the “Settings” menu, and then press the
key “ENT” or “►” to enter the menu.
key “ENT” to enter the menu.
4. Press the key “▲” or “▼” to move the cursor.
5. Press the key “+” or “-” to page up/down.
7. Press the key “ESC” to exit this menu (returning to the menu “Settings”).
If the displayed information exceeds 14 lines, the scroll bar will appear on the right side of
the LCD to indicate the quantity of al l displayed information of the command menu and the
relative location of information where the current cursor points at.
8.4.5 Print Device Records

2. Press the key “▲” or “▼” to move the cursor to the “Print” menu, and then press the
“ENT” or “►” to enter the menu.
“ENT” to enter the menu.
 Selecting the “Disturb Records”, and then
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Press the “＋” or “－” to select pervious or next record. After pressing the key “ENT”,
the LCD will display “Start Printing... ”, and then automatically exit this menu
(returning to the menu “Print”). If the printer doesn’t complete its current print task
and re-start it for printing, and the LCD will display “Printer Busy…”. Press the key
“ESC” to exit this menu (returning to the menu “Print”).
 Selecting the command menu “Superv Events” or “IO Events”, and then press the
key “▲” or “▼” to move the cursor. Press the “＋” or “－” to select the starting and
ending numbers of printing message. After pressing the key “ ENT”, the LCD will
display “Start Printing…”, and then automatically exit this menu (return ing to the
menu “Print”). Press the key “ESC” to exit this menu (returning to the menu “Print”).
4. If selecting the command menu “Device Info”, “Device Status“ or “IEC103 Info”, press
the key “ENT”, the LCD will display “Start printing..”, and then automatically exit this menu
(returning to the menu “Print”).
5. If selecting the “Settings”, press the key “ENT” or “►” to enter the next level of menu.
6. After entering the submenu of “Settings”, press the key “▲” or “▼” to move the cursor,
and then press the key “ENT” to print the corresponding default value. If selecting any
item to printing:
Press the key “＋” or “－” to select the setting group to be printed. After pressing the key
“ENT”, the LCD will display “Start Printing…”, and then automatically exit this menu
(returning to the menu “Settings”). Press the key “ESC” to exit this menu (returning to the
menu “Settings”).
7. After entering the submenu “Waveforms”, press the key “ENT” or “►” to enter the next
level of menu. After entering the submenu of “Waveforms”, press the “＋” or “－” to
select the waveform item to be printed and press “ENT” to enter. If there is no any
waveform data, the LCD will display “No Waveform Data!” (If there is no any waveform
data, users can execute the command menu “Trig Oscillograph” in the menu “Local
Cmd”, then waveform data can be generated). With waveform data existing:
Press the key “＋” or “－” to select pervious or next record. After pressing the key “ENT”,
the LCD will display “Start Printing…”, and then automatically exit this menu (returning to
the menu “Waveforms”). If the printer does not complete its current print task and
re-start it for printing, and the LCD will display “Printer Busy…”. Press the key “ESC” to
exit this menu (returning to the menu “Waveforms”).
8.4.6 Modify Device Setting

2. Press the key “▲” or “▼” to move the cursor to the “Settings” menu, and then press
the key “ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to any command menu, and then press
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the key “ENT” to enter the menu.
4. Press the key “▲” or “▼” to move the cursor.
5. Press the key “+” or “-” to page up/down.
7. Press the key “ESC” to exit this menu (returning to the menu “Settings”).
Following takes modification of device settings as an example.
8. Select the command menu “Device Settings” “Comm Settings” or “Label Settings”,
users need to enter the submenu “Device Setup” firstly.
9. Selecting the command menu “Device Settings”, move the cursor to the setting item
to be modified, and then press the key “ENT”.
Press the key “＋” or “－” to modify the value (if the modified value is of multi-bit, press
the key “◄” or “►” to move the cursor to the digit bit, and then press the “ ＋” or “－” to
modify the value), press the key “ESC” to cancel the modification and return to the
displayed interface of the command menu “Device Settings”. Press the key “ENT” to
automatically exit this menu (returning to the displayed interface of the command menu
“Device Settings”).
Move the cursor to continue modifying other setting items. After all set ting values are
modified, press the key “◄”, “►” or “ESC”, and the LCD will display “Save or Not?”.
Directly press the “ESC” or press the key “◄” or “►” to move the cursor. Select the
“Cancel”, and then press the key “ENT” to automatically exit this menu (returning to the
displayed interface of the command menu “Device Settings”).
Press the key “◄” or “►” to move the cursor. Select “No” and press the key “ENT”, all
modified setting item will restore to its original value, exit this menu (returning to the
menu “Settings”).
Press the key “◄” or “►” to move the cursor to select “Yes”, and then press the key
“ENT”, the LCD will display password input interface.
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Password:
____
Figure 8.4-1 Display of inputting password
Input a 4-bit password (“＋”, “◄”, “▲” or “－”). If the password is incorrect, continue
inputting it, and then press the “ESC” to exit the password input interface and return to
the displayed interface of the command menu “Device Settings”. If the password is
correct, LCD will display “Save Settings…”, and then exit this menu (returning to the
displayed interface of the command menu “Device Settings”), with all modified setting
items as modified values.
10. If selecting the command menu of protection element such as “Tr Diff Settings”, the
LCD will display the following interface:
Tr Diff Settings
Please Select Group for Config
Active Group: 01
Selected Group: 02
Figure 8.4-2 Display 1 of modifying settings
Then move the cursor to the modified value and press “ENT” to enter. If the setting
[Tr.87T.I_Biased] is selected to modify, then press the “ENT” to enter and the LCD will
display the following interface. is shown the “＋” or “－” to modify the value and then press
the “ENT” to enter.
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Tr.87T.I_Biased
Current Value 0.22
Modified Value 0.2 2
Min Value 0.10
Max Value 1.50
Figure 8.4-3 Display 2 of modifying settings
11. If selecting the other menus, move the cursor to the setting to be modified, and then
press the “ENT”.
For different setting items, their displayed interfaces are different but their modification methods
are the same.
After modifying the settings (except for communication settings), the “HEALTHY” indicator of the
protection device will go out, and the protection device will automatically restart and r e-check the
protection setting. If the check doesn’t pass, the protection device will be blocked.
8.4.7 Copy Device Setting

1. Press the key “▲” to enter the main menu;
2. Press the key “▲” or “▼” to move the cursor to the “Settings” menu, and then press the
key “ENT” or “►” to enter the menu;
3. Press the key “▲” or “▼” to move the cursor to the command menu “ Copy Settings”,
and then press the key “ENT” to enter the menu. The following display will be shown on
LCD.
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Copy Settings
Active Group: 01
Copy To Group: 02
Figure 8.4-4 Display of copy settings
Press the key “＋” or “－” to modify the value. Press the key “ESC”, and return to the
menu “Settings”. Press the “ENT”, the LCD will display the interface for password input,
if the password is incorrect, continue inputting it, press the key “ESC” to exit the
password input interface and return to the menu “ Settings”. If the password is correct,
the LCD will display “Copy Settings Success!”, and exit this menu (returnin g to the menu
“Settings”).
8.4.8 Switch Setting Group

1. Exit the main menu.
2. Press the “GRP” button.
Change Active Group
Active Group: 01
Change To Group: 02
Figure 8.4-5 Display of switching setting group
Press the “＋” or “－” to modify the value, and then press the key “ESC” to exit this menu
(returning to the main menu). After pressing the key “ENT”, the LCD will display the password
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input interface. If the password is incorrect, continue inputting it, and then press the key “ ESC” to
exit the password input interface and return to its original state. If the password is correct, the
“HEALTHY” indicator of the protection device will go out, and the protection device will re -check
the protection setting. If the check doesn’t pass, the protection device will be blocked. If the check
is successful, the LCD will return to its original state.
8.4.9 Delete Records

NOTICE!
The operation of deleting device records will delete ALL messages saved by the
protection device, including disturbance records, supervision events and binary events,
but it will NOT DELETE the user operation reports (i.e. device logs). Furthermore, all
deleted records are IRRECOVERABLE after deletion, please do the operation with
great cautious.
1. Exit the main menu.
2. Press the “＋”, “－”, “＋”, “－” and key “ENT”; Press the key “ESC” to exit this menu
(returning to the original state). Press the key “ENT” to carry out the deletion.
Press <ENT> To Clear

Press <ESC> To Exit
Figure 8.4-6 Display of deleting report
8.4.10 Modify Device Clock

2. Press the key “▲” or “▼” to move the cursor to the “Clock” menu, and then press the key
“ENT” to enter clock display.
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Clock
Year 2008
Month 11
Day 28
Hour 20
Minute 59
Second 14
Figure 8.4-7 Display of modifying clock
3. Press the key “▲” or “▼” to move the cursor to the date or time to be modified.
4. Press the key “＋” or “－”, to modify value, and then press the key “ENT” to save the
modification and return to the main menu.
5. Press the key “ESC” to cancel the modification and return to the main menu.
8.4.11 Check Software Version

2. Press the key “▲” or “▼” to move the cursor to the “Information” menu, and then press
the “ENT” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to the command menu “ Version Info”, and
then press the key “ENT” to display the software version.
4. Press the key “ESC” to return to the main menu.
8.4.12 View Module Information

2. Press the key “▲” or “▼” to move the cursor to the “Information” menu, and then press
the key “ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to the command menu “ Board Info”, and
then press the “ENT” to enter the menu.
4. Press the key “▲” or “▼” to move the scroll bar.
5. Press the key “ENT” or “ESC” to exit this menu (returning to the “Information” menu).
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8.4.13 Select Language
2. Press the key “▲” or “▼” to move the cursor to the command menu “ Language”, and
then press the key “ENT” to enter the menu and the following display will be shown on
LCD.
Please Select Language:
1 中文
2 English
Figure 8.4-8 Display of selecting language
3. Press the key “▲” or “▼” to move the cursor to the language user preferred and press
the key “ENT” to execute language switching. After language switching is finished, LCD
will return to the menu “Language”, and the display language is changed. Otherwise,
press the key “ESC” to cancel language switching and return to the menu “ Language”.
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9 Configurabl e Function
Table of Contents
9 Configurable Function ....................................................................... 9-a
9.1 General Description ................................................................................................... 9-1
9.2 Introduction on PCS-Explorer Software ............................................................... 9-1

9.3 Device Setup ................................................................................................................ 9-1
9.3.1 Device Information ...........................................................................................................9-2
9.3.2 Function Configuration .....................................................................................................9-2
9.3.3 Function Group Configuration ..........................................................................................9-2
9.4 Program Configuration .............................................................................................. 9-3

9.4.1 LED Configuration ............................................................................................................9-3
9.4.2 Configuration of BI and BO...............................................................................................9-5
9.5 Setting Configuration................................................................................................. 9-7

9.5.1 Active Setting Group Selection .........................................................................................9-7
9.5.2 Browsing Settings ............................................................................................................9-8
9.5.3 Modify Name and Value of Settings..................................................................................9-8
List of Figures
Figure 9.3-1 Setting device information ................................................................................ 9-2
Figure 9.3-2 Function configuration interface....................................................................... 9-2
Figure 9.3-3 Function group configuration interface............................................................ 9-3
Figure 9.5-1 Setup of setting group ....................................................................................... 9-8
Figure 9.5-2 Modify setting name command ......................................................................... 9-8
Figure 9.5-3 Modify setting name dialog box ........................................................................ 9-9
Figure 9.5-4 Modify a setting value........................................................................................ 9-9
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Date: 2015-07-29
9.1 General Description
By adoption of PCS-Explorer software, it is able to make device configuration, function

configuration, LCD configuration, binary input and binary output configuration, LED indicator
configuration, setting configuration and programming logic for PCS-985TE.
9.2 Introduction on PCS-Explorer Software
PCS-Explorer software is developed in order to meet customer’s demand on functions of UAPC

platform device such as device configuration and programmable design. It selects substation as
the core of data management and the device as fundamental unit, supportin g one substation to
govern many devices. The software provides on-line and off-line functions: on-line mode: Ethernet
connected with the device supporting IEC60870-5-103 and capable of uploading and downloading
configuration files through Ethernet net; off-line mode: off-line setting configuration. In addition, it
also supports programmable logic to meet customer’s demand. Please refer to instruction Manual
of “PCS-Explorer Auxiliary Software” for details.
Overall functions:
 Programmable logic (off-line function)
 Device configuration (off-line function)
 Function configuration (off-line function)
 LCD configuration (off-line function)
 LED indicators configuration (off-line function)
 Binary input signals configuration (off-line function)
 Binary output signals configuration (off-line function)
 Setting configuration (off-line & on-line function)
 Real-time display of analogue and digital quantity of device (on-line function)
 Display of sequence of report (SOE) (on-line function)
 Analysis of waveform (off-line & on-line function)
 File downloading/uploading (on-line function)
9.3 Device Setup
Click “Device Config”→“Device Setup” node, and four labels are displayed in the edit window. The
four labels are used to set device information, configure the software and hardware related
function according to the selected series number of MOT, configure protection function and
configure protection function group respectively.
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9.3.1 Device Information
Select “Device Information” page to view the basic information of the device. All these information
are default settings in the selected driver package for creatin g the device. Part of the basic
information can be modified including “Project Name”, “User File Version” and “User Modify Time”.
Figure 9.3-1 Setting device information
9.3.2 Function Configuration
Choose “Function Configuration” page to enter function configuration interface as shown below
(the content may vary subject to created projects). Click the pull-down list in “Code” column to
perform function configuration.
Figure 9.3-2 Function configuration interface
9.3.3 Function Group Configuration
Choose “Function Group Configuration” page to enter function group configuration interface as
shown below (the content may vary subject to created projects). Click the pull-down list in “Code”
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column to perform function group configuration.
Figure 9.3-3 Function group configuration interface
9.4 Program Configuration
9.4.1 LED Configuration
On front panel of the device, two columns of indicators are normally provided. The first two
indicators indicate device running status (Healthy) and alarm status (Alarm). Colors of these
indicators may vary with functions of device.
The third LED (i.e. in3) is configured as the protection tripping LED indicator (TRIP) as default. If
user want to configure the third LED as other functions, please inform manufacturer when placing
an order.
The control of these indicators is configured by LED element configuration in PCS-Explorer.
Click “Program”→“B01:MON_Main” node, and select “LED” page to view and configure LED
element.
The following is an example of LED configuration:
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Figure 9.4-1 Example of LED configuration
Double click LED element to open its attributes setup window. users can see that it consists of 4
sub-pages. Switch to “Func Block Parameter” sub-page. Here, indicators LED3~20 can be set.
Each indicator has two items to be set: Parameter “ledx_latched” (x=3~20): click corresponding
entry under “Set Value” to select “yes” or “no”. If “yes” is selected, indicator attribute is “latched”,
indicating that after this indicator is lit, it will remain on even the initiation signal disappears until it
is reset. If “no” is selected, indicator attribute is “un-latched”, indicating that the indicator status will
follow the change of its initiation signal.
The other parameter is “ledx_color” (x=3~20): The color of indicator can be selected as required:
green, yellow, and red.
After completion of setup, click “OK” to close attributes setup window. The set parameters will be
displayed on the element, as shown below.
Figure 9.4-2 LED indicators configuration interface
Next, indicators initiation signals should be placed on the page and connect them to corresponding
input interfaces of LED element: select the output signal from the “Source” tab at the right side of
the window to be used as input source. Press and hold left button of mouse, and directly drag it to
the page. When this signal passes input signal connection point, a red dot will appear to prompt
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connection. After placing it at a suitable position, connection line will be automatically generated to
connect this input signal.
9.4.2 Configuration of BI and BO
The device is normally configured with a number of IO modules. Quantities may vary with different
project.
These BI and BO modules are normally configured according to general configuration.

Corresponding modules are usually selected according to the application. However, in some
cases, addition of IO modules may be required according to the changing requirements. At this
time, configuration of signals and parameters of additional IO modules is required. After creation of
a device using the template driver package by PCS-Explorer, required configuration can be
performed on editable page.
9.4.2.1 Configuration of BI
Takes BI module in slot No.10 as an example.
Click “Program” node. Unfold module node “B10:BI_NR1504”, one page node: “NR1504” is
shown.
Figure 9.4-3 Module nodes and pages in program configuration
Click the page “NR1504”, the corresponding BI configuration graph is shown in an editing window.
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Figure 9.4-4 Configuration graph of NR1504
In the graph, numbers in the “PIN” column are input terminal numbers of NR150 4 module, and
name or function of each pin is described in the “BI_Name” column.
For the two parameters columns of symbols “ ” and “ ”, the former indicates BI delay
pick up time and the latter indicates BI delay drop off time. If voltage applied between a BI input
and the common terminal exceeds the BI delay pick up time, corresponding output signal will be
energized, and if the applied voltage is disappeared for a period exceeding the BI delay drop off
time, the output signal will be reset.
All configurable binary inputs can be viewed in the “Destination” tab at the right side of the window
(variable library). The input signals of BI modules can be configured or modified according to the
application or drag the required signals from the variable library.
Please refer to the input signals table in Section “Inputs and Outputs” of each protection element in
Chapter 3 for the detailed description of each configurable binary inputs.
9.4.2.2 Configuration of BO
Takes BO module in slot No.13 as an example.
Click “Program” node. Unfold module node “B13:BO1”, one page node: “NR1523A” is shown.
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Figure 9.4-5 Configuration graph of NR1523A
In the graph, numbers in the “PIN” column are input terminal numbers of NR1523A module, and
name or function of each pin is described in the “BO_Name” column.
Inputs of all configurable binary outputs can be viewed in the “Source” tab at the right side of the
window (variable library). As shown in the figure, each input corresponds to one output contact of
the BO module. The output contact of BO module will operate (output relay pickup or reset) in
response to the status change of corresponding input signal. The output contacts of BO modules
can be configured or modified according to the application or drag the required signals from the
variable library.
Please refer to the output signals table in Section “Inputs and Outputs” of each protection element
in Chapter 3 for the detailed description of each configurable binary outputs.
9.5 Setting Configuration
9.5.1 Active Setting Group Selection
Click “Settings” node to enter “Settings” interface. In the middle of editing window is the setting
group setup interface, where two parameters can be set: “Active Group” and “Setting Groups:
[1-31]” (shown in Figure 9.5-1), users can change the number in the two text boxes then click the
button “Set” to modify the two parameters. The text box of “Active Group” is used for users to
change the current active setting group. The text box of “Setting Groups: [1-31]” is used for users
to change the number of active setting groups, the number of sub -nodes of “Setting” node will
change with this parameter.
Several sub-nodes: “Global” and “Group x” (x: 1~n, n is the number that inputted in the text box of
“Setting Groups: [1-31]”, n should not be larger than 31). Among them, global settings (the
sub-node “Global”) are common for all setting groups. In setting groups Group 1~Group n, only
one group is the current active setting group used in device operation, and mainly includes
protection settings, the current active setting group can be switched among Group 1~Group n
when required.
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Figure 9.5-1 Setup of setting group
9.5.2 Browsing Settings
Click “Settings”→“Global” node, five sub-nodes are unfolded (number of sub-nodes may vary with
different device models) in the edit window. These sub-nodes are used to set system settings,
logic links, device settings, communication settings and label settings.
Click “Settings”→“Group x” node, all the protective settings of corresponding group can be shown
by clicking corresponding setting menu item.
9.5.3 Modify Name and Value of Settings
Although there are many setting group nodes, settings under these nodes have the same layout in
editing page. Therefore, steps of modification of settings are basically the same. It is seen from the
graph that when any setting node is clicked and open, the editing page will display name, value,
range, step, and unit of the settings in this sequence. Here, user can modify name and set value of
the settings according to actual application requirements.
Figure 9.5-2 Modify setting name command
The name of a setting is the name user will finally see on the device. Users can suitably modify
this name according to actual project requirements: right click on the name entry to be modified to
pop up a right-key context menu, execute command “Modify Name”; the following window will pop
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up:
Figure 9.5-3 Modify setting name dialog box
In the “Modify Name” dialog box, users will see two entries, “Original Name” is the default name of
this setting in the symbol library, and “Name” is the name currently used, and can be modified.
Modified setting value must not exceed its range (if there has an ordain). There are two types of
set value modification operation: direct input of the value after double clicking corresponding entry
of the setting value, or selection from a pull-down menu.
User can also right click the entry of set value and select “Get Default Value” in the right-key
context menu, so as to obtain default set value of this entry from the symbol library.
During modification and editing operations of settings in the customizing editing window, modified
item will become red, till users perform saving operation.
Figure 9.5-4 Modify a setting value
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Table of Contents
10 Communications............................................................................. 10-a
10.1 General Description ...............................................................................................10-1
10.2 Rear Communication Port Information .............................................................10-1

10.2.1 RS-485 Interface ..........................................................................................................10-1
10.2.2 Ethernet Interface.........................................................................................................10-3
10.2.3 IEC60870-5-103 Communication .................................................................................10-4
10.3 IEC60870-5-103 Interface over Serial Port .......................................................10-4

10.3.1 Physical Connection and Link Layer.............................................................................10-5
10.3.2 Initialization ..................................................................................................................10-5
10.3.3 Time Synchronization ...................................................................................................10-5
10.3.4 Spontaneous Events ....................................................................................................10-5
10.3.5 General Interrogation ...................................................................................................10-6
10.3.6 General Functions ........................................................................................................10-6
10.3.7 Disturbance Records....................................................................................................10-6
10.4 IEC60870-5-103 Interface over Ethernet ...........................................................10-6

10.5 Messages Description for IEC61850 Protocol ................................................10-6
10.5.1 Overview......................................................................................................................10-6
10.5.2 Communication Profiles ...............................................................................................10-7
10.5.3 MMS Communication Network Deployment .................................................................10-8
10.5.4 Server Data Organization ........................................................................................... 10-11
10.5.5 Server Features and Configuration.............................................................................10-14
10.5.6 ACSI Conformance ....................................................................................................10-16
10.5.7 Logical Nodes ............................................................................................................10-20
10.6 DNP3.0 Interface .................................................................................................. 10-23

10.6.1 Overview....................................................................................................................10-23
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10.6.2 Link Layer Functions ..................................................................................................10-23
10.6.3 Transport Functions ...................................................................................................10-23
10.6.4 Application Layer Functions........................................................................................10-23
List of Figures
Figure 10.2-1 EIA RS-485 bus connection arrangements ................................................... 10-2
Figure 10.2-2 Ethernet communication cable ..................................................................... 10-3
Figure 10.2-3 Ethernet communication structure ............................................................... 10-4
Figure 10.5-1 Dual-net full duplex mode sharing the RCB block instance........................ 10-9
Figure 10.5-2 Dual-net hot-standby mode sharing the same RCB instance.................... 10-10
Figure 10.5-3 Dual-net full duplex mode with 2 independent RCB instances ..................10-11
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10.1 General Description
This section introduces NR’s remote communications interfaces. The protective device is
compatible with three protocols via the rear communication interface ( RS-485 or Ethernet). The
protocol provided by the protective device is indicated in the submenu in the “ Comm Settings”
column. Using the keypad and LCD to set the parameter [Protocol_RS485A] and
[Protocol_RS485B], the corresponding protocol will be selected.
The rear EIA RS-485 interface is isolated and is suitable for permanent connection no matter
whichever protocol is selected. It has advantage that 32 protective devices can be “daisy chained”
together in electrical connection using a twisted pair.
It should be noted that the descriptions in this section do not aim to fully introduce the protocol
itself. The relevant documentation for the protocol should be referred for this information. This
section serves to describe the specific implementation of the protocol in the relay.
10.2 Rear Communication Port Information
10.2.1 RS-485 Interface
This protective device provides two rear RS-485 communication ports, and each port has three
terminals in the 12-terminal screw connector located on the back of the relay. Each port has a
ground terminal for earth shield of communication cable. The rear ports provide RS-485 serial data
communication and are intended for permanently wired connection to a remote control center.
10.2.1.1 EIA RS-485 Standardized Bus
The EIA RS-485 two-wire connection provides a half-duplex fully isolated serial connection to the
product. The connection is polarized and whilst the product’s connection diagrams indicate the
polarization of the connection terminals it should be borne in mind that there is no agreed
definition of which terminal is which. If the master is unable to communicate with the product, but
the communication parameters match, then it is possible that the two -wire connection is reversed.
10.2.1.2 Bus Termination
The EIA RS-485 bus must have 120Ω (Ohm) ½ Watt terminating resistors fitted at either end
across the signal wires (refer to Figure 10.2-1). Some devices may be able to provide the bus
terminating resistors by different connection or configuration arrangements, in which case
separate external components will not be required. However, this product does not provide such a
facility, so an external termination resistor is required when it is located at the bus terminus.
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EIA RS-485
Master 120 Ohm
120 Ohm
Slave Slave Slave
Figure 10.2-1 EIA RS-485 bus connection arrangements
10.2.1.3 Bus Connections & Topologies
The EIA RS-485 requires that each device is directly connected to the physical cable i.e. the
communications bus. Stubs and tees are strictly forbidden, such as star topologies. Loop bus
topologies are not part of the EIA RS-485 standard and are forbidden also.
Two-core screened cable is recommended. The specification of the cable will be dependent on the
application, although a multi-strand 0.5mm2 per core is normally adequate. Total cable length
must not exceed 500m. The screen must be continuous and connected to ground at one end,
normally at the master connection point; it is important to avoid circulating currents, especia lly
when the cable runs between buildings, for both safety and noise reasons.
This product does not provide a signal ground connection. If a signal ground connection is present
in the bus cable then it must be ignored, although it must have continuity for the benefit of other
devices connected to the bus. The signal ground shall not be connected to the cables screen or to
the product’s chassis at any stage. This is for both safety and noise reasons.
10.2.1.4 Biasing
It may also be necessary to bias the signal wires to prevent jabber. Jabber occurs when the signal
level has an indeterminate state due to inactively driven of tubs. This can occur when all the slaves
are in receive mode and the master unit is slow to turn from receive mode to transmit mode. The
reason is that the master purposefully waits in receive mode, or even in a high impedance state,
until it has something to transmit. Jabber can result in the loss of first bits of the first character in
the packet for receiving device(s), which will lead to the rejection of messages for slave units,
causing non-responding between master unit and slave unit. This could brings poor response
times (due to retries), increase in message error counters, erratic communications, and even a
complete failure to communicate.
Biasing requires that the signal lines shall be weakly pulled to a defined voltage level of about 1V.
There should be only one bias point on the bus, which is best situated at the master connection
point. The DC source used for the bias must be clean; other wise noise will be injected. Please
note that some devices may (optionally) be able to provide the bus bias that the external
components will not be required.
NOTICE!
It is extremely IMPORTANT that the 120Ω termination resistors are fitted. Failure to do
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will result in an excessive bias voltage that may damage the devices connected to the
bus.
As the field voltage is much higher than that required, NR CANNOT assume
responsibility for any damage that may occur to a device connected to the network as a
result of incorrect application of this voltage.
ENSURE that the field voltage is not being used for other purposes (i.e. powering logic
inputs) as this may cause noise to be passed to the communication network.
10.2.2 Ethernet Interface
This protective device can provide four rear Ethernet interfaces (optional) and they are unattached
to each other. Parameters of each Ethernet port can be configured in the submenu “ Comm
Settings”.
10.2.2.1 Ethernet Standardized Communication Cable
It is recommended to use twisted screened eight-core cable as the communication cable. A picture
is shown bellow.
Figure 10.2-2 Ethernet communication cable
10.2.2.2 Connections and Topologies
Each device is connected with an exchanger via communication cable, and thereby it forms a star
structure network. Dual-network is recommended in order to increase reliability. SCADA is also
connected to the exchanger acting as the master station, and every device which has been
connected to the exchanger will act as a slave unit.
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SCADA
Exchanger A
Exchanger B
Equipment Equipment Equipment
Figure 10.2-3 Ethernet communication structure
10.2.3 IEC60870-5-103 Communication
The IEC specification IEC60870-5-103: Telecontrol Equipment and Systems, Part 5: Transmission
Protocols Section 103 defines the use of standards IEC60870-5-1 to IEC60870-5-5 to perform
communication with protective device. The standard configuration of IEC60870 -5-103 protocol is
using a twisted pair EIA RS-485 connection over distances up to 500m. It also supports an
Ethernet for communication between devices. The relay operates as a slave unit in the system to
respond commands received from master station.
To use the rear port with IEC60870-5-103 communication, the relevant settings of the protective
device must be configured by using keypad and LCD user interface. In the submenu “ Comm
Settings”, set the parameters [Protocol_RS485A], [Protocol_RS485B] and [Baud_RS485]. To use
the Ethernet port with IEC60870-5-103 communication, the IP address and the submask of each
Ethernet port shall be set in the same submenu. Please refer to the corresponding section in
Chapter “Settings” for further details.
10.3 IEC60870-5-103 Interface over Serial Port
The IEC60870-5-103 interface over serial port (RS-485) is a master/slave interface and the
protective device is the slave device.
The protective device conforms to compatibility level 3.
The following IEC60870-5-103 facilities are supported by this interface:
 Initialization (reset)
 Time synchronization
 Event record extraction
 General interrogation
 General commands
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 Disturbance records
10.3.1 Physical Connection and Link Layer
Two EIA RS-485 standardized ports are available for IEC60870-5-103 in this protective device.
The transmission speed is optional: 4800 bit/s, 9600 bit/s, 19200 bit/s or 38400 bit /s.
The link layer strictly abides by the rules defined in the IEC60870-5-103.
10.3.2 Initialization
When the protective device is powered up, or the communication parameters are changed, a reset
command is required to initialize the communications. The protective device will respond to either
of the two reset commands (Reset CU or Reset FCB), the difference is that the Reset CU will clear
any unsent messages in the transmit buffer.
The protective device will respond to the reset command with an identification mes sage ASDU 5,
the COT (Cause Of Transmission) of this response will be either Reset CU or Reset FCB
depending on the nature of the reset command.
10.3.3 Time Synchronization
The time and date of protective device can be set by time synchronization feature of the
IEC60870-5-103 protocol. The transmission delay as specified in IEC60870 -5-103 will be
corrected in the protective device. If the time synchronization message is sent as a send/confirm
message, then the protective device will respond with a confirmation. Wh ether the
time-synchronization message is sent as a send confirmation or a broadcast (send/no reply)
message, a time synchronization class 1 event will be generated/produced.
If the protective device clock is synchronized using the IRIG-B input, the protection device will not
be able to set the time using the IEC60870-5-103 interface. For attempt to set the time via the
interface, the protective device will create an event with the date and time taken from the IRIG -B
synchronized internal clock.
10.3.4 Spontaneous Events
Events are categorized by the following information:
 Type identification (TYP)
 Function type (FUN)
 Information number (INF)
Messages sent to substation automation system are grouped according to IEC60870 -5-103
protocol. Operation elements are sent by ASDU2 (time-tagged message with relative time), and
status of binary Input and alarm element are sent by ASDU1 (time-tagged message). The cause of
transmission (COT) of these responses is 1.
The complete list of all events produced by the protective device can be printed by choosing the
submenu “IEC103 Info” in the menu “Print”.
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10.3.5 General Interrogation
The GI can be used to read the status of the relay, the function numbers, and the information
numbers that will be returned during the GI cycle. The GI cycle strictly abides by the rules defined
in the IEC60870-5-103.
Refer the IEC60870-5-103 standard can get the enough details about general interrogation.
10.3.6 General Functions
The general functions can be used to read the setting and protection measurement of t he relay,
and modify the setting. Two supported type identifications are ASDU 21 and ASDU 10. For more
details about generic functions, please see the IEC60870-5-103 standard.
Generic service group numbers supported by the relay can be printed by the submenu “IEC103
Info” in the menu “Print”.
10.3.7 Disturbance Records

This protective device can store up to 32 disturbance records in its memory. Pickup of fault
detector or operation of relay will be stored as disturbance recorders in the protective device.
The disturbance records are stored in uncompressed format and can be extracted using the
standard mechanisms described in IEC60870-5-103.
It can be printed by the submenu “IEC103 Info” in the menu “Print”
10.4 IEC60870-5-103 Interface over Ethernet
The IEC60870-5-103 interface over Ethernet is a master/slave interface with the relay as the slave
device. All the functions provided by this relay are based on generic functions of the
IEC60870-5-103. This relay will send all the relevant information on group caption to SAS or RTU
after establishing a successful communication link.
10.5 Messages Description for IEC61850 Protocol
10.5.1 Overview
The IEC 61850 standard is the result of years of work by electric utilities and vendors of electronic
device to produce standardized communications systems. IEC 61850 is a series of standards
describing client/server and peer-to-peer communications, substation design and configuration,
testing, environmental and project standards. The complete set includes:
 IEC 61850-1: Introduction and overview
 IEC 61850-2: Glossary
 IEC 61850-3: General requirements
 IEC 61850-4: System and project management
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 IEC 61850-5: Communications and requirements for functions and device models
 IEC 61850-6: Configuration description language for communication in electrical su bstations

related to IEDs
 IEC 61850-7-1: Basic communication structure for substation and feeder device - Principles
and models
 IEC 61850-7-2: Basic communication structure for substation and feeder device - Abstract
communication service interface (ACSI)
 IEC 61850-7-3: Basic communication structure for substation and feeder device – Common
data classes
 IEC 61850-7-4: Basic communication structure for substation and feeder device – Compatible
logical node classes and data classes
 IEC 61850-8-1: Specific Communication Service Mapping (SCSM) – Mappings to MMS (ISO
9506-1 and ISO 9506-2) and to ISO/IEC 8802-3
 IEC 61850-9-1: Specific Communication Service Mapping (SCSM) – Sampled values over
serial unidirectional multidrop point to point link
 IEC 61850-9-2: Specific Communication Service Mapping (SCSM) – Sampled values over
ISO/IEC 8802-3
 IEC 61850-10: Conformance testing
These documents can be obtained from the IEC (http://www.iec.ch). It is strongly recommended
that all those involved with any IEC 61850 implementation obtain this document set.
10.5.2 Communication Profiles
The relay supports IEC 61850 server services over TCP/IP communication protocol stacks. The
TCP/IP profile requires IP address to establish communications. These addresses are located in
the submenu “Settings→Device Setup→Comm Settings”.
1. MMS protocol
IEC 61850 specifies the use of the Manufacturing Message Specification (MMS) at the upper
(application) layer for transfer of real-time data. This protocol has been in existence for a number
of years and provides a set of services suitable for the transfer of data within a substation LAN
environment. IEC 61850-7-2 abstract services and objects are mapped to actual MMS protocol
services in IEC61850-8-1.
2. Client/server
This is a connection-oriented type of communication. The connection is initiated by the client, and
communication activity is controlled by the client. IEC61850 clients are often substation computers
running HMI programs or SOE logging software. Servers are usually substation device such as
protection relays, meters, RTUs, instrument transformers, tap changers, or bay controllers.
Please note that gateways can be considered as clients and servers subject to the communication
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object. When retrieving data from IEDs within the substation, the gatewa ys are considered as
servers whereas transmitting data to control centers, the gateways are considered as clients.
3. Peer-to-peer
This is a non-connection-oriented high speed communication between substation device, such as

protection relays. GOOSE is the method of peer-to-peer communication.
4. Substation configuration language (SCL)
A substation configuration language is a number of files used to describe IED configurations and
communication systems according to IEC 61850-5 and IEC 61850-7. Each configured device has
an IED Capability Description (ICD) file and a Configured IED Description (CID) file. The
substation single line information is stored in a System Specification Description (SSD) file. The
entire substation configuration is stored in a Substation Configuration Description (SCD) file. The
SCD file is the combination of the following items: individual ICD files, SSD file, communication
system parameters (MMS, GOOSE control block, SV control block), as well as GOOSE/SV
connection relationship amongst IEDs.
10.5.3 MMS Communication Network Deployment
To enhance the stability and reliability of SAS, dual-MMS Ethernet is widely adopted. This section
is applied to introduce the details of dual-MMS Ethernet technology. Generally, single-MMS
Ethernet is recommended to be adopted in the SAS of 110kV and lower voltage levels, while
dual-MMS Ethernet is recommended to be adopted in the SAS of voltage levels above 110kV.
Client-server mode is adopted: clients (SCADA, control center and etc.) communicate with the
IEDs via MMS communication network, and the IEDs operate as the servers. IEDs are connected
to clients passively, and they can interact with the clients according to the configuration and the
issued command of the clients.
Three modes for dual-MMS Ethernet (abbreviated as dual-net) are provided as below.
NOTICE!
Hereinafter, the normal operation status of net means the physical link and TCP link are
both ok. The abnormal operation status of net means physical link or TCP link is
broken.
1) Mode 1: Dual-net full duplex mode sharing the same RCB instance
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Client Client
Net A Net B Net A Net B
Report Instance 1 Report Instance 1
RptEna = true RptEna = true
Report Control Block Report Control Block

IED (Server) IED (Server)
Normal operation status Abnormal operation status
TCP Link
MMS Link
Figure 10.5-1 Dual-net full duplex mode sharing the RCB block instance
Net A and Net B share the same report control block (abbreviated as RCB) enabled by the client.
IED sends undifferentiated date through dual-net to the clients. If one net is physically
disconnected, the flag of RCB instance (i.e.: “RptEna” in above figure) is still “true”. Only when
both Net A and Net B are disconnected, the flag of the RCB instance will automatically change to
“false”.
In normal operation status of mode 1, IED provides the same MMS service for Net A and Net B. If
one net is physically disconnected (i.e.: “Abnormal operation status” in above figure), the working
mode will switch to single-net mode seamlessly and immediately. Network communication
supervision is unnecessary here, and Buffered Report Control Block (abbreviated as BRCB) need
not to be used. On the other net, date alternation works normally. Therefore, MMS service can
interact normally without interruption. This mode ensures no data loss during one net is in
abnormal operation status.
In mode 1, one report will be transmitted twice via dual nets for the same report instance, so the
client needs to distinguish whether two reports are same according to corresponding EntryIDs.
2) Mode 2: Dual-net hot-standby mode sharing the same RCB instance
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Client Client
Report Instance 1 Report Instance 1
RptEna = true RptEna = true

Normal operation status Abnormal operation status
TCP Link
Main MMS Link
Standby MMS Link
Figure 10.5-2 Dual-net hot-standby mode sharing the same RCB instance
In mode 2, the MMS service is provided on main MMS link, no MMS service interacts on the
standby MMS link. The definitions of two links are as follows:
 Main MMS Link: Physically connected, TCP level connected, MMS report service available.
 Standby MMS Link: Physically connected, TCP level connected, MMS report service not
available.
If the main net fails to operate (i.e.: “Abnormal operation status” in the above figure), the IED will
set “RptEna” to “false”. Meanwhile the client will detect the failure by heartbeat message or
“keep-alive”, it will automatically enable the RCB instance by setting “RptEna” back to “true”
through standby MMS link. By the buffer function of BRCB, the IED can provide uninterrupted
MMS service on the standby net. However, the differences of BRCB standards among different
manufacturers may cause data loss. Moreover, if duration of net switch is too long, the data loss is
positively as the capacity of BRCB’s buffer function is limited.
NOTICE!
In mode 1 and mode 2, Net A IED host address and Net B IED host address must be
the same. E.g.: if the subnet mask is 255.255.0.0, network prefix of Net A is
198.120.0.0, network prefix of Net B is 198.121.0.0, Net A IP address of the IED is
198.120.1.2, and then Net B IP address of the IED must be configured as 198.121.1.2,
i.e.: Net A IED host address =1x256+2=258, Net B IED host address =1x256+2=258,
Net A IED host address equals to Net B IED host address.
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3) Mode 3: Dual-net full duplex mode with 2 independent RCB instances
Client Client
Report Instance 1 Report Instance 2 Report Instance 1 Report Instance 2
RptEna = true RptEna = true RptEna = false RptEna = true

TCP Link
MMS Link
Figure 10.5-3 Dual-net full duplex mode with 2 independent RCB instances
In mode 3, IED provides 2 report instances for each RCB, Net A and Net B work independently
from each other, failures of one net will not affect the other net at all.
In this mode, 2 report instances are required for each client. Therefore, the IED may be unable to
provide enough report instances if there are too many clients.
Net A and Net B send the same report separately when they operates normally, To ensure no
repeated data is saved into database, massive calculation is required for the client.
Moreover, accurate clock synchronization of the IED is required to distinguish whether 2 reports
are the same report according to the timestamps. Clock synchronization error of the IED may lead
to report loss/redundancy.
As a conclusion:
In mode 2, it’s difficult to realize seamless switchover between dual nets;
In mode 3, the IED may be unable to provide enough report instances if too many clients are
applied on site.
For the consideration of client treatment and IED implementation, mode 1 (Dual-net full duplex
mode sharing the same report instance) is recommended for MMS communication network
deployment.
10.5.4 Server Data Organization
IEC61850 defines an object-oriented approach to data and services. An IEC61850 physical device
can contain one or more logical device(s) (for proxy). Each logical device can contain many logical
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nodes. Each logical node can contain many data objects. Each data object is composed of data
attributes and data attribute components. Services are available at each level for performing
various functions, such as reading, writing, control commands, and reporting.
Each IED represents one IEC61850 physical device. The physical device contains one or more
logical device(s), and the logical device contains many logical nodes. The logical node LPHD
contains information about the IED physical device. The logical node LLN0 contains common
information about the IED logical device.
10.5.4.1 Digital Status Values
The GGIO logical node is used to provide access to digital status points (including general I/O
inputs and warnings) and associated timestamps and quality flags. The data content must be
configured before using. GGIO provides digital status points for access by clients. It is intended for
the use of GGIO by client to access to digital status values from PCS-985TE relays. Clients can
utilize the IEC61850 buffered report from GGIO to build sequence of events (SOE) logs and HMI
display screens. Buffered reporting should generally be used for SOE logs since the buffering
capability reduces the chances of missing data state changes. All needed status data objects are
transmitted to HMI clients via buffered reporting, and the corresponding buffered reporting control
block (BRCB) is defined in LLN0.
10.5.4.2 Analog Values
Most of measured analog values are available through the MMXU logical nodes, and metering
values in MMTR, the others in MMXN, MSQI and so on. Data of each MMXU logical node is
provided from a IED current/voltage “source”. There is one MMXU available for each configurable
source. Data of MMXU1 is provided from CT/VT source 1 (usually for protection purpose), and
data of MMXU2 is provided from CT/VT source 2 (usually for monitor and display purpose). All
these analog data objects are transmitted to HMI clients via unbuffered reporting periodically, and
the corresponding unbuffered reporting control block (URCB) is defined in LLN0. MMXUx logical
nodes provide the following data for each source:
 MMXU.MX.Hz: frequency
 MMXU.MX.PPV.phsAB: phase AB voltage magnitude and angle
 MMXU.MX.PPV.phsBC: phase BC voltage magnitude and angle
 MMXU.MX.PPV.phsCA: Phase CA voltage magnitude and angle
 MMXU.MX.PhV.phsA: phase AG voltage magnitude and angle
 MMXU.MX.PhV.phsB: phase BG voltage magnitude and angle
 MMXU.MX.PhV.phsC: phase CG voltage magnitude and angle
 MMXU.MX.A.phsA: phase A current magnitude and angle
 MMXU.MX.A.phsB: phase B current magnitude and angle
 MMXU.MX.A.phsC: phase C current magnitude and angle
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10.5.4.3 Protection Logical Nodes
The following list describes the protection elements for PCS-985TE relays. The specified relay will
contain a subset of protection elements from this list.
 PDIF: current differential and transfer trip
 PTOC: Time overcurrent
 SCAS: Mechanical relay protection
 PDIS: Distance protection
 PDOP: Directional over power
 PVPH: Volts per Hz
 PDIR: Fault direction comparison
 PVCE: Voltage control element
 PTTR: Thermal overload
 PVOC: Voltage controlled time overcurrent
 PIOC: Instantaneous overcurrent
 PZSG: Fundamental zero-sequence voltage stator ground fault protection
The protection elements listed above contain start (pickup) and operate flags, instead of any
element has its own start (pickup) flag separately, all the elements share a common start (pickup)
flags “PTRC.ST.Str.general”. The operate flag for PDIF1 is “PDIF1.ST.Op.general”. For
PCS-985TErelay protection elements, these flags take their values from related module for the
corresponding element. Similar to digital status values, the protection trip information is reported
via BRCB, and it also locates in LLN0.
10.5.4.4 LLN0 and Other Logical Nodes
Logical node LLN0 is essential for an IEC61850 based IED. This LN shall be used to address
common issues for Logical Devices. Most of the public services, the common settings, control
values and some device oriented data objects are available here. The public services may be
BRCB, URCB and GSE control blocks and similar global defined for the whole device; the
common settings include all the setting items of communication settings, system settings and
some of the protection setting items, which can be configured to two or more protec tion elements
(logical nodes). In LLN0, the item Loc is a device control object, this item indicates the local
operation for complete logical device, when it is true, all the remote control commands to the IED
will be blocked until Loc is changed to false. In PCS-985TE relays, besides the logical nodes
described above, there are some other logical nodes in the IEDs:
 LPHD: Physical device information, the logical node to model common issues for physical
device.
 PTRC: Protection trip conditioning, it is used to connect the “operate” outputs of one or more
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protection functions to a common “trip” to be transmitted to XCBR. In addition or alternatively, any

combination of “operate” outputs of protection functions may be combined to a new “operate” of
PTRC.
 RDRE: Disturbance recorder function. It triggers fault wave recorder and its output refers to
the “IEEE Standard Format for Transient Data Exchange (COMTRADE) for Power System” (IEC
60255-24). All enabled channels are included in the recording and is independent of the trigger
mode.
 TCTR: Current transformer
 TVTR: Voltage transformer
 YPTR: Power transformer
10.5.5 Server Features and Configuration
10.5.5.1 Buffered/unbuffered Reporting
IEC61850 buffered and unbuffered reporting control blocks are located in LLN0, they can be
configured to transmit information of protection trip information (in the Protection logical nodes),
binary status values (in GGIO) and analog measured/calculated values (in MMXU, MMTR and
MSQI). The reporting control blocks can be configured in CID files, an d then be sent to the IED via
an IEC61850 client. The following items can be configured.
 TrgOps: Trigger options.
The following bits are supported by PCS-985TE relays:
－ Bit 1: Data-change
－ Bit 4: Integrity
－ Bit 5: General interrogation
 OptFlds: Option Fields.
The following bits are supported by PCS-985TE relays:
－ Bit 1: Sequence-number
－ Bit 2: Report-time-stamp
－ Bit 3: Reason-for-inclusion
－ Bit 4: Data-set-name
－ Bit 5: Data-reference
－ Bit 6: Buffer-overflow (for buffered reports only)
－ Bit 7: EntryID (for buffered reports only)
－ Bit 8: Conf-revision
－ Bit 9: Segmentation
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 IntgPd: Integrity period.
 BufTm: Buffer time.
10.5.5.2 File Transfer
MMS file services allows transfer of oscillography, event record or other files from a PCS-985TE
relay.
10.5.5.3 Timestamps
The timestamp values associated with all IEC61850 data items represent the time of the last
change of either the value or quality flags of the data item.
10.5.5.4 Logical Node Name Prefixes
IEC61850 specifies that each logical node can have a name with a total length of 11 characters.
The name is composed of:
 A five or six-character name prefix.
 A four-character standard name (for example, MMXU, GGIO, PIOC, etc.).
 A one or two-character instantiation index.
Complete names are in the form of xxxxxxPTOC1, where the xxxxxx character string is
configurable. Details regarding the logical node naming rules are given in IEC61850 parts 6 and
7-2. It is recommended that a consistent naming convention be used for an entire substation
project.
10.5.5.5 GOOSE Services
IEC61850 specifies the type of broadcast data transfer services: Generic Object Oriented
Substation Events (GOOSE). IEC61850 GOOSE services provide virtual LAN (VLAN) support,
Ethernet priority tagging, and Ether-type Application ID configuration. The support for VLANs and
priority tagging allows for the optimization of Ethernet network traffic. GOOSE messages can be
given a higher priority than standard Ethernet traffic, and they can be separated onto specific
VLANs. Devices that transmit GOOSE messages also function as server s. Each GOOSE
publisher contains a “GOOSE control block” to configure and control the transmission.
The GOOSE transmission (including subscribing and publishing) is controlled by GOOSE logic link
settings in device.
The relay supports IEC61850 Generic Object Oriented Substation Event (GOOSE)
communication. All GOOSE messages contain IEC61850 data collected into a dataset. It is this
dataset that is transferred using GOOSE message services. The GOOSE related dataset is
configured in the CID file and it is recommended that the fixed GOOSE be used for
implementations that require GOOSE data transfer between PCS-985TE relays.
IEC61850 GOOSE messaging contains a number of configurable parameters, all of which must be
correct to achieve the successful transfer of data. It is critical that the configured datasets at the
transmission and reception devices are an exact match in terms of data structure, and that the
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GOOSE addresses and name strings match exactly.
10.5.6 ACSI Conformance
10.5.6.1 ACSI Basic Conformance Statement
Services Client Server PCS-985TE
Client-Server Roles
B11 Server side (of Two-party Application-Association) － C1 Y
B12 Client side (of Two-party Application-Association) C1 － N
SCSMS Supported
B21 SCSM: IEC 61850-8-1 used N N Y
B22 SCSM: IEC 61850-9-1 used N N N
B23 SCSM: IEC 61850-9-2 used N N N
B24 SCSM: other N N N
Generic Substation Event Model (GSE)
B31 Publisher side － O Y
B32 Subscriber side O － Y
Transmission Of Sampled Value Model (SVC)
B41 Publisher side － O N
B42 Subscriber side O － N
Where:
C1: Shall be "M" if support for LOGICAL-DEVICE model has been declared
O: Optional
M: Mandatory
Y: Supported by PCS-985TE relay
N: Currently not supported by PCS-985TE relay
10.5.6.2 ACSI Models Conformance Statement
M1 Logical device C2 C2 Y
M2 Logical node C3 C3 Y
M3 Data C4 C4 Y
M4 Data set C5 C5 Y
M5 Substitution O O Y
M6 Setting group control O O Y
Reporting
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M7 Buffered report control O O Y
M7-1 sequence-number Y Y Y
M7-2 report-time-stamp Y Y Y
M7-3 reason-for-inclusion Y Y Y
M7-4 data-set-name Y Y Y
M7-5 data-reference Y Y Y
M7-6 buffer-overflow Y Y N
M7-7 entryID Y Y Y
M7-8 BufTm N N N
M7-9 IntgPd Y Y Y
M7-10 GI Y Y Y
M8 Unbuffered report control M M Y
M8-1 sequence-number Y Y Y
M8-2 report-time-stamp Y Y Y
M8-3 reason-for-inclusion Y Y Y
M8-4 data-set-name Y Y Y
M8-5 data-reference Y Y Y
M8-6 BufTm N N N
M8-7 IntgPd N Y Y
Logging
M9 Log control O O N
M9-1 IntgPd N N N
M10 Log O O N
GSE
M12 GOOSE O O Y
M13 GSSE O O N
M14 Multicast SVC O O N
M15 Unicast SVC O O N
M16 Time M M Y
M17 File transfer O O Y
Where:
C2: Shall be "M" if support for LOGICAL-NODE model has been declared
C3: Shall be "M" if support for DATA model has been declared
C4: Shall be "M" if support for DATA-SET, Substitution, Report, Log Control, or Time models has
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been declared
C5: Shall be "M" if support for Report, GSE, or SMV models has been declared
M: Mandatory
Y: Supported by the relay
N: Currently not supported by the relay
10.5.6.3 ACSI Services Conformance Statement
Service Server/Publisher PCS-985TE
Server
S1 ServerDirectory M Y
Application association
S2 Associate M Y
S3 Abort M Y
S4 Release M Y
Logical device
S5 LogicalDeviceDirectory M Y
Logical node
S6 LogicalNodeDirectory M Y
S7 GetAllDataValues M Y
Data
S8 GetDataValues M Y
S9 SetDataValues M Y
S10 GetDataDirectory M Y
S11 GetDataDefinition M Y
Data set
S12 GetDataSetValues M Y
S13 SetDataSetValues O Y
S14 CreateDataSet O N
S15 DeleteDataSet O N
S16 GetDataSetDirectory M Y
Substitution
S17 SetDataValues M Y
Setting group control
S18 SelectActiveSG M/O Y
S19 SelectEditSG M/O Y
S20 SetSGValuess M/O Y
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S21 ConfirmEditSGValues M/O Y
S22 GetSGValues M/O Y
S23 GetSGCBValues M/O Y
Reporting
Buffered report control block
S24 Report M Y
S24-1 data-change M Y
S24-2 qchg-change M N
S24-3 data-update M N
S25 GetBRCBValues M Y
S26 SetBRCBValues M Y
Unbuffered report control block
S27 Report M Y
S27-1 data-change M Y
S27-2 qchg-change M N
S27-3 data-update M N
S28 GetURCBValues M Y
S29 SetURCBValues M Y
Logging
Log control block
S30 GetLCBValues O N
S31 SetLCBValues O N
Log
S32 QueryLogByTime O N
S33 QueryLogAfter O N
S34 GetLogStatusValues O N
Generic substation event model (GSE)
GOOSE control block
S35 SendGOOSEMessage M Y
S36 GetGoReference O Y
S37 GetGOOSEElementNumber O N
S38 GetGoCBValues M Y
S39 SetGoCBValuess M N
Control
S51 Select O N
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S52 SelectWithValue M Y
S53 Cancel M Y
S54 Operate M Y
S55 Command-Termination O Y
S56 TimeActivated-Operate O N
File transfer
S57 GetFile M/O Y
S58 SetFile O N
S59 DeleteFile O N
S60 GetFileAttributeValues M/O Y
Time
SNTP M Y
10.5.7 Logical Nodes
10.5.7.1 Logical Nodes Table
The relay support IEC61850 logical nodes as indicated in the following table. Note that the actual
instantiation of each logical node is determined by the product order code.
Nodes PCS-985TE
L: System Logical Nodes
LPHD: Ph ysical device information YES
LLN0: Logical node zero YES
P: Logical Nodes For Protection Functions
PDIF: Differential YES
PDIR: Direction comparison YES
PDIS: Distance YES
PDOP: Directional overpower －
PDUP: Directional underpower －
PFRC: Rate of change of frequency －
PHAR: Harmonic restraint －
PHIZ: Ground detector －
PIOC: Instantaneous overcurrent YES
PMRI: Motor restart inhibition －
PMSS: Motor starting time supervision －
POPF: Over power factor －
PPAM: Phase angle measuring －
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Nodes PCS-985TE
PSCH: Protection scheme －
PSDE: Sensitive directional earth fault －
PTEF: Transient earth fault －
PTOC: Time overcurrent YES
PTOF: Overfrequency －
PTOV: Overvoltage YES
PTRC: Protection trip conditioning YES
PTTR: Thermal overload YES
PTUC: Undercurrent －
PTUV: Undervoltage －
PUPF: Underpower factor －
PTUF: Underfrequency －
PVOC: Voltage controlled time overcurrent YES
PVPH: Volts per Hz YES
PZSU: Zero speed or underspeed －
R: Logical Nodes For Protection Related Functions
RDRE: Disturbance recorder function YES
RADR: Disturbance recorder channel analogue －
RBDR: Disturbance recorder channel binary －
RDRS: Disturbance record handling －
RBRF: Breaker failure －
RDIR: Directional element YES
RFLO: Fault locator －
RPSB: Power swing detection/blocking －
RREC: Autoreclosing －
RSYN: Synchronism-check or synchronizing －
C: Logical Nodes For Control
CALH: Alarm handling －
CCGR: Cooling group control －
CILO: Interlocking －
CPOW: Point-on-wave switching －
CSWI: Switch controller －
G: Logical Nodes For Generic References
GAPC: Generic automatic process control －
GGIO: Generic process I/O YES
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Nodes PCS-985TE
GSAL: Generic security application －
I: Logical Nodes For Interfacing And Archiving
IARC: Archiving －
IHMI: Human machine interface －
ITCI: Telecontrol interface －
ITMI: Telemonitoring interface －
A: Logical Nodes For Automatic Control
ANCR: Neutral current regulator －
ARCO: Reactive power control －
ATCC: Automatic tap changer controller －
AVCO: Voltage control －
M: Logical Nodes For Metering And Measurement
MDIF: Differential measurements YES
MHAI: Harmonics or interharmonics －
MHAN: Non phase related harmonics or interharmonic －
MMTR: Metering －
MMXN: Non phase related measurement YES
MMXU: Measurement YES
MSQI: Sequence and imbalance YES
MSTA: Metering statistics －
S: Logical Nodes For Sensors And Monitoring
SARC: Monitoring and diagnostics for arcs －
SIMG: Insulation medium supervision (gas) －
SIML: Insulation medium supervision (liquid) －
SPDC: Monitoring and diagnostics for partial discharges －
X: Logical Nodes For Switchgear
TCTR: Current transformer YES
TVTR: Voltage transformer YES
Y: Logical Nodes For Power Transformers
YEFN: Earth fault neutralizer (Peterson coil) －
YLTC: Tap changer －
YPSH: Power shunt －
YPTR: Power transformer YES
Z: Logical Nodes For Further Power System Equipment
ZAXN: Au xiliary network －
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Nodes PCS-985TE
ZBAT: Battery －
ZBSH: Bushing －
ZCAB: Power cable －
ZCAP: Capacitor bank －
ZCON: Converter －
ZGEN: Generator －
ZGIL: Gas insulated line －
ZLIN: Power overhead line －
ZMOT: Motor －
ZREA: Reactor －
ZRRC: Rotating reactive component －
ZSAR: Surge arrestor －
ZTCF: Thyristor controlled frequency converter －
ZTRC: Th yristor controlled reactive component －
10.6 DNP3.0 Interface
10.6.1 Overview
The descriptions given here are intended to accompany this relay. The DNP3.0 protocol is not
described here; please refer to the DNP3.0 protocol standard for the details about the DNP3.0
implementation. This manual only specifies which objects, variations and qualifiers are supported
in this relay, and also specifies what data is available from this relay via DNP3.0.
The relay operates as a DNP3.0 slave and supports subset level 3 of the protocol, plus some of
the features from level 4. The DNP3.0 communication uses the Ethernet ports (electrical or optical)
at the rear side of this relay.
10.6.2 Link Layer Functions
Please see the DNP3.0 protocol standard for the details about the linker layer functions.
10.6.3 Transport Functions
Please see the DNP3.0 protocol standard for the details about the transport functions.
10.6.4 Application Layer Functions
10.6.4.1 Function Code
Function Code Function

0 (0x00) Confirm
1 (0x01) Read
2 (0x02) Write
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Function Code Function

3 (0x03) Select
4 (0x04) Operate
5 (0x05) Direct Operate
6 (0x06) Direct Operate No Acknowledgment
13 (0x0D) Cold Restart
14 (0x0E) Warm Restart
20 (0x14) Enable Unsolicited Responses
21 (0x15) Disable Unsolicited Responses
22 (0x16) Assign Class
23 (0x17) Delay Measurement
10.6.4.2 Supported Object List
The supported object groups and object variations are show in the following table.
Request: Master may issue/Outstation shall parse
Function code: decimalism
Qualifier code: hexadecimal
OBJ ECT GROUP & VARIATION REQUEST

Group/Variation
Description Function code Qualifier code
No.
1 (read) 00, 01 (start ~ stop)
1 0 Binary Input: An y Variation
22 (assign class) 06 (no range, or all)
00, 01 (start ~ stop)
1 1 Binary Input: Packed format 1 (read)
06 (no range, or all)
1 2 Binary Input: With flags 1 (read)
2 0 Binary Input Event: An y Variation 1 (read)
07, 08 (limited qty)
2 1 Binary Input Event: Without time 1 (read)
2 2 Binary Input Event: With absolute time 1 (read)
2 3 Binary Input Event: With relative time 1 (read)
10 0 Binary output: Any Variation 1 (read)
10 0 Binary output: Any Variation 1 (read)
10 1 Binary output: Packed format 2 (write) 00, 01 (start ~ stop)
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Group/Variation
No.
3 (select)
Binary Command: Control relay output block 4 (operate) 17, 28 (index)
12 1
(CROB) 5 (direct op)
6 (dir. op, no ack) 17, 28 (index)
1 (read) 00, 01 (start ~ stop)
30 0 Analog Input: An y Variation
22 (assign class) 06 (no range, or all)
30 1 Analog Input: 32 ~ bit with flag 1 (read)
30 2 Analog Input: 16 ~ bit with flag 1 (read)
30 3 Analog Input: 32 ~ bit without flag 1 (read)
30 4 Analog Input: 16 ~ bit without flag 1 (read)
30 5 Analog Input: Single ~ prec flt ~ pt with flag 1 (read)
32 0 Analog Input Event: An y Variation 1 (read)
07,08 (limited qty)
32 1 Analog Input Event: 32 ~ bit without time 1 (read)
07,08 (limited qty)
32 2 Analog Input Event: 16 ~ bit without time 1 (read)
07,08 (limited qty)
Analog Input Event: Single ~ prec flt ~ pt 06 (no range, or all)
32 5 1 (read)
without time 07,08 (limited qty)
34 0 Analog Input Deadband: An y Variation 1 (read)
1 (read)
34 1 Analog Input Deadband: 16 ~ bit
2 (write)
17,28 (index)
1 (read)
2 (write)
17,28 (index)
1 (read)
34 3 Analog Input Deadband: Single ~ prec flt ~ pt
2 (write)
17,28 (index)
40 0 Analog Output Status: An y Variation 1 (read)
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Group/Variation
No.
40 1 Analog Output Status: 32 ~ bit with flag 1 (read)
40 2 Analog Output Status: 16 ~ bit with flag 1 (read)
Analog Output Status: single ~ prec flt ~ pt with 00, 01 (start ~ stop)
40 3 1 (read)
flag 06 (no range, or all)
3 (select)
4 (operate) 17,28 (index)
41 1 Analog Output: 32 ~ bit
5 (direct op)
6 (dir. Op, no ack) 17,28 (index)
3 (select)
41 2 Analog Output: 16 ~ bit
5 (direct op)
3 (select)
41 3 Analog Output: Single ~ prec ft ~ pt
5 (direct op)
1 (read) 07 (limited qty = 1)
50 1 Time and Data: Absolute time
2 (write) 07 (limited qty = 1)
Time and Data: Absolute time at last recorded
50 3 2 (write) 07 (limited qty = 1)
time
Time and Data CTO: Absolute time,
51 1
synchronized
Time and Data CTO: Absolute time,
51 2
unsynchronized
1 (read)
60 1 Class Objects: Class 0 data 06 (no range, or all)
22 (assign class)
1 (read)
07,08 (limited qty)
60 2 Class Objects: Class 1 data 20 (enable unsol.)
21 (disable unsol.) 06 (no range, or all)
22 (assign class)
1 (read)
07,08 (limited qty)
60 3 Class Objects: Class 2 data 20 (enable unsol.)
22 (assign class)
60 4 Class Objects : Class 3 data 1 (read)
07,08 (limited qty)
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Group/Variation
No.
20 (enable unsol.)
22 (assign class)
Response: Master shall parse\Outstation may issue
Function code: decimalism
Qualifier code: hexadecimal
OBJ ECT GROUP & VARIATION RESPONSE

Group/Variation
No.
1 0 Binary Input: An y Variation
1 1 Binary Input: Packed format 129 (response) 00, 01 (start ~ stop)
1 2 Binary Input: With flags 129 (response) 00, 01 (start ~ stop)
2 0 Binary Input Event: An y Variation
129 (response)
2 1 Binary Input Event: Without time 17, 28 (index)
130 (unsol. resp)
129 (response)
2 2 Binary Input Event: With absolute time 17, 28 (index)
130 (unsol. resp)
129 (response)
2 3 Binary Input Event: With relative time 17, 28 (index)
130 (unsol. resp)
10 0 Binary output: Any Variation
10 0 Binary output: Any Variation
10 1 Binary output: Packed format
Binary Command: Control relay output block 129 (response) echo of request
12 1
(CROB)
30 0 Analog Input: An y Variation
30 1 Analog Input: 32 ~ bit with flag 129 (response) 00, 01 (start ~ stop)
30 2 Analog Input: 16 ~ bit with flag 129 (response) 00, 01 (start ~ stop)
30 3 Analog Input: 32 ~ bit without flag 129 (response) 00, 01 (start ~ stop)
30 4 Analog Input: 16 ~ bit without flag 129 (response) 00, 01 (start ~ stop)
30 5 Analog Input: Single ~ prec flt ~ pt with flag 129 (response) 00, 01 (start ~ stop)
32 0 Analog Input Event: An y Variation
129 (response)
32 1 Analog Input Event: 32 ~ bit without time 17,28 (index)
130 (unsol. resp)
129 (response)
32 2 Analog Input Event: 16 ~ bit without time 17,28 (index)
130 (unsol. resp)
Analog Input Event: Single ~ prec flt ~ pt without 129 (response)
32 5 17,28 (index)
time 130 (unsol. resp)
34 0 Analog Input Deadband: An y Variation
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OBJ ECT GROUP & VARIATION RESPONSE

Group/Variation
No.
129 (response) 00, 01 (start ~ stop)


34 3 Analog Input Deadband: Single ~ prec flt ~ pt
40 0 Analog Output Status: An y Variation

40 1 Analog Output Status: 32 ~ bit with flag 129 (response) 00, 01 (start ~ stop)
40 2 Analog Output Status: 16 ~ bit with flag 129 (response) 00, 01 (start ~ stop)
Analog Output Status: single ~ prec flt ~ pt with
40 3 129 (response) 00, 01 (start ~ stop)
flag
Analog Output: 129 (response) echo of request
41 1
32 ~ bit
41 2
16 ~ bit
41 3
Single ~ prec ft ~ pt
129 (response) 07 (limited qty = 1)
50 1 Time and Data: Absolute time
Time and Data: Absolute time at last recorded

50 3
time
Time and Data CTO: Absolute time, 129 (response)
51 1 07 (limited qty = 1)
synchronized 130 (unsol. resp)
Time and Data CTO: Absolute time, 129 (response)
51 2 07 (limited qty = 1)
unsynchronized 130 (unsol. resp)
60 1 Class Objects: Class 0 data
60 4 Class Objects : Class 3 data
10.6.4.3 Communication Table Configuration
This relay now supports 4 Ethernet clients and 2 serial port clients. Each client can be set the DNP
related communication parameters respectively and be selected the user-defined communication
table. This relay supports a default communication table and 4 user -defined communication tables,
and the default communication table is fixed by the manufacturer and not permitted to configure by
the user.
The user can configure the user-defined communication table through the PCS-Explorer
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10 Communications
configuration tool auxiliary software. The object groups “Binary Input”, “Binary Output”, “Analog
Input” and “Analog Output” can be configured according to the practical engineering demand.
10.6.4.4 Analog Input and Output Configuration
To the analog inputs, the attributes “deadband” and “factor” of each analog input can be configured
independently. To the analog outputs, only the attribute “factor” of each analog output needs to be
configured. If the integer mode is adopted for the data formats of analog values (to “Analog Input”,
“Object Variation” is 1, 2 and 3; to “Analog Output”, “Object Variation” is 1 and 2.), the analog
values will be multiplied by the “factor” respectively to ensure their accuracy. And if the float mode
is adopted for the data formats of analog values, the actual float analog values will be sent directly.
The judgment method of the analog input change is as below: Calculate the difference between
the current new value and the stored history value and make the difference value multiply by the
“factor”, then compare the result with the “deadband” value. If the result is greater than the
“deadband” value, then an event message of corresponding analog input change will be cr eated.
In normal communication process, the master can online read or modify a “deadband” value by
reading or modifying the variation in “Group34”.
10.6.4.5 Binary Output Configuration
The remote control signals, logic links and external extended output commands can be configured
into the “Binary Output” group. The supported control functions are listed as below.
Information Point Pulse On/Null Pulse On/Close Pulse On/Trip Latch On/Null Latch Off/Null
Remote Control Not supported Close Trip Close Trip
Logic Link Not supported Set Clear Set Clear
Extended Output See following description
To an extended output command, if a selected command is controlled remotely, this command

point will output a high ~ level pulse. The pulse width can be decided by the “On ~ time” in the
related “Binary Command” which is from the DNP3.0 master. If the “On ~ time” is set as “0”, the
default pulse width is 500ms.
10.6.4.6 Unsolicited Messages
This relay does not transmit the unsolicited messages if the related logic setting is set as “0”. If the
unsolicited messages want to be transmitted, the related logic setting should be set as “1” or the
DNP3.0 master will transmit “Enable Unsolicited” command to this relay through “Function Code
20” (Enable Unsolicited Messages). If the “Binary Input” state changes or the difference value of
the “Analog Input” is greater than the “deadband” value, this device will transmit unsolicited
messages. If the DNP3.0 master needs not to receive the unsolicited messages, it should forbid
this relay to transmit the unsolicited messages by setting the related logic setting as “0” or through
the “Function Code 21” (Disable Unsolicited Messages).
10.6.4.7 Class Configuration
If the DNP3.0 master calls the Class0 data, this relay will transmit all actual values of the “Analog
Input”, “Binary Input” and “Analog Output”. The classes of the “Analog Input” and “Binary Input”
can be defined by modifying relevant settings. In communication process, the DNP3.0 master can
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online modify the class of an “Analog Input” or a “Binary Input” through “Function Code 22” (Assign
Class).
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11 Installation
11 Installation
Table of Contents
11 Installation ....................................................................................... 11-a
11.1 Overview.................................................................................................................... 11-1
11.2 Safety Information .................................................................................................. 11-1

11.3 Check the Shipment ............................................................................................... 11-2
11.4 Material and Tools Required ................................................................................ 11-2
11.5 Device Location and Ambient Conditions........................................................ 11-2
11.6 Mechanical Installation .......................................................................................... 11-3
11.7 Electrical Installation and Wiring ........................................................................ 11-4

11.7.1 Grounding Guidelines ................................................................................................... 11-4
11.7.2 Cubicle Grounding........................................................................................................ 11-4
11.7.3 Ground Connection on the Device ................................................................................ 11-5
11.7.4 Grounding Strips and their Installation .......................................................................... 11-5
11.7.5 Guidelines for Wiring .................................................................................................... 11-6
11.7.6 Wiring for Electrical Cables........................................................................................... 11-6
List of Figures
Figure 11.6-1 Dimensions and panel cut-out of PCS-985TI .................................................11-3
Figure 11.6-2 Demonstration of plugging a board into its corresponding slot ..................11-3
Figure 11.7-1 Cubicle grounding system..............................................................................11-5
Figure 11.7-2 Ground terminal of this device .......................................................................11-5
Figure 11.7-3 Ground strip and termination .........................................................................11-6
Figure 11.7-4 Glancing demo about the wiring for electrical cables...................................11-7
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11 Installation
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11 Installation
11.1 Overview
The device must be shipped, stored and installed with the greatest care.
Choose the place of installation such that the communication interface and the controls on the
front of the device are easily accessible.
Air must circulate freely around the device. Observe all the requirements regarding place of
installation and ambient conditions given in this instruction manual.
Take care that the external wiring is properly brought into the device and terminated correctly and
pay special attention to grounding. Strictly observe the corresponding guidelines contained i n this
section.
11.2 Safety Information

Modules and units may only be replaced by correspondingly trained personnel. Always observe
the basic precautions to avoid damage due to electrostatic discharge when handling the device.
In certain cases, the settings have to be configured according to the demands of the engineering
configuration after replacement. It is therefore assumed that the personnel who replace modules
and units are familiar with the use of the operator program on the service PC.
WARNING!
ONLY insert or withdraw a module while the device power supply is switched off. To this
end, disconnect the power supply cable that connects with the PWR module.
NOTICE!
Industry packs and ribbon cables may ONLY be replaced on a workbench for electronic
equipment. Electronic components are sensitive to electrostatic discharge when not in
the unit's housing.
NOTICE!
Jumper links may ONLY be changed on a workbench for electronic equipment.

Electronic components are sensitive to electrostatic discharge when not in the unit's
housing.
NOTICE!
A module can ONLY be inserted in the slot designated in the chapter 6. Components
can be damaged or destroyed by inserting module in a wrong slot.
The basic precautions to guard against electrostatic discharge are as follows:
 Should boards have to be removed from this device installed in a grounded cubicle in an HV
switchgear installation, please discharge yourself by touching station ground (the cubicle)
beforehand.
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11 Installation
 Only hold electronic boards at the edges, taking care not to touch the components.
 Only works on the board which has been removed from the cubicle on a workbench designed
for electronic equipment and wear a grounded wristband. Do not wear a grounded wristband,
however, while inserting or withdrawing units.
 Always store and ship the electronic boards in their original packing. Place electronic parts in
electrostatic screened packing materials.
11.3 Check the Shipment

Check that the consignment is complete immediately upon receipt. Notify the nearest NR
Company or agent, should departures from the delivery note, the shipping papers or the order be
found.
Visually inspect all the material when unpacking it. When there is evidence of transport damage,
lodge a claim immediately in writing with the last carrier and notify the neares t NR Company or
agent.
If the equipment is not going to be installed immediately, store all the parts in their original packing
in a clean dry place at a moderate temperature. The humidity at a maximum temperature and the
permissible storage temperature range in dry air are listed in Chapter “Technical Data”.
11.4 Material and Tools Required

The necessary mounting kits will be provided, including screws, pincers and assembly
instructions.
A suitable drill and spanners are required to secure the cubicles to the f loor using the plugs
provided (if this device is mounted in cubicles).
11.5 Device Location and Ambient Conditions

NOTICE!
Excessively high temperature can appreciably reduce the operating life of this device.
The place of installation should permit easy access especially to front of the device, i.e. to the
human machine interface of the equipment.
There should also be free access at the rear of the equipment for additions and replacement of
electronic boards.
Since every piece of technical equipment can be damaged or destroyed by inadmissible ambient
conditions, such as:
1. The location should not be exposed to excessive air pollution (dust, aggressive substances).
2. Surge voltages of high amplitude and short rise time, extreme changes of temperature, high
levels of humidity, severe vibration and strong induced magnetic fields should be avoided as
far as possible.
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11 Installation
3. Air must not be allowed to circulate freely around the equipment.
The equipment can in principle be mounted in any attitude, but it is normally mounted vert ically
(visibility of markings).
11.6 Mechanical Installation

NOTICE!
It is necessary to leave enough space top and bottom of the cut-out in the cubicle for
heat emission of this device.
The device is made of one 4U height 19" chassis with 8 connectors on its rear panel. Following
figure shows the dimensions and cut-out size in the cubicle of this device for reference in
mounting.
482.6 (290.0)
465.0
101.6
177.0
465.0±0.2
+0.4
451.0 -0.0
4-Φ6.8
+0.4
179.0 -0.0
101.6±0.1
Figure 11.6-1 Dimensions and panel cut-out of PCS-985TI
Following figure shows the installation way of a module being plugged into a corresponding slot.
Figure 11.6-2 Demonstration of plugging a board into its corresponding slot
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11 Installation
In the case of equipment supplied in cubicles, place the cubicles on the foundations that have
been prepared. Take care while doing so not to jam or otherwise damage any of the cables that
have already been installed. Secure the cubicles to the foundations.
11.7 Electrical Installation and Wiring

11.7.1 Grounding Guidelines
NOTICE!
All these precautions can only be effective if the station ground is of good quality.
Switching operations in HV installations generate transient over voltages on control signal cables.
There is also a background of electromagnetic RF fields in electrical installations that can induce
spurious currents in the devices themselves or the leads connected to them.
All these influences can influence the operation of electronic apparatus.
On the other hand, electronic apparatus can transmit interference tha t can disrupt the operation of
other apparatus.
In order to minimize these influences as far as possible, certain standards have to be observed
with respect to grounding, wiring and screening.
11.7.2 Cubicle Grounding
The cubicle must be designed and fitted out such that the impedance for RF interference of the
ground path from the electronic device to the cubicle ground terminal is as low as possible.
Metal accessories such as side plates, blanking plates etc., must be effectively connected
surface-to-surface to the grounded frame to ensure a low-impedance path to ground for RF
interference. The contact surfaces must not only conduct well, they must also be non -corroding.
NOTICE!
If the above conditions are not fulfilled, there is a possibility of the cubicle or p arts of it
forming a resonant circuit at certain frequencies that would amplify the transmission of
interference by the devices installed and also reduce their immunity to induced
interference.
Movable parts of the cubicle such as doors (front and back) or hinged equipment frames must be
effectively grounded to the frame by three braided copper strips (see Figure 11.7-1).
The metal parts of the cubicle housing and the ground rail are interconnected electrically
conducting and corrosion proof. The contact surfaces shall be as large as possible.
NOTICE!
For metallic connections please observe the voltage difference of both materials
according to the electrochemical code.
The cubicle ground rail must be effectively connected to the station ground rail by a
grounding strip (braided copper).
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11 Installation
Door or hinged
equipment frame
Cubicle ground
rail close to floor
Braided
copper strip
Station
ground
Conducting
connection
Figure 11.7-1 Cubicle grounding system
11.7.3 Ground Connection on the Device
There is a ground terminal on the rear panel, and the ground br aided copper strip can be
connected with it. Take care that the grounding strip is always as short as possible. The main thing
is that the device is only grounded at one point. Grounding loops from unit to unit are not allowed.
There are some ground terminals on some connectors of this device, and the sign is “GND”. All the
ground terminals are connected in the cabinet of this device. Therefore, the ground terminal on the
rear panel (see Figure 11.7-2) is the only ground terminal of this device.
Figure 11.7-2 Ground terminal of this device
11.7.4 Grounding Strips and their Installation
High frequency currents are produced by interference in the ground connections and because of
skin effect at these frequencies, only the surface region of the grounding strips is of consequence.
The grounding strips must therefore be of (preferably tinned) braided copper and not round copper
conductors, as the cross-section of round copper would have to be too large.
Proper terminations must be fitted to both ends (press/pinch fit and tinned) with a hole for bolting
them firmly to the items to be connected.
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11 Installation
The surfaces to which the grounding strips are bolted must be electrically conducting and
non-corroding.
The following figure shows the ground strip and termination.
Press/pinch fit
cable terminal
Braided
copper strip Terminal bolt
Contact surface
Figure 11.7-3 Ground strip and termination
11.7.5 Guidelines for Wiring
There are several types of cables that are used in the connectio n of this device: braided copper
cable, serial communication cable etc. Recommendation of each cable:
2 2
 Grounding: braided copper cable, 2.5mm ~ 6.0mm
 Power supply, binary inputs & outputs: brained copper cable, 1.0mm 2 ~ 2.5mm2
 AC voltage inputs: brained copper cable, 1.0mm2 ~ 2.5mm2
 AC current inputs: brained copper cable, 1.5mm2 ~ 4.0mm2
 Serial communication: 4-core shielded braided cable
 Ethernet communication: 4-pair shielded twisted category 5E cable
11.7.6 Wiring for Electrical Cables
DANGER!
NEVER allow a open current transformer (CT) secondary circuit connected to this
device while the primary system is live. Open CT circuit will produce a dangerously high
voltage that cause death.
A female connector is used for connecting the wires with it, and then a fe male connector plugs into
a corresponding male connector that is in the front of one board. See Chapter “Hardware” for
further details about the pin defines of these connectors.
The following figure shows the glancing demo about the wiring for the electric al cables.
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11 Installation
01 02
03 04
Tighten 05 06
07 08
09 10
11 12
01
13 14
15 16
17 18
19 20
21 22
23 24
Figure 11.7-4 Glancing demo about the wiring for electrical cables
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11 Installation
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12 Commissioning
12 Commissioning
Table of Contents
12 Commissioning ............................................................................... 12-a
12.1 Overview ................................................................................................................... 12-1
12.2 Safety Instructions................................................................................................. 12-1
12.3 Commission Tools ................................................................................................. 12-1
12.4 Setting Familiarization .......................................................................................... 12-2

12.5 Product Checks ...................................................................................................... 12-2
12.5.1 With the Device De-energized ..................................................................................... 12-3
12.5.2 With the Device Energized........................................................................................... 12-5
12.5.3 On-load Checks........................................................................................................... 12-6
12.6 Final Checks ............................................................................................................ 12-7
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12 Commissioning
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12 Commissioning
12.1 Overview
This device is numerical in their design, implementing all functions in software. The device
employs a high degree self-checking, so in the unlikely event of a failure, it will give an alarm.
Blank commissioning test and setting records are provided at the end of this manual for
completion as required.
Before carrying out any work on the device, the user should be familiar with the contents of the
safety and technical data sections and the ratings on the device’s rating label.
12.2 Safety Instructions
DANGER!
Current transformer secondary circuits MUST be short-circuited BEFORE the current

leads to the device are disconnected.
WARNING!
ONLY qualified personnel should work on or in the vicinity of this device. This
personnel MUST be familiar with all safety regulations and service procedures
described in this manual. During operating of electrical device, certain part of the
device is under high voltage. Severe personal injury and significant device damage
could result from improper behavior.
Particular attention must be drawn to the following:
 The earthing screw of the device must be connected solidly to the protective earth conductor
before any other electrical connection is made.
 Hazardous voltages can be present on all circuits and components connected to the supply
voltage or to the measuring and test quantities.
 Hazardous voltages can be present in the device even after disconnection of the supply
voltage (storage capacitors!)
 The limit values stated in the Chapter “Technical Data” must not be exceeded at all, not even
during testing and commissioning.
 When testing the device with secondary test equipment, make sure that no other
measurement quantities are connected. Take also into consideration that the trip circuits and
may be close commands to the circuit breakers and other primary switches are disconnected
from the device unless expressly stated.
12.3 Commission Tools

Minimum equipment required:
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12 Commissioning
NOTICE!
Modern test set may contain many of the above features in one unit.
 Multifunctional dynamic current and voltage injection test set with interval timer.
 Multimeter with suitable AC current range and AC/DC voltage ranges of 0~440V and 0~250V
respectively.
 Continuity tester (if not included in the multimeter).
 Phase angle meter.
 Phase rotation meter.
Optional equipment:
 An electronic or brushless insulation tester with a DC output not exceeding 500V (for
insulation resistance test when required).
 A portable PC, with appropriate software (this enables the rear communications port to be
tested, if this is to be used, and will also save considerable time during commissioning).
 EIA RS-485 to EIA RS-232 converter (if EIA RS-485 IEC60870-5-103 port is being tested).
 Tester: HELP-9000.
12.4 Setting Familiarization

When commissioning this device for the first time, sufficient time should be allowed to become
familiar with the method by which the settings are applied. A detailed description of the menu
structure of this device is contained in Chapter “Operation Theory” and Chapter “Settings”.
With the front cover in place all keys are accessible. All menu cells can be read. The LED
indicators and alarms can be reset. Protection or configuration settings can be changed, or fault
and event records cleared. However, menu cells will require the appropriate password to be
entered before changes can be made.
Alternatively, if a portable PC is available together with suitable setting software (such as

PCS-9700 HMI software), the menu can be viewed one page at a time to display a full column of
data and text. This PC software also allows settings to be entered more easily, saved to a file on
disk for future reference or printed to produce a setting record. Refer to the PC software user
manual for details. If the software is being used for the first time, allow sufficient time to become
familiar with its operation.
12.5 Product Checks

These product checks cover all aspects of the device which should be checked to ensure that it
has not been physically damaged prior to commissioning, is functioning correctly and all input
quantity measurements are within the stated tolerances.
If the application-specific settings have been applied to the device prior to commissioning, it is
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12 Commissioning
advisable to make a copy of the settings so as to allow them restoration later. This could be done
by extracting the settings from the device itself via printer or manually creating a setting record.
12.5.1 With the Device De-energized
This device is fully numerical and the hardware is continuously monitored. Commissioning tests
can be kept to a minimum and need only include hardware tests and conjunctive tests. The
function tests are carried out according to user’s correlative regulations.
The following tests are necessary to ensure the normal operation of the equipment before it is first
put into service.
 Hardware tests
These tests are performed for the following hardware to ensure that there is no hardware
defect. Defects of hardware circuits other than the following can be detected by
self-monitoring when the DC power is supplied.
 User interfaces test
 Binary input circuits and output circuits test
 AC input circuits test
 Function tests
These tests are performed for the following functions that are fully software -based.
 Measuring elements test
 Timers test
 Conjunctive tests
The tests are performed after the device is connected with the primary equipment and other
external equipment.
 On load test.
 Phase sequence check and polarity check.
12.5.1.1 Visual Inspection
After unpacking the product, check for any damage to the device case. If there is any damage, the
internal module might also have been affected, contact the vendor. The following items listed are
necessary.
 Device panel
Carefully examine the device panel, device inside and other parts inside to see that no
physical damage has occurred since installation.
 Panel wiring
Check the conducting wire which is used in the panel to assure that their cross section
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12 Commissioning
meeting the requirement.
Carefully examine the wiring to see that they are no connection failure exists.
 Device plug-in modules
Check each plug-in module of the equipment on the panel to make sure that they are well
installed into the equipment without any screw loosened.
 Earthing cable
Check whether the earthing cable from the panel terminal block is safely screwed to the panel
steel sheet.
 Switch, keypad, isolator binary inputs and push button
Check whether all the switches, equipment keypad, isolator binary inputs and push buttons
work normally and smoothly.
12.5.1.2 Insulation Test (if required)
Insulation resistance tests are only necessary during commissioning if it is required for them to be
done and they have not been performed during installation.
Isolate all wiring from the earth and test the isolation with an electronic or brushless insulation
tester at a DC voltage not exceeding 500V, The circuits need to be tested should include:
 Voltage transformer circuits
 Current transformer circuits
 DC power supply
 Optic-isolated control inputs
 Output contacts
 Communication ports
The insulation resistance should be greater than 100MΩ at 500V.
Test method:
To unplug all the terminals sockets of this device, and do the Insulation resistance test for each
circuit above with an electronic or brushless insulation tester.
On completion of the insulation resistance tests, ensure all external wiring is correctly
reconnected to the device.
12.5.1.3 External Wiring
Check that the external wiring is correct to the relevant device diagram and scheme diagram.
Ensure as far as practical that phasing/phase rotation appears to be as expected.
Check the wiring against the schematic diagram for the installation to ensure compliance with the
customer’s normal practice.
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12 Commissioning
12.5.1.4 Auxiliary Power Supply
WARNING!
Energize this device ONLY if the power supply is within the specified operating range in
the Chapter “Technical Data”.
The device only can be operated under the auxiliary power supply depending on the device’s
nominal power supply rating.
The incoming voltage must be within the operating range specified in Chapter “Technical Data”,
before energizing the device, measure the auxiliary supply to ensure it within the operating range.
Other requirements to the auxiliary power supply are specified in Chapter “Technical Data”. See
this section for further details about the parameters of the power supply.
12.5.2 With the Device Energized

The following groups of checks verify that the device hardware and software is functioning
correctly and should be carried out with the auxiliary supply applied to the device.
The current and voltage transformer connections must remain isolated from the device for these
checks. The trip circuit should also remain isolated to prevent accidental operation of the
associated circuit breaker.
12.5.2.1 Front Panel LCD Display
Connect the device to DC power supply correctly and turn the device on. Check program version
and forming time displayed in command menu to ensure that are corresponding to what ordered.
12.5.2.2 Date and Time
If the time and date is not being maintained by substation automation system, the date and t ime
should be set manually.
Set the date and time to the correct local time and date using menu item “ Clock”.
In the event of the auxiliary supply failing, with a battery fitted on CPU board, the time and date
will be maintained. Therefore when the auxiliary supply is restored the time and date will be
correct and not need to set again.
To test this, remove the auxiliary supply from the device for approximately 30s. After being
re-energized, the time and date should be correct.
12.5.2.3 Light Emitting Diodes (LEDs)
On power up, the green LED “HEALTHY” should have illuminated and stayed on indicating that
the device is healthy.
The device has latched signal devices which remember the state of the trip, auto-reclose when
the device was last energized from an auxiliary supply. Therefore these indicators may also
illuminate when the auxiliary supply is applied. If any of these LEDs are on then they should be
Date: 2015-07-29
12 Commissioning
reset before proceeding with further testing. If the LED successfully reset, the LED goes out.
There is no testing required for that that LED because it is known to be operational.
It is likely that alarms related to voltage transformer supervision will not reset at this stage.
12.5.2.4 Testing HEALTHY and ALARM LEDs
Apply the rated DC power supply and check that the “HEALTHY” LED is lighting in green. We
need to emphasize that the “HEALTHY” LED is always lighting in operation course except that the
equipment find serious errors in it.
Produce one of the abnormal conditions listed in Chapter “Supervision”, the “ALARM ” LED will
light in yellow. When abnormal condition reset, the “ALARM ” LED extinguishes.
12.5.2.5 Testing AC Current Inputs
NOTICE!
The closing circuit should remain isolated during these checks to prevent accidental
operation of the associated circuit breaker.
This test verified that the accuracy of current measurement is within the acceptable tolerances.
Apply rated current to each current transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in th e devices menu.
12.5.2.6 Testing AC Voltage Inputs
NOTICE!
The closing circuit should remain isolated during these checks to prevent accidental
operation of the associated circuit breaker.
This test verified that the accuracy of voltage measurement is within the acceptable tolerances.
Apply rated voltage to each voltage transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in the devices menu.
12.5.2.7 Testing Binary Inputs
This test checks that all the binary inputs on the equipment are functioning correctly.
The binary inputs should be energized one at a time, see external connection diagrams for
terminal numbers.
Ensure that the voltage applied on the binary input must be within the operating range.
The status of each binary input can be viewed using device menu. Sign “1” denotes an energized
input and sign “0” denotes a de-energized input.
12.5.3 On-load Checks
The objectives of the on-load checks are:
1. Confirm the external wiring to the current and voltage inputs is correct.
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12 Commissioning
2. Measure the magnitude of on-load current and voltage (if applicable).
3. Check the polarity of each current transformer.
However, these checks can only be carried out if there are no restrictions preventing the
tenderization of the plant being protected.
Remove all test leads, temporary shorting leads, etc. and replace any external wiring that has
been removed to allow testing.
If it has been necessary to disconnect any of the external wiring from the device in order to
perform any of the foregoing tests, it should be ensured that all connections are replaced in
accordance with the relevant external connection or scheme diagram. Confirm current and
voltage transformer wiring.
12.6 Final Checks

After the above tests are completed, remove all test or temporary shorting leads, etc. If it has been
necessary to disconnect any of the external wiring from the device in order to perform the wiring
verification tests, it should be ensured that all connections are replaced in accordance with the
relevant external connection or scheme diagram.
Ensure that the device has been restored to service.
If the device is in a new installation or the circuit breaker has just been maintained, the circuit
breaker maintenance and current counters should be zero. If a test block is installed, remove the
test plug and replace the cover so that the device is put into service.
Ensure that all event records, fault records and alarms have been cleared and LED’s has been
reset before leaving the device.
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12 Commissioning
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13 Maintenance
13 Maintenance
Table of Contents
13 Maintenance .................................................................................... 13-a
13.1 Appearance Check .................................................................................................13-3
13.2 Failure Tracing and Repair ...................................................................................13-3

13.3 Replace Failed Modules ........................................................................................13-4
13.4 Cleaning ....................................................................................................................13-5
13.5 Storage ......................................................................................................................13-5
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13 Maintenance

Date: 2015-07-29
13 Maintenance
This device is designed to require no special maintenance. All measurement and signal
processing circuit are fully solid state. All input modules are also fully solid state. The output relays
are hermetically sealed.
Since the device is almost completely self-monitored, from the measuring inputs to the output
relays, hardware and software defects are automatically detected and reported. The
self-monitoring ensures the high availability of the device and generally allows for a corrective
rather than preventive maintenance strategy. Therefore, maintenance checks in short intervals are
not required.
Operation of the device is automatically blocked when a hardware failure is detected. If a problem
is detected in the external measuring circuits, the device normally only provides alarm messages.
13.1 Appearance Check

1. The device case should be clean without any dust stratification. Case cover should be sealed
well. No component has any mechanical damage and distortion, and they should be firmly
fixed in the case. Device terminals should be in good condition. The keys on the front panel
with very good feeling can be operated flexibly.
2. It is only allowed to plug or withdraw device board when the supply is reliably switched off.
Never allow the CT secondary circuit connected to this equipment to be opened while the
primary system is live when withdrawing an AC module. Never try to insert or withdraw the
device board when it is unnecessary.
3. Check weld spots on PCB whether they are well soldered without any rosin joint. All dual
inline components must be well plugged.
13.2 Failure Tracing and Repair

Failures will be detected by automatic supervision or regular testing.
When a failure is detected by supervision, a remote alarm is issued and the failure is indicated on
the front panel with LED indicators and LCD display. It is also recorded in the event record.
Failures detected by supervision are traced by checking the “ Superv State” screen on the LCD.
When a failure is detected during regular testing, confirm the following:
1. Test circuit connections are correct
2. Modules are securely inserted in position
3. Correct DC power voltage is applied
4. Correct AC inputs are applied
5. Test procedures comply with those stated in the manual
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13 Maintenance
13.3 Replace Failed Modules
WARNING!
Module can ONLY be replaced while the device power supply is switched off.
ONLY appropriately trained and qualified personnel can perform the replacement by
strictly observing the precautions against electrostatic discharge.
WARNING!
Five seconds is NECESSARY for discharging the voltage. Hazardous voltage can be
present in the DC circuit just after switching off the DC power supply.
CAUTION!
Take anti-static measures such as wearing an earthed wristband and placing modules
on an earthed conductive mat when handling a module. Otherwise, electronic
components could be damaged.
CAUTION!
Check the device configuration after a replacement of module. Unintended operation of

device may occur.
If the failure is identified to be in the device module and the user has spare modules, the user can
recover the device by replacing the failed modules.
Repair at the site should be limited to module replacement. Maintenance at the component level is
not recommended.
Check that the replacement module has an identical module name (AI, PWR, MON, BI, BO, etc.)
and hardware type-form as the removed module. Furthermore, the MON module replaced should
have the same software version. In addition, the AI and PWR module replaced should have the
same ratings.
The module name is indicated on the top front of the module. The software version is indicated in
LCD menu “Information”->“Version Info”.
1) Replacing a module
 Switch off the DC power supply
 Disconnect the trip outputs
 Short circuit all AC current inputs and disconnect all AC voltage inputs
 Unscrew the module connector
 Unplug the connector from the target module.

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13 Maintenance
 Unscrew the module.
 Pull out the module
 Inset the replacement module in the reverser procedure.
 After replacing the MON module, input the application-specific setting values again.
2) Replacing the Human Machine Interface Module (front panel)
 Open the device front panel
 Unplug the ribbon cable on the front panel by pushing the catch outside.
 Detach the HMI module from the device
 Attach the replacement module in the reverse procedure.
13.4 Cleaning
Before cleaning the device, ensure that all AC/DC supplies, current transformer connections are
isolated to prevent any chance of an electric shock whilst cleaning. Use a smooth cloth to clean
the front panel. Do not use abrasive material or detergent chemicals.
13.5 Storage
The spare device or module should be stored in a dry and clean room. Based on IEC standard
60255-1 the storage temperature should be from -40°C to +70°C, but the temperature of from 0°C
to +40°C is recommended for long-term storage.
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13 Maintenance

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14 Decommi ssioning and Di sposal
14 Decommissioning and Disposal
Table of Contents
14 Decommissioning and Disposal .................................................. 14-a
14.1 Decommissioning ...................................................................................................14-3
14.2 Disposal.....................................................................................................................14-3
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14 Decommi ssi oning and Di sposal
14.1 Decommissioning
DANGER!
Switch OFF the circuit breaker for primary CTs and VTs BEFORE disconnecting the
cables of AI module.
WARNING!
Switch OFF the external miniature circuit breaker of device power supply BEFORE
disconnecting the power supply cable connected to the PWR module.
WARNING!
KEEP an adequate safety distance to live parts of the power substation.
1. Switching off
To switch off this device, switch off the external miniature circuit breaker of the power supply.
2. Disconnecting cables
Disconnect the cables in accordance with the rules and recommendations made by relational
department.
3. Dismantling
The device rack may now be removed from the system cubicle, after which the cubicles may
also be removed.
14.2 Disposal
NOTICE!
Strictly observe all local and national laws and regulations when disposing the device.
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Date: 2015-07-29
15 Manual Version Hi story
15 Manual Version History

In the latest version of the instruction manual, several descriptions on existing features have been
modified.
Manual version and modification history records
Manual Version Software

Date Description of change
Source New Version
R1.00 R1.00 2015-07-29 Form the original manual.
PCS-985TI Transformer Relay 15-1
Date: 2015-07-29
15 Manual Version Hi story
15-2 PCS-985TI Transformer Relay
Date: 2015-07-29

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Health and Safety

Qualified personnel are individuals who:

 Are trained in emergency procedures (first aid).

Instructions and Warnings

PCS-985TE Transformer Relay i

Securely earthed the earthing terminal of the device.

ii PCS-985TE Transformer Relay

 Printed circuit board

Carefully handle connection cables without applying excessive force.

The firmware may be upgraded to add new features or enhance/modify existing

Copyright © 2015 NR. All rights reserved.

We reserve the rights to make technical improvements without notice.

NR ELECTRIC CO., LTD. Tel: +86-25-87178888

P/N: ZL_PCS-985TE_X_Instruction Manual_EN_Overseas General_X Version: R1.00

PCS-985TE Transformer Relay iii

All contents provided by this manual are summarized as below:

8 Human Machine Interface

iv PCS-985TE Transformer Relay

Introduce the recommendations on unpacking, handling, inspection and storage of th is relay. A

14 Decommissioning and Disposal

15 Manual Version History

Typographic and Graphical Conventions

The following symbols are used in drawings:

BI Binary signal via opto-coupler

SET I> Input signal from comparator with setting

EN Input signal of logic setting for function enabling

SIG Input of binary signal except those signals via opto-coupler

OTH Input of other signal

PCS-985TE Transformer Relay v

XXX Output signal

---xxx is the symbol

Symbol Corresponding Relationship

vi PCS-985TE Transformer Relay

Figure 1.1-1 Typical protection scheme 1 of PCS-985TE......................................................... 1-1

Figure 1.1-2 Typical protection scheme 2 of PCS-985TE......................................................... 1-2

Figure 1.1-3 Typical protection scheme 3 of PCS-985TE......................................................... 1-2

Table 1.2-1 Protective functions of PCS-985TE .................................................................... 1-3

Table 1.2-2 Miscellaneous functions of PCS-985TE ............................................................. 1-3

PCS-985TE Transformer Relay 1-a

1-b PCS-985TE Transformer Relay

PCS-985TE is a kind of high performance numerical transformer protection device, which

Figure 1.1-1 ~ Figure 1.1-3 show typical protection schemes of PCS-985TE.

Figure 1.1-1 Typical protection scheme 1 of PCS-985TE

PCS-985TE Transformer Relay 1-1

Figure 1.1-2 Typical protection scheme 2 of PCS-985TE

Branch A1 Branch A2 Branch B1 Branch B2

abc abc abc abc

Figure 1.1-3 Typical protection scheme 3 of PCS-985TE

1-2 PCS-985TE Transformer Relay

Table 1.2-1 Protective functions of PCS-985TE

No. Function ANSI

Table 1.2-2 Miscellaneous functions of PCS-985TE

Measurement 24 samples per cycle for current and voltage measurement

Configurable function Programmable binary inputs

PCS-985TE Transformer Relay 1-3

Programmable binary outputs

Programmable LED indicators

Configurable protection functions

Self-supervision Relay hardware supervision and secondary circuit supervision

Disturbance 64 fault reports

1024 supervision alarm events

Event recording 1024 binary input events