Hooghly Engineering and Technology College

(MAKAUT)

Name: ​ARKADEEP ROY

2nd Yr.(4th Sem)

Univ. Registration No.: ​181760110009

Univ. Roll No.: ​17600118065

Experiment 1:​ ​ Design ROM using VHDL code.

Objective :​ ​To Construct ROM using VHDL code.

Theory: ​A ​read-only memory(ROM) is a memory unit that performs the read operation only; it does
not have a write capability. This implies that the binary information stored in a ROM is made
permanent during the hardware production of the unit and cannot be altered by writing different words
into it.
Whereas a RAM is a general-purpose device whose contents can be altered during the computational
process, a ROM is restricted to reading words that are permanently stored within the unit. The binary
information to be stored, specified by the designer, is then embedded in the unit to form the required
interconnection pattern. ROMs come with special internal electronic fuses that can be programmed
for a specific configuration. Once the pattern is established, it stays within the unit even when power
is turned off and on again.

ROM​:

An m x n ROM is an array of binary cells organized into m words of n bits each. As shown in the block
diagram below, a ROM has k address input lines to select one of 2​k = m words of memory, and n
input lines, one for each bit of the word. An integrated circuit ROM may also have one or more enable
inputs for expanding a number of packages into a ROM with larger capacity.
The ROM does not need a read-control line since at any given time, the output lines automatically
provide the n bits of the word selected by the address value. Because the outputs are a function of
only the present inputs (the address lines), a ROM is classified as a combinational circuit. In fact, a
ROM is constructed internally with decoders and a set of OR gates. There is no need for providing
storage capabilities as in RAM, since the values of the bits in the ROM are permanently fixed.ROMs
find a wide range of applications in the design of digital systems. As such, it can implement any
combinational circuit with k inputs and n outputs.

Block Diagram :
Circuit Diagram:

Truth Table :

Behavioural VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ROM_METHOD_1 is
port( Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Enable : in STD_LOGIC;
Read1 : in STD_LOGIC;
Address : in STD_LOGIC_VECTOR(4 downto 0);
Data_out : out STD_LOGIC_VECTOR(7 downto 0)
);
end ROM_METHOD_1;
architecture Behavioral of ROM_METHOD_1 is
type ROM_Array is array (0 to 31)
of STD_LOGIC_VECTOR(7 downto 0);
constant Content: ROM_METHOD_1_Array := (
0 => "00000001",
1 => "00000010",
2 => "00000011",
3 => "00000100",
4 => "00000101",
5 => "00000110",
6 => "00000111",
7 => "00001000",
8 => "00001001",
9 => "00001010",
10 => "00001011",
11 => "00001100",
12 => "00001101",
13 => "00001110",
14 => "00001111",
OTHERS => "11111111"
);
begin
process(Clock, Reset, Read1, Address)
begin
if(Reset = '1') then
Data_out <= "ZZZZZZZZ";
elsif(Clock'event and Clock = '1') then
if Enable = '1' then
if(Read1 = '1') then
Data_out <= Content(conv_integer(Address));
else
Data_out <= "ZZZZZZZZ";
end if;
end if;
end if;
end process;
end Behavioral;
Output:

Conclusion: ​In this experiment now we are able to realize the design of ROM by implementing in
VHDL codes and we have also obtained the output waveform.

Experiment 2 :​ Design Multiplexer using VHDL code.

Objective :​ Construct a 4x1 MUX by implementing in VHDL code.

Theory: ​Multiplexer is a combinational circuit that has a maximum of 2​n data inputs, ‘n’ selection
lines and single output line. One of these data inputs will be connected to the output based on the
values of selection lines.
Since there are ‘n’ selection lines, there will be 2​n possible combinations of zeros and ones. So,
each combination will select only one data input. Multiplexer is also called a Mux.​Multiplexers  are 
mainly  used  to  increase  the  amount  of  the  data  that  can  be  sent  over  the  network within a certain 
amount of time and bandwidth. 

MUX:  ​The multiplexer is one of the most important components in communications networking. Its
central function, from the network managers viewpoint, is to concentrate many users (or
information channels) on to a single transmission channel in order to maximise the efficiency of
that channel: it is used in almost every aspect of networking digital data, voice and video. This
section will describe the advantages and disadvantages of different data multiplexing techniques,
why these different techniques evolved to solve particular network engineering problems and how
they fit into modern networks.Given a transmission channel, there are two ways the available
bandwidth can be used: firstly by dividing the available bandwidth frequency spectrum into a
subset of frequencies, each of which can then simultaneously use the transmission channel and
allocate each frequency band to an input channel that needs to be multiplexed; or secondly,
allocate all the available bandwidth to each channel for a fixed discrete time period.
Block Diagram :

Circuit Diagram :

Truth Table:
Behavioural VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FourToOneMUX is
port( A,B,C,D : in STD_LOGIC;
S0,S1: in STD_LOGIC;
Z: out STD_LOGIC );
end FourToOneMUX;

architecture bhv of FourToOneMUX is

begin
process (A,B,C,D,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
Z <= A;
elsif (S0 ='1' and S1 = '0') then
Z <= B;
elsif (S0 ='0' and S1 = '1') then
Z <= C;
else
Z <= D;
end if;
end process;
end bhv;

Output:

Conclusion: In this experiment now we are able to realize the design of 4X1 MUX by
implementing in VHDL codes and we have also obtained the output waveform.