Designing suggestions for space

application

By Francesco Poderico
francesco_poderico@yahoo.com
 OUTLINE
● Cumulative effects on digital CMOS circuits
● Cumulative effects on analog circuits
● SEE on digital and analog circuits
TID effects on digital CMOS circuits
As we are talking on digital circuits we are interested to
understand how the speed is effected and how the input and
output threshold are effected as well.
●
Ron = 1/[μ Cox(W/L) (Vgs-Vt)] (μ↓ Vt ↑ => Ron↑)
●
Gm = μ Cox(W/L) (Vgs-Vt) (Gm ↓)
●
Vt increase (in module)
●
Leakage current between drain and source
increase
●
Leakage current between adjacent MOS
increase
TID effects on digital CMOS circuits
● Vtn on N-MOS and P-MOS
Variation of Vt for N-MOS and P-MOS

Vtno
radiation

Vtp0
TID effects on digital CMOS circuits
● A reduction of Vt on N-MOS may prevent MOS
to switch off
● Even the Id/Vgs is reduced prevent N-MOS to
switch off as well
Id
Id

radiation
radiation

Vgs
Vgs
TID effects on digital CMOS circuits
● Vtn increase may prevent N-MOS from switch
ON

Id

2 1 3

radiation

Vgs
TID effects on digital CMOS circuits
● The leakage current between D and S may
prevent NMOS to switch OFF!
Id

Vgs
● The leakag current between MOS ,ay prevent
the circuits to work correctly
● Increase of static power
TID effects on digital CMOS circuits
● An increase (abs) of vtp can prevent PMOS to
switch ON

Id

radiation

Vgs
 Question
● On Microspace application do you prefer to use
an NAND gate or an NOR gate ?
Solution : NAND gate
 Timing issues
●
μ decrease => the rising and falling edge slows
down. This may cause unwanted glitches for
not synchronous designs, and not meeting the
timing for synchronous designs.
●
Solution => use only synchronous design if
possible, add an high margin (e.g. 50%) for
micro-space solutions!
 Dynamic power
● As consequences of slower rising and falling
edge, the dynamic power will increase!
● Solution on micro-space product add a further
margin of 20% on the power budget!
Cumulative effect on analog circuits
● DC Biasing on CMOS amplifier
I = (μ Cox/2)(w/L)(Vg-Vt)²
– Before irradiation everything it's OK!
– After irradiation: DC point is shifted (I decreased, V
modified)
●
Possible solutions:
Raise Vdd to restore the initial I (difficult solution)
– Power consumption will increase!
 G BW product
● GBW~ gm/Cout
●
gm =μCox(W/L)(Vg-Vt)= 2[(μCox/2)(W/L)Ibias]½
●
When dose ↑ => μ ↓, Vtn ↑ => gm ↓ => GBW ↓

Possible corrections
●
Raise Vdd (obviously not easy)
 G BW product
● GBW~ gm/Cout
●
gm =μCox(W/L)(Vg-Vt)= 2[(μCox/2)(W/L)Ibias]½
●
When dose ↑ => μ ↓, Vtn ↑ => gm ↓ => GBW ↓

Possible corrections
●
Raise Vdd (obviously not easy)
 G BW product
●
As GBW will reduce => the phase margin will
get smaller!
Possible solutions:
●
Have a large phase margin at beginning of
project ( e.g. MF > 80⁰)
●
Use Miller effect to improve stability
●
Make a pole zero compensation
●
Use passive filter as much as possible
 BJT OP AMP vs MOS OP AMP

● A mismatch on the Vt due to different dose

radiation will cause a mismatch. For this reason
is better to use in the differential stage BJT
transistor
● Do not use MOS diff AMP as comparator!

Vt1 /= Vt2 => input offset voltage increase

 Bipolar differential amplifier with
“standard” mirror current
● Better than MOS
●
As β ↓ the Rin ↓, gain ↓, BW↓ , Ic ↑

Iref
Ic = Iref-2Iref/β
Ib
 Bipolar differential amplifier with
Wilson mirror current
● Ic is more stable over radiation

Iref

Ic ~ Iref-2Iref/β²
Single stage amplifier with low input
impedance
● When you need a low impedance amplifier, it is
better to drive the current from the collector.
● How is possible to improve this circuit?

T1
Better solution (for high irradiation)
● Consider to use a Wilson

T1
 OP AMP LATCH UP
● Due to the discharge of the internal
compensation capacitor of the OP AMP
● SEE on Q18, if CC2 has a large voltage across
it, it will destroy Q18.
 OP AMP LATCH UP
● Solution 1 use an OP AMP without internal
compensation capacitor (YES A VERY OLD OP
AMP)
● For micro-space application consider an audio
OP AMP (they have a resister in series to the
compensation capacitor)
● Try to minimize the maximum voltage across
the Capacitor
 SINGLE EVENT LATCHUP on
CMOS
● An high energy particle trigger the parasitic
thuristor, Vdd is shorted to gnd causing an high
current that damage the chip
High energy particle
 Latch up solution 1
● Use CMOS LATCH UP immune
High energy particle

SiO2

The SiO2 “stops” the funnelling to short Vdd to Vss, the thyristor is not present
any more
 Latch up solution 2
● Use a current limiter in series to the device to
protect.
● It may be too slow!
● Bypass capacitor may contain enough energy
to damage the device
 SEU protection
● Add a series resister to minimize current due to
SEU

C
Ic