The City College of New York

School of Engineering
EE32200 Electrical Engineering Laboratory II
Section 27667
Spring Semester 2022

Lab Report Experiment #1

Flip Flops and Sequential Circuits

Instructor:
Saurabh Sachdeva
Student Name:
Ronny Vintimilla

03/09/2022
Introduction
In this practice are used some Flip Flops such as J-K, D, gates and Integrated

Circuits. From here, we built a sequential circuit which have memory. Its block diagram

is made up of input, output, clock, combinational logic circuit, and a memory element

like flip flops. The Flip Flops have two stable states which store binary data. The flip

flops can make counters, shift registers, and some state machines. The first part of our

experiment was built D Flip Flop to analyze its functionality. The second part of our

experiment was design different Flip Flop to form counters and register to analyze its

performance.

Purpose

The main objective of this practice was to know the performance of some Flip

Flops for designing different sequential circuits.

Equipment

1. Protoboard
2. Triple Power Supply
3. Digital Voltmeter
4. Function Generator
5. Oscilloscope

Procedure in Multisim:

The following figure of some Flip Flops was simulated using Multisim to

determine the timing diagram of each other, as shown below.

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Step 1: Level – Sensitive Latch

Circuit 1

Fig.1. Level Sensitive Latch on Multisim with 4 NAND gates and 1 NOT gate

Fig.2. Time diagram for the D flip flop

1. We will build the level sensitive latch circuit of Figure 1 using Multisim.
2. We will use Word Generator to monitor the inputs such as D and CP. And
we will use Logic Analyzer to monitor the outputs such as Q. When the
clock takes logic 1 the output will be the same as input. And with logic 0
output remains unchanged
3. We will simulate the latch by setting the signal rate for the word generator
to 1 KHz and setting for the Logic Analyzer to frequency 10 KHz.

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Questions

a) Explain in your lab report the different between a D-type edge triggered

flip flop and the D-type latch shown in figure 1?

The D-type latch has a high clock pulse which allow a change of state. While

edge triggered flip flop has a clock signal which transfers input data to output

data.

b) For the 74LS74 IC and the 74LS76 IC state whether the Q outputs change

on the rising edge of the clock or the falling edge of the clock?

For both flip flops, the D input on the 74LS74 its Q output changes on the rising
edge of the clock. While The J-K input on the 74LS76 or 74LS112 the Q output
changes on the falling edge of the clock.

c) Explain the different between a synchronous counter and a ripple counter.

Synchronous counter:
Flip Flops are triggered with the same clock simultaneously
Fast in operation
No decoding errors
Operates in any desired count sequence
Ripple Counter:
Flip Flops are triggered with different clock
Slower in operation
Decoding errors
Operates in only in fixed count sequences

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 Step 2: 3 -bit modulo 8 synchronous counter

Circuit 2

Fig.3. 3-bit modulo 8 synchronous counter

Fig.4. Timing diagram for modulo 8 counter

1. We will build the circuit synchronous counter of Figure 3 using Multisim and
designing with the 74LS76 J-K flip flop ICS.
2. We will use three JK flip flops to 3 bits.
3. We will count from 0 to 7 since we will use 3 bits which means 23 = 8.

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Step 3: 3 -bit modulo ripple counter

Circuit 3

Fig.5. 3 bit modulo ripple counter

Fig.6. Timing diagram for ripple counter

1. We will build the circuit ripple counter of Figure 5 using Multisim and
designing with the 74LS74 D flip flop ICS.
2. We will use three D flip flops to 3 bits.
3. We will count up from 0 to 7 and not down since we will use 3 bits which
means 23 = 8.

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Step 4: 4 -bit shift register

Circuit 4

Fig.7. 4 bit shift register

Fig.8. Timing diagram for 4 bit shift register

1. We will build the circuit shift register of Figure 7 using Multisim and designing
with the 74LS74 D flip flop ICS.
2. We will use 4 D flip flops to 4 bits.
3. We will count up from 0 to 15 and not down since we will use 4 bits which
means 24 = 16.

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Procedure in Laboratory:

Data/ Observations

The following data of output signal Q1, Q2, Q3, Q4 of each figure was

experimentally determined from different instruments such as box and oscilloscope and

programs such as Labview, to each circuit, as shown below.

In each circuit, we used a capacitor of 0.1 uF between the power and ground pins

of each flip flop and a resistor of 10K ohms in series for each output.

Step 2: 3 -bit modulo 8 synchronous counter

Circuit 2

Fig.9. Output bits of Q1, Q2, Q3 for modulo 8 synchronous counter using J-K Flip Flop
ICs.

Fig.10. Output signal of Q1, Q2, Q3 for modulo 8 synchronous counter using
Oscilloscope.

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 1. We built the circuit of Figure 3 on our protoboard and designing with 2 the
74LS112 J-K flip flop ICS and one 74LS00N NAND.
2. We used 2 J-k flip flops to 3 bits and connected a resistor for each output Q1,
Q2, Q3.
3. We placed a capacitor in the V++ pin of each J-K flip flop.
4. We set the power supply to 5V and placed wires for Q1, Q2, Q3 between the
box and protoboard as well for Clock and ground.
5. We used Labview Vi and selected Word Generator/ Logic Analyzer and
obtained the figure 9.
6. Once the Labview was running, we obtained activated bits or deactivated bits
according to our counter. It quickly counted from 0 to 7 and saved the data and
graph as shown figure 9. We noticed that our counter was counting correctly
because it was from 0 to 7.
7. After that, we used the function generator setting 1kHz square wave with 5V
high and 0V low levels and connected output of function generator in our clock
pin.
8. We set the oscilloscope with the time/div to 1mS/div, the vertical scale to 5V for
all 3 channels.
9. We align the traces as clop in the top and Q1, Q2 ,Q3 respectively.
10. We connected the oscilloscope considering channel 1 as input of clock, channel
2 as input of Q1, channel 3 as input of Q2, channel 4 as input of Q3.
11. We used Labview for Save Oscilloscope image as shown Figure 10.

Step 3: 3 -bit modulo ripple counter

Circuit 3

Fig.11. Output bits of Q1, Q2, Q3 for modulo ripple counter using D Flip Flop ICs.

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Fig.12. Output signal of Q1, Q2, Q3 for modulo ripple counter using Oscilloscope.

1. We built the circuit of Figure 5 on our protoboard and designing with 2 the
74LS74 D flip flop ICS.
2. We used 2 D flip flops to 3 bits and connected a resistor for each output Q1, Q2,
Q3.
3. We placed a capacitor in the V++ pin of each D flip flop.
4. We set the power supply to 5V and placed wires for Q1, Q2, Q3 between the
box and protoboard as well for Clock and ground.
5. We used Labview Vi and selected Word Generator/ Logic Analyzer and
obtained the Figure 11.
6. Once the Labview was running, we obtained activated bits or deactivated bits
according to our counter. It quickly counted from 0 to 7 and saved the data and
graph as shown figure 11. We noticed that our counter was counting correctly
because it was from 0 to 7.
7. After that, we used the function generator setting 1kHz square wave with 5V
high and 0V low levels and connected output of function generator in our clock
pin.
8. We set the oscilloscope with the time/div to 1mS/div, the vertical scale to 5V for
all 3 channels.
9. We align the traces as clop in the top and Q1, Q2, Q3 respectively.
10. We connected the oscilloscope considering channel 1 as input of clock, channel
2 as input of Q1, channel 3 as input of Q2, channel 4 as input of Q3.
11. We used Labview for Save Oscilloscope image as shown Figure 12.

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Step 4: 4 -bit shift register

Circuit 4

Fig.13. Output bits of Q1, Q2, Q3, Q4 for shift register using D Flip Flop ICs.

Fig.14. Output signal of Q1, Q2, Q3, Q4 for shift register using Oscilloscope.
1. We built the circuit of Figure 7 on our protoboard and designing with 2 the
74LS74 D flip flop ICS.
2. We used 2 D flip flops to 3 bits and connected a resistor for each output Q1, Q2,
Q3, Q4.
3. We placed a capacitor in the V++ pin of each D flip flop.
4. We set the power supply to 5V and placed wires for Q1, Q2, Q3, Q4 between
the box and protoboard as well for Clock and ground.
5. We used Labview Vi and selected Word Generator/ Logic Analyzer and
obtained the figure 13.
6. Once the Labview was running, we obtained activated bits or deactivated bits
according to our counter. It quickly counted from 0 to 15 and saved the data and
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 graph as shown figure 13. We noticed that our counter was counting correctly
because it was from 0 to 15.
7. After that, we used the function generator setting 1kHz square wave with 5V
high and 0V low levels and connected output of function generator in our clock
pin.
8. We set the oscilloscope with the time/div to 1mS/div, the vertical scale to 5V for
all 3 channels.
9. We align the traces as clop in the top and Q1, Q2, Q3 respectively.
10. We connected the oscilloscope considering channel 1 as input of clock, channel
2 as input of Q1, channel 3 as input of Q2, channel 4 as input of Q3.
11. We used Labview for Save Oscilloscope image as shown Figure 14..

Fig.14. Output bits of Q1, Q2, Q3, Q4 for monitoring by Labview VI.

Questions

a) Discuss all results obtained include all logic diagrams, data, and images?
We obtained the same output digital signal from Multisim as Oscilloscope for
circuit 2, 3 and 4. From LabVIEW VI (Word generator/ Logic Analyzer, we got
binary numbers from 0 to 7 by circuit 1,2,3 and from 0 to 15 by circuit 4 which
represented a correct increasing count. All flip flops such as D or J-K and
sequential circuits were tested and verified its correct performance.

b) How would you make a mod 32 counter?

To build a flip flop which counts from 0 to 31, we will use 5 bits because
25 = 32.
Therefore, we will use 5 D flip flops to 5 bits.

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 c) Explain the difference between a synchronous and a ripple counter?
Synchronous counter:
Flip Flops are triggered with the same clock simultaneously
Fast in operation
No decoding errors
Operates in any desired count sequence
Ripple Counter:
Flip Flops are triggered with different clock
Slower in operation
Decoding errors
Operates in only in fixed count sequences
d) Explain the difference between an edge trigger flip flop and a latch.

Edge trigger flip flop:

Output changes depending on its clock signal if it is clock rising or falling edge.
Latch:
Output changes depending on its clock pulses if it is high or low.

Conclusion

Overall, the experiment achieved to acquire, compare, verify the digital signal

from Multisim and Oscilloscope in each circuit were the same and counted in an

increasing way. By monitoring each digital signal, we must use the box as shown figure

14 with correct connection. Also, this experiment is performed an analysis of the

synchronous and the ripple counter getting great differences from designing in parallel

and series respectively among others more. As a result, the waveform of oscilloscope

showed great similarities in the simulated and in the measured. The most import in each

circuit were, we used a capacitor of 0.1 uF between the power and ground pins of each

flip flop and a resistor of 10K ohms in series for each output. This prevented noise from

occurring and interrupting the output digital signal.

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