2.

1 Introduction

Basic of Memory Hierarchy: Quick Review

3 Cs Models
-compulsory
-Capacity
-Conflict

6 common power implications of these trade-offs

1. Larger blocksize to reduce miss rate

2. Bigger caches to reduce miss rate
3. Higher associativity to reduce miss penalty
4. Multi level caches to reduce miss penalty
5. Giving priorities read misses over writes to reduce miss penalty
6. Avoiding address translation during indexing of the cache to reduce hit time

2.2 Ten Advanced Optimizations of Cache Performamce

They examine into 5 categories:

1. Reducing the hit time
2.Increasing Cache bandwidth
3.reducing the miss penalty
4.Reducing the miss rate
5.Reducing the miss penalty or miss rate via parallelism

First Optimization: Small and Simple First-Level Caches to Reuce Hit Time and Power
Second Optimization: Way Prediction to Reduce Hit Time
Third Optimization: Piplened Cache Access to Increse Cache bandwidth
Fourth Optimization: Nonblocking Caches to Increase Cache Bandwidth
Fifth Optimization: Multibanked Caches to Increase Cache Bandwidth
Sixth Optimization: Critical Word First and Early Restart to Reduce Miss Penalty
Seventh Optimization: Merging Write Buffer to Reduce Miss Penalty
Eighth Optimization: Compiler Optimizations to Reduce Miss Rate

2 modern compiler:
- Loop Interchange
- Blocking

Ninth Optimization: Hardware Prefetching of Instructions and Data o Reduce Miss Penalty or Miss Rate
Tenth Optimization: Compiler- Controlled Prefetching to Reduce Miss Penalty or Miss Rate
2 flavors of prefetch:
- Register prefetch
- Cache prefetch

Cache Optimization Summary

2.3 Memory Technology and Optimization
SRAM Technology
DRAM Technology
Improving Memory Performance inside a DRAM Chip
-Grpahics Data RAMs
Reducing Power Consumption in SDRAMs
Flash Memory
-(Exaplain the 5 difference between Flash and standard DRAM)
Enchancing Dependability in Memmory Systems
3 unrecoverable erros in 3 years operation
-Parity Only
- ECC only
- Chipkill

2.4 Protection: Virtual Memory and Virtual Machines

Protection via Virtual Memory

4 architecture must do

Protection Machine
2 benefits that are commercially significant
- Managing Software
- Managing Hardware

Requirements of a Virtual MAchine Monitor

- 2 qualitative requirements
- 2 Basic requirements of system virtual machines

(Lack of) instruction Set Architecture Support of Virtual Machines

Impact of Virtual Machines on Virtual Memory and I/O
An Example VMM: The Xen Virtual Machine

2.5 Crosscutting Issues: The Design of Memory Hierarchies

Protection and Instruction Set Architecture

3 steps to improve performance of virtual machine

Coherency of Cached Data

2.6 Putting it all together: Memory Hierarchies in the ARM Cortex - A8 and Intel Core
i7

The ARM Cortex-A8

-Performance of the Cortex-A8 Memory Hierarchy
The Intel Core i7
-Performance of the i7 Memory system
2.7 Fallacies and Pitfalls

Fallacy (predicting cache performance of one program from another)

Pitfall (simulating enough instructions to get accurate performance measures of the memory hierarchy)
Pitfall (Not delivering high memory bandwidth in a cache-based system)
Pitfall(Implementing a virtual machine monitor on an instruction set architecture that wasn't designed
to be virtualizable)

2.8 Concluding Reamarks: Looking Ahead

2.9 Historical Perpective and References

Case study by Norman P. Jouppi, Naveen Muralimanohar, and sheng Li

case study 1: Optimizing Cache Performance via Advaned Techniques

Concept illustrated by this case study
- Non-blocking Caches
- Compiler Optimizations for Caches
- Software and Hardware Prefetching
-Calculating Impact of Cache Performance on More Complex Processors

Case study 2: Putting It all together: Highly Parallel Memory Systems

Concept illustrated by this case study
- Crosscutting Issues: The Design of Memory Hierarchies

Explain the Floorplan of the Alpha 21264[Kessler 1999]