Chapter 1

Analog Representation: In analog representation a quantity is represented by a continuously

variable, proportional indicator. The quantities can vary over a continuous range of values.

Digital Representation: In digital representation the quantities are represented not by

continuously variable indicators but by symbols called digits. The quantities can take on only
discrete values.
Analog = continuous values / Real world
Digital = discrete set of values (step by step) / Logical

Digital Systems: A digital system is a combination of devices designed to manipulate logical

information or physical quantities that are represented in digital form; that is, the quantities
can take on only discrete values.

Analog Systems: An analog system contains devices that manipulate physical quantities that
are represented in analog form; that is, the quantities can vary over a continuous range of
values.

Advantages & Limitations of Digital Techniques:

Advantages Limitations
1) Easier to design
2) Information storage is easy
3) Accuracy & precision is easier to
maintain 1. The real world is analog
4) Operation can be programmed 2. Processing digital signals takes time
5) Circuits are less affected by noise
6) More digital circuitry can be fabricated
on IC chips

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Converting Analog to Digital Form: Analog to Digital Converter (ADC) works as follows:
 Sample the analog signal
 Quantify it to determine the Resolution
 Set binary values
 Send the digital values

Digital Temperature Control System: The figure describes a precision temperature-

regulation system. A user pushes up or down buttons to set the desired temperature in 0.1°
increments (digital representation). A temperature sensor in the heated space converts the
measured temperature to a proportional voltage. This analog voltage is converted to a
digital quantity by an analog-to-digital converter (ADC). This value is then compared to the
desired value and used to determine a digital value of how much heat is needed. The digital
value is converted to an analog quantity (voltage) by a digital-to-analog converter (DAC).
This voltage is applied to a heating element, which will produce heat that is related to the
voltage applied and will affect the temperature of the space.

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Memory: When an input signal is applied to most devices or circuits, the output somehow
changes in response to the input, and when the input signal is removed, the output returns to
its original state. These circuits do not exhibit the property of memory because their outputs
revert back to normal. In digital circuitry certain types of devices and circuits do have memory.
When an input is applied to such a circuit, the output will change its state, but it will remain in
the new state even after the input is removed. This property of retaining its response to a
momentary input is called memory.

Microcomputer VS Microcontroller:

Microcomputer Microcontroller

Can be programmed by user Can’t be programmed by user

Basically has all the elements of a
Basically is a CPU
complete computer

Difference between serial and parallel transmission:

Serial Parallel

Data flows in a line Data flows in multiple lines

Cost efficient Not cost efficient

1-bit transfers at one clock pulse 8-bits transfers at one clock pulse

Relatively slow Relatively fast

Used for long-distance Used for short-distance

Simple circuitry Complex circuitry

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 Chapter 2
Number System Conversion:

Binary -> Decimal: (Weight Based)

Decimal -> Binary: (Reverse Counting)

Decimal -> Binary: (Repeated Division)

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Hex -> Decimal: (Weight Based)

Decimal -> Hex: (Repeated Division)

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 Hex -> Binary: (Equivalent 4-bit)

Binary -> Hex: (Equivalent 4-bit)

Code: When numbers, letters, or words are represented by a special group of symbols, we say
that they are being encoded, and the group of symbols is called a code.

Straight Binary Coding: When a decimal number is represented by its equivalent binary
number, we call it straight binary coding.

BCD (Binary Coded Decimal): If each digit of a decimal number is represented by its binary
equivalent, the result is a code called binary-coded-decimal or BCD.

Decimal -> BCD:

BCD -> Decimal:

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 Forbidden Group:

Equivalent BCD for 10-16 are called forbidden group and regarded as error when
occurred.

BCD VS Binary:

BCD Binary/Straight Binary

Not a number system
Converts each decimal digit to binary
individually
Doesn’t use all possible 4-bit groups,
therefore somewhat inefficient
Relatively easy for converting to and from
decimal
A number system
Takes the complete decimal number and
represents it in binary
Not inefficient in that manner
Conversion can become long and
complicated

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Gray Code: Gray code has been developed as a way to represent a sequence of numbers. The
unique aspect of the Gray code is that only one bit ever changes between two successive
numbers in the sequence.

Binary -> Gray:

Gray -> Binary:

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Bytes: A byte is a group of 8-bits.

Nibbles: A nibble is a group of 4-bits.

Words: A word is a group of bits that represents certain unit of information. The word size can
be defined as the number of bits in the binary word that a digital system operates on. This PC
has a word size of 64-bits.

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ASCII Code (American Standard Code for Information Interchange): The ASCII code is a 7-bit
code, and so it has 27 = 128 possible code groups.

Parity Bit: A parity bit is an extra bit that is attached to a code group that is being transferred
from one location to another for the sole purpose of detecting error in the code. The parity bit
is made either 0 or 1, depending on the number of 1s that are contained in the code group.

Even-Parity Method Odd-Parity Method

Number of 1s in the code

Add 1 as the 8th bit Add 0 as the 8th bit
is odd

Number of 1s in the code

Add 0 as the 8th bit Add 1 as the 8th bit
is even

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 Chapter 3
Boolean algebra: Boolean algebra is a division of mathematics that deals with operations on
logical values or truth values true (1) and false (0).

Postulates of Boolean algebra:

AND OR NOT
x+0=x x.1=x 𝑥=x
x+1=1 x. 0 = 0
x+x=x x.x = x
x+𝒙=1 x. 𝒙 = 0

Multivariable Theorems:

 x+y=y+x [commutative law]

 x.y=y.x [commutative law]
 x + (y + z) = (x + y) + z = x + y + z [associative law]
 x(yz) = (xy)z = xyz [associative law]
 x(y + z) = xy + xz [distributive law]
 (w + x)(y + z) = wy + xy + wz + xz [distributive law]
 x + xy = x
 x + 𝑥y = x + y ->
 𝑥 + xy = 𝑥 + y ->

Proof:

x + 𝑥y 𝑥 + xy

= x.1 + 𝑥y = 𝑥.1 + xy

= x(1 + y) + 𝑥y = 𝑥(1 + y) + xy

= x + xy + 𝑥y = 𝑥 + 𝑥y + xy

= x + y(x + 𝑥) = x + y = 𝑥 + y(𝑥 + x) = 𝑥 + y

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Demorgan’s Theorem:

Truth Table: A truth table is a means for describing how a logic circuit’s output depends on the
logic levels present at the circuit’s inputs.

Basic Gates:

OR gate AND gate NOT gate

AND
Performs OR operation (Combination) NOT operation (Inversion)
operation(Multiplication)

Expression x = A+B x = A.B x=𝐴

Output=1 Any input = 1 All input = 1 Input = 0

Output=0 All input = 0 Any input = 0 Input = 1

Describing Logic Circuits Algebraically: Any circuit can be described using the 3-basic Boolean
operations (AND, OR and NOR).

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Evaluating Logic Circuit Outputs: For the case (A=0, B=1, C=1, D=1)

Implementing Circuits from Boolean Expression: Implement x = (A+B)(𝐵+C).

NOR gate NAND gate

Expression x=𝐴+𝐵 x = 𝐴. 𝐵

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Universality of NAND:

Universality of NOR:

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 Chapter 4

Sum of Products: This is a common method for circuit simplification.

Products of Sum:

Simplifying Logic Circuits:

Algebraic Simplification:

1. The original expression is put into SOP form by repeated application of DeMorgan’s
theorems and multiplication of terms.
2. Once the original expression is in SOP form, the product terms are checked for common
factors, and factoring is performed wherever possible. The factoring should result in the
elimination of one or more terms.

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Designing Combinational Logic Circuits:

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Complete Design Procedure:

1. Interpret the problem and set up a truth table to describe its operation.
2. Write the AND (product) term for each case where the output is 1.
3. Write the sum-of-products (SOP) expression for the output.
4. Simplify the output expression if possible.
5. Implement the circuit for the final, simplified expression.

Set-up truth AND inputs, Sum-of- Simplify Implement

table for output 1 product expression circuit

Karnaugh Map Method: The Karnaugh map (K map) is a graphical tool used to simplify a logic
equation or to convert a truth table to its corresponding logic circuit in a simple, orderly
process. Its practical usefulness is limited to 5 or 6 variables.

Karnaugh Map Format:

1. Gives the value of output x for each combination of inputs.

2. Adjacent squares differ only in one variable. The top row and the bottom row also
follow this condition.
3. Top-to-bottom labeling: 𝐴𝐵 , 𝐴B, AB, A𝐵
4. Left-to-right labeling: 𝐶 𝐷 , 𝐶 D, CD, C𝐷
5. OR together the squares containing a 1.

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Looping: The process of combining the 1s in the K-map is called looping.

Looping Groups of Two (Pairs):

Looping a pair of adjacent 1s in a K map eliminates the variable

that appears in complemented and uncomplemented form.

Looping Groups of Four (Quads):

Looping a quad of adjacent 1s in a K map eliminates the two

variables that appear in complemented and uncomplemented
form.

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Looping Groups of Eight (Octets):

Looping an octet of adjacent 1s in a K map eliminates the three

variables that appear in complemented and uncomplemented
form.

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 Pair Looping Quad Looping Octet Looping

Loops 2 adjacent 1s 4 adjacent 1s 8 adjacent 1s

Eliminates 1 variable 2 variables 3 variables

Exclusive-OR & Exclusive-NOR:

Ex-OR Ex-NOR

Input
Only two inputs Only two inputs
number

Output x = 𝐴B + A𝐵 x = AB + 𝐴𝐵

Output
x=AB x=𝐴𝐵
(shorthand)

Symbol

Output = 1 Inputs are different Inputs are same

Parity Generator:

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Parity Checker:

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 Chapter 5
Flip-Flop: A flip-flop or latch is a circuit that stores a single bit and has two stable states 1 and 0.

Q = 1 -> SET state

Q = 0 -> CLEAR or RESET state

NAND Latch:

 NAND-1’s output is one of NAND-2’s inputs.

 NAND-2’s output is one of NAND-1’s inputs.
 Other two inputs of the latch are SET and RESET.
 SET input sets Q to 1 state.
 RESET input resets Q to 0 state.
 SET = RESET = 1 -> resting state of the latch.
 When SET = 0 -> Q becomes 1.
 When RESET = 0 -> Q becomes 0.

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Setting Latch:

 For (a) where Q=0 & 𝑄=1, when SET=0 -> Q becomes 1 and forces 𝑄 to become 0.
 For (b) where Q=1 & 𝑄=0, when SET=0 -> Q stays 1 and forces 𝑄 to stay 0.
 Hence, only changing SET to low makes/keeps Q HIGH and it stays like this for the whole
clock pulse.

Re-setting Latch:

 For (a) where Q=1 & 𝑄=0, when SET=0 -> Q stays 0 and keeps 𝑄 at 0.
 For (b) where Q=0 & 𝑄=1, when SET=0 -> 𝑄 becomes 1 and forces Q to become 0.
 Hence, only changing RESET to low makes/keeps Q LOW and it stays like this for the
whole clock pulse.

NAND Latch Table:

SET RESET OUTPUT

1 1 No change
0 1 Q=1
1 0 Q=0
0 0 INVALID* (Q=𝑄=1)

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NOR Latch:

 SET input sets Q to 1 state.

 RESET input resets Q to 0 state.
 SET = RESET = 0 -> resting state of the latch.
 When SET = 1 -> Q becomes 1.
 When RESET = 1 -> Q becomes 0.

NOR Latch Table:

SET RESET OUTPUT

0 0 No change
1 0 Q=1
0 1 Q=0
1 1 INVALID* (Q=𝑄=1)

Digital Pulses: In a digital system, when a signal switches from inactive state to active state, it
creates an effect in the circuit. Then the signal return to its inactive state but the effect remains
in the system. These signals are called pulses.

 positive pulse-> performs intended function, when signal goes HIGH.

 negative pulse->performs intended function, when signal goes LOW.
 It takes time for the pulse waveform to change from one level to the other.
 tr (rise time) -> voltage change 10% - 90%.
 tf (fall time) -> voltage change 90% -10%.
 tw (pulse duration) -> time between the points when leading edge & trailing edge is
50%.

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Asynchronous vs Synchronous:

Asynchronous Synchronous
Depends both on input change and clock
Output change Depends only on input change
pulse
Design Difficult to design Easier to design
Troubleshoot Difficult to troubleshoot Easier to troubleshoot

Clocked Flip-Flops: A flip-flop circuit that is set and reset at specific times by adding clock pulses
to the input so that the circuit is triggered only if both the clock pulse and inputs trigger and
clock pulses are present simultaneously.

 Clocked FFs have a clock input, often named CLK.

 CLK is edge-triggered; but the latch is level-triggered.
 When a CLK input has a triangle, it means inputs activate while PGT.
 When a CLK input has a bubble and a triangle, it means inputs activate while NGT.
 Clocked FFs have one or more control inputs that are synchronized with CLK.
 These control inputs are called synchronous control inputs.
 The control inputs control WHAT (i.e. what state the output will go to).
 The CLK input controls WHEN.

Edge-triggered Level-triggered

Circuit activates at the positive or Circuit activates when the clock

negative edge of the clock signal. pulse is at a particular level.

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Setup and Hold Times:

 The setup time, tS, is the time interval before the active transition where the control
input (data) must be held.
 The hold time, tH, is the time interval after the active transition where the control input
(data) must be held.
 The control inputs must be stable (unchanging) for at least a time interval equal to
tS(min) before the clock transition, and for at least a time interval equal to tH(min) after
the clock transition.

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Clocked S-R Flip-Flop: Works as an S-R flip-flop only when the clock pulse is triggered. The
following clocked S-R flip-flop works on PGT and uses the NOR latch:

Internal Circuitry of Edge-triggered S-R Flip-Flop: The circuit contains three sections:

1. A basic NAND latch formed by NAND-3 and NAND-4.

2. A pulse-steering circuit formed by NAND-1 and NAND-2.
3. An edge-detector circuit.

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Edge-detector circuit:

 𝐶𝐿𝐾 occur a little bit after CLK, cause of the Inverter.

 For (a), CLK* becomes HIGH only when there’s a PGT, otherwise LOW.
 For (b), CLK* becomes HIGH only when there’s a NGT, otherwise LOW.

Clocked J-K Flip-Flop: The J and K inputs control the state of the FF in the same ways as S and R
inputs do for the clocked S-R flip-flop except for one major difference: the J=K=1 condition
doesn’t result in an ambiguous output. It generates a different state called toggle, in which the
FF changes state for each PGT/NGT of the clock. The following clocked J-K flip-flop works in PGT
and uses the NOR latch:

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Internal Circuitry of the Edge-Triggered Flip-Flop: The circuit contains three sections:

1. A basic NAND latch formed by NAND-3 and NAND-4.

2. A pulse-steering circuit formed by NAND-1 and NAND-2.
3. An edge-detector circuit.

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Clocked D Flip-Flop:

 It has only one control input named D (data).

 Q changes into the same state as D when PGT occurs at CLK.

Implementation of D Flip-Flop:

 Add a single Inverter to the edge-detector J-K flip-flop.

 Consider D=J and 𝐷=K.

The same can be done to convert an S-R flip-flop into a D flip-flop.

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 Chapter 7
Asynchronous (Ripple) Counter:

 J=K=1 for all the FFs, meaning they’re all in toggle mode.
 Clock pulses are applied only to CLK of flip-flop A.
 A acts as CLK for B, B for C and C for D.
 A toggles after 1 clock cycle, B after 2 clock cycle, C after 4 clock cycle and D after 8 clock
cycle.
 D, C, B and A represent a 4-bit binary number, with D as the MSB.
 Counting starts from 0000 to 1111 for the 15 clock cycle.
 After 15 clock cycle, the counter returns to 0000 state, thus going through a complete
cycle.
 It’s called asynchronous counter as the FFs don’t change in exact synchronism with the
clock pulse.
 It’s called rippling counter as the FFs respond one after another like a rippling effect.
 There is a propagation delay between the successive FFs.

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MOD Number: Number of states a counter goes through before it recycles back to its starting
state. For N number of FFs,

MOD number = 2N

Frequency Division:

 Each FF provides an output waveform that is exactly half the frequency of the waveform
at its CLK input.
𝐹𝑟𝑒𝑞𝑢𝑛𝑐𝑦 𝑜𝑓 𝑡ℎ𝑒 𝑖𝑛𝑝𝑢𝑡 𝑐𝑙𝑜𝑐𝑘
 Frequency of the last 𝐹𝐹 = .
𝑀𝑂𝐷 𝑛𝑢𝑚𝑏𝑒𝑟

Synchronous (Parallel) Counters:

 All the FFs are triggered simultaneously by CLK, the clock input pulses.
 Only flip-flop A, the LSB, has permanent J and K as HIGH.
 Each FF should have its J and K inputs connected, so that they are HIGH only when the
outputs of all lower-order FFs are in the HIGH state.
 This counter needs more circuitry.

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Synchronous Counter vs Asynchronous Counter:

Synchronous Counter Asynchronous Counter

All FFs are triggered simultaneously Different FFs are triggered with
Triggering FF
with the same clock different clock
Operation speed Operations are faster Operations are slower

Decoding error Doesn’t produce decoding error Produces decoding errors

Other names Also called Parallel counter Also called Serial/Ripple Counter

Total delay FF tpd + AND gate tpd N × tpd

Circuit design Complex circuitry Easier circuitry

Input frequency Can operate at higher input frequency Not useful at high input frequency

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Decoding Counters:

LED indicator Electronic decoding

LEDs are connected with every FF output
Counting is determined mentally
LEDs on/off combinations are visualized and
the number is decoded by the binary states
of the LED
Inconvenient for large size counter
Need human intervention
Electronic detectors are connected with
every FF output
No mental operation is required
The corresponding number is visualized
Operates smoothly even for large size
counter
Doesn’t need human intervention

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