(DTACK)

(CS)
CS_DRAM
U24
1
CLK
VCC 2 19 (AREQ)
1 I0 IO0
3 18 (ENCAS)
AS I1 IO1
CPU RN4 10K COPROCESSOR 4
I2 O2
17
8 3 5 16
1MHZ CLK Q0 I3 O3
4 U30 U29 6 15
Q1 I4 O4 DRAM CTRLR

2
3
4
5
6
7
8
9
9 5 7 14
AS CLR Q2 ADDW I5 O5 32 MB DRAM
6 E1 H2 8 13
Q3 CLK HALT 11 I6 IO6
VCC 10 C3 CLK 9 12
Q4 BGACK I7 IO7 STERM
11 A1 13 11 U23
Q5 F12 BR MRESET RESET OE
1 12 U11:D MRESET RESET L1 4 SIMM1
DSA Q6 CIIN SENSE 22
2 13 13 12 (8uS) H1 E2 GAL16V8 43 47 71
DSB Q7 BERR AVEC 28 WE R27 WE BLKSEL3
J1 R/W R/W DRAM GLUE 71 66
D2 CBACK 20 WAITIN WAITIN BLKSEL2
74LS04 FC0 FC0 31 DS DS 54 70 46
C1 DSACK0_COP DSACK0 21 R/W WIN PD3 BLKSEL1
74LS164 U35 FC1 FC1 32 AS AS 69 29
R/W D1 DSACK1_COP DSACK1 PD2 BLKSEL0
FC2 FC2 M1 U21 41 68 11
DBEN ADS PD1 CASP
L3 M2 A0 1 55 67
WR R/W ECS U33 I0 AREQ PD0
U11:B K2 D3 A1 2 19 58
DS DS OCS 1 I1 O0 CS
4 3 J2 B1 I0 3 18 78 38 64 D31
RD AS AS RMC 2 19 SIZ0 I2 IO1 WAIT MP3 DQ31
B2 AS I1 O0 CPUSPC 4 17 35 62 D30
F1 BG 3 18 SIZ1 I3 IO2 MP2 DQ30
74LS04 DSACK0 DSACK0 C2 FC2 I2 IO1 5 16 37 60 D29
G2 CIOUT 4 17 R/W I4 IO3 MP1 DQ29
DSACK1 DSACK1 K1 FC1 I3 IO2 6 15 35 36 58 D28
G1 CBREQ 5 16 I5 IO4 ECAS0 74AS32 MP0 DQ28
STERM STERM J13 FC0 I4 IO3 7 14 36 56 D27
REFILL A19 6 15 A13 I6 IO5 ECAS1 U16:D DQ27
E13 I5 IO4 8 13 37 12 10 54 D26
IPEND A18 7 14 A14 I7 IO6 ECAS2 11 42 DQ26
H12 I6 IO5 9 12 38 49 13 R22 CAS3 52 D25
CDIS CDIS A17 8 13 I8 O7 ECAS3 CAS0 DQ25
F13 I7 IO6 11 U16:C 50 D24
MMUDIS MMUDIS A16 9 12 29 I9 9 10 DQ24
U20 I8 O7 CS 39 8 41 27 D23
A15 11 B0 50 10 R20 CAS2 DQ23
10 9 H13 L2 I9 GAL16V8 A4 40 CAS1 25 D22
0 A0 IPL0 SIZ0 SIZ0 VCC B1 U16:A DQ22
11 7 G13 K3 BYTE DECODE 74AS32 1 10 23 D21
IRQ_NET 1 A1 IPL1 SIZ1 SIZ1 GAL16V8 3 43 DQ21
12 6 G12 A12 9 51 2 R23 CAS1 21 D20
IRQ_IDE 2 A2 IPL2 COPRO DECODE R0 CAS2 DQ20
13 J12 18 A13 14 U16:B 9 D19
IRQ_SER 3 STATUS SIZ1 R1 4 74AS32 10 DQ19
1 14 CLK25M A14 16 6 40 7 D18
IRQ_KEYB 4 GS R2 52 5 R19 CAS0 DQ18

11
10
2 D0 K13 A2 A0 D0 3 A15 18 CAS3 5 D17

9
8
IRQ_PAR 5 D0 A0 D0 26 VCC R3 DQ17
3 D1 K12 C4 A1 D1 2 A0 A16 20 74AS32 3 D16
IRQ_FDC 6 D1 A1 D1 25 A1 R4 22 DQ16
4 D2 L13 D13 A2 D2 1 A1 A17 22 45 33 65 D15
7 D2 A2 D2 24 A2 R5 RAS0 R17 RAS3 DQ15
D3 M13 D12 A3 D3 68 A2 14 A18 24 46 34 63 D14
D3 A3 D3 23 A3 R6 RAS1 R18 RAS2 DQ14
5 15 D4 L12 C13 A4 D4 67 A3 A19 26 47 45 61 D13
EI EO D4 A4 D4 22 A4 R7 RAS2 R26 RAS1 DQ13
D5 K11 C12 A5 D5 66 A4 A20 28 48 44 57 D12
D5 A5 D5 R8 RAS3 R25 RAS0 DQ12
74LS148 D6 M12 D11 A6 D6 65 X3 A23 30 55 D11
D6 A6 D6 R9 10 (Q0-Q10) DQ11

7
6
5
4
9
8
7
6
5
4
3
2

D7 L11 B13 A7 D7 64 25 MHz A24 33 8 19 53 D10

VCC D7 A7 D7 R10 Q10 R13 A10 DQ10
D8 N13 B12 A8 D8 62 7 32 51 D9
D8 A8 D8 Q9 R16 A9 DQ9
D9 M11 C11 A9 D9 60 A2 13 6 31 49 D8
D9 A9 D9 C0 Q8 R15 A8 DQ8
1 D10 L10 A13 A10 D10 59 A3 15 5 28 26 D7
D10 A10 D10 C1 Q7 R14 A7 DQ7
D11 N12 C10 A11 D11 58 A5 17 4 18 24 D6
RN3 D11 A11 D11 C2 Q6 R12 A6 DQ6
VCC D12 M10 B11 A12 D12 57 A6 19 2 17 22 D5
10K D12 A12 D12 VCC C3 Q5 R9 A5 DQ5
D13 N11 A12 A13 D13 56 A7 21 84 16 20 D4
D13 A13 D13 C4 Q4 R10 A4 DQ4
D14 M9 B10 A14 D14 55 74LS74 A8 23 82 15 8 D3
D14 A14 D14 C5 Q3 R11 A3 DQ3
D15 N10 A11 A15 D15 54 U34:B A9 25 81 14 6 D2

10
D15 A15 D15 C6 Q2 R5 A2 DQ2
R2 R1 D16 N9 B9 A16 D16 50 A10 27 80 13 4 D1
D16 A16 D16 C7 Q1 R4 A1 DQ1
4K7 4K7 D17 M8 A10 A17 D17 49 12 8 A11 29 79 12 2 D0
D17 A17 D17 D Q C8 Q0 R3 A0 DQ0

S
D18 N8 C8 A18 D18 48 A21 31
U1:C D18 A18 D18 C9
10 D19 N7 A9 A19 D19 47 11 A22 34 SIMM72PIN
8 D19 A19 D19 CLK C10 76
9 D20 M7 B8 A20 D20 46 ATACKB
D20 A20 D20 77
D21 N6 A8 A21 D21 45 9 (12.5MHZ) 68 GRANTB

R
74ALS00 NMI1 D21 A21 D21 Q DELCLK 72 VCC
D22 M6 B7 A22 D22 44 VCC RFIP
NMI D22 A22 D22
D23 N5 A7 A23 D23 42

13
D23 A23 D23
D24 M5 A6 A24 D24 40 57
D24 A24 D24 67 LOCK
D25 N4 B6 A25 D25 39 CLK 56
U1:B D25 A25 D25 AREQB VCC
4 D26 N3 A5 A26 D26 38 69 70 RN2
6 D26 A26 D26 MRESET DISRFSH RFSH
5 D27 M4 B5 A27 D27 37 10K
D27 A27 D27 1
D28 N2 A4 A28 D28 36

4
74ALS00 D28 A28 D28 60
D29 M3 B4 A29 D29 35 CAP
D29 A29 D29 2 6 (SEE SHEET 2) 62 65
D11 U1:A D30 L4 A3 A30 D30 34 D Q ML COLINC

S
R55 2 D30 A30 D30
3 D31 N1 B3 A31 D31 33 R/W 74LS74 C44
1 AS D31 A31 D31 3

2
3
4
5
6
7
8
9
CLK U34:A DP8422V 1nF
330 ACTIVITY
74ALS00
5

R
D1 U1:D MC68030 MC68882 Q
R8
11
13 VCC WAIT STATE 1
12 J11 CDIS

1
U12 2
330 STATUS CACHE
74ALS00
8 3
CLK Q0 DELAY80NS 1
4 J12 MMUDIS
Q1 DELAY160NS 2
9 5 MMU
VCC AS CLR Q2 DELAY240NS
FLASH SRAM Q3
6
DELAY320NS
VCC 10 1
U4 U9 Q4 DELAY400NS J9 ADDW
11 2
D24 13 12 A0 D24 13 12 A0 Q5 DELAY480NS ADDW
D0 A0 D0 A0 1 12
D25 14 11 A1 D25 14 11 A1 DSA Q6 DELAY560NS
D1 A1 D1 A1 2 13
D26 15 10 A2 D26 15 10 A2 C1 C43 C49 C4 C61 C58 DSB Q7 DELAY640NS 1
D2 A2 D2 A2 J10 WAITIN
D27 17 9 A3 D27 17 9 A3 330p 330p 330p 330p 330p 330p 2
D3 A3 D3 A3 WAITIN
D28 18 8 A4 D28 18 8 A4
D4 A4 D4 A4 VCC VCC 74LS164
D29 19 7 A5 D29 19 7 A5
D5 A5 D5 A5
D30 20 6 A6 D30 20 6 A6
D6 A6 D6 A6 D3
D31 21 5 A7 D31 21 5 A7 VCC R6
D7 A7 D7 A7 U32
27 A8 27 A8

8
A8 A8 555 DRAM CONFIGURATION JUMPERS
26 A9 26 A9 POWER 330
A9 A9
23 A10 23 A10 J1 R54 R53

VCC
A10 A10 WAITIN ADDW WAIT STATES
25 A11 25 A11 C45 C2 C59 C62 C3 C50 1 4K7 10K 4
A11 A11 RST MRESET
4 A12 4 A12 10uF 10uF 10uF 10uF 10uF 10uF 2
A12 A12 6 ON ON 4
28 A13 28 A13 3 THRS U11:C
A13 A13 ON OFF 3
29 A14 29 A14 4 7 3 5 6
A14 A14 DISCH OUTP MRESET OFF ON 3
3 A15 3 A15 VCC
A15 A15 2 OFF OFF 2
2 A16 2 A16 POWER TRIG 74LS04
A16 A16
30 A17 30 A17 5
A17 A17 CRTLV
1 1

GND
A18 A18
A18 A18
C9 C13 C53 C20 C37 C21 C6 C40 C8 C68 C69
22 22
CE CS_ROM CE CS_SRAM RESET1 10uF

1
24 24 1nF 1nF 1nF 1nF 1nF 1nF 1nF 1nF 1nF 1nF
OE RD OE RD 1
31 31
WE WR WE WR 2
CPU/Memory Sheet 1 of 4 Rev 1.0
RESET
29F040 628512 Paul D. Fincato 2012-2014
Welcome back to the nineties!
22 August 2014
B
 CHIP SELECT 1 DSACK0 LOGIC
(/BLKSEL)
GAL16V8
GAL16V8
CSEL1.1
U36 DTACK0.1 U18
A25 1 1
A25 A24 A23 A22 A21 A20 A19 A18 A17 GND I0 CS_ROM I0
A24 2 19 /ROM /RAM /FDC /RTC /SND /KEY DSNET /DSER /DPAR GND 2 19
A16 /CPUSPC NC /CSDRAM /CSVRAM /CSENET /CSROM /CSRAM /BLKSEL VCC I1 O0 CS_SRAM I1 O0
A23 3 18 /DSCOP /DS0 DLA DLB DLC /DA /DB NC NC VCC 3 18
I2 IO1 CS_SRAM CS_FDC I2 IO1
A22 4 17 4 17
I3 IO2 CS_ROM CS_RTC I3 IO2
A21 5 16 DA = ROM * DLA 5 16
BLKSEL = CPUSPC * /A25 * /A24 * /A23 * /A22 * /A21 * A20 * /A19 * /A18 * /A17 * /A16 I4 IO3 CS_ENET CS_SND I4 IO3
A20 6 15 + RAM * DLA 6 15
CSROM = CPUSPC * /A25 * /A24 * /A23 * /A22 * /A21 * /A20 * /A19 I5 IO4 CS_VIDM CS_KEY I5 IO4 DELAY640NS
A19 7 14 + FDC * DLB 7 14
CSRAM = CPUSPC * /A25 * /A24 * /A23 * /A22 * /A21 * /A20 * A19 I6 IO5 CS_DRAM DTACK_NET I6 IO5 DELAY240NS
A18 8 13 + RTC * DLC 8 13
CSENET = CPUSPC * /A25 * /A24 * /A23 * /A22 * /A21 * A20 * /A19 * /A18 * /A17 * A16 I7 IO6 DTACK_SER I7 IO6 DELAY160NS
A17 9 12 + SND * DLC 9 12
CSVRAM = CPUSPC * /A25 * /A24 * /A23 * /A22 * A21 I8 O7 CPUSPC DTACK_PAR I8 O7 DSACK0
A16 11 + KEY * DLC 11
CSDRAM = CPUSPC * A25 I9 DSACK0_COP I9
+ /DSNET
GAL16V8 GAL16V8
CHIP SELECT 1 DB = DSER DSACK0
+ DPAR
+ DSCOP

DS0 = DA + DB

CHIP SELECT 2 DSACK1 / MISC DECODE

U27 U19
1 1
I0 DTACK_VID I0
A15 2 19 2 19
I1 O0 CS_KEYB GAL16V8 DSACK1_COP I1 O0 DSACK1
GAL16V8 A14 3 18 3 18
I2 IO1 CS_IDE DTACK1.1 DTACK_IDE I2 IO1
CSEL2.1 A13 4 17 4 17
I3 IO2 CS_VIDR CS_VIDM I3 IO2
A12 5 16 5 16
I4 IO3 CS_SND /DVID /DCOP DIDE /CSVM /CSVR P24 P25 /WR A0 GND CS_VIDR I4 IO3
/BLKSEL A15 A14 A13 A12 A11 A10 A9 A8 GND A11 6 15 6 15
I5 IO4 CS_RTC /CSSND /BDIR /BC1 /INTKB /CSVID NC NC NC /DS1 VCC P24 I5 IO4 CS_VIDEO
NC /CSSER /CSPAR /CSFDC /CSRTC /CSSND /CSVIDR /CSIDE /CSKEYB VCC A10 7 14 7 14
I6 IO5 CS_FDC P25 I6 IO5 INT_KEYB
A9 8 13 8 13
I7 IO6 CS_PAR DS1 = DVID + DCOP + /DIDE ; DSACK1 WR I7 IO6 BC1
A8 9 12 9 12
I8 O7 CS_SER A0 I8 O7 BDIR
CSSER = BLKSEL * /A15 * /A14 * /A13 * /A12 * /A11 * /A10 * /A9 * /A8 11 11
I9 CSVID = CSVM + CSVR ; VIDEO CS_SND I9
CSPAR = BLKSEL * /A15 * /A14 * /A13 * /A12 * /A11 * /A10 * /A9 * A8
CSFDC = BLKSEL * /A15 * /A14 * /A13 * /A12 * /A11 * /A10 * A9 * /A8 16V8 GAL16V8
INTKB = P24 + P25 ; KEYB INT
CSRTC = BLKSEL * /A15 * /A14 * /A13 * /A12 * /A11 * /A10 * A9 * A8 CHIP SELECT 2 DSACK1/MISC VCC
CSSND = BLKSEL * /A15 * /A14 * /A13 * /A12 * /A11 * A10 * /A9 * /A8
BDIR = CSSND * WR ; SOUND CS
CSVIDR = BLKSEL * /A15 * /A14 * /A13 * /A12 * A11 * /A10 * /A9 * /A8
BC1 = CSSND * A0
CSIDE = BLKSEL * /A15 * /A14 * /A13 * /A12 * A11 * /A10 * /A9 * A8
CSKEYB = BLKSEL * /A15 * /A14 * /A13 * /A12 * /A11 * A10 * /A9 * A8
C54 C38 C72 C35
1nF 1nF 1nF 1nF

MEMORY MAP BYTE DECODE DRAM INTERFACE COPROCESSOR DECODE NOTES:

8422V PROGRAMMING
GAL16V8 GAL16V8 GAL16V8
DEVICE BASE ADDRESS SIZE (BYTES) TI DP8422V Datasheet Ref. Page 9 section 3.2.2
BDECD.1 DRMGLU.1 COPRO.1
HEX DEC HEX
-------------------------------------------------------- Chip select access programming. Reset causes /DISRFSH to assert and FF to assert /ML.
A0 A1 SIZ0 SIZ1 RW NC NC NC NC GND BCLK /CS /AS NC /DTACK NC /ADDW CLK NC GND CLK AS FC2 FC1 FC0 A19 A18 A17 A16 GND
ROM 00000000-0007FFFF 524288 00080000 The first write of CPU on boot MUST provide 8422 programming data with program word on address bus, asserting /CS_DRAM
NC /UUD /UMD /LMD /LLD NC NC NC NC VCC /OE /STERM /DC NC /DB /DA NC /ENCAS /AREQ VCC A15 /CS /CLKD A14 A13 NC NC NC CPU VCC
SRAM 00080000-000FFFFF 524288 00080000 Upon write completion FF will negate /ML and write cycle terminates via normal /STERM. 8422 will be ready for
SERPORT 00100000-001000FF 256 00000100 normal operation.
UUD = RW + /A0 * /A1 AREQ = /AS * /CS * CLK CS = FC2 * FC1 * FC0
PARPORT 00100100-001001FF 256 00000100
+ /AREQ * /CS * /CLK * /A19 * /A18 * A17 * /A16
FDC 00100200-001002FF 256 00000100
UMD = RW * /A15 * /A14 * A13
RTC 00100300-001003FF 256 00000100
+ A0 * /A1 ENCAS = /AREQ * /CS * DC * /CLK
SOUND 00100400-001004FF 256 00000100
+ /A1 * /SIZ0 + /AREQ * /CS * /CLK
KEYBD 00100500-001005FF 256 00000100
+ /A1 * SIZ1 + FC2 * FC1 * FC0
--- 00100600-001009FF
DC = /AS * /CS * /DB * /CLK * /A19 * /A18 * A17 * /A16
VIDREG* 00100A00-00100AFF 256 00000100
LMD = RW + /AS * /CS * /DC * CLK * /A15 * /A14 * A13
IDE* 00100B00-00100BFF 256 00000100
+ /A0 * A1 * /AS
--- 00100C00-0010FFFF
+ /A1 * /SIZ0 * /SIZ1 STERM = /AS * /CS * /DA * DB * /CLK * /ADDW
ETHNET 00110000-0011FFFF 65536 00010000
+ /A1 * SIZ0 * SIZ1 + /AS * /CS * /DTACK * DB * /CLK * ADDW + FC2 * FC1 * FC0
--- 00120000-001FFFFF
+ /A1 * A0 * /SIZ0 + /STERM * CLK * /A19 * /A18 * A17 * /A16
VIDRAM* 00200000-003FFFFF 2097152 00200000
* /A15 * /A14 * A13
--- 00400000-01FFFFFF
LLD = RW DA.R = /AREQ * /CS * /DTACK * DB * /ADDW * /CLKD
DRAM# 02000000-03FFFFFF 33554432 02000000
+ A0 * A1
--- 04000000-FFFFFFFF
+ A0 * SIZ0 * SIZ1 DB.R = /AREQ * /CS * /DTACK * /DA * DB * /ADDW CLKD = CLK
+ /SIZ0 * /SIZ1 + /AREQ * /CS * /DTACK * DB * ADDW
*16 bit device / #32 bit device
+ A1 * SIZ1 ; PDF - added for peripheral chipselect1 logic
CPU = FC2 * FC1 * FC0
IDE is base address for drive 0
Drive 1 is base + 128
DESCRIPTION: DESCRIPTION:
DESCRIPTION:
Byte select logic on 32 bit bus DP8422V DRAM Controller Interface logic
MC68030 User's manual section 12-13 National Application Note AN-537 MC68882 chip select logic
Figure 12-7 "Interfacing the DP8420A/21A/22A to the 68030 Microprocessor" MC68030 User's manual section 12-8
Page 3 Figure 12-4

PDF -
converted from National PLAN format
removed EXST from equations (External STERM)

Glue Logic Sheet 2 of 4 Rev 1.0

Paul D. Fincato 2012-2014

Welcome back to the nineties!
22 August 2014
B
 VCC

J8:A
R21 STACKED-CONN-D9M DISK
PARALLEL J6 33K SERIAL
1
U3 1 U8 U15 J2
PPSTROBE 14 6
BD31 3 4 2 BD31 21 1 2
D7 PA0 15 D7 33 11 14 2 MRESET
2 5 3 PPERROR 25 TXDA T1IN T1OUT 3 4

DATA BYTES SWAPPED

BD30 BD30 BD31 BD16

BUFFERED DATA
D6 PA1 16 D6 32 10 7 7
BD29 1 6 4 PPINIT BD29 20 OP0/CTSA T2IN T2OUT BD30 5 6 BD17
D5 PA2 17 D5 35 12 13 3

FOR BIG ENDIAN

BD28 52 7 5 PPSEL BD28 26 RXDA R1OUT R1IN BD29 7 8 BD18
D4 PA3 18 D4 8 9 8 8
BD27 51 9 6 BD27 19 IP0/RTSA R2OUT R2IN BD28 9 10 BD19
D3 PA4 19 D3 4
BD26 50 10 7 BD26 27 J4 C27 BD27 11 12 BD20
D2 PA5 20 D2 VS+ C1+ 9
BD25 49 11 8 BD25 18 31 1 2 1 10u BD26 13 14 BD21
D1 PA6 21 D1 OP2 C19 VS- C1- 5
BD24 48 12 9 BD24 28 15 2 6 3 C17 BD25 15 16 BD22
D0 PA7 22 D0 OP3 C2+
10 30 3 4 10u BD24 17 18 BD23
U17 PPACK 23 OP4 C15 C2-
BA4 28 18 11 BA3 7 16 4 5 19 20
D31 18 2 BD31 RS5 PB0 24 RS4 OP5 10u 10u J8:B
B0 A0 BA3 29 19 12 BA2 6 29 5 MAX232 STACKED-CONN-D9M 21 22
D30 17 3 BD30 RS4 PB1 25 RS3 OP6
B1 A1 BA2 30 22 13 BA1 4 17 6 23 24
16 4 RS3 PB2 PPSEL RS2 OP7 WR
UNBUFFERED

D29 BD29
B2 A2 BA1 31 23 1 BA0 2 10 25 26
15 5 RS2 PB3 RS1 U14 RD
DATA

D28 BD28
B3 A3 BA0 32 24 2 CONN-SIL6 15 27 28
D27 14 6 BD27 RS1 PB4 CONN-D25F 9 (INVERSION IN GAL) DTACK_IDE
B4 A4 25 3 R/W R/W 13 11 14 11 29 30
D26 13 7 BD26 PB5 38 TXDB T1IN T1OUT
B5 A5 47 26 4 J5 MRESET RESET 14 10 7 16 10 11 31 32
D25 12 8 BD25 R/W R/W PB6 10 OP1/CTSB T2IN T2OUT IRQ_IDE
B6 A6 43 27 5 CONN-SIL8 DTACK_SER DTACK 11 12 13 12 BA1 33 34
D24 11 9 BD24 MRESET RESET PB7 39 RXDB R1OUT R1IN U11:E
B7 A7 46 6 CS_SER CS 5 9 8 17 BA0 35 36 BA2
DTACK_PAR DTACK IP1/RTSB R2OUT R2IN 74LS04 R24
45 34 7 VCC 13 10k 37 38
1 CS_PAR CS PC0 C18 18
R/W AB/BA 35 8 VS+ C1+ 39 40
19 PC1 2 1 10u
CPUSPC CE 14 36 41 C25 VS- C1- 14
PPACK H1 PC2/TIN IACK 6 3 C16
15 37 24 J7 C2+ IDE 40 PIN
74LS245 PPSTROBE H2 PC3/TOUT IRQ_SER INT C14 4 10u
16 38 40 1 C2- VCC
PPERROR H3 PC4/DMAREQ IP2 10u 10u 5
17 39 3.6864M 3 2
U10 PPINIT H4 PC5/PIRQ IRQ_PAR IP3 MAX232 D2 R7
40 37 43 3
D23 18 2 BD23 PC6/PIACK X2 IP4
B0 A0 44 41 36 42 4
D22 17 3 BD22 8MHZ CLK PC7/TIACK X1/CLK IP5 330
B1 A1 X1 IDE ACTIVITY
16 4
UNBUFFERED

D21 BD21
B2 A2 TS68230FN TS68681 CONN-SIL4
D20 15 5 BD20 C11 C12
B3 A3
DATA

D19 14 6 BD19 10p 10p

B4 A4 J17:A (IDE0 BASE)
D18 13 7 BD18 STACKED-CONN-D9M
B5 A5
D17 12
B6 A6
8 BD17 FLOPPY SOUND U5:B
D16 11 9 BD16 U2 J3 U28 1
B7 A7 BA7 14 12
BD31 14 39 2 1 BD31 30 FB19 6 A Y0
D7 RCW/RPM D7 13 11 (IDE1 BASE+128)
1 BD30 13 4 3 BD30 31 FB20 2 B Y1
R/W AB/BA D6 D6 10
19 BD29 12 36 6 5 BD29 32 21 FB17 7 Y2
CPUSPC CE D5 MO1/DS3 D5 IOA0 VCC 15 9
BD28 11 43 8 7 BD28 33 20 FB18 3 CS_IDE E Y3
D4 IDX D4 IOA1
74LS245 BD27 10 37 10 9 BD27 34 19 FB15 8
D3 MO2/DS4 D3 IOA2 74LS139
BD26 9 33 12 11 BD26 35 18 FB16 4
D2 DS1 D2 IOA3
BD25 8 35 14 13 BD25 36 17 FB14 9
D1 DS2 D1 IOA4
BD24 7 16 15 BD24 37 16 FB13 5
D0 D0 IOA5
VCC 31 18 17 15 FB12 CLOCK
DIRC VCC IOA6
32 20 19 14
5
STEP
30 22 21
IOA7 Atari Compatible Joysticks J17:B STACKED-CONN-D9M U7
DACK WD BD27 11
U5:A 6 29 24 23 25 13 10 D3
TC WE A8 IOB0 BD26 12
BA1 2 4 (FDC BASE) 3 42 26 25 28 12 FB11 15 D2
A Y0 CS TR00 BC2 IOB1 BD25 13
BA2 3 5 (FDC BASE+2) 18 41 28 27 24 11 FB9 11 D1
B Y1 LDOR WP A9 IOB2 BD24 14
6 (FDC BASE+4) 19 21 30 29 10 FB10 16 D0
Y2 LDCR RDD IOB3 VCC
1 7 BA0 4 28 32 31 9 FB7 12 BA3 7
CS_FDC E Y3 A0 HS IOB4 A3
2 40 34 33 23 8 FB8 17 BA2 6
WR WR DCHG MRESET RESET IOB5 A2
74LS139 1 38 7 FB4 13 BA1 5
RD RD HDL IOB6 A1
27 FLOPPY 34 PIN 27 6 FB6 18 VCC BA0 4
20 PCVAL BDIR BDIR IOB7 A0
MRESET RESET (GLUE GAL) 29 FB3 14
BC1 BC1
FB5 3
ALE
15 26 8
DMA XT1 16MHZ 39 RD RD
U11:F 25 VCC TEST1 10
9
8
7
6
5
4
3
2

XT1 38 26 WR WR
8 9 16 OUTC TEST2 15
IRQ_FDC IRQ 3 MRESET CS1
24 23 OUTB 2
DRV XT2 4 22 CS
74LS04 17 22 OUTA CLK 1MHZ
DCHGEN XT2 1 1 18
STD.P VIN
37C65CLJP RN1 AY-3-8910 C52
R37
150 10K 10uF RTC72421
J15
2
U6
3
KEYBOARD/MOUSE 1 1
VCC
VCCO
U26 R36
RV2 RV1 C51 STEREO JACK 6 8
BD31 19 10K C48 C41 10uF CEO VCCI
D7 27 5K 5K
BD30 18 P10 270p 270p 5 B1
D6 R35 R41 R38 R39 R40 CS_RTC CE
BD29 17 U25:F 74LS06 1K 1K 1K 10K 10K
BD28 16
D5
J13 Keyboard VBAT1
2
D4 38 9 8 1 3 1 2
BD27 15 P27 DATA TOL
D3 VCC 2 7
BD26 14 NC1 6 5 VBAT2 CR2032
D2 6
BD25 13 NC2

4
3
2
1
D1 U25:D 74LS06 4
BD24 12 VCC 4 3 DS1210
D0 37 13 12 5
P26 CLK 1-2 = MIX B and A
BA0 9 3 2 1 J16
A0 GND 3-4 = MIX B and C
1
35 T0 6 PIN MINI DIN Channel Select 16MHZ

10
11
P24 P24 28

8
9
(GLUE GAL) 36 P11 VCC
P25 P25
U13
U25:E 74LS06 Mouse
6 J14 1 12
CS_KEYB CS 23 11 10 1 14 CKB QA 8MHZ
U31 10 P22 DATA 14 9
WR WR VCC 2 U25:B X5 CKA QB 4MHZ
A0 18 2 BA0 8 NC1 6 5 VCC 8
B0 A0 RD RD 6 16MHZ QC 2MHZ
UNBUFFERED

NC2 74LS06
A1 17 3 BA1 11
ADDRESS

B1 A1 U25:A 74LS06 4 QD 1MHZ

A2 16 4 BA2 VCC 4 3 3 4 2

4
5
6
7
B2 A2 4 24 1 2 5 R0(1)
A3 15 5 BA3 MRESET RESET P23 CLK 3
B3 A3 3 2 1 R0(2)
A4 14 6 BA4 GND
B4 A4 7
13 7 TL_EA 6 PIN MINI DIN C22 C30 C47 C7 C26 C42 C70 C46 C60 C63 C10 C73 74LS93
B5 A5 39 5 6 1nF 1nF 1nF 1nF 1nF 1nF 1nF 1nF 1nF 1nF 1nF 1nF
BUFFERED ADDRESS

12 8 T1
B6 A6
11 9 VCC
B7 A7 U25:C
5
2 TH_SS 74LS06
1 XTAL1 25
AB/BA 3 TH_PROG
19 8MHZ XTAL2 26
CPUSPC CE TH_SSPP
74LS245 VT82C42

Peripherals Sheet 3 of 4 Rev 1.0

Paul D. Fincato 2012-2014

Welcome back to the nineties!
22 August 2014
B
 VIDEO ETHERNET

VCC ETH_AVCC

U37

47
57
S1D13505 VCC
R43 R45 R48 U38 U22
HR911105A
10k 10k 10k

AVCC
AVCC
P1
4 29 R30
CS_VIDEO CS OE
5 BA0 5
CS_VIDR M/R A0
1K

10
8 53 13 BA1 7 R32

9
SIZ0 WE0 WE WE A1 C34
9 54 14 BA2 8
DS WE1 RAS RAS A2 10nF
10 51 31 BA3 9 58 200 6
R/W RD/WR LCAS LCAS A3 TPIN- RD-
7 52 30 BA4 10 5
SIZ1 RD UCAS UCAS A4 RDC
11 59 3
A5 TPIN+ RD+
6 61 17 VCC 12
AS BS MA0 A0 A6

INTERNAL DECODE TO IO BASE 0300H

15 63 18 13 C33
DSACK1_VID WAIT MA1 A1 A7 10nF
65 19 15 46 2
MA2 A2 A8 TPOUT- TD-
11 67 20 16 4
MRESET RESET MA3 A3 A9 TDC
66 23 18 45 1
MA4 A4 A10 TPOUT+ TD+
A0 3 64 24 19
AB0 MA5 A5 A11
A1 2 62 25 20 7
AB1 MA6 A6 A12 NC
A2 1 60 26 21 8/15/16
AB2 MA7 A7 A13 GND
A3 128 58 27 22 VCC
AB3 MA8 A8 A14
A4 127 56 28 23 VCC
AB4 MA9 A9 A15

12

11
A5 126 59 24 65
AB5 MA10 A16 JP R29
A6 125 57 25 RX LED
AB6 MA11 A17
A7 124 26 1K
AB7 A18 77
A8 123 35 2 27 BD7
AB8 MD0 DQ1 A19
A9 122 37 3
AB9 MD1 DQ2
A10 121 39 4 R31
AB10 MD2 DQ3
A11 120 41 5 BD24 36 10K
AB11 MD3 DQ4 D0
A12 119 43 7 BD25 37
AB12 MD4 DQ5 D1
A13 118 45 8 BD26 38
AB13 MD5 DQ6 D2 64
A14 117 47 9 BD27 39 AUI
AB14 MD6 DQ7 D3
A15 116 49 10 BD28 40 VCC
AB15 MD7 DQ8 D4
A16 115 48 33 BD29 41 TX LED 1K
AB16 MD8 DQ9 D5
A17 114 46 34 BD30 42 60 D4
AB17 MD9 DQ10 D6 LEDBNC R33
A18 113 44 35 BD31 43 63
AB18 MD10 DQ11 D7 LED2
A19 112 42 36 95 62
AB19 MD11 DQ12 D8 LED1
A20 111 40 38 94 61
AB20 MD12 DQ13 D9 LED0
38 39 93
MD13 DQ14 D10
D16 31 36 40 92 4 1 2
DB0 MD14 DQ15 D11 INT0 IRQ_NET
D17 30 34 41 91 3
ENDIANESS CONTROLLED BY MDx VALUES

DB1 MD15 DQ16 D12 INT1

D18 29 VCC 90 2 74LS04
DB2 D13 INT2
D19 28 88 1 U11:A
DB3 D14 INT3
D20 27 71 AS4C1M16E5 87 100
DB4 SUSPEND D15 INT4
D21 26 70 99
DB5 TESTEN VCC INT5
D22 25 98
DB6 INT6
D23 24 J18 97
DB7 FB23 32 INT7
D24 23 100 RED 1 SMEMWB
DB8 RED 31
D25 22 9 SMEMRB C29
DB9 FB24 10p
D26 21 103 GREEN 2 35
DB10 GREEN (INVERSION IN GAL) DTACK_NET IOCHRDY 51
D27 20 10 29 X2
DB11 FB25 RD IORB
D28 19 105 BLUE 3 30 R28
DB12 BLUE WR IOWB
D29 18 11 33 1M 20MHZ
DB13 R52 MRESET RSTDRV
D30 17 108 4 X2
DB14 VSYNC 34
D31 16 12 CS_NET AEN
DB15 39 R51 96 50
107 5 IOCS16B X1
DACVSS1

DACVDD1
DACVDD2

HSYNC FB26

AGND
AGND
DACVSS

DACVDD

13 39 13 C32
BUSCLK
69 101 6 R34 10p
CLKI IREF FB27
27K
10
11

VCC 14
8
9

RTL8019AS

52
44
R46 R49 R50 7
VID_AVCC
106
98

99
102
104

150 150 150 15

14 40 MHz X4 Q1 8
R44
2N2222A
2.5k CONN-D15F ETH_AGND
VID_AGND
VID_AGND
4
5
6
7

R47 R42
1k 140
S1D13505 CONFIGURATION

WAIT# - WAIT HIGH

PRIMARY BUS INTF

SUSPEND# INPUT
SYMMETRIC 1MB

SYMMETRIC 1MB

BUSCLK 1:1 CLK

GPO POLARITY
VID_AGND

MC68K BUS2

MC68K BUS2

MC68K BUS2
16 BIT HOST

BIG ENDIAN
VID_AVCC
VCC VCC ETH_AVCC MD 0 1 2 3 4 5 6 7 8 9 10 11 12
VCC VID_AVCC
VALUE 0 0 1 0 0 1 1 0 X 0 0 0 0
D6 D10 D8
FB2 C28
FB22 1N914 1N914 1N914 C36 0 = INTERNAL PULLDOWN
C31 C39
C5 C67 C65 C56 C66 C64 C55 C24 C57 C23 C71 1nF 1uF
RED BLUE GREEN 1nF 1nF
1nF 1uF 1nF 1nF 1nF 1nF 1nF 1nF 1nF 1nF 1nF
D5 D9 D7
FB1
FB21 1N914 1N914 1N914
ETH_AGND
VID_AGND

VID_AGND Video/Ethernet Sheet 4 of 4 Rev 1.0

Paul D. Fincato 2012-2014

Welcome back to the nineties!
22 August 2014
B