Digital Logic Design

Chapter 3: Combinational Logic Fall

circuits 2022

Huynh Kha Tu, PhD.

hktu@hcmiu.edu.vn
O1.610, A2.708
 SCSE

Design
Step 1: Consider the statements of the problem.
Step 2:Define the inputs and outputs:
o The inputs are considered the variables.
o The outputs are considered functions
Step 3: Draw the block diagram of the circuit
Step 4: Write the Truth Table to express the relationship between the
inputs and outputs so that the requirements of the problem are met.
 SCSE

Design
The Truth Table consists of 2n binary combinations for n inputs. The
outputs’ binary values are defined based on the statements of
problem.
+ If the inputs’ binary combinations are valid: The output will be
“0” or “1”.
+ If the inputs’ binary combinations are not mentioned (or do not
happen): The output is considered “don’t care” case.
 SCSE

Design
Step 5: Define the Boolean functions simplified for the output
functions . The output’s Boolean functions are defined from the
Truth Table by algebraic methods or K-map.
Step 6: Draw the logic diagrams.
 SCSE

Example
Given a function F with 4 inputs. The function F=1 if the number of
inputs “1” is greater than or equal to the number of inputs “0”.
Otherwise, F=0.
a. Represent the function F in K-map.
b. Simplify the function F and draw the circuit using only NAND gates.
 SCSE

Example
Given a combinational circuit having the operation as in the table.
E X1 X0 Y0 Y1 Y2 Y3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

a. Design this circuit using logic gates.

b. Using the combinational circuit designed in question a (drawn in
the Block diagram) and logic gates to implement the Boolean
function F(A,B,C) = (4,6)
 SCSE

Example
We can use common MSI chips such as:
o Decoder/Encoder.
o Multiplexer- MUX.
o Demultiplexer- DEMUX.
o Adder, ...
to implement a combinational logic circuit.
 SCSE

Combinational logic circuits

Decoder
The most common decoder is binary decoder: has n inputs, 2n
outputs, enable inputs.
When all enable inputs are active, decoder starts operation: Only one
of 2n outputs are active at one time.
o The active output is the output whose index is defined from
o the inputs’ binary combinations.
 SCSE

Example
Consider the decoder 2 to 4, high active outputs.

Design
 SCSE

Example
Circuit diagram
 SCSE

Example
Consider the decoder 2 to 4, low active outputs.
 SCSE

Example
Circuit diagram
 SCSE

Example
Consider the decoder 2 to 4, low active outputs, 1 low active enable input.
 SCSE

Example
Circuit diagram
 SCSE

Combinational logic circuits

74LS139 consists 2 decoders 2 to 4
 SCSE

Combinational logic circuits

74LS138: decoder 3 to 8
 SCSE

Combinational logic circuits

74LS138: decoder 3 to 8
 SCSE

Combinational logic circuits

74LS138: decoder 3 to 8
Two decoders n to 2n can be connected together to create a decoder (n+1) to 2n+1.
 SCSE

Combinational logic circuits

o Each output of the decoder n to 2n (high active output) is a n-
variable minterm.
o If the output is low active, each output is a maxterm
o A decoder n to 2n connecting to logic gates can be used to
implement one or n-variable Boolean function.
 SCSE

Combinational logic circuits

Example:
Using 74LS138 and logic gates to implement the following functions
 SCSE

Combinational logic circuits

 SCSE

Combinational logic circuits

 SCSE

Combinational logic circuits

Example:
Using 74LS138 and logic gates to implement the following functions
 SCSE

Combinational logic circuits

Encoder
Comparing with decoder, it operates reversely .
o Has 2n (or less) inputs and n outputs.
o Among 2n inputs, there is only one active input at one time. The
index of the active input defines the output’s binary combinations.
 SCSE

Example
Consider the encoder 4 to 2.
 SCSE

Example
Circuit diagram
 SCSE

Combinational logic circuits

Priority encoder: is the encoder having the priority property. In case

of having 2 or more inputs are active at the same time, the input
having the most priority will impact on the output.
 SCSE

Example
Priority encoder 4 to 2: priority order is increased from x3 to x0.
 SCSE

Example
Circuit diagram
 SCSE

Combinational logic circuits

74LS148: priority encoder 8 to 3
 SCSE

Combinational logic circuits

74LS148: priority encoder 8 to 3