UNIT-III BASIC PROCESSING UNIT AND PIPELINIG

PART A
1. Draw the four stages in the pipelining
Time
Clock cycle 1 2 3 4 5 6 7

Instruction

I1 F1 D1 E1 W1

I2 F2 D2 E2 W2

I3 F3 D3 E3 W3

I4 F4 D4 E4 W4

(a) Instruction execution divided into four steps

Interstage buffers

D : Decode
F : Fetch instruction E: Execute W : Write
instruction and fetch operation results
operands
B1 B2 B3

(b) Hardware organization

Figure 8.2. A 4-stage pipeline.

2. Compare Instruction Pipelining and hazard in pipelining

Any condition that causes a pipeline to stall is called a hazard.
Data hazard – any condition in which either the source or the destination operands of an
instruction are not available at the time expected in the pipeline. So some operation has to
be delayed, and the pipeline stalls.
Instruction (control) hazard – a delay in the availability of an instruction causes the
pipeline to stall.
Structural hazard – the situation when two instructions require the use of a given
hardware resource at the same time.

3. Write a note on Instruction Hazard

 The instruction fetch unit of the CPU is responsible for providing a stream of instructions
to the execution unit. The instructions fetched by the fetch unit are in consecutive
memory locations and they are executed.
However the problem arises when one of the instructions is a branching instruction to
some other memory location. Thus all the instruction fetched in the pipeline from
consecutive memory locations are invalid now and need to removed(also called flushing
of the pipeline).This induces a stall till new instructions are again fetched from the
memory address specified in the branch instruction. Thus the time lost as a result of this
is called a branch penalty. Often dedicated hardware is incorporated in the fetch unit to
identify branch instructions and compute branch addresses as soon as possible and
reducing the resulting delay as a result.

4. Define Hardwired Control

To execute instructions, the processor must have some means of generating the control
signals needed in the proper sequence. hardwired control is a technique used to resolve
this issue. The Hardwired Control organization involves the control logic to be
implemented with gates, flip-flops, decoders, and other digital circuits.

5. What is Pipelining
Pipelining is widely used in modern processors. Pipelining improves system
performance in terms of throughput. Pipelined organization requires sophisticated
compilation techniques.

6. What do you mean by Micro programmed Control?

The control signals associated with operations are stored in special memory units
inaccessible by the programmer as Control Words. Control signals are generated by a
program are similar to machine language programs. Micro-programmed control unit is
slower in speed because of the time it takes to fetch microinstructions from the control
memory.

7. What is Program counter

The processor keeps track of the address of the memory location containing the next
instruction to be fetched using the program counter (PC) or Instruction Pointer (IP)

8. What is the prupose of Instruction Register

Instruction register, IR is another key register in the processor, which is used to hold the
op-codes before decoding.

9. Differentiate between the static and dynamic branch prediction.

Static Branch Prediction in general is a prediction that uses information that was
gathered before the execution of the program. ... Dynamic Branch Prediction on the
other hand uses information about taken or not taken branches gathered at run-time
to predict the outcome of a branch.
10. Define Superscalar operation
Superscalar Processors are capable of achieving an instruction execution throughput of
more than one instruction per cycle. The operations performed by the superscalar
processors are called as superscalar operation
PART B
1. Explain basic operation of a Four Stage pipelining with a neat diagram
2. i) Discuss the various hazards that might arise in a pipeline
ii) Explain the Issues affecting pipeline performance
3. What is a Data hazard? How do you overcome it? And discuss its side effects.
4. i) Describe the methods for dealing with the branch hazards .
ii) Discuss in detail about hazards due to unconditional branching
5. What are the hazards of conditional branches in pipelines? How it can be resolved?

UNIT-IV MEMORY SYATEM

PART A
1. State the advantages of Cache Memory
Cache memory is faster than main memory.
It consumes less access time as compared to main memory.
It stores the program that can be executed within a short period of time.
It stores data for temporary use.
2. Distinguish between static RAM and dynamic RAM.
Static RAM uses a completely different technology. ... So static RAM is fast and
expensive, and dynamic RAM is less expensive and slower. Therefore static RAM is
used to create the CPU's speed-sensitive cache, while dynamic RAM forms the larger
system RAM space

3. Give the features of a ROM.

A ROM chip is used in the start-up process of a computer.
A ROM is a non-volatile memory.
ROM allows the user to read the information but can not change them.
ROM stores all the applications needed for the initial boot of the computer.
Long term memory.

4. Differntiate RAM and ROM

RAM, which stands for random access memory, and ROM, which stands for read-only
memory, are both present in your computer. RAM is volatile memory that temporarily
stores the files you are working on. ROM is non-volatile memory that permanently stores
instructions for your computer.
5. What are the various types of Memory System

Primary Memory and Secondary memory are the types of Memory System. Primary
memory is also called internal memory whereas Secondary memory is also known as a
Backup memory or Auxiliary memory. Primary memory data is directly accessed by the
processing unit whereas Secondary memory data cannot be accessed directly by the
processor.

6. What is double data rate SDRAMs?

DDR SDRAM means that this type of SDRAM fetches data on both the leading edge and
the falling edge of the clock signal that regulates it, thus the name “Double Data
Rate”. Double Data Rate SDRAMs are most efficiently used in applications where block
transfers are required

7. Define locality of reference. What are its types?

Analysis of programs indicates that many instructions in localized areas of a program are
executed repeatedly during some period of time, while the others are accessed relatively
less frequently.
a. These instructions may be the ones in a loop, nested loop or few procedures
calling each other repeatedly.
b. This is called “locality of reference”.
8. List the mapping techniques.
c. Direct mapping
d. Associative mapping
c. Set-associative mapping.
9. Write a note on interleaved memory?
 Divides the memory system into a number of memory modules. Each module has its
own address buffer register (ABR) and data buffer register (DBR).
 Arranges addressing so that successive words in the address space are placed in different
modules.
 When requests for memory access involve consecutive addresses, the access will be to
different modules.
 Since parallel access to these modules is possible, the average rate of fetching words
from the Main Memory can be increased.

10. Define Size and Cost

 A big challenge in the design of a computer system is to provide a sufficiently large
memory, with a reasonable speed at an affordable cost.
 Static RAM:

 Very fast, but expensive, because a basic SRAM cell has a complex circuit
making it impossible to pack a large number of cells onto a single chip.
 Dynamic RAM:

 Simpler basic cell circuit, hence are much less expensive, but significantly slower
than SRAMs.
 Magnetic disks:

 Storage provided by DRAMs is higher than SRAMs, but is still less than what is
necessary.
 Secondary storage such as magnetic disks provide a large amount
of storage, but is much slower than DRAMs.
PART-B
1. (i) Analyze the memory hierarchy in terms of speed, size and Cost.
ii) Draw the block diagram of Virtual memory and explain.
2. Explain the need for cache memory and Discuss the various mapping techniques used in
cache memories.
3. Write about mapping function? What are the ways the cache can be mapped?
4. Illustreate the different types of mapping functions in cache memory
5. What is virtual memory? Explain how the logical address is translated into physical
address in the virtual memory system with a neat diagram.