DESIGN OF MULTI-PHASE DC-DC
CONVERTER WITH AVERAGED CURRENT
SHARING CONTROL
GUO Guoyoiig
(Institute of Microelectronics, Tsinghua University, Beijing China 100084)
Email: gungy99@mnils.tsinghua.edu.cn
Telephone & Fax: 010-82641333
Abstract: A novel multi-phase PWM DC-DC
couverter is desigued, in order to solve the
problem of meeting tlie power supply requirements
of the new geueratioi~ microprocessor which
requires 40-100A currents, lower voltage and
better current transient response. In multi-
phase converter. how to balance tlie currents in
each phase is most important, arid tlie averaged
curreut sharing is a11 effective way. Tlie
multi-phase couverter, by distributing the power
and load ciirreiit results iu siualler and lower cost
trausistor with fewer input and output capacitors. It
meets tlie specifications of Intel's VRM9.0 design
guideline for the power supply of high-
perfonname Pentimii IV ceutral processing units.
1. I n t r o d u c t i o n
Multi-phase DC-DC converter provides several
advantages over a single phase power supply. The
merits of multi-phase converter include expandability
of output power. high reliability. luglier load
frequency and smaller output voltage ripple.
Multi-phase DC-DC converters require an explicit
current slnring ineclianisni to ensure even distribution
of current and thennal stresses among the modules
and to prevent operation of one or more modules in a
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SHI Bingxue
. .
current limiting mode [I1. Without a current sharing
mechanism even small imbalances in modules'
output voltages can cause the output currents to be
significantly different t21. Tlie averaged current
sharing is a good selection. In averaged current
sharing, each c l m e l current changes along with the
averaged current.of all channel currents. In tlus:paper,
a novel multi-phase PWM DC- DC controller for
advauced inicroprocessor is designed, by distributing
the power and load current. wluch results in smaller
and lower cost transistors. These reductions accrue
from the highereffective conversion frequency with
ripple current bf higher frequincr . .
due to the $lase
interleaving process of this topology. Outstiding
features of tlus controller IC include programming
VID,codes from the microprocessor
. . that ranges.from
1.1-1.85Vwithastepof25mV.
2.Voltrge loop, and , a v e r a g e d current
. .
sharing control
The diagram of voltage loop and averaged
c u n p . n t ' s l ~ n gcontrol is 'shown in Figurel. Both
voltage' and current loop are used to precisely
regulate voltage and tightIy control output cumnt 11.
and 12. of the two power channels. The voltage loop
comprises the E k r Atnplifier, Comparators,' and
Power Stages. ' n i e averaged current sharing scheme
applies hvo identical modules.
.. with individual
 ' . ,
.. .
. ,

, . ,. ,:.. . ,

, ,, :

..
~ . ...
, ,
. . ,.,' . . .

Figure 1. Diagram o f . v o l t a g e loop and averaged

current sharing
.. .
voltage ~dops. In the absence'of current sharing contrdl any
. . . I. .
small imbalance in parameters' associated 'with the
... . .
The 'mechanism of boltage loop is s i ~ n p l e ' [ ~ ~ [voltage
~ ~ . ' loop gain of individual conve~ters~willcause
For the meraged current sharing control. the large differences 'in conveher' 'output c k n t . '
'

averaged current of 11. and I2 is dedicated to be the Averaged current sharing controi is embedded in the
reference current for current sharing 'loops.'Voitage voltage loop. It forces the multi-phase converters to
error signals of the modules are adjusted accordingly share current by adjusting the effective voltage
to correct the imbalances of the load currents. reference signals 'to tlie voltage loop. The 'current
. ,. , . . .
I. . .
share bus is forced tlmugh the current~sekingblock
> ,. ., . ,
. . . . I '

... , , . . I . . ' . .
I .

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 to a voltage proportional to the output current of tlie
ayeraged current. Wlule tlie effective voltage
refcrcnce signal of the averaged current is unaffected
by tlie cnrrent share circuit. and the effective voltage
reference signal of the each niodule are adjusted so as
to increase their output current to a magnitude almost
equaling the a\:eraged corrent.
3. Schematic structure and simulations of
the regulator
The diagram of tlie proposed multi-phase
DC-DC converter is shown in Figure 2. where the
part inside tlie dashed line block is the controller.
while the part ontside the dashed line block is its
peripheral circuit and driven. When input voltage
J.;, (12V) and J';, (jV)go above tlie'thresholds, the
powerai reset circuit outputs a startup signal. which
makes the ?stem begin to work. The difference
between VDACOUT and tlie feedback of the actual
output voltage at FB is amplified by the error
amplifier. then the resull is applied to the block of
current sensing and processing. and is coinpared with
the difference between the averaged current and each
channel current. The output signals of the current
processing block are compared with the interleaved
saw-tooth. and the results are the interleaved PWM
signals. In order IO protect the microprocessor. the
?stem provides the Cunctions of the over-current.
over-voltage. under-voltage and soft-start protection.
-. 1,..
1'
. - _.
,j XI: '* : :e :I
Figure 3. The output voltage and the Vss
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The total circuit is simulated with BiCMOS
Hspice process parameter. Figure 3 sl~oows the
simulated output voltage compared with the soft-start
voltage Vss It can be seen that during the startup
process. the output voltage is rising almost linearly
from OV to the eqected voltage. aiid there is no big
over-shoots.
The most important difference between
single-phase and multi-phase power supply is the
current balancing circuit. With tlie current balancing,
the system can operate at higher load current and
higher frequency. Figure 4 is tlie simulation result of
the ,current balancing. The currents of the four
channels are balanced very wrell. and frequency of the
output load current is four times of the frequency of
the channel current.
4. Conclusion
A novel multi-phase converter for advanced
microprocessor is designed and simulated with
BiCEdOS Hspice process paraneter. As compared
with the conventional single-phase converter for PC
motherboard. this power converter can meet the
denwnds of lugher current, lower voltage and better
transient current response. Based on the averaged
current sharing. the channel currents of each module
are regulated to be balanceable. The simulation result
can meet the specifications of Intel's VRM9.0 design
guidelines for Pentium IV CPUs ['I.
Acknowledgments: The autlioors gratefully
acknowledge tlie support froin Shanghai
Tsinghuaclup Cvstal Microelectronics Co. Ltd.
;.~
nt
524
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25 -

20 -

II
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.415n 2.42m 2.425m 2.43m 2.435m

Figure 4. Cumnt balancing of four modules

References
1. Zllou. X. W.. Wog. P.. Lee. E, Investigation
of candidate VRM topologies for future
ndcropmcesson. IEEE Transactions on Power
Electronics. 2000. pp. 1172- 1182.
2. Zliou. X. W.. Xu. P.. Lee. E. A novel current
sllaring control technique for low voltage high
current voltage regulator inodule applications.
IEEE Tonsactions on Power Electronics. 2000.
pp.1153- 1162.
3. Chen. L.. Slu. B. X.. Lu, C.. A hybrid I-in-l
DC-DC controller chip for a PC main-board.
International Journal of Electronics. 88,
200 I .pp.789-799.

4. CHEM hi, SHI Bingwe, DAI Tiejun, e t al.

Realizat.ion of pi11se-wi dt.h wodulat.ion
c h i p f o r iigli-efficiency high-precision
srvitching regulator [.I]. J Tsinghua Univ,
1999, 39(1) : 38-41. (in Chinese)

4. VRM9.0 DC-DC Converter Design Guidelines.

Intel Corp.. 2000.

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