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An Efficient Hardware-based Human Body Communication

Transceiver Architecture for WBAN Applications

Sujaya BL , S.B. BhanuPrashanth

PII: S2666-285X(21)00098-4
DOI: https://doi.org/10.1016/j.gltp.2021.08.070
Reference: GLTP 94

To appear in: Global Transitions Proceedings

Received date: 9 June 2021

Accepted date: 26 June 2021

Please cite this article as: Sujaya BL , S.B. BhanuPrashanth , An Efficient Hardware-based Human
Body Communication Transceiver Architecture for WBAN Applications, Global Transitions Proceedings
(2021), doi: https://doi.org/10.1016/j.gltp.2021.08.070

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An Efficient Hardware-based Human Body Communication Transceiver Architecture for WBAN

Applications

Sujaya B.La , S.B. BhanuPrashanthb

a
Department of Electronics & Communication Engineering, BNMIT, Bengaluru, India
b
Department of Medical Electronics Engineering, BMSCE, Bengaluru, India
* Corresponding author. Tel.: +91-9845482348; E-mail address: sujayabl@bnmit.in

Abstract

The wireless body area network (WBANs) technology is a promising technology for Continuous Health care monitoring and real-time support
at high speed. Human body communication (HBC) is one of the non-Radio frequencies (RF) overcomes the drawbacks of RF-based wireless
standards is as per IEEE 802.15.6 physical layer standards. In this Article, an area and power-optimized HBC digital transceiver hardware
architecture are designed for WBAN applications. The proposed HBC Digital Transceiver is designed per IEEE 802.15.6 Physical layer (PHY)
standards using the Frequency selection digital transmission (FSDT) method. The Walsh coding mechanism with Frequency shift codes (FSC)
is used for frequency spreading and despreading generation in HBC Transmitter and receivers. The HBC Digital transceiver is designed and
implemented on Artrix-7 FPGA. The design utilizes < 2 % chip area and works at 255.31 MHz operating frequency on Artix-7 FPGA. The
HBC transceiver works with a data rate of 9.52 Mbps by consuming 101 mW of power for 100 MHz carrier frequency. In addition, the HBC
transceiver obtains the Bit error rate (BER) ratio of 10-4 by transmitting 10188 bits. The proposed HBC transceiver is compared with exiting
IEEE 802.15.6 PHY standards and similar Existing HBC architectures with better performance improvements.

Keywords: Frequency selection digital transmission (FSDT); Human Body communications(HBC); IEEE 802.15.6; Phyiscal Layer; Radio Frequency (RF);

1. Introduction

The Body area networks (BANs) are commonly used in most healthcare industries for continuous health monitoring. The
BAN contains many operating sensors, which are used to measure critical physiological and physical features. The better
flexibility and portability features are provided by adding wireless connectivity to the BAN system. Radio-frequency (RF) based
wireless technologies are introduced in most BAN applications to monitor the health status. The RF-based wireless data
communication protocols like Bluetooth, ZigBee are successfully implemented on BAN applications for data communications
[1]. But these RF-based BAN applications consume high amounts of power, have security issues, and influence electromagnetic
interference. The WBAN is used in healthcare, entertainment, sports, military, and defense applications. Many challenges need to
be addressed while implementing any devices for WBAN applications like Power consumption, reliability, threats, and
heterogeneity of devices [2].
The IEEE 802.15.6 Physical standard is having three main categories for WBAN devices, namely: Narrowband (NB), Ultra-
wideband (UWB), and Human Body communication (HBC). Both the NB and UBW PHY standards come under an RF-based
wireless system, whereas HBC comes under non-RF based wireless-system. The NB and UWB PHY standards support a range of
100- 1000 kbps and 395 kbps – 12.63 Mbps data rates. At the same time, HBC supports 164-1312.5 Kbps data rates with 21 MHz
carrier frequency. Few parameters need to be considered, like security, energy consumption, and frequency reusability for
designing the IEEE 802.15.6 PHY standards, a few [3]. The digital Transceiver uses the human body as a channel by using either
Capacitive or Galvanic. These Coupling methods have few desirable features like little signal leakage with high security, lower
carrier frequency, and lesser signal attenuation with low transmission power [4-5]. The real-time implementation of HBC using
different platforms like Field-programmable Gate Array (FPGA) and Application Specific Integrated Circuits (AISC) for WBAN
applications provides better performance metrics like power consumption, data rate, BER ratio [6-7].
The HBC modem architecture is shown in Fig. 1. It mainly contains MAC controller, interface modules, HBC Transmitter
(HBC-TX) module, HBC-Receiver (HBC-RX) module, and Analog Frontend (AFE) Unit. The interface unit receives the data

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Peer-review under responsibility of the scientific committee of the 8th International Conference on Through-Life Engineering Service – TESConf 2019.

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 / Procedia Manufacturing 00 (2019) 000–000 2

from the Medium access controller (MAC) controller and stores the First in First out (FIFO) unit information. The HBC digital
TX process the FIFO data and passes it to the AFE unit. The AFE unit performs the capacitive coupling operation using
electrodes and generates the demodulated electric signals. The receiver side interface unit process the human body data via the
HBC Digital RX unit and sends back the MAC controller. The MAC controller verifies whether the received data is the same as
transmitted data; if it matches, then the complete HBC data operation is successful. The data controlling functions of the human
body are processed using a MAC controller.
HBC
Transceiver

HBC TX HBC
Interface Transmitter
(TX) Module

Electrode
Controller

HBC
AFE

HBC RX HBC Receiver

Interface (RX) Module

Fig. 1. Overview of HBC Modem

The non-RF-based wireless system monitors the BAN applications, which overcomes most RF-based wireless system issues
like Resource utilization, battery usage, and security issues. Most of the available HBC systems are implemented with AFE unit
on ASIC platform and very focus on digital Transceiver on FPGA platform. The implemented HBC system on FPGA is lagging
with performance issues like Data rate, power, and Chip area. The current HBC system provides data rates in the range of
1Mbps- 6Mbps, which is relatively less. So there is a need for an efficient HBC digital transceiver to improve the data rate for
WBAN applications to overcome the mentioned above issues.
An efficient HBC digital transceiver with hardware architecture is designed for Wireless BAN applications on the FPGA
platform in this article. The organization of the articles as follows: The review of the recent existing Work with limitations is in
section 2. The Proposed HBC digital transceiver architecture is explained in detail in section 3. Section 4 gives the results and
discussion for the HBC digital transceiver. Finally, it concludes the overall Work with improvements in section 5.

2. Related Works

This section provides the existing work reviews of Different IEEE 802.15.6 Physical layer standards architectures. Mohandas
et al. [8] present the Narrowband based Physical Layer baseband transceiver architecture for IEEE 802.15.6 WBAN applications.
The Work uses Different binary phase-shift keying (DBPSK) and Differential quadrature PSK (DQPSK) modulation techniques
for designing the NB PHY system. The Work provides up to 971.4 kbps data rate by consuming 162 μW of power at 6MHz
carrier frequency. Manch et al. [9] present the IEEE 802.15.6 based Digital Baseband Transceiver with low power features using
90nm CMOS Technology. The Narrow Band (NB) based Transceiver is also designed for comparison purposes with HBC. The
HBC provides a 1.325Mbps data rate, consumes 15% less power and 32% less area utilization than NB-based transceivers.
Eddabbah et al. [10] present the IEEE 8902.15.6 based HBC transceiver for BAN applications to analyze the Bit error rate and
Message integrity. The Work analyzes the BER rate for different distance methods like Jaccard, Cosine, Humming, and
Chebyshev distance for the given signal-to-noise ratio values.
Ali et al. [11] [17] present the HBC physical layer transceiver for wireless BAN applications with low-power features. The
HBC architecture is modeled in a MATLAB environment later synthesized on 90-nm CMOS technology. The Transmitter and
receiver consume 237 μW and 400 μW power, respectively, with a data rate of 164- 1312.5kbps. In addition to that, an auto
encoder-based HBC transceiver is designed for WBAN applications. The HBC modules use an additional Deep-neural network
(DNN) based Encoder and decoder with proper frame synchronization. The Work consumes 1.46mW of power with a maximum
data rate of 5.25Mbps.
Park et al. [12] present HBC with Digital capsule endoscopy (DCE), which provides a high data rate with lower power
consumption. The Work uses the FSDT modulation technique with a carrier frequency of 32MHz on 130nm FPGA. The DCE-
based HBC transmitter consumes 3.7 mW of power for 480X480 resolution images with a 3.13 frame/sec rate.
Chung et al. [13] present the HBC transceiver using Walsh codes on Virtex-7 FPGA. The design provides a data rate of
12.5Mcps with a Bit error rate of < 10 -5 and covers the 140 cm maximum transmission distance. Yuan et al. [14] explain the
Adaptive IEEE 802.15.6 MAC protocol FOIR WBAN applications. The design provides high-energy efficiency with adaptive
features. The works analyses the Average delay, normalized throughput, and average energy consumption for the given nodes.
Vijayalakshmi et al. [15] present the Digital transceiver for Body channel communication with high-efficiency and low-power
features. The design using a Humming codes-based Transmitter with Frequency shift key (FSK) modulation to reduce the power
consumption. The design provides a 60Mbps data rate by consuming 1mW total power. Wei et al. [16] present Intra-body
communication (IBC) transceiver module with Galvanic Coupling features on FPGA. The IBC is designed using the Differential
Phase shift keying (D-PSK) modulation technique. The IBC works at a 1Mbps data rate by using a carrier frequency of 2MHz.
 / Procedia Manufacturing 00 (2019) 000–000 3

3. HBC Transceiver Module

The IEEE 802.15.6 physical layer standard is considered for designing the Human body communication digital transceiver
module. The HBC transceiver module mainly contains an HBC transmitter, the Human body as a Channel, and receiver Modules.
The HBC transceiver uses Frequency selective Digital transmission (FSDT) scheme, and the overview of the HBC transceiver is
represented in Fig. 2.

HBC Transmitter Human Body HBC Receiver

(TX) (Channel) (RX)
Fig. 2. HBC Transceiver Overview

3.1. HBC Transmitter

The HBC transmitter hardware architecture is represented in Fig. 3. The HBC Transmitter mainly contains five units, namely:
Preamble generator, Start of Frame Delimiter (SFD) generator, Physical Layer convergence protocol (PLCP) header generation,
Physical layer service data unit (PSDU) generation, and Multiplexor.

Preamble generator Spreader-1

SFD generator Spreader-2

M
Header Generator CRC U
X TX
out
Data FS-
Data Generator S2P
Input Spreader
Fig. 3. HBC Transmitter Hardware architecture

The preamble sequence is generated based on gold codes and frequency shift code (FSC). The two 32-bit gold codes are
generated using the below polynomials and represented in Eq. (1) and (2):
x10  x 3  1 (1)
x10  x8  x3  x 2  1 (2)
These two 32-bit gold codes are concatenated to frame a single 64-bit gold sequence. Repeat the 64-bit gold sequence four
times to communicate the 256-bit gold code. Similarly, define two FSC's, and it is set to "AA" and "55" for the given gold code
'0' and '1'respectively. If the gold value is set to '0', multiply the 256-bit gold code with "AA" to generate the 264-bit preamble
sequence. If the gold value is set to '1', multiply the 256-bit gold code with "55" to generate the 264-bit preamble sequence.
The start of frame delimiter (SFD) initiates the packet sequence and consider as SFD data. However, in design, the rate
indicator is not considered and uses only SFD data to initiates the HBC process. Therefore, the SFD generation process is the
same as the Preamble sequence generation process and generates 80-bit SFD data.
The PLCP Header with Payload data generation is represented in Fig. 4. The 16-bit PLCP header mainly selects data rate, pilot
insertion, burst mode selection, and seed insertion.

Fig. 4. PLCP Header with MAC format

The 3-bit data rate is fixed to 1.3125 Mbps by using the "011" value. The "000" are inserted into the pilot, and burst mode is
not used in this HBC design. The scrambler-based seed is disabled in this design. The 8-bit medium access control (MAC) data is
considered user payload data. The 8-bit cyclic redundancy check (CRC8) is set by using the polynomial, and it is mentioned in
Eq. (3):
x8  x7  x3  x2  1 (3)

The PSDU gives the medium access control (MAC) data information using the First-in, first-out (FIFO) interface unit. The
data process mechanism is controlled using the FSDT technique. Initially, The FIFO provides the 1-bit sequence of the data at
the rate of 1.3125Mbps in the data generator unit. The 1-bit data is later framed into 4-bit using serial to parallel (S2P) converter.
Finally, the Frequency spreader (FS) receives the 4-bit parallel data performs the mapping operation using Walsh codes and
Frequency Shift code (FSC). Table 1. shows the Walsh code generation for the given S2P unit. Finally, the 16-bit Walsh code is
multiplied with 8-bit FCS to generate the final data.
 / Procedia Manufacturing 00 (2019) 000–000 4

Table 1. Generation of Walsh Code for the S2P data

S2P data Walsh Code S2P data Walsh Code
0000 FFFF 1000 FF00
0001 AAAA 1001 AA55
0010 CCCC 1010 CC33
0011 9999 1011 9966
0100 F0F0 1100 F00F
0101 A5A5 1101 A55A
0110 C3C3 1110 C33C
0111 9696 1111 9669

The S2P module provides the data at 328ksps by performing four times shifting operations. At the same time, FS-spreader gives
5.25Mcps by multiplying the Walsh code with 8-bit FCS. The Multiplexor receives Preamble, SFD, Header, and PSDU data
information, provides the HBC transmitter output based on the user select line. The Transmitted output is mixed with Additive
white Gaussian noise (AWGN) with a scaling factor of 4dB. Finally, the corrupted data is input to the HBC receiver module.

3.2. HBC Receiver

The HBC receiver hardware architecture is represented in Fig. 5. The HBC receiver mainly contains three units:
Demultiplexer, PSDU data recovery unit, and PLCP header recovery unit.
The Demultiplexer receives the corrupted data and generates the PSDU and header information based on the user select line.
Then, the frame synchronization is performed with a proper clock mechanism for the received header and PSDU data. FS
despreader is similar to the FS spreader by dividing the 16-bit demodulated Walsh code with 8-bit FSC. Here The 4-bit FS
despreader output is input to the Parallel to serial (P2S) unit, and it provides the 1-bit serial data in a sequence. Finally, the PSDU
recovery module receives the recovered data in a sequence, the same as the input sequence [22-24].
HBC Receiver

D
FS- Data HBC TR
P2S
E Despreader Recover output
M
RX U
input X
CRC Header Processor

Fig. 5. HBC Receiver Hardware architecture

4. Results and Analysis

The HBC digital transceiver is designed on Xilinx ISE 14.7 environment with Verilog-HDL programming and implemented
on Artix-7 FPGA. The HBC digital transceiver simulation, synthesis, Comparison, and performance results are discussed in this
section. The simulation result of the HBC transceiver module is represented in Fig. 6.

Fig. 6. Simulation Results of HBC transceiver Module

The global clock (clk) is activated with a lower asynchronous reset (rst). Keep the rate indicator (ri) low throughout the
design. The 2-bit select line (sel) is used in both the multiplexer and demultiplexer modules of HBC Transmitter and receiver
modules. The preamble generated data is considered for the "00" select line, the SFD data is considered for "01", the header data
is considered for the "10" select line. Primary user data (PSDU) considered for the "11" select line. Initiates the load signal and a
sequence of data to start the PSDU operation. After 10.5 clock cycles, the HBC digital transceiver gives the output, which is the
same as the original input with delay.
 / Procedia Manufacturing 00 (2019) 000–000 5

Additionally, the error finding mechanism is also incorporated in the HBC to find out the BER rate. The Simulation Results
of HBC transceiver Module with Error Finding is represented in Fig. 7. The 10.5 clock cycles of delay are used in the data input
signal (din2) signal is introduced to match the received HBC data output (data_out). The 16-bit counter is used to count the
number of errors is appear in the HBC transceiver. The main counter is used to calculate the overall input sequence transmitted in
the HBC transceiver. The error appearance is highlighted in red color in Fig. 7.

Fig. 7. Simulation Results of HBC transceiver Module with Error Finding

The BER calculation is performed based on the simulation results of the HBC transceiver. The HBC Transceiver receives
10188 data bits with a scaling factor of 4 and obtains the bit error rate (BER) of 3.92x10-3 for a 6 dB Signal to Noise Ratio
(SNR)[25-26].
The HBC transceiver is synthesized on Artix-7 FPGA, and it is tabulated in Table 2. It utilizes the 196 slice registers, 1137
Slice LUT's and 134 LUT-FF pairs. The design works at 255.31 MHz operating frequency and consumes 101mW of total Power
on Artix-7 FPGA.
Table 2. Resource Utilization on HBC transceiver Module on Artix-7 FPGA
Resources HBC Transceiver
Slices 196
Slice LUTs 1137
LUT-FF pairs 134
Max. Frequency (MHz) 255.31
Total Power (mW) 101
Latency (clock cycles) 10.5
Throughput (Mbps) 24.31

The HBC transceiver obtains final output by 10.5 clock cycles of latency with a throughput of 24.31 Mbps. The 9.52 Mbps
throughput and 48.57Kbps/Slice efficiency are accepted for the HBC transceiver at 100 MHz frequency. The Capacitive
coupling-based HBC module uses 100MHz for WBAN applications [4].
The HBC transceiver Chip resource utilization on Artix-7 FPGA using FPGA Editor Tool is represented in Fig. 8. The
resource utilization is analyzed after place route operation on Xilinx Environment. Overall, the chip area resources like Slice
Utilizes 1%, and LUTs utilize 2% of resources on Artix-7 FPGA.
 / Procedia Manufacturing 00 (2019) 000–000 6

Fig. 8. Chip Resources utilization on Artix-7 of HBC transceiver

The Comparison of proposed Work with existing IEEE 802.15.6 standard works is tabulated in Table 3. For the Comparison
of the HBC work, the different resource parameters like the coding scheme, chip area used, power consumption, and Selection of
FPGA's are considered. The existing Narrow-band Physical Layer (NB-PHY) [18] design uses BCH coding approach, and it
utilizes 2668 slices, 3161 LUT's and consumes 117mW Power on Virtex-6 FPGA. The Human body-based physical layer (HBC-
PHY) [19-21] design uses Walsh coding approach, and it utilizes 5231 slices LUT's and consumes 114mW Power on Artix-7
FPGA. The proposed HBC transceiver design uses a Walsh code scheme for modulation and utilizes fewer Slices and LUT's
with minimal power than the existing 802.15.6 standards [18] [21].
Table 3. Resource Comparison of proposed Work with existing IEEE 802.15.6 standards
HBC- PHY Proposed
Resources NB-PHY [18]
[19] HBC-PHY
Coding Scheme BCH Walsh Walsh
Slices 2668 NA 196
LUT's 3161 5231 1137
Power (mW) 117 114 101
FPGA Virtex-6 Artix-7 Artix-7

The performance parameters comparison of proposed Work with different existing works on different nm FPGA's is tabulated in
Table 4. For Performance comparison of the HBC work, the various design parameters like the CMOS Technology, Modulation
technique used, selected Carrier frequency, Core Voltage (V), BER ratio, consumed power (mW), and data rate (Mbps) are
considered.
The existing HBC [18] design uses 130nm CMOS Technology. The FSDT modulation scheme is selected for HBC design;
32MHz carrier frequency is used, the core voltage of 3V is set, and it consumes the 114-mW Power with 6 Mbps of data rate.
Similarly, the HBC [19] design uses 90nm CMOS Technology; the wideband signaling scheme is used for modulation with 100
MHz carrier frequency. The core voltage of 1V is fixed and consumes the 158 mW Power with 3.125 Mbps of data rate. The
proposed HBC work gives a better data rate and power consumption than the existing HBC modules [19] [24].
Table 4. Performance comparison of Proposed with exiting HBC works
Park et al. Chung et al. Proposed
Parameters
[21] [24] HBC-PHY
28 nm
CMOS Technology 130 nm FPGA 90 nm FPGA FPGA

Modulation FSDT Wideband FSDT

Carrier Frq. (MHz) 32 100 100
Core Voltage (V) 3 1 1
BER NA < 10-8 10-4
Power (mW) 114 158 101
Data Rate (Mbps) 6 3.125 9.52
 / Procedia Manufacturing 00 (2019) 000–000 7

The proposed Work obtains nearly 10-4 BER by transmitting 10188 bits of data to the HBC transceiver module, whereas the
existing HBC [20] brings the BER of < 10 -8 by gives more data to the HBC modules. Therefore, the BER ratio will be improved
by providing more data to the HBC transceiver module.

5. Conclusion

In this article, an efficient HBC digital transceiver is designed on Artix-7 FPGA. The HBC transmitter, channel, and receiver
modules are instantiated into the HBC transceiver module. The HBC Transceiver uses an FSDT scheme with Walsh code
modulation for data (PSDU) generation. The IEEE 802.15.6 Physical layer standard is incorporated in the proposed HBC
transceiver. The simulation results of the HBC PHY module give the Latency, BER ratio results and are verified with given data
inputs. Still, the BER can be improved by providing more input data in a sequence. The Proposed Work is compared with
existing different IEEE 802.15.6 PHY approaches and similar existing HBC PHY modules with performance improvements. In
the future, use different modulation techniques to improvise the performance metrics in real-time scenarios.

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