Seat Number Co) TE — a Teor Electronics Circuit Design (1090) P. Pages: 4 S Time : Three Hours Instructions to Candidates : 4. Do not write anything on question paper except Seat No. s 2. Graph or diagram should be drawn with the black ink pen bejng used for writing paper or black HB pencil. v Students should note, no supplement will be provided. Each question carries equal marks. Assume suitable data, if required. ay Unless specified for transistor and diodes, make of device is silicon. S Attempt any two questions from each unit. Unless specified in question, use data infor question paper. a 9. Use of non programmable calculator is allowed. one ox in at the end of UNIT-1 4. a) Design a discrete series voltage regulator for following conditions: 10 Regulated output voltage Vi = 12V Ag= Max. load current Imax = 100mA Input voltage, Vin = 2022V Draw the designed circuit diagram, along with all ratings of components used. 4 b) Design a regulated poweF supply using IC 317 for- 10 Veo Draw the circuit diagram. Design should include external components fop!C 317. Heat sink, if required, and unregulated power supply’ For ICLM347 use data- TPC GPCI ie° CW @cs°C/W Dropout. 150 935 23 2 Voltage 2v Se oe © TRY 045 1 P.T.ORY - 045 ¢) Design a switching regulator circuit using LM2575/LM1575 for 10 Vo=12V, =0.3A, Vin=2042V at 30°C. Draw designed circuit diagram. Calculate the component values connected around IC, Heat sink calculations, if required. [No need to design unregulated power supply.] For IC 2575/1575 use data- Veat fo Qja®C/Wje°CIW Ocg°C/W TPC 0.8V 12mA 65 3 2 150 UNIT - II 2. a) Design a single stage CE amplifier with (Partially bypassed emitter,” 10 resistor) for 4 Av250, Q points (1mA,5V), S=10,RI=10K 9 ¢ Riw=100kQ, Rs=600 0, F.=50Hz Use BJT having hfe=200, hie=10k a Use potential divider bias network. b) Design a single stage common source JFET amplifier Av=-25, peak output voltage swing=3.5V loa=lossi2, Fi=20Hz, Riw=100KQ Use FET having los: : Draw the designed circuit. Design must include calculation of bias components, selection of Voo, calculation of external capacitors. provide. 10 ©) Design two stage voltage series, feedback amplifier to provide the 10 following specifications i) Closed loop voltage gain Ave>420 ii) Use identical stages, each having same bias network with 5=10, Qpoints (2MA, 5V),VRe=2V (voltage across emitter resistor) iii) Take Vec=10V é Use transistor with hfemin =200, hie=2.5kQ Draw the designed circuit? Design must include bias components calculations and feedback network component calculation. [No need of external and bypass‘capacitor calculations] ae UNIT - Il 3. a) Design a classiA transformer coupled amplifier for following 10 requirement i) Pye =S0mW ii) R.=50 iii) Veg 10V iv) niranstormer = 70% v) Stability factor $=10. Use hfemin = 100.b) c) b) TRY - 045 Design an audio complementary symmetry amplifier for producing 10 maximum ac power of 0.5 W to feed resistive load of 1009 use hfe=50. [No need of external capacitor calculations] Design a class B transformer coupled amplifier to give output 10 Power of 10 W to a resistive load of 40, If efficiency of output transformer is 80% and stability factor for bias network is 8 with Vec= 18V Ss UNIT - IV $ Design an astable multivibrator for duty cycle of 50%, amplitude of 10 output signal required of 8V, and frequency 1KHz. Use the Value of collector current 2mA and transistor hfe=100 w Design Hartley oscillator using BUT for following requirements 10 Fo=3.2MHz, Av=25, Qpoin (mA, 5V), S=4 Vre= 3V (voltage-Aacross emitter resistor). Use capacitor 0.01 uF in feedback network. For BUT use hfe =50, hie=10kQ, ro=200kQ. Design single tuned amplifier using FET (N- channél) for following 10 specifications. i) Av=100 ii) F ili) Qettective =15 iv) Ri v) Bias requirement-set loe=Inssi2 Vos For FET use loss=7mA, Ve=-6V, gmo=5m¥, rd=50KQ Draw the designed circuit diagram. Design must include bias components and tuned circuit component calculation. [No need to calculate coupling and bypass capacitors] MHz MQ SV-with Voo=20V. UNIT -V Design low pass filter fora’ 10 i) Order of filter is 208° ii) Using 2dB peak Ghebyshev response. ili) Fe=800HZ iv) Use sallen key unity gain method. v) DC gain of 5. Take a=0.886, kep=1.333 Design a bandpass filter for following requirements. 10 i) Ave ji) Q=20 il) Fe6oHz iv) Roll off rate 60dB/decade & 3 PTORY - 045 c) Design non inverting amplifier using single +5V supply with an AC 10 gain of 18, a frequency range of 20 Hz to 20kHz and Zi = 100k2, F.=20Hz. Draw the designed diagram design must include all component values. ones codes ata Inrmaon peas VES wmax=25mA m4 O i) BZZ15 tzmax=25mA_ 12 O Transistors Transistor ‘Type 80227 PNP 40 250 3A 125M ECNt00 NPN 0547 NEN, TREY 045 4 215/30