Class: T. E.

E & C Electronic Circuit Design

University questions
Q. No. 1 Design a self-bias Network, used to bias BJT for following requirements:
i) Q-points [1mA, 5V]
ii) Stability factor S=9
iii) Supply voltage VCC=15V, VRC=3V
BJT has hfemin=150, Draw the designed circuit diagram. Also verify the result by using D. C. analysis
method.

Q. No. 2 Design a voltage divider bias circuit for Q-point (7.5V, 1.5 mA) with S≤3. Assume transistor hFE=100.
Verify that designed circuit meets stability factor constraints.

Q. No. 3 Design a single stage common emitter configuration amplifier with S=10, Q-points (5V, 2mA), cut-off
frequency fL=100Hz to have gain greater than 70. Modify the circuit to give gain of 10. Design all the
components with transistor rating. State the feedback methodology used to stabilize the gain. Make
suitable assumption for hFE.

Q. No. 4 Design a single stage amplifier using BJT for

i) Voltage gainAV≥100 ii) Stability factorS=7
i) Q-points [1mA, 4V] iv) I/P resistance Ri≥5kΩ
i) fL=20Hz, fH=20kHz vi) Phase shift ∅=180 0
i) RLW=100kΩ viii) Source resistance=0.6kΩ
Use transistor with hfe(min)=200, hie=10kΩ, fT=10MHz
Design circuit must include calculation of bias components and external capacitors. Also specify the
configuration of BJT amplifier? Draw the designed circuit diagram.

Q. No. 5 Design a single stage amplifier in a C. E. configuration with emitter By-passed for following requirements:
i) Voltage gain AV≥100 ii) Stability Factor S=6
i) Q-points [1mA, 3V] iv) I/P resistance Ri=5kΩ
i) fL=20Hz, fH=20kHz vi) RLW=100kΩ
Source resistance RS=600Ω. Use BJT with hfe(min)=200, hie=10kΩ, fT=10MHz.
Design circuit must include calculation of bias components and external capacitors. Draw the designed
circuit diagram.

Q. No. 6 Design single stage C. E. amplifier having following specification:

VCC=24V, hfe=100, hie=1kΩ, external load resistance =120kΩ, cut-off frequency range 100Hz to 50 kHz.
Draw designed circuit diagram and design all components value and their ratings.

Q. No. 7 For a C. E. amplifier shown in figure, estimate value of supply voltage and all external capacitors to get
lower cut off frequency of 100 Hz. Take Q-points [3.73mA, 9.75V] and transistor used have hfe=100 and
hie=1.1kΩ

Unit-II- Design of Small Signal Amplifiers using BJT / FET Page 1

Solution of University Question
 Class: T. E. E & C Electronic Circuit Design

Q. No. 8 The amplifier shown in figure is CE amplifier with emitter bypassed. Modify this amplifier to use emitter
current feedback to give AVF=70. The lower cut off frequency is fL=100Hz. The signal source resistance is
RS=600Ω. Design must include calculation of new value of emitter resistance [By passed and un bypassed
part] and external capacitors.

Q. No. 9 Design a single stage C. E. amplifier with [partially by-passed and partially un bypassed emitter resistance]
for Avs≥50, Q points[1mA, 5V], S=10, R i=10kΩ, RLW=100kΩ, Rs=0.6kΩ, fL=50Hz. Use BJT having
hfe=200, hie=10kΩ. Use potential divider bias network.

Q. No. 10 Design single stage C. E. amplifier with [partially by-passed and partially un bypassed emitter resistance]
for Avs≥50, Q points[1mA, VCEq≥5V], S=10, Ri=10kΩ, RLW=100kΩ, Rs=0.6kΩ, fL=50Hz. Use BJT having
hfe=200, hie=10kΩ. Use potential divider bias network.

Q. No. 11 Design a single stage C. E. amplifier with [partially bypassed and partially un bypassed Emitter
Resistance] for
A VS ≥50 , Q po int s [ I Cq=1mA , V CEq ≥5V ] , Ri =10 kΩ , R LW =100 k Ω, S=10 , R S=0. 6 k Ω BJT
h =200 , h =10 k Ω
have fe ie CEI1330
Q. No. 12 For a C. E. amplifier shown in figure, is CE amplifier with emitter resistance by passed. Modify this
amplifier to use emitter current feedback to give A VF=70. The lower cut off frequency is f L=100Hz. The
signal source resistance is RS=600Ω. Design must include calculation of new value of emitter resistance
[By passed and un bypassed part] and external capacitors. Used BJT have h fe=100, hie=1kΩ

Unit-II- Design of Small Signal Amplifiers using BJT / FET Page 2

Solution of University Question
 Class: T. E. E & C Electronic Circuit Design

Q. No. 13 Design a single stage Common Base amplifier for

A V ≥50 , Ri ≥75 Ω, R LW =50 k Ω,
R S =50 Ω, S=10 , Q points [1mA, V ≥3V]. Assume used transistor have h fe=100 , hie=10 kΩ .
CEq
Use potential divider bias network.

Q. No. 14 Design a single stage Common Base amplifier for

A V ≥50 , Ri ≥75 Ω, R LW =50 k Ω,
R S =50 Ω, S=10 , Q points [1mA, 3V]. Assume used transistor have h fe=100 , hie=10 kΩ .
CEI1330

Q. No. 15 Design a single stage Common Base amplifier for

A V ≥50 , Ri ≥75 Ω, R LW =50 k Ω,
R S =50 Ω, S=10 , Q points [1mA, V ≥3V]. Assume used transistor have h fe=100 , hie=10 kΩ .Use
CEq

potential divider bias network.

Q. No. 16 Design a self-bias circuit for N-channel JFET for following requirments:
i) Q-points [5mA, 15V] ii) Supply voltage VDD=22V
ii) I/P resistance of bias network Ri≥1MΩ
Use FET 2N590 with IDSS=6mA, VP = -2.5V. Design must include calculation of bias components. Draw
the designed circuit diagram?

Q. No. 17 Design single stage common source amplifier with Bypass source resistance for
I DSS
A V ≥80 , R i≥500 k Ω, Q po int s I dq= , V DSq ≥3V , RS =0. 5 k Ω, R LW =100 k Ω
2
f L=20 Hz take V RD=V R 3 where R 3 is the source resistance of device. FET used have
I DSS =2 mA , V P =−5 V , g mo=12 ms , r d =80 kΩ . Use potential Divider Bias Network.
CEI1330

Q. No. 18 Design single stage JFET amplifier for the following requirements:
i) Voltage gain V
A =25 , R =1 M Ω
i
I
[ DSS , 12V ]
ii) Q-points 2 , Using self-Bias

Unit-II- Design of Small Signal Amplifiers using BJT / FET Page 3

Solution of University Question
 Class: T. E. E & C Electronic Circuit Design
0
iii) Phase shift φ=180 iv) fL=20Hz
Draw designed circuit. Design must include calculation of bias component and external coupling
capacitors. FET used is n-channel with
I DSS =2 mA , V P =−6 V , g mo=0.3 ms , r d =50 kΩ

Q. No. 19 Design a single stage C. S. JFET amplifier to provide.

i) Voltage gain AV=25
ii) Peak O/P voltage VOP=3.5V
iii) IDq=IDSS/2
iv) fL=20Hz
v) RLW=100kΩ
I DSS =2 mA , V P =−6 V , g mo=0.3 ms , r d =50 kΩ
Use a FET having
Draw designed circuit. Design must include calculation of bias component and external coupling
capacitors.

Q. No. 20 Design common source amplifier with V DD of 18V, IDSS=9 mA, VP=-4V and RL(ext)=4kΩ and cut-off
frequency 50Hz. Draw the O/P waveform of the amplifier if I/P is 50mV and 2.5V.

Q. No. 21 Design a voltage divider bias circuit for N-channel FET to set Q-points [3mA, 10V]. Take V DD=25V and
voltage across drain resistance RD(VRD) equal to voltage across source resistance RS(VRS) equal to 2.5V.
FET used has IDSS=8mA, VP = -6V. The I/P resistance of this network should bre R i=1MΩ. Draw the
circuit diagram.

Q. No. 22 Design a JFET common source amplifier to provide voltage gain of -20, V O=3V (rms) with zero drift
biasing, fL=20Hz. Use FET Pd(max)=0.3W, IDSS=7mA, VP=-2.5V, gmo=5mS, rd=50kΩ. Draw designed
diagram and design all component values.

Q. No. 23 Design a single stage common source FET amplifier [without source resistance] or by pass source
resistance for following requirments:
i) Potential divider bias network.
ii) VDq=5V, IDq=IDSS/2
iii) Avs≥50, Ri≥800kΩ
iv) Fl=20Hz, RLW=20kΩ
Take same voltage drop across drain and source resistance [V RD=VR3], where VR3=voltage drop across
source resistance of device. Use FET having following parameters I DSS=2mA, VP= -6V, gmo=8mS, rd=80kΩ

Q. No. 24 Design a single stage JFET for AV=25, Ri≥1MΩ, Q points [IDSS/2, 12V] with self bias Φ=180 0between
I/P and O/P, fL=20Hz. Used FET has parameters: I DSS=2mA, VP=-6V, gmo=0.3mS and rd=50kΩ.

Q. No. 25 Design a single stage common Drain amplifier for following requirements.
i) Use potential divider bias network.
ii) AV=0.99, Ri≥500kΩ, Ro≤200Ω
iii) RLW=500kΩ, VDq=5V, RS=0.6kΩ, IDq=IDSS/2.
iv) FET used in this design have IDSS=2mA, VP=-5V, gmo=8mS.

Unit-II- Design of Small Signal Amplifiers using BJT / FET Page 4

Solution of University Question
 Class: T. E. E & C Electronic Circuit Design

Q. No. 26 Design a single stage common gate amplifier with self-bias for A vs=40, Ri≤150Ω,
RLW=100kΩ, Rs=50Ω, fL=20Hz, Q points [IDSS/2, 3V]. Consider VR3=VRD, Where R3 is source resistance
connected at source terminal of FET. FET has parameters.
IDSS=2mA, VP=-6V, gmo=10mS and IGSS=200nA.

Q. No. 27 Design a single stage common gate amplifier with self-bias network for following requirements:
i) AVS=40, Ri≤150Ω RLW=100kΩ, Rs=50Ω, fL=20Hz,
ii) Q points [IDSS/2,VDS≥ 3V].
iii) Consider VR3=VRD, Where R3 is source resistance connected at source terminal of FET.
FET has parameters. IDSS=2mA, VP=-6V, gmo=10mS and IGSS=200nA.

Q. no. 28 Design a voltage series [two stages] feedback amplifier for following requirements:
i) Overall voltage gain AVF=120
ii) VO=6V(p-p), RLW=10kΩ, VCC=10V
iii) Q-points for both stages [2mA, 5V]
iv) Stability factor S=10
Draw the designed circuit diagram. Design must include calculation of bias components, [no need of
calculation for external coupling capacitors]. Use transistors BC 109 with h femin=200, hie=2.6kΩ

Q. No. 29 Design a two-stage feedback amplifier to provide the following specifications.

i) Closed loop voltage Gain
A VF ≥120
ii)
Used Identical stages, each having Bias network with stability factor S=10, with Q-points (2mA,

5V)
iii) Take VCC=10V and working load resistance 100kΩ
iv) O/P voltage swing is VOp-p=9V
Use transistor with hfemin=150, hie=2.5kΩ.
Draw the designed circuit diagram. Design must include calculation of bias components and feedback
network component. [no need of calculation for external coupling and by-pass capacitors].

Q. No. 30 Design a voltage series [two stages] feedback amplifier for following requirements:
i) Overall voltage gain AVF≥120
ii) VO=9V(p-p), RLW=5kΩ, VCC=12V
iii) Q-points for both stages [2mA, 5V]
iv) Stability factor S=10
Draw the designed circuit diagram. Design must include calculation of bias components, [no need of
calculation for external coupling capacitors]. Use transistors BC 109 with h femin=200, hie=2.6kΩ

Q. No. 31 Design a two stage feedback amplifier to provide the following specification:
Avf=100, use identical stage, each having same bias network. V CC=15V, RL=3kΩ, RS=600Ω, VO=9V(p-p),
fL=50Hz, S=10, Q-points [6V, 2.5mA], use h fe=80, hie=842Ω. Draw the designed diagram. Design must
include bias component calculations and feedback network component calculation. [No need of external
coupling and by pass capacitor calculation]

Unit-II- Design of Small Signal Amplifiers using BJT / FET Page 5

Solution of University Question
 Class: T. E. E & C Electronic Circuit Design
Q. No. 32 Design voltage series feedback amplifier [two stage] so as to provide
i) Avf≥100
ii) Use identical stages with potential divider bias network with S=10 and Q point (2mA, 5V)
iii) VCC=10V and RLW=100kΩ
iv) O/P voltage swing Vop-p=9V
Used transistor have hfe=200 and hie=2.5kΩ

Unit-II- Design of Small Signal Amplifiers using BJT / FET Page 6

Solution of University Question