gm/ID Design Considerations for Subthreshold-based

CMOS Two-stage Operational Amplifiers

Chaiyanut Aueamnuay
aueamnuc@oregonstate.edu
Ajmal Vadakkan Kayyil Jialin Liu Narayana Bhagirath Thota David J. Allstot
vadakk@oregonstate.edu liuj6@oregonstate.edu thotan@oregonstate.edu allstot@oregonstate.edu
School of EECS
Oregon State University
Corvallis, OR 97331 USA

Abstract—The gm/ID-based design of analog integrated First Stage Second Stage

Bias
circuits introduced by Silveira, et al. in 1996 [1] employs an VDD
empirical transistor sizing methodology using SPICE-generated
lookup tables. In the design of ultra-low-power amplifiers, the VB5,7
M9 M5
iconic plots of gm/ID vs VOV suggest that some devices should be M8 M7
operated deep in weak inversion (e.g., VOV ≃ _0.2V) where gm/ID VB12 Compensation
is near maximum. Performance parameters such as gain, CC
bandwidth, thermal noise, power dissipation, etc., benefit from M11 M1 M2
this choice. However, in applications where small-signal settling VN VP M12
CL
time is critical (e.g., precision switched-capacitor circuits), the I REF
unity-gain phase margin, PM, is a parameter of paramount
importance. PM (i.e., small-signal settling time) vs. VOV (i.e., M10 M3 M4 M6
strong, moderate or weak inversion) design considerations are
presented in this paper. The key result is that as the design Vss
choice of VOV moves the region of operation from strong to
moderate to weak inversion, PM is reduced substantially and Fig. 1. Two-stage OTA with conventional PVT-tracking compensation.
settling time is increased dramatically. In addition to new design First Stage
Bias Second Stage
insights, area-efficient device layout techniques are illustrated
VDD
that improve performance.
Keywords—gm/ID-based design, sub-threshold amplifier M9 VB5,7 M5
design, two-stage CMOS OTA, phase margin versus settling time M8 M7
Compensation
I. INTRODUCTION IB RC CC
The classical two-stage OTA (Fig. 1) is arguably the most IB M1 M2
important CMOS analog circuit building block. Introduced in VN VP
CL
1980 [2], it enabled the first commercial CMOS PCM Filter RB
M10
chip [3], and four decades later, it is still a mainstay of mixed- M3
M13 M4 M6
signal IC design. Billions of units have been manufactured.
The seminal design used the PVT-tracking Miller pole- Vss
splitting frequency compensation technique shown in Fig. 1.
As was common practice then, all devices were operated in Fig. 2. Two-stage OTA with low-voltage PVT-tracking compensation.
saturation in strong inversion except M12, the triode-region
compensation resistance. An alternative PVT-tracking Miller
frequency compensation technique (Fig. 2) achieves similar
performance at lower supply voltages, which is attractive for
deeply-scaled CMOS technologies [4][5].
Contemporary versions of these and other amplifiers aim
to save power by operating the input stage in saturation in
weak (or moderate) inversion. Of course, both stages operate
in this region for biomedical and other IoT applications.
The gm/ID-based design techniques introduced by Silveira,
et al. in 1996 [1], and detailed by Jespers and Murmann in
2017 [6], have been employed in previous subthreshold
circuits. In some cases, VOV was designed to be ~ -0.2V to
maximize the gm/ID ratio to minimize power dissipation for
given gain, bandwidth, noise, etc., specifications. It is well
known, however, that the unity-gain phase margin (PM) is
critical in determining the small-signal settling time in, for
example, precision switched-capacitor circuits [1][7][8]; this
effect is vividly illustrated in Fig. 3 (Fig. 3 from [8]). The key
point of this paper is that VOV should be chosen after careful
consideration of the critical PM parameter that determines the
small-signal settling time.

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 II. CMOS TWO-STAGE OTA WITH RC COMPENSATION TABLE I. TARGET DESIGN SPECIFICATIONS
Before the gm/ID designs are undertaken, some basic OTA VDD (V) 1.8
performance characteristics are reviewed briefly using the Gain (dB) > 60
small-signal model for the CMOS two-stage OTA in Fig. 4. UGB (MHz) > 50
Its small-signal transfer function (assuming the dominant-pole Unity-gain PM (°) > 60
Input- referred Thermal Noise @10MHz (nV/√Hz) < 15
approximation) is:
𝐴0 (1 −
𝑠
)
CL (pF) 5
𝑉𝑜𝑢𝑡 (𝑠)
= 𝑠 𝑠
𝜔𝑧
𝑠 (1) The gm/ID design methodology flows according to the
𝑉𝑖𝑛 (𝑆) (1 + ) (1 + ) (1 + )
𝜔𝑝1 𝜔𝑝2 𝜔𝑝3 seminal publications [1][6]. Herein, PMOS input pair, M1-2,
Assuming 𝜔p1 << 𝜔p2 and 𝜔p3, and 𝜔p2 << 𝜔p3, the is biased for seven comparative designs ranging from strong
approximate pole and zero locations and voltage gain are: through moderate to weak inversion operation with
VOV = 0.1V, 0.05V, 0V, -0.05V, -0.1V, -0.15V, and -0.2V.
(2)
1 𝑔𝑚6 1
ωp1 ≃ − , ωp2 ≃ − , ωp3 ≃ −
𝑅1 𝑔𝑚6 𝑅2 𝐶𝐶 𝐶𝐿 𝑅12 𝐶1 VOV = 0.15 V for all other devices in all seven cases. As VOV
1 is decreased, the corresponding PMOS gm/ID values increase
ω𝑧 ≃ 1 (3) monotonically for a given L as plotted in Fig. 5. The PMOS
𝐶𝐶 ( − 𝑅12 )
𝑔𝑚6
L is selected based on the voltage gain requirements. Note
𝐴𝑉 = 𝐴1 𝐴2 = 𝑔𝑚1 (𝑟𝑜2 //𝑟𝑜4 )𝑔𝑚6 (𝑟𝑜6 //𝑟𝑜7 ) = 𝑔𝑚1 𝑅1 𝑔𝑚6 𝑅2 (4) from Fig. 6 that higher values of gm/ID correspond to higher
voltage gains for a given L. For L = 300 nm, for example, the
From (1), the two-stage OTA comprises three LHP poles
voltage gain is minimum at VOV = 0.1V where gm/ID = 10 S/A
and one zero. 𝜔p1 is the dominant pole, and, by design, the and maximum at VOV = -0.2V where gm/ID = 27 S/A. Hence,
non-dominant pole, 𝜔p2, is cancelled by 𝜔z using a the same length, L1,2 = 300 nm, is used for all seven designs.
compensation resistance:
𝐶𝐶 + 𝐶𝐿
𝑅𝑐 = (5)
𝑔𝑚6 𝐶𝐶
After successful pole-zero cancellation, 𝜔p3 becomes the
non-dominant pole, which determines PM. Assuming a 90°
phase shift for the dominant pole, 𝜔p1, the unity-gain phase
margin is:
𝜔
PM = 90° − 𝑡𝑎𝑛−1 ( 𝑢 ) (6)
𝜔𝑝3

For a given unity-gain bandwidth and PM, the required

location for 𝜔p3 is found from (6) as:
𝜔𝑢
𝜔𝑝3 = (7)
𝑡𝑎𝑛(90° − 𝑃𝑀)
After algebraic manipulations using (2), (5) and (7),
𝑔𝑚6 𝜔𝑢 𝐶𝐿 Fig. 5. PMOS gm/ID vs. VOV. For all PMOS devices except the input pair,
= (1 + ) (8) M1-2, gm/ID = 8 S/A for VOV = 0.15V.
𝐶1 𝑡𝑎𝑛(90° − 𝑃𝑀) 𝐶𝐶
where C1 is the parasitic capacitance at the output node of the
first gain stage; C1 comprises Cdd-M2, Cdd-M4 and Cgg-M6 (Css-M12
(Fig. 1) is neglected). The design considerations presented
herein are driven by (6) and (8). Specifically, as VOV is made
more negative in moving from strong to moderate to weak
inversion operation to save power, C1 increases substantially
which decreases both p3 and PM.
Rc Cc
Vin Vout
+
V1 CL
R1 C1 R2
gm1Vin gm6V1
-

Fig. 6. Intrinsic PMOS small-signal voltage gain, AIP, vs. gm/ID. AIP = 36 dB
Fig. 4. Small-signal model of the two-stage OTA with Miller RC pole- for L= 300 nm and gm/ID = 8 S/A.
splitting pole-zero cancelling frequency compensation.
The thermal noise and u determine CC according to:
III. COMPARATIVE GM/ID DESIGNS FROM STRONG TO 𝑔𝑚
( )
MODERATE TO WEAK INVERSION 𝑆𝑛(𝑓) =
8𝐾𝑇𝛾
[1 +
𝐼𝐷 4
] (9)
𝑔𝑚
𝜔𝑢∙ 𝐶𝑐
The gm/ID methodology is now applied to the design of the ( )
𝐼𝐷 1
two-stage OTA wherein, for simplicity, fixed DC bias Including margins to absorb PVT variations, the input-
voltages (VB12 in Fig. 1 and VB5,7 in Figs. 1 and 2) are used in referred noise and UGB targets of Table I are tightened to
place of the PVT-based bias networks. The VOV of the PMOS
10 nV√Hz and 70 MHz, respectively.
input pair, M1-2, is varied by design from strong through 𝑔𝑚1
moderate to weak inversion; all other devices are maintained 𝑈𝐺𝐵 = (10)
2𝜋 𝐶𝑐
at a constant VOV in strong inversion. Target design
CC = 1 pF and 𝑔𝑚1−2 ≃ 0.44 mS from (9) and (10).
specifications are given in Table I.

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 The small-signal transconductance of the second stage,
gm6, is determined by the location of p2 that is, by design,
cancelled by z. In an optimum design, p2 is based on the
value of RC and doublet settling time considerations [7].
Herein, fp2 = 30 MHz is assumed for all seven designs. Thus,
from (2), gm6 ≃ 0.94 ms.
With gm1-2, gm6 and CC known, (5) gives RC ≃ 6.38 kΩ.
From (6), p3 determines PM for a given UGB. The
acceptable range for these designs is PM > 60° (Table I).
Including margins to accommodate PVT variations, a design
target of PM = 70° is chosen for all seven circuits. Assuming
for now that Cgg-M6 is dominant compared to Cdd-M2 and
Cdd-M4, (This assumption breaks down badly for M1-2
operating in weak inversion as shown later), C1 ≃ Cgg-M6. Fig. 9. DC bias currents of the PMOS input pair and parasitic capacitances
From (8), Cdd-M1-2, Cdd-M3-4 and Cgg-M6 that comprise C1 at the output of the first
𝑔𝑚6 stage vs. VOV values in strong, moderate, and weak inversion.
fT_M6 = (11) plotted. Whereas Cdd-M4 and Cgg-M6 remain relatively constant
𝐶𝑔𝑔_𝑀6
Thus, fT-M6 ≃ 1.2 GHz for PM = 70°. as VOV is reduced, Cdd-M2 becomes increasingly dominant for
For the NMOS devices, gm/ID = 9 S/A at VOV = 0.15 V VOV < -0.1V with a concomitant dramatic increase in small-
from Fig. 7 and from Fig. 8 the NMOS L should be < 900 nm. signal settling time as expected from Fig. 3. The key point is
Including margins, all seven designs are implemented with that if small-signal settling time is a critical, operation in deep
L = 700 nm. Using an AIN graph similar to Fig. 6 (not shown) weak inversion should be avoided for two-stage OTAs.
gives AIN = 43 dB. Av is computed from (4) for the worst- TABLE II. SIMULATION RESULTS VS. VOV
case with VOV = 0.1 V for M1-2 and the L values determined Case I II III IV V VI VII
above as AV = A1A2 = (54.6 V/V)(45.1 V/V) = 2462.2 V/V = VOV of M1-2 (V) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1
Gain (dB) 73 72.6 72 71 70 69 67
67.8 dB, which is comfortably above the target value.
Unity-gain BW 29.3 44 56.6 62 61.5 62 59
(MHz)
Phase margin (°) 14.6 33 55 66 72.2 73.5 75.3
Input-referred
noise @10MHz 10.6 10.6 10.7 10.8 11.4 11.7 13
(nV/√Hz)
First-stage 0.06 0.07 0.07 0.09 0.1 0.13 0.15
Power (mW)
Total power 0.24 0.25 0.25 0.26 0.28 0.31 0.33
(mW)
CC (pF) 1 1 1 1 1 1 1

IV. SIMULATION RESULTS AND DISCUSSION

Fig. 7. gm/ID vs. VOV for the NMOS devices. gm/ID = 9 for VOV = 0.15V for
all NMOS devices in these designs,.
Fig. 8. NMOS fT vs. gm/ID for a range of L values. fT ≃ 2 GHz at gm/ID = 9
S/A and L = 700 nm.
Fig. 9 illustrates the cause of the PM, and hence the
settling time failures at VOV < -0.1V. First, it shows the
relationship between the DC bias currents of the PMOS pair
vs. VOV. Clearly, little power is saved for VOV < -0.1V. More
importantly, parasitic capacitances Cdd-M2, Cdd-M4 and Cgg-M6
that contribute to C1 at the output of the first stage are also
Following the gm/ID design details determined above with
some simplifying assumptions, SPICE simulation results for
the seven designs with PMOS input pair VOV values ranging
from 0.1V (strong inversion) to -0.2V (deep weak inversion)
are summarized in Table. II.
These somewhat astonishing results show extreme
failures (highlighted in red) to meet the PM specifications at
VOV < -0.1V. There are two main reasons for the sharp
reduction in PM. First, the assumption that Cgg-M6 is the
dominant component of C1 no longer holds. It is true that
biasing the PMOS input pair in weak inversion gives higher
gm/ID, which enables less DC bias current. However,
VOV < -0.1V comes with the cost of much wider devices to
maintain gm at the lower current levels.
Although the results of Fig. 9 depict a severe problem for
deep weak inversion designs, some improvements in
performance can be achieved using non-standard layout
techniques for critical devices. Note from Fig. 9 that Cdd-M1,2
is by far the dominant parasitic that limits PM performance.
It is separated into two parts: Cdd-M1,2 = Cgd-M1,2 + Cdb-M1,2.
Cgd-M1,2 is, to a good approximation, constant for all three
regions of operation:
Cgd-M1,2 = CoverlapW (12)

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 TABLE. III. COMPARATIVE PM RESULTS FOR THE THREE
DIFFERENT LAYOUTS (FIG. 10) OF M1-2
STANDARD SHAPE
VOV of M1-2 (V) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1
Gain (dB) 73 72.6 72 71 70 69 67
Unity-gain BW 29.3 44 56.6 62 61.5 62 59
(MHz)
Phase margin (°) 14.6 33 55 66 72.2 73.5 75.3

FINGER SHAPE
VOV of M1-2 (V) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1
Gain (dB) 73 72.7 72 71 70 68.4 67
Unity-gain BW 33 47.5 58.6 63 60.6 61 58.3
(MHz)
W = 22 λ and L = 2 λ Phase margin (°) 14.5 36.5 58.7 68.4 73.5 74.6 75.8
AD = 6 λ x 22 λ = 132 λ2; PD = 2 x 6 λ + 22 λ = 34 λ
(a) U SHAPE
VOV of M1-2 (V) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1
Gain (dB) 73 72.7 72 71 70 69 67
Unity-gain BW 34.8 49 59.7 64.34 61.8 62.5 59
(MHz)
Phase margin (° 19 39.7 60.4 69 73.6 74.5 75.8

significantly increased compared to the standard layout, the

correspondingly large Css-M1,2 parasitic capacitance has no
effect on the performances of interest because it is connected
to the common source node of the input pair and is not in the
signal path.
W = 7λ x 3 = 21 λ and L = 2 λ The standard and U-shaped layouts have W ≃ 22 λ
AD = 2 x (6 λ x 7λ) = 84 λ2; PD = 4 x 6 λ + 7 λ = 31 λ whereas W = 21 λ for the 3-finger layout. L = 2 λ in all cases.
(b) Note that AD is reduced by nearly 4X from 132 λ2 (standard)
to 84 λ2 (3 fingers) to 36 λ2 (U-shape). In addition, PD is
reduced by nearly 6X from 34 λ (standard) to 31 λ (3 fingers)
to 6 λ (U-shape). These simple techniques do not cost any
additional power dissipation or require any design
modifications, but PM performance is improved as shown in
Table III.
V. CONCLUSIONS
Seven CMOS two-stage low-power OTAs were designed
using the gm/ID methodology. The VOV values of the PMOS
input-pair were varied from VOV = 0.1 V in strong inversion
to VOV = -0.2 in deep weak inversion. The key observation is
that as VOV, and thus the DC bias current in the first stage is
W = 22 λ and L = 2 λ reduced, which is desired to save power, the unity-gain PM
AD = 6 λ x 6λ = 36 λ2; PD = 6 λ decreases dramatically because of the much wider PMOS
(c) devices with correspondingly larger parasitic capacitances,
which is unacceptable. This somewhat surprising result
Fig. 10. Three different transistor layouts: (a) Standard, (b) multi-finger, and
(c) U shapes. occurs because the gate-capacitance of second stage gain
whereas Cdb-M1,2 is approximately [9] device (e.g., Cgg-M6), which is dominant in strong inversion,
is no longer the dominant in deep weak inversion. Instead, a
𝐴𝐷 𝐶𝐽 𝑃𝐷 𝐶𝐽𝑆𝑊
Cdb-M1,2 = 𝑉 + 𝑉 (13) large PMOS drain capacitance (i.e., Cdd-M2) becomes the
(1+ 𝐷𝐵 )𝑀𝐽 (1+ 𝐷𝐵 )𝑀𝐽𝑆𝑊 dominant component of C1. This effect leads to extreme PM
𝑃𝐵 𝑃𝐵
where AD and PD are the area and perimeter, respectively, of and small-signal settling time failures in weak inversion.
the drain diffusion. Two simple layout techniques (i.e., multi-finger and U
From (12), Cgd-M1,2 is fixed by the width of the PMOS shapes) were described that mitigate this effect. The bottom-
input pair, which follows from the design value of VOV. From line conclusion is that gain stages operated in deep weak
(13), however, Cdb-M1,2 depends on the AD and PD of M1-2. inversion may suffer catastrophic small-signal settling time
Thus, if they are reduced, not by design, but by layout, failures even though gain, bandwidth, noise, etc. performance
Cdd-M1,2 becomes a smaller contributor to the total parasitic goals are met.
capacitance, C1. Based on this observation, the AD and PD
values for three different transistor layouts with
approximately the same W and equal L values are compared
using universal λ layout rules with λ = 90 nm for the 180nm
CMOS process. Note that although AS and PS are both

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