MODELS OF THE FINITE STATE MACHINES

VALERI SOLOVJEV†, MARIUSZ CHYŻY‡

† Technical University of Białystok, Department of Computer Science, Wiejska 45 A,

15-351 Białystok, Poland.        † walsol@ii.pb.bialystok.pl,    ‡ marchy@bialystok.tpsa.pl

Abstract. This work considers eleven different structural models of Finite State Machines
(FSMs) which can be realized on modern programmable logic devices (PLDs) and complex
programmable logic devices (CPLDs). For each FSM structure valuations of the realization
are given. Timing diagrams for FSMs work in maximum operating frequency are analyzed.

Key Words. Models of finite state machines (FSM), logic design, programmable logic
devices (PLD).

1. INTRODUCTION Timing diagrams for SMs work in

In previous papers [4, 5] we considered
seven structural models of Finite State
Machines (FSMs) possible to implement
in programmable logic devices (PLDs).
Below we present eleven different models
of Finite State Machines (FSMs) which
can be realized on modern PLDs and
complex programmable logic devices
(CPLDs) [3, 6, 7].
Nowadays two models of state machines
(SMs) are well considered [1-3]: the
Mealy machine and the Moore one. Model
of the machine of class C is also known
[2]. In this machine, the output vectors
coincide with the codes of the SM's
internal states. Nonetheless not all-
possible SM models, allowing realization
on modern PLDs are still considered. The
influence of the output and input registers
on the SM work, issues of timing
coordination of signals transferred
between different machines et al. are also
not considered. These problems become
especially important when it is required to
reach the maximum speed of the device,
approaching to the extreme operating
frequency of the PLD.
maximum operating frequency are
analyzed.
2. STRUCTURES OF THE FINITE
STATE MACHINES
In practice, two models of SMs are the
most popular: the Mealy machine and the
Moore one. The behavior of the Mealy one
is described with the help of the equations:
at+1 = j(zt, at);
                  (1)
wt = y(zt, at);
here the transition function j defines the
next state at+1 of the machine, and the
output function y - the machine output wt.
The characteristic for the Mealy machine
is the fact that the output vector wt
depends on both the input zt and the
present state at.
In the Moore machine the output function
depends only on the present state a t and
does not depend on the input vector z t,
therefore the behavior of the Moore
machine is described by equations:

In this work different structural models of at+1 = j(zt, at);      

SMs are considered. Valuations of the (2)
realizations of each structure are given. wt = y(at).
At the implementation of the FSMs, their
transition functions j and output functions
y are realized with the help of the
combinational circuits CLj and CLy
respectively, and the memory of the
machine is realized as a register RG
which, in each moment of the machine
time t, stores a code of the internal state at.
The block diagrams of the Mealy and
Moore machines are shown in Fig. 1,a and
Fig. 1,b respectively. Peculiarity of the
Moore form is the fact, that the
combinational circuit CLy, realizing the
output function, has not direct
communication with the SM inputs.

For some machines the output vectors wt

coincide with the codes of the internal
state at. In this situation, it is the
characteristic kind of the Moore machine,
the behavior of which is described by
equations:

at+1 = j(zt, at);

(3)
wt = at .

This type of the SM is named as the

machine of class C [2], similarly the
Mealy (Fig. 1,а) and Moore (Fig. 1,b)
machines are called the machines of class
A and B, respectively. The structure of the
Moore form of class C is shown in
Fig. 1,c. Its feature is the absence of the
combinational circuit CLy, besides the
SM outputs are passed to the input of the
combinational circuit CLj. One should
note that the given structure is easily
realizable on PLDs, as all registered
outputs have feedbacks to the
combinational part of PLD.

Fig. 1. Basic FSMs structures: a) - Mealy

machine of class A; b) Moore machine of
class B; c) Moore machine of class C; d)
Mealy machine of class D

Some PLDs permit to use their registers in

a feedback loop (Fig. 1,d). This structure is
referred to as the machine of class D and
corresponds to the case, when the code of
the next state simultaneously defines the
SM output wt. The behavior the SM of
class D is described by equations:

at+1 = j(zt, at);

(4)
wt = at +1.

The distinction between the machines of

class C and D consists in the fact, that the
output wt of the machine of class C
coincides with a code of the present state
at, and the output wt of the machine of
class D defines a code of the next state a t+1.
In the machine of class C the output vector
wt is completely defined by a code of the
present state at. In this sense, the machine
of class C is the Moore one. In the
machine of class D the output vector w t is
defined by a code of the next state a t+1. As
the transition function depends on both:
the present state and on the input vector, so
the output of this machine also depends on
the present state and the input. Therefore
the machine of class D is the Mealy one.

For some devices it is important, that their

outputs be generated accordingly to
synchronization signal CLK. With this
purpose, models of machines with
additional output registers RGO (Fig. 2) are
used. Fig. 2 depicts the structure ABO with
the output registers RGO. It is common for
Mealy and Moore machines (the dashed
line designates the connection related to
the Mealy machine). There is no point in
inserting the additional output register into
the structure of the SM of class C, because
the SM's memory register RG fulfills its
role. The structure DO of the SM of class D
with the output registers is depicted in
Fig. 2,b.
Fig. 2. Structures of the FSMs with the
registered inputs: a) combined model AB O
of Mealy and Moore machines; b) model
DO of Mealy machine of class D
The structures in Fig. 3,a, Fig. 3,b and
Fig. 3,c define models of the SMs ABI, СI
and DI with the registered inputs. They
correspond to the SMs of classes A, B, C
and D (model ABI is common for the SMs
of classes A and В).
 Fig. 4. Structures of the FSMs with the
registered both inputs and outputs: a)
combined model ABIO of Mealy and
Moore machines; b) model DIO of Mealy
machine of class D

3. THE COMPLEXITY OF THE

REALIZATION

Let the FSM be characterized by number L

of input variables of set X = {x 1,..., xL}, by
number N of output variables of set Y =
Fig. 3. Structures of the FSMs with the
{y1,..., yN} and by number R of bits of a
registered outputs: a) combined model ABI
code of internal states, R = int log2 M,
of Mealy and Moore machines; b) model
where M – the number of SM internal
CI of Moore machine of class C; b) model
states. For valuation of the complexity of
DI of Mealy machine of class D
the realization of the considered SM
structures, it will be assumed, that R < N,
In some cases, one is forced to insert into
what is true for the majority of cases.
the SMs structures both input, and output
Table 1 shows parameters of the
registers (Fig. 4). The combined structure
considered classes of SMs from the point
ABIO (Fig. 4,а) corresponds to the SMs of
of view of complexity of their realization.
classes A and B, and the structure D IO
Types of inputs and outputs are marked
(Fig. 4,b) – to the Mealy machine of class
here as follows: c - combinational, r -
D. The SM of class C with the registered
registered.
inputs and outputs meets the structure С I
(Fig. 3,b).
Table 1. Complexity of the realization of
different SM models.
SM In Out Buried Input All Outputs,
model triggers buffers triggers inputs and
macrocells
A c c R - R L+N+R
B c c R - R L+N+R
 C c r - - N L+N as the SM period or simply as the period.
D c c N - N L+N In Fig. 5 the beginning of each period is
ABO c r R - N+R L+N+R defined by establishment of the stable
DO c r N - 2N L+2N internal state of the machine. In each
ABI r c R L L+R L+N+R period both the feedback signals,
CI r r - L L+N L+N determining the code of the SM's internal
state, and the input signals should be stable
DI r c N L L+N L+N
during the time tS before the active edge of
ABIO r r R L L+N+R L+N+R
the clock (CLK) is applied and must
DIO r r N L L+2N L+2N remain stable during the time t H after that.
The code of the following state will occur
The valuation of the total number of on flip-flop outputs after the time t CO since
inputs, outputs and buried triggers shows, the occurrence of the clock pulse.
that the most economic are the structures
of models C, CI, D and DI, and the least For the structure of the Mealy machine of
economic - structures of models D O and class A, the output vector wt will be
DIO. The fact of the matter is that for the worked out by the combinational circuit
realization of SM memory, models C and CLy after the time tPD since the
D do not require additional buried establishment of the SM's code and still
macrocell, as the memory in these will be stable for not less than t S + tH of
structures is realized directly by the output stability of the input vector z t. If the input
macrocells. However the placement of the signals of the vector zt will remain stable
registers on the output of the SM of class more than the time tS + tH, then the output
D additionally requires N macrocells, signals also will be stable longer.
therefore the structures DO and DIO are the
most uneconomic. For the correct SM operation, in each
period the input signals can change from
In the case when R > N, the structures C, the moment of time tS + tH since beginning
CI, D and DI become the most economic, of the period to the beginning of the
and the structures A, B, ABO, ABI and following period. In other time within the
ABIO – the least economic. limits of each period, the input signals
should be stable. Therefore, when it is
spoken [4], that the SM model of class A is
4. TIMING CONSIDERATIONS asynchronous in the sense, that the output
signals change together with the changes
We will consider the operation of various of input signals, it is not absolutely so. To
SM structures in real, instead of the assure the correct operation of the Mealy
machine's time and at maximum speed. machine of class A, the changes of the
input signals should be strictly agreed to
At the timing analysis of work of PLD, the the clock, hence, the changes of output
following parameters are important [4]: signals also will be agreed with the CLK
tCO – the clock-to-output delay; signal, i.e. the structure A seems to be the
tPD – the propagation delay; synchronous one. In the case when the
tS – the setup time; input signals can change at any moment,
tH – the hold time; the behavior of the Mealy machine of class
The minimum period tP of time of change A is unpredictable.
of SM states is determined by the value:
The output signals of the structure of the
tP = tS + tCO,     Moore machine of class B are formed on
                (5)
outputs of the combinational circuit CLy
after the time tPD since the establishment of
and the maximum frequency fmax of
the code of the SM state.
operation of the SM is defined by the
expression:
The output signals of the Mealy and
Moore machines of classes A and B within
fmax = 1/tP.
the limits of each period are formed
                  (6)
simultaneously, however the output signals
of the Moore machine of class B remain
The timing diagrams for the SM models
stable longer, than the output signals of the
for maximum operating frequency are
Mealy machine of class A, as in the
shown in Fig. 5. The length of time, when
structure B the output signals depend only
the SM is in a certain state, will be named
on the change of the state, and in the
structure A additionally on the change of
the input signals.
Fig. 5. Timing diagrams for the basic
FSMs structures for the FSMs with the
registered inputs and/or outputs
In the structure of the machine of class C
the output signals change simultaneously
with the change of the state, i.e. the time
tPD earlier, than in the structures of the
machines of classes А and В, as there is no
delay on the combinational circuit CLy.
Therefore, the machine of class C has the
highest speed in the sense of a moment of
formation of the output signals within the
limits of one period.
The output signals of the machine of class
D are formed in the same moment of time,
as in the structure A: after the time t PD
since establishment of a state and remain
stable when the input signals are stable.
In the structures of the machines AB O and
DO with the registered outputs the output
signals are formed as in the machine of
class C, but with one period delay. The
drawback of the structures ABO and DO
consists in one period delay of a sequence
of formed output signals.
For the stable work of the input registers
RGI the input signals zt should remain
stable during the time tS before the clock
pulse and the time tH after it. The input
signals of the vector zt1, taken from outputs
of the registers RGI, will be stable after the
time tCO since the clock pulse and will
remain stable till the beginning of the
following period. The change of values of
signals zt1 is preceded by a short period of
instability, explainable by the operation of
the register RGI.
For steady work of the other parts of the
structures ABI, CI and DI it is necessary,
that the input signals of the vector z t1 be
stable in each period for not less than t S +
tH. This condition is satisfied in PLDs by
fulfillment of the inequality: tCO > tH.
In the structures ABI, CI and DI transitions
are carried out in the beginning of each
period, but with one period delay in
comparison with the structures A-D. So
also the output signals will be formed with
one period delay: in the structures AB I and
DI after the time tPD since the change of the
state, and in the structure CI
simultaneously with the change of the
state.
The drawback of the structures ABI, CI and
DI with the registered inputs consists in the
fact that the machines will function with
one period delay. Besides the main
purpose: an opportunity of change of input
signals in any moment of time, is not
achieved. The fact of the matter is that for
the correct work of the registers RGI the
signals zt should change like in the
considered early structures: in strictly
certain moment of time within the limits of
each period.
Structures ABIO and DIO with registered
both inputs and outputs have all defects of
the structures with registered outputs and
registered inputs. The input registers cause
one period delay of SM work (the changes
of the states), and the output registers
cause the additional one period delay of
the formed output signals. Thus, the
structures ABIO and DIO generate the output
signals with two periods delay.
To buffer the input signals, which can
change in any moment of time, one should
apply latches instead of the flip-flops. The
structures ABI', CI', DI', ABIO' and DIO with
the latched inputs operate similarly to
structures ABI, CI, DI, ABIO and DIO with
the registered inputs, but on one period
faster.
input. The output signals for these
structures are formed simultaneously with
the establishment of the internal state of
the machine, i.e. with the beginning of the
next period. The structures A, B, D and the
ABI' and DI' with the latched inputs are the
following as regards the speed. The output
signals in these structures are formed after
the time tPD since the beginning of the
following period. The structures ABO, DO
and CI, and also ABIO' and DIO' with the
latched inputs work with one period delay.
Next, in terms of the speed, follow the
structures ABI and DI, the output signals of
which are formed in the subsequent period
with the delay time tPD. And the lowest
speed have the structures ABIO and DIO,
working with two periods delay.

Table 2. Results of the analysis of the SM

timing diagrams
SM Delay time since Duration of outputs
model the beginning of stability
the period
A tPD tS + tH
B tPD »tP
C 0 »tP
D tPD tS + tH
ABO tP »tP
DO tP »tP
ABI tP + tPD »tP
CI tP »tP
DI tP + tPD »tP
ABIO 2tP »tP
DIO 2tP »tP
ABI’ tPD tS + tH
CI’ 0 »tP
DI’ tPD tS + tH
ABIO’ tP »tP
DIO’ tP »tP

Fig. 6. Structure of the FSM with the

latched input (a) and timing diagrams for it
(b)

The results of the analysis of the timing

diagrams for the considered structures of
FSMs are indicated in Table 2. The most
high-speed is the machine of class C and
the structure of model CI' with the latched
For the majority of structures, the output
signals are stable during the time of
approximately one period tP (actually it is
a little bit less because of instability at
transitions). For the structures A, D, AB I'
and DI', the duration of the output stability
is smaller however the preservation of the
stability of the output signals during the
time tS + tH is guaranteed. When in these
structures the time of the stability of the
input signals is increased then the time of
outputs stability also increases, but does
not exceed the value of tP.

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Acknowledgements

This work has been performed in the

frameworks of the Rector's project No.
W/II/4/99 financed by KBN in the years
1996-1998.