Clock Dist

Keeping The Clock Pure
or alternately
Making The Impurities Digestible
“Timing is everything.”
© John Knight
Dig Cir p. 99 Revised; January 13, 2005 Slide 0
Carleton University © John Knight Vitesse

Digital Circuits p. 100 Revised; January 13, 2005 Comment on Slide 1
Timing Properties of Flip-Flops

Simultaneous Signal Changes.
Gate Two inputs change at once Fig. 1-1
Result: runt pulse
With Feedback
Latch
D Two inputs change at once
1/ Result: runt pulse may be captured
C 2
for a while
D Two inputs change, D a hair late.
C 1 Result: old D captured
D
Two inputs change, D a hair early.
C 0
Result: new D captured
δ Different internal delays

Runt level is generated when D and C D
change together at internal feedback loop. 1/
2
At inputs, changes are offset by δ. C
© John Knight
Flip Flop Timing Properties

Simultaneous changes
If two signals change at the same time, the gate output may change its mind, and cause the output to have a runt
pulse.
Simultaneous change in combinational circuits
In combinational circuits, these runt pulses are usually smoothed out as they pass through the next gate.
Simultaneous change in latches and flip flops
In latches and flip flops, the runt pulse may be fed back and captured in the feedback loop. This is unstable
storage, and will decay toward either a 0 or a 1, but it will sometimes stay for a clock cycle or more, enough to
corrupt the data.
Moving edges a picosecond apart will stop the runt pulse from being captured.
Simultaneous changes at flip flop inputs make the output indeterminate
However, if D changes too close to the clock edge, one cannot be sure if one will capture the desired old D
signal, capture 1/2, or capture the new D signal a clock cycle early. For this reason, we avoid changing D too
close to the clock active edge.

Restricted Region for a Family of FF
FIG. 1-2 .
10°C Many supposedly indentical flip-flops
D
C 20°C
D
0°C, C -10°C
D D
VDD=3.2V VDD=3.3V
C 40°C
δ C
-20°C, VDD=3.3V D
D C 60°C
D
VDD=3.0V VDD=3.4V D
C VDD=3.2V
C C
Run them over temperature range 70°C

D
Run over supply voltage range. C VDD=3.6V
Get all different internal δ. δ
δ = delay at which one gets the runt level.
δ
D Worst case δ, D after C
Specification for a
C restricted region around the clock edge
D where D must not change.
Worst case δ, D before C • Good for all ff of this design
C
• Good for temperature range
δ
• Good for VDD range
© John Knight
Timing Properties of Flip-Flops A Specification for how far to keep D from
A Specification for how far to keep D from C

For a single flip-flop the moving the change in D a picosecond or less will change one from successful D
capture, through the runt capture region, and into the premature capture of the new D signal.
Production (processing) variations
If δ is the delay between the C (clock) and D edges that puts one right in the middle of the runt-pulse region,
production variations will cause δ to be different even for flip flops of identical design.
Temperature and VDD variations
Temperature and supply voltage changes will cause further changes in δ.
Setting the spec
To make a specification for the design, one takes the flip flop and obtains the delay over supply voltage,
temperature and processing variations. From these one extracts the extreme δmax and δmin. From these the flip-
flop designer sets up a specification for how close D changes can be to C (clock) changes. If this spec. is obeyed,
the flip flop output will always be correct when operated within the VDD and temperature ranges.

Setup Time and Hold Time
FIG. 1-3 .
Flip-flops have a restricted region around the active clock edge

If the D changes in these regions,Q is idefinite.
Q may follow:
- the old D input,
- the new D input,
- take a runt “1/2” level.
Region where data must hold still
D INPUT Setup time Setup time

Hold time
D INPUT D Q Hold time (negative)
CLOCK C
CLOCK
Q
Setup time.........the interval before the clock where the data must stay stable.
Hold time ..........the interval after the clock where the data must stay stable.
Most modern flip-flops have a zero or a negative hold time.

Negative hold time.....data can change slightly before the clock edge and still be captured.
© John Knight
Timing Properties of Flip-Flops A Specification for how far to keep D from
Setup Time and Hold Time
The restrictive time region around the clock edge is given two time specifications:
Setup time. . . . . . . . . .the interval before the clock where the data must not change.
Hold time . . . . . . . . . the interval after the clock where the data must not change.
Circuit design is easier if the hold time is made short, preferably

long delay in D
zero or negative, so modern flip-flops usually have a zero hold time. delays
D D
The designer can slide the position of the restricted region by
adding delay in either the clock or data lead. Adding delay in the D C Q C
lead, for example means the setup time will be longer, since D must
delays D
arrive earlier to overcome the delay. However the hold time will D
decrease by the same amount. C Q long delay in C
With circuit synthesis, the logic synthesiser will check that that data
cannot change inside these two specifications.

Synchronous and Asynchronous Signals Fig. 1-4

Restricted Region
Summary of the Restricted Region
Restricted region: D INPUT
Time interval around clock edge Setup time
where D should not change. Hold time
CLOCK
Otherwise Q may not followD.
1) Q Q followed D
Synchronous Signals
2) Q Q did not follow D
Synchronous signal
A signal constrained so it cannot change Q went
3) Q metastable
in the restricted region.
Asynchronous signal
can and will change anywhere.
Sample D inputs.
The upper two are synchronous;
The one above the clock is asynchronous;
it has a transition inside the restricted region.
Restricted Region
Assume
D in they don’t
D Q D in; Synchronous become
CLOCK C asynchronous
D in; Synchronous
off stage.
D in; Asynchronous
CLOCK
Fig. 1-5
© John Knight
Timing Properties of Flip-Flops Synchronous Signals
Synchronous Signals
The signals which travel around inside digital circuits are synchronous.
It is fairly easy to make them synchronous with a limited knowledge of circuit delays.
Asynchronous signals may happen when:
• Signals come in from off chip.
• Signals come from a circuit driven by another clock.
• Signals generated by using the clock for something other than latches or flip flops,
for example gates in the clock lead,
or driving the select on a mux from the clock.

Clock-to-Output Propagation Delay, tCHQV
tprop(clk-to-output)
D
Time from active clock edge until Q changes.
Another name is tCHQV CLOCK
(time from Clock going High to Q becoming Valid). Q tCHQV
Any reasonable flip-flop will have Clock High to Q Valid
The Output Signal From a Clocked Flip-Flop is Always Synchronous

Any signal passing through a flip-flop is synchronous
if tCHQV > tHOLD.
Delay tCHQV, moves Q changes out of the restricted region.
The Q signal below is synchronous. It results from passing signal Din through a D flip-flop.
FIG. 1-6 The Q output is always synchronous, even if the input D is not.
Restricted Region
tHOLD tHOLD
Din; Asynchronous
tCHQV
Q; Synchronous tCHQV
D in D Q CLOCK
CLOCK C
If Q changes,
its changes will be a synchronous.
© John Knight
Timing Properties of Flip-Flops The Output Signal From a Clocked Flip-
The Output Signal From a Clocked Flip-Flop is Always Synchronous

Clock-to-output delay
The delay for a change in Q to reach the output from the clock edge.
Flip flop designers should make the clock-to-output delay longer than the hold time.
• One good way is to make the hold time zero. This saves adding delay in the flip-flop output, which
might slow down the circuit.
• Later we shall see that tCHCV > tHOLD is essential in shift registers.
A flip-flop output is synchronous
The output is synchronous even if the input is not. The flip flop only changes as a result of the clock. The clock-
to-output delay always moves the signal out of the restricted region for the next flip flop.
There are two exceptions:
• There areso many gates after the flip-flop the data change is delayed into the next restricted region in
the following flip-flops.
• The input causes a runt level to be captured. In this case we say the flip flop goes metastable. This is
considered in another set of notes.

Clock-to-Clock Logic Propagation Delays.

Maximum Logic Propagation Delays
Synchronous circuit are made of flip-flops with logic between them.
FIG. 1-7 One flip-flop feeding through logic into another flip-flop.
• Q1 takes tCHQV to get out of FF1.
• The propagation delay through the gate(s) is tPD.
• D2 must reach the FF2 at least tSETUP before the next clock edge.
tPD tSETUP
FF2
D1 Q1 Q2
D
D2
D tCLOCK ≥ tCHQV + tPD + tSETUP
C t CHQV C
tCLOCK
Alternative forms:
-
tPD ≤ tCLOCK - tSETUP - tCHQV

tPD(MAX) = tCLOCK - tSETUP - tCHQV
© John Knight
Timing Properties of Flip-Flops Maximum Clock-to-to-Clock Propagation
Maximum Clock-to-to-Clock Propagation Delay

This is the main timing constraint in digital circuits.
Not meeting this constraint is called a setup-time violation.

Minimum Logic Propagation Delays.
Happens when tCHQV < tHOLD.
tCHQV
Clock two flip-flops on the same edge.
D1 D Q1
For a long hold time,
FF1 can flip within the long tHOLD, C
and send its new output to FF2 FF1 tPD
fast enough to flip FF2 on the same clock edge.
D2
D Q2
To avoid double flips:- C
tHOLD ≤ tCHQV + tPD FF2
or
tPD ≥ tHOLD - tCHQV
Fig. 1-8
The minimum allowable propagation delay:-

tPD(MIN) = tHOLD - tCHQV
How can a FF have tCHQV < tHOLD?

If there were two flip-flop designs.
One FF1 could have a short tCHQV and FF2 a long tHOLD.
A slow rising edge on the clock could also do this.
© John Knight
Minimum logic propagation delay

A circuit which cannot meet this timing constraint is said to have a hold-time violation.
In circuits with any logic between flip flops, the logic delay is almost certainly enough so hold time violations
cannot occur.
Shift registers do not have logic between the flip flops. They are susceptible to hold-time violations.
Flip flops shold not have tCHQV < tHOLD
Properly designed flip flops do not. Not all flip flops are properly design. Also some very high-speed flip-flops
are so hard to make work, that this problem may be forgiven.

Minimum Propagation Delay; Different Picture.
The minimum delay appears when the hold time is longer than tCHQV.
Then:
D1 can flip Q1 of FF1,
and travel through the gate and reach FF2 inside its hold time.
FF2 may also change on the first clock edge!
tHOLD Excessively long hold time

tCHQV D1
D1 D Q1 tCHQV tCHQV
C tPD CLK tCHQV
CLK
FF1 Very small
Q1
D2 is just a little early, inside the
D2 tCHQV D2 hold time.
D Q2
C Q2 changed, when it should
tPD(MIN) Q2 have waited till the next active
FF2
clock edge.
tHOLD
tHOLD = tCHQV + tPD(MIN)
Fig. 1-9
© John Knight
Hold-Time Violations
Hold problems can be cured by inserting a pair of inverters in the offending lead. Synthesizers will do this
automatically if the fix-hold option is specified.

Digital Circuits p. 116 Revised; January 13, 2005 Comment on Slide 8n
Clock Skew.
Clock Skew.
Clock skew
When the clock edge does not reach all the flip-flops at the same time.
Positive skew
The data and clock are delayed in the same direction.
The right flip-flop receives the delayed clock.
D1 D Q1 D2 D Q2
tPD
C C
tSKEW
Fig. 1-10
Negative skew
The data and clock are delayed in opposite directions.
The right flip-flop receives the early clock.
D1 D Q1 D2 D Q2
tPD
C tSKEW C
Fig. 1-11
© John Knight
Clock Skew.

Clock Skew.
Positive Clock Skew Increases the Effective Clock Period
If there is a positive skew,

there is more time to get to FF2
FF1 FF2
D1 D D Q2
C C
tSKEW
CLOCK1 CLOCK2
tCLOCK
D1
tSKEW
CLOCK1
CLOCK2
Q2
tCLOCK + tSKEW
Fig. 1-12
© John Knight
Clock Skew.
Positive Clock Skew Increases the Effective Clock Period

Clock Skew.
Maximum Logic Delays With Clock Skew
Positive Skew Increases tPD(MAX)
With positive skew, there is more time to get to FF2,

tPD(MAX) is increased by the amount of the skew.
tCHQV tPD tSETUP

D1 D D Q2
C C
tSKEW
FF1 CLOCK1 CLOCK2 FF2
tCLOCK
D1 tSETUP
tSKEW
CLOCK1
CLOCK2
Q1
D2
tCHQV
tPD(MAX)
tSETUP
Q2
tCLOCK + tSKEW
Fig. 1-13
tCLOCK + tSKEW = tCHQV + tPD(MAX) + tSETUP
© John Knight
Clock Skew.
Maximum Logic Delays With Clock Skew

Clock Skew.
Minimum propagation delay limit with skew
With positive clock skew, the clock to FF2 is delayed.

• tSKEW acts like an increase in the hold time of FF2.
• Skew may make the effective tPD < tPD(MIN).
D1
(a)
CLOCK1
Gate with
tCHQV
Q1 tPD<tPD(MIN)
Q1
tPD
D1
D tCHQV
tPD(MIN)
C tPD
tSKEW CLOCK2
D2 D2 D2 is just inside the hold time

Q2
D tSKEW
Q2 Q2 changed too soon.
C
tHOLD
tCHQV + tPD ≥ tSKEW + tHOLD

tCHQV + tPD(MIN) = tSKEW + tHOLD
Fig. 1-14
© John Knight
Clock Skew. Maximum Positive Skew For A Shift
Maximum Positive Skew For A Shift Register

The minimum logic delay tPD(MIN) is worse with positive skew.
The minimum logic delay needed to avoid the restricted region is increased.
All flip-flops should have tCHQV ≥ tHOLD, so tPD(MIN) = 0. Note one cannot have a negative tPD.
With skew one may require tPD(MIN) > 0.
tSKEW + tHOLD = tCHQV + tPD(MIN)

⇒ tPD ≥ tHOLD + tSKEW - tCHQV
PROB 1.1 • FIND THE MAXIMUM DELAY IN THE CLOCK BUFFERS FOR THE SHIFT REGISTER SHOWN.
tCHQV=2 tCHQV=2
D1 Q1 tPD=0 D2 Q2 tPD=0 D3 Q3
D D D
tPD (Q to D) = 0 ns
C
tSKEW1-2 C tSKEW2-3 C
tCHQV = 2 ns max
CLOCK1 CLOCK2 CLOCK3 tHOLD = -1 ns min
Solution
For Q1 to D2 For Q2 to D3
tPD ≥ tHOLD + tSKEW - tCHQV tPD ≥ tHOLD + tSKEW - tCHQV
Delay CLOCK1 to CLOCK2
0 ≥ -1 + tSKEW1-2 - 2 0 ≥ -1 + tSKEW2-3 - 2 may be up to 3 ns.
tSKEW1-2 ≤ +3 tSKEW2-3 ≤ +3 Delay CLOCK1 to CLOCK3
may be up to6 ns.
tSKEW1-3 = tSKEW1-2 + tSKEW2-3 ≤ +6

Clock Skew.
Maximum Negative Skew For A Shift Register
The clock delays are opposite to the data delays,
tSKEW is negative.
PROB 1.2 Find the maximum delay in the clock buffers.

.
Fig. 1-15
tCHQV=2 tCHQV=2
D1 D Q1 tPD=0 D2 D Q2 tPD=0 D3 D Q3 tPD (Q to D) = 0 ns
C C C tHOLD = -1 ns min
tSKEW tSKEW
CLOCK1 CLOCK2 CLOCK3 tCHQV = 2 ns max
tSKEW is negative that is
Solution tSKEW = -|tSKEW|
For Q1 to D2
tPD ≥ tHOLD + tSKEW - tCHQV
0 ≥ -1 - |tSKEW1-2| - 2
+3 ≥ - |tSKEW1-2|
+3 ≥ tSKEW1-2 > - tCLOCK Pos skew can be up to 3 ns.
Any negative skew up to a clock cycle is ok
In shift registers, route the clock against the shift.
© John Knight
Shift Registers Should Have The Data Flow Opposite the Clock Flow

Clock Skew.
Maximum and Minimum Delay With Bounded Skew
Know max skew in clock network

Don’t know sign.
Must assume worst case sign,

positive when calculating tPD(MIN)
negative when calculating tPD(MAX).
Sumary of Min and Max tPD

Skew has unknown sign
For tPD(MIN) (use “+” skew) For tPD(MAX) (use “-” skew)
tPD ≥ tHOLD + tSKEW - tCHQV tPD ≤ tCLOCK + tSKEW - tSETUP - tCHQV
tPD(MIN) = tHOLD + |tSKEW| - tCHQV tPD(MAX) = tCLOCK - |tSKEW| - tSETUP - tCHQV
© John Knight
Allowed Logic Delays With Skew

PROB 1.2 • MAXIMUM AND MINIMUM DELAY WITH BOUNDED SKEW
Two registers of D flip-flops have a clock skew which is between -3 and 3 ns.
Q1 is the collective name for any or all outputs of the right-hand register.
D2 is the same for the inputs of the right-hand register.
Find tPD (MIN) and tPD (MAX).
tSKEW = tEDGE-CLOCK2 - tEDGE-CLOCK2
delay ≤ 3 |tSKEW| ≤ 3 ns
50 MHz tCLOCK = 20 ns
CLOCK1 CLOCK2
C1 C1 tHOLD = 0 ns min
D1 Q1 D2 Q2
1D COMBINATIONAL 1D tCHQV = 2 ns max
1D LOGIC 1D tSETUP = 4 ns max
delay ≤ 3 1D tPD(MIN) =? 1D
1D tPD(MAX) =? 1D
1D 1D
Solution:
For tPD(MIN) (use “+” skew) For tPD(MAX) (use “-” skew)
tPD ≥ tHOLD + tSKEW - tCHQV tPD ≤ tCLOCK + tSKEW - tSETUP - tCHQV
tPD(MIN) = 0 + 3 - 2 tPD(MAX) = 20 + (- 3) - 4 - 2
= 1 ns = 11 ns

Clock Skew.
Summary of Simple Propagation Delay Bounds
positive skew-
Clock delay in the same direction as data-flow delay.
tSKEW = tDESTINATION-CLOCK-EDGE - tSOURCE-CLOCK-EDGE
tPD(MAX) = tCLOCK + tSKEW - tCHQV - tSETUP
tPD(MIN) = tSKEW + tHOLD - tCHQV
Positive skew:
• allows longer logic delays
• forces the minimum delay to be longer.
Negative skew:
• allows a shorter minimum logic delay
• forces the maximum logic delays to be shorter.
Rule of thumb for maximum clock skew

a) Assume very fast paths between flip-flops tPD(MIN) =0.
b) Assume proper hold time in flip-flops tHOLD ≤ 0.
Approximate bound on skew is -
tSKEW ≤ tCHQV
© John Knight
Clock Skew. A Bound on Skew is Known but Not The
A Bound on Skew is Known but Not The Sign

A designer may have a good idea how much skew is in the clock system, but he/she may not know where the
individual flip flops will be connected, and cnnot tell the sign of the skew.
Then designs must be done so that either positive or negative skew is acceptable.

Gating the Clock
Gating the Clock

The Temptation To Gate The Clock.
A simple way to disable a flip-flop.
It may save area or power.
Problems:
1) Adds clock skew.
2) Can cause a false clock edge.
3) Full-scan testing will not test it.
4) Many synthesis tools and FPGAs do not support it.
FIG. 1-16 Two methods of disabling flip flops

(a) “Approved” method of enabling/disabling a D flip-flop.
No clock skew, no false clock edges, scan testable, tools support , FPGA support.
(b) Clock gating, the “high risk” way to enable/disable the flip-flop.
Saves power by not clocking nonflipping flip-flops.
(a) MU (b)
X INPUT 1D Q
1
1/1 1D Q ENABLE(H) C1
INPUT 1 G1 C1
CLOCK
ENABLE(H)
CLOCK
© John Knight
Gating the Clock A Bound on Skew is Known but Not The
Gating the Clock

To Gate or Not to Gate
There is a great temptation to gate the clock, particularly by inexperienced designers. Many of the reasons for
gating the clock are unnecessary, and not worth the troubles it causes.
The only common valid reason for gating the clock is to save clock power.
A common pseudo reason is a change in data rate. This is better done by using enabled flip flops, and disabling
the flip flops instead of gating the clock.
Tool Support
If you wish to gate the clock. check that your synthesis tool, and your test insertion/generation tools will support
it.

Gating the Clock
Problems from Clock Gating

Clock Skew From Gating the Clock
Clock skew reduces tPD margins.
Covered in last section.
False Clock Edges.
EN signal may cause false GCLK edges.
Changes in EN must be restricted.
FIG. 1-17 False clock edges caused by the EN signal rising while the clock is high.
EN will cause false clocking if it rises when the clock is high (φhigh).
EN should rise when clock is low (φlow).
Restricted Region
EN must not rise herein
INPUT Q EN
1D
EN Problem edge No problem Problem edge
C1
GCLK φlow
CLK CLK φhigh
GCLK
False clock edges

Proper (though skewed) clock edge
© John Knight
Gating the Clock Gating the Clock Causes Problems
Gating the Clock Causes Problems

Clock Skew
Adding Gates in the clock line causes skew. This will lower the bounds on the minimum and maximum
propagation delays through the logic, according to:
tPD(MIN) = tSKEW + tHOLD - tCHQV
tPD(MAX) = tCLOCK -| tSKEW| - tCHQV - tSETUP

Gating the Clock
Two Cases Of Clock Gating
Restrict EN changes to avoid false clock edges.
Case a) AND gate, NOR gate

EN may change only in the last half cycle
.
INPUT Q Q EN
IN
1D 1D
EN EN GCLK
C1 C1 CLK
CLK CLK No!
GCLK
Case b) OR gate, NAND gate

EN may change only in the first half cycle
IN Q INPUT (a) Q
1D
EN
1D
EN GCLK EN
C1 C1 CLK No!
CLK
CLK GCLK
© John Knight
FIG. 1-1 False clock edges, when the first half-clock-cycle is restricted
Restricted Region
(a) EN
IN 1D Q
EN GCLK C1 CLK φhigh No upward transitions
CLK
allowed in the restricted
GCLK
region ( φhigh).
OK edge False False
Restricted Region
(b)
IN 1D Q EN_N
EN_N GCLK C1 No downward transitions
CLK φlow
CLK allowed in the restricted
region ( φlow).
GCLK
OK edge False OK

Gating the Clock
Details of Gating With OR or NAND Gates

FIG. 1-18 False clock edges, when the second half-clock-cycle is restricted
Restricted Region
EN_N No upward transitions

IN Q
1D allowed in the restricted
EN_N GCLK CLK φlow
C1
CLK region (φlow).
GCLK
False OK
OK edge
Restricted Region
EN No downward transitions
INPUT Q
allowed in the restricted
1D
EN
CLK φhigh region (φhigh).
C1
CLK GCLK
GCLK
False False
OK edge
© John Knight

Gating the Clock
Clock Gating Summary TCLK/2 < tPD < TCLK
counter
D No glitches in first half
1) EN must not change in the first half cycle C
ENABLE_ON_7_COUNT
EN changes in the last half of the clock cycle. D
Gives more time to generate the EN, but C tPD INPUT Q
It has both an upper and lower bound on its delay. D 1D
It must be glitch free in the first half cycle. C
C1
This is very difficult to design! CLK
INPUT Q Q
1D EN 1D
EN EN_N
C1 C1
CLK CLK
2) EN must not change in the second half cycle

EN changes in the first half of the clock cycle.
The EN signal must be generated quickly within 1/2 cycle
It must be glitch free in the last half cycle but there it has settled down.
This is simple to design except for speed requirement.
Q EN Q
1D 1D
EN_N EN
C1 C1
CLK CLK
© John Knight
Gating the Clock Generating the Enable Signal
Generating the Enable Signal

With AND gating
If the EN signal has more than minimal complexity, it is hard to make it glitch free. See the unit on hazards with
multiple input changes.
Most logic is designed with only an upper bound on tPD. The lower bound is usually zero which is easy to
meet.
Consider a gate with tPD(min)=0.2, tPD(nom)=0.3, tPD(max)=0.4. tCLK=1.0.
Two of these gates in series easily meet the the max. specification, but violate the min. specification. This
illustrates that it is more difficult to meet the double specification.
Hazards
In the first half of the clock cycle, the flip flop outputs have recently changed, and it is difficult to avoid multi-
variable-change hazards.
With OR gating
Here the EN signal must be complete and stable in the first half of the clock cycle. However there is no
minimum timing specification to meet.
Hazards
In the second half of the clock cycle, the signal is stable, there are no changes to create new glitches, and the
circuit does not have to be hazard free.

Gating the Clock
Safe Clock-Gating Using a Latch. (safe except for skew!)
EN-RAW is latched and applied to an AND gate.

• Clock high (φ1):
Glitches in EN-RAW are stopped by the latch in store mode.
• Clock low (φ2):
Glitches in EN-RAW are stopped by the AND gate.
This method is good for shutting down a subcircuit for several cycles.
For example shutting off the floating point unit in a microcomputer.
FIG. 1-19 A clock gating method with no false clock edges.
Q1 and Q2 are enabled when EN-RAW is high.

The latch stops glitches when the clock is high.
The AND stops glitches when the clock is low.
TRANSPARENT COMB
SHUT LATCH LOGIC 1D Q1
DOWN Q3 EN
LOGIC 1D C1
EN-RAW GCLK
C1
CLK 1D Q2
GCLK
C1
© John Knight
Gating the Clock Generating the Enable Signal

Gating the Clock
FIG. 1-20 Waveforms for a gated clock with no false edges.
GCLK is enabled for EN-RAW high.
The latch ensures the EN will not change in the restricted region for AND type gating.
1st half LATCH

COMB CLK LATCH TRANSP’T LATCH
LOGIC
LATCH STORES STORES
SHUT 1D Q1
DOWN EN-RAW Q3 EN EN-RAW
LOGIC 1D C1
C1 EN
GCLK
CLK LATCH 1D Q2
GCLK ENABLED
C1
LATCH AND GATE

STOPS STOPS
GLITCH GLITCH
When gating the clock to save power:

• One normally gates many flip-flops at once.
For one flip-flop, the power for the extra latch may be more than the saving.
• One normally shuts off the clock for many cycles at a time.
The clock skew is minimized if an AND is placed in every clock line.
The full-scan test people will not like this.
© John Knight
Gating the Clock Gating With a Latch and a Gate
Gating With a Latch and a Gate

This method avoids:
• Critical timing in the EN generating logic
• Concern about glitches in the EN generating circuits
However:
• It still adds clock skew which reduces the bounds on the propagation delay.
• If used on one or two flip flops. the latch will consume more power than one saves by gating the clock.
Hence one needs to shut down a reasonable number of flip flops with one clock control.

Multiple Clocks
Multiple Clocks
Why Two Clock Frequencies?
The internal clock for (Pentium, Alpha, Power PC, Spark, Xeon) is too fast for the board circuitry.
With both slow and fast logic, save power by using a slow clock for the slow logic.
Basic Methods
Enabled Flip-Flops 1D
• Clock all flip-flops at high-speed and enable the flip-flops at a lower speed. EN
Is the safest (easiest) method. C1
Will not give much power saving.
Gate Clock
INPUT Q
• Gate the high-speed clock with a slower signal. 1D
Will give medium power reduction. EN
C1
Will use less power in the flip-flops, CLK
But:
Charging and discharging the clock line at high speed wastes power.
Gated clock are subject to false edges and skew.
Divide the clock
• Divider can supply different frequencies to different flip-flops.
Can give lower power. Q
But:- 1D
Watch skew between the main and divided clocks. CLK C1
Divider/counters may glitches which will poison clock lines. CLK/2
Q
© John Knight
Multiple Clocks Multiple Clocks
Multiple Clocks
Why not to use multiple clocks
• It saves having to make multiple clock distribution networks on chip.
These networks take a lot of space and are difficult to layout.
• It saves having to keep active edges synchronized within some small skew.
Why use multiple clocks
• Clocking flip flops faster than necessary for the data rate, wastes power.
• If two data rates are completely asynchronous, and their data rates are near the maximum clock speed
desired for the chip, it may be necessary to clock the data streams at their own clock rate.


Clock Dist

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Keeping The Clock Pure

Making The Impurities Digestible

Carleton University © John Knight Vitesse

Timing Properties of Flip-Flops

Result: runt pulse

D Two inputs change, D a hair late.

C 1 Result: old D captured

δ Different internal delays

Timing Properties of Flip-Flops

Flip Flop Timing Properties

Carleton University © John Knight Vitesse

Run them over temperature range 70°C

Timing Properties of Flip-Flops A Specification for how far to keep D from

A Specification for how far to keep D from C

Carleton University © John Knight Vitesse

Flip-ﬂops have a restricted region around the active clock edge

Region where data must hold still

D INPUT Setup time Setup time

Most modern ﬂip-ﬂops have a zero or a negative hold time.

Timing Properties of Flip-Flops A Specification for how far to keep D from

Setup Time and Hold Time

Circuit design is easier if the hold time is made short, preferably

Carleton University © John Knight Vitesse

Synchronous and Asynchronous Signals Fig. 1-4

Timing Properties of Flip-Flops Synchronous Signals

Carleton University © John Knight Vitesse

The Output Signal From a Clocked Flip-Flop is Always Synchronous

Timing Properties of Flip-Flops The Output Signal From a Clocked Flip-

The Output Signal From a Clocked Flip-Flop is Always Synchronous

Carleton University © John Knight Vitesse

Clock-to-Clock Logic Propagation Delays.

Synchronous circuit are made of ﬂip-ﬂops with logic between them.

tPD ≤ tCLOCK - tSETUP - tCHQV

Timing Properties of Flip-Flops Maximum Clock-to-to-Clock Propagation

Maximum Clock-to-to-Clock Propagation Delay

Carleton University © John Knight Vitesse

The minimum allowable propagation delay:-

How can a FF have tCHQV < tHOLD?

Timing Properties of Flip-Flops Maximum Clock-to-to-Clock Propagation

Minimum logic propagation delay

Carleton University © John Knight Vitesse

tHOLD Excessively long hold time

Timing Properties of Flip-Flops Maximum Clock-to-to-Clock Propagation

Carleton University © John Knight Vitesse

Carleton University © John Knight Vitesse

If there is a positive skew,

Positive Clock Skew Increases the Effective Clock Period

Carleton University © John Knight Vitesse

With positive skew, there is more time to get to FF2,

tCHQV tPD tSETUP

Maximum Logic Delays With Clock Skew

Carleton University © John Knight Vitesse

With positive clock skew, the clock to FF2 is delayed.

D2 D2 D2 is just inside the hold time

tCHQV + tPD ≥ tSKEW + tHOLD

Clock Skew. Maximum Positive Skew For A Shift

Maximum Positive Skew For A Shift Register

tSKEW + tHOLD = tCHQV + tPD(MIN)

Carleton University © John Knight Vitesse

PROB 1.2 Find the maximum delay in the clock buffers.

In shift registers, route the clock against the shift.

Clock Skew. Maximum Positive Skew For A Shift

Carleton University © John Knight Vitesse