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FPGA Implementation of LTE Physical Downlink Control Channel under MIMO

Technique

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 RESEARCH ARTICLE Adv. Sci. Lett. 21, No. 1, 2015

Copyright © 2015 American Scientific Publishers Advanced Science Letters

All rights reserved Vol. 21, No. 1, 2015
Printed in the United States of America

FPGA Implementation of LTE Physical Downlink

Control Channel under MIMO Technique
M.A. Mohamed1, H.M. Abd-Elatty2, M.E.A. AboEl-Seoud1, W.M. Raslan4

1,3
Electronics & Communications Engineering Department, Faculty of Engineering, Mansoura University, Egypt
2
Electrical Engineering Department, Faculty of Engineering, Port-Said University, Egypt
4
Electronics & Communications Engineering Department, Faculty of Engineering, Sinai University, Egypt

The main objective of this paper is implementation of both transmitter and receiver of Physical Downlink Control Channel
(PDCCH). The design process of PDCCH transmitter and receiver are carried out in architecture under Multiple Input
Multiple Output (MIMO) 2×2 antenna configurations. Xilinx Spartan3E XC3S500E board and Xilinx Integrated Simulation
Environment (ISE) tool are used to accomplish our chip design and algorithm verification work. Simulation of the
transmitter and receiver are carried out by using ModelSim SE 6.5. Based on simulation and implementation, results are
discussed in terms of Register Transfer Level (RTL) design, FPGA editor, power estimation and resource estimation. The
results can be further improved in term of speed, no. of registers, and frequency.

Keywords: Long Term Evolution (LTE), Physical Downlink Control Channel (PDCCH), Downlink Control Information
(DCI), Multiple Input Multiple Output (MIMO), Field Programmable Gate Array (FPGA), Register Transfer Level (RTL).

1. INTRODUCTION The PDCCH supports four formats numbered from 0, 1, 2,

and 3 as shown in Table 18. Each CCE has 9 REGs in
LTE is the fourth generation technology aiming at PDCCH. Format of 0 carries 72 PDCCH bits.
faster data downloading and uploading, higher throughput,
reduced power consumption, efficiency and flexibility1.
LTE downlink physical channels include three control
channels and three transport channels2. The control
channels are needed for the successful reception,
demodulation, decoding of the data transmitted3. The
main downlink control channel is PDCCH, which carries
the Downlink Control Information (DCI) which is
transmitted as an aggregation of Control Channel
Elements (CCEs)4. CCEs consists of Resource Element
Groups (REGs) each containing four Resource Elements
(REs) with a RE carrying two bits5. PDCCH carries
information about the Resource Block (RB) allocation,
modulation, coding scheme and power control
information6. PDCCH occupies the first 1, 2, 3 OFDM
symbols of a subframe as shown in the Figure 1 7.
The DCI and PDCCH are having specific formats. Fig.1. Resource Element Groups (REGs).
29 Adv. Sci. Lett. Vol. 21, No. 1, 2015 1936-6612/2015/4/400/008 doi:10.1166/asl.2015.5740
Adv. Sci. Lett. 21, No. 1, 2015 RESEARCH ARTICLE

Table.1. PDCCH Format.

PDCCH Number of Number of Number of
Format CCEs REGs PDCCH bits
0 1 9 72
1 2 18 144
2 4 36 288
3 8 72 576

The DCI information is generated in particular

formats9. Each format contains a specific set of
information and has a specific purpose.
In earlier cases, the previous work10 shows the design
and implementation of PDCCH under SISO environment
using Virtex-5 FPGA. In previous work6 implements a
Single Input Single Output Architecture for the
Fig.2. Physical Channel Processing of PDCCH.
transmission and reception of three control channels of
LTE (PDCCH, PHICH and PCFICH) using Virtex 5 b  i    b  i   c  i   mod2 (1)
board for Implementation.
The objectives of this paper are proposed HDL design where b(i) is the original information and the scrambling
of transmitter and receiver architecture of LTE PDCCH sequence c(n) is given by
 
for 2×2 MIMO, Realize a design using VHDL language,
implement this design on a FPGA, verify and test for its c n   x1 n   x2 n  mod2 (2)
functionality, and analyze its performance.
FPGAs are flexible and reconfigurable integrated where x1(n) and x2(n) are generated using (3) and (4)
circuits, the high speed, parallel architecture provides
complete control over the degree of parallelism in the 
x1 n31  x1 n3  x1 n  mod2  (3)
design. Many recent high speed digital signal processing
  x  
 x2 n 2  x2 n1  x2 n  mod2 (4)
applications such as networking and mobile x2 n31 2 n  3
communications are implemented by using FPGA11.
This paper is organized as follows. In section 2, each
The scrambling sequence generator shall be initialized
block of transmitter and receiver architecture and the idea
with
of its implementation are explained in brief. In section 4,
the implementation of overall of the transmitter and cinit   ns / 2 29  N ID
cell
(5)
receiver architecture with RTL design, simulation results
and resource utilization are explained. Finally, the major where ns is the slot number within a radio frame and
cell
conclusion is discussed in section 5. N ID the physical layer cell identity12.

2. SYSTEM DESIGN MODEL 2.3. Modulation

The PDCCH transmitted and received physical QPSK modulation is used in PDCCH as in Table 2.
channel processes are summarized in Figure 2. Figure 3 The implementation of modulation and demodulation has
and Figure 4 show transmitter and receiver architecture been done using LUT‟s table.
respectively. Table.2. QPSK Modulation.
, I Q
2.1. Multiplexing 00 1/ 1/
01 1/ -1/
The coded DCI bits are multiplexed to generate a 10 -1/ 1/
format payload according to Table 1. 11 -1/ -1/

2.2. Scrambling 2.4. Layer Mapping

Significance of this module is making the data as The complex-valued modulation symbols for each of
unintelligible to the intruder. To achieve this, pseudo the codewords to be transmitted are mapped onto two
random gold sequence is generated continuously at the layers as shown in Figure 57 and the mapping is defined
transmitter. The incoming data and gold sequence are by
logically combined using XOR operation to generate the
x  0  i   d 0  2i  (6)
scrambled bits. Mathematically, it is given by 8.
x 1  i   d 0  2i  1 (7)
30
 RESEARCH ARTICLE Adv. Sci. Lett. 21, No. 1, 2015

 
layer
with Msymb  Msymb
0
/2 The precoding matrix for the two antenna case is
given in by8
The implementation of layer mapper in transmitter is  (0) 
 y (2i )   Re( (0)) 
x (i ) 
carried out using serial to parallel converter and shift  (1)   1 0 j 0 
 y (2i )  1 0 1 0 j  Re( x ( i ) ) 
 (1)
register. The implementation of the delayer mapper in
     (8)
receiver is carried out using parallel to serial converter  y (0)  2 0 1 0 j   im( x (0)) 
and shift register.  (2i 1)    (i ) 

 (1)  1 0  j 0   (1) 

2.5. Precoding
Precoding is the means of achieving transmitter
diversity. The layer mapped symbols are multiplied with
the precoding matrix in which the columns are orthogonal
to each other so that the transmitted symbols won‟t
interfere 15.
 y (2i 1)   im ( x (i )) 
 
The implementation of precoder has been done using
parallel to serial converter and number of shift registers
equal to the number of antennas and decoder has been
implemented using serial to parallel converter and shift
register. Figure 6 shows the precoder and resource
element mapping.

Fig.3. Transmitter Architecture for PDCCH.

Fig.4. Receiver Architecture for PDCCH.

31 Adv. Sci. Lett. Vol. 21, No. 1, 2015 1936-6612/2015/4/400/008 doi:10.1166/asl.2015.5740

Adv. Sci. Lett. 21, No. 1, 2015
Fig.5. Layer Mapper.
Fig.6. Precoder and RE Mapping.
2.6. OFDM
Figure 7 shows the block diagram of Orthogonal
Frequency-Division Multiplexing (OFDM) block.
Fig.7. Block diagram of OFDM block
The shift registers is responsible for arranging the
data in the OFDM symbol and by this we construct our
time slot we which to transmit.
The Inverse Fast Fourier Transform (IFFT) core acts
as an orthogonal carriers generator and after the OFDM
symbol comes out from it each subcarrier in it will be
orthogonal on the other thus transmission can be made in
a narrow Bandwidth. The FFT/IFFT core is an IP CORE
solution from Xilinx, which can be used to perform both
direct fast Fourier transform and the inverse transform13.
Write counter is used to write data in the registers
and read counter is used to read from the registers and
sends the data to the IFFT block.
The controller responsible for informing IFFT core
to start trans-form the data and give read counter enable
to begin to read data from registers. IFFT controller is
implemented using finite state machine technique.
3. ASSUMPTIONS
The basic assumptions are used in the design are
shown in Table 3. A minimal channel bandwidth of about
1.4 MHz is assumed with 6 physical resource blocks out
of the available bandwidths (1.4, 3, 5, 10, 15 and 20). The
RESEARCH ARTICLE
subcarriers are placed with a spacing of 15 kHz. Normal
cyclic prefix assumed.
Table.3. Assumptions of the Design
Parameter Assumption
Channel Bandwidth 1.4 MHz
Number of Physical RBs 6
Subcarrier Spacing 15 kHz
Cyclic Prefix Normal
Frame Structure FDD
Number of Antenna Used 2
4. RESULTS AND DISCUSSION
In a typical design flow, multiple stages of the design
process are as follows:
 Design Entity: VHDL are used to design the
architecture of the system14.
 Behavioral Simulation: By using behavioral
simulation we can verify the functionality of the code
designed for our system. The simulation has been done
by using ModelSim SE6.5.
 Synthesis: The synthesis process includes the
compilation of the sub-modules in the main module
and the analysis of the hierarchy of the design15.
 Design Implementation: It includes the following three
processes (Translation - Mapping - Place & Route)
Figure 8 shows simulation of transmitter and Figure 9
shows simulation of receiver.
The variables "clk", "reset", "en" is the inputs given,
and transmitter and receiver can send and receive the
information if reset is disabled. If the variable „reset‟ is
enabled, all the channels are setting for their initial value
again.
For the transmitter, the “scr_out_s” is the scrambled
output for the channel and give as input to QPSK
modulation module. Variables “qpsk_real_s” and
“qpsk_img_s” are the modulated output of the QPSK
modulation module. The layer mapped output is given by
“m_o_r1” and “m_o_im2” for the antenna 1 and
“m_o_r2”and “m_o_im2” for the antenna 2, while the
precoded output are “p_o_r1” and “p_o_im1” for the
antenna1 and “p_o_r2” and “p_o_im2” for the antenna2.
The final transmitted output through the antenna is given
by “xk0_re” and “xk0_im” for antenna 1and “xk1_re”
and “xk1_im” for antenna 2, which are the output from
the the Xilinx LogiCORE IP FFT using two channel.
For the receiver, the variables “xn0_re”and “xn0_im”
are the input to the FFT from antenna 1 and variables
“xn1_re” and “xn1_im” are the input to the FFT from
antenna 2. “xk0_re_s”, “xk0_im_s”, “xk1_re_s” and
“xk1_im_s” are the inputs to the decoding block. The
variables “del_out_real_s” and “del_out_img_s” are the
output from the delayer mapper and input to the
descrambling block. Gold sequence same as that in the
transmitter is generated using slot number and physical
layer cell ID. It is used to descramble the decoded bits.
Finally, variable “data_out” is the output from the
receiver.
30
 RESEARCH ARTICLE Adv. Sci. Lett. 21, No. 1, 2015

Fig.8. Simulation Output for PDCCH Transmitter under 2x2 MIMO.

Fig.9. Simulation Output for PDCCH Receiver under 2x2 MIMO.

The RTL diagram for the transmitter and receiver is 5. CONCLUSION
shown in Figure 10 and 11.
The resource estimation of synthesizing transmitter In this paper, we successfully implement the transmitter
and receiver designs using Xilinx synthesis technology and receiver of PDCCH channel under transmit diversity
tool are tabulated in table 4 and table 5. technique using FPGA. The design architecture of
Table.4. Resource Estimation - Transmitter transmitter and receiver of downlink PDCCH channel
Device Utilization Summary (estimated values) under MIMO (2×2) environment coded in VHDL
Logic Utilization Used Available Utilization
No. of Slices 1054 4656 22% language. The simulation of physical channel processing
No. of Slice Flip Flops 1658 9312 17% that consists of steps scrambling, modulation, layer
No. of 4 input LUTs 1142 9312 12% mapping, precoding and mapping to resource elements,
No. of bonded IOBs 71 232 30% demapping from resource elements, decoding, delayer
No. of BRAMs 3 20 15% mapping, demodulation and descrambling are carried out
No. of MULT18X18SIOs 4 20 20%
using ModelSim SE 6.5. The implementation of the
No. of GCLKS 1 4 4%
downlink transmitter and receiver architecture of PDCCH
Table.5. Resource Estimation - Receiver
Device Utilization Summary (estimated values)
is synthesized using Xilinx ISE 10.1 and realized using
Logic Utilization Used Available Utilization Xilinx Spartan3E XC3S500E board. The results are
No. of Slices 991 4656 21% discussed in terms of resources estimation and RTL
No. of Slice Flip Flops 1567 9312 16% schematics and show that the proposed HDL design and
No. of 4 input LUTs 1089 9312 11% implementation is more effective.
No. of bonded IOBs 70 232 30%
No. of BRAMs 3 20 15%
No. of MULT18X18SIOs 4 20 20%
No. of GCLKS 1 4 4%
33 Adv. Sci. Lett. Vol. 21, No. 1, 2015 1936-6612/2015/4/400/008 doi:10.1166/asl.2015.5740
Adv. Sci. Lett. 21, No. 1, 2015 RESEARCH ARTICLE

Fig.10. RTL Design of PDCCH Transmitter for Two antennas.

Fig.11.RTL Design of PDCCH Receiver for Two antennas.

the 3GPP-LTE Physical Control Channels”, EURASIP Journal
on Wireless Communications and Networking, Vol. 2010, Article
REFERENCES ID 914934, Nov. 2010.
[6] S.S. Ameer Abbas, K. S. Geethu and S. J. Thiruvengadam,
[1] http://www.3gpp.org/LTE "Implementation of SISO Architecture for LTE Downlink
[2] “Introducing LTE Advanced”, Agilent Technologies Applica-tion Control Channels in Virtex 5.", International Journal of
Note 5990-6706EN, November 2010. Engineering and Innovative Technology (IJEIT) Vol.1, Issue 5,
[3] D.G. Gonzalez, M.G. Lozano, and S.R. Boque. "Intercell May 2012, pp:195-201.‫‏‬
Interference Coordination for the ePDCCH in LTE-Advanced [7] Khan Farooq, “LTE for 4G mobile broadband: air interface
Macrocellular Deployments.", ICWMC 2013, The Ninth technologies and performance”, Cambridge University Press,
International Conference on Wireless and Mobile 2009, pp: 371-372.
Communications, pp: 200-208, 2013. [8] 3GPP Technical Specification Group Radio Access Network;
[4] S.S. Abbas, S.J. Thiruvengadam, “FPGA Implementation of Evolved Universal Terrestrial Radio Access (E-UTRA); Physical
3GPP-LTE Physical Downlink Control Channel Using Diversity channels and Modulation (Release10),” 3GPP TS 36.211 v
Techniques,” WSEAS Transactions on Signal Processing, Vol. 9 10.0.0 (2010-12).
Issue 2, pp84-97, Apr2013. [9] COX. Christopher, “An introduction to LTE: LTE, LTE-
[5] S.J. Thiruvengadam, M.A. Jalloul, “Performance Analysis of advanced, SAE and 4G mobile communications”, Wiley2012.
34
 RESEARCH ARTICLE Adv. Sci. Lett. 21, No. 1, 2015

[10] S.S. Ameer Abbas, K. S. Geethu and S. J. Thiruvengadam,

“Realization of Physical Downlink Control Channel (PDCCH)
for LTE under SISO Environment using PlanAhead Tool and
Virtex 5 FPGA”, IJETAE, Apr2012, Vol.2, Issue 4, p173-182
[11] M.A. Mohamed, A.S. Samarah and M.I. Fath Allah,
“Implementation of the OFDM Physical Layer Using FPGA”,
IJCSI International Journal of Computer Science, Vol.9 Issues 2,
pp612-618, March2012.
[12] 3GPP Technical Specification Group Radio Access Network;
Evolved Universal Terrestrial Radio Access (E-UTRA);
Multiplexing and channel coding (Release10)”, 3GPP TS 36.212
v 10.0.0 (2010-12).
[13] http://www.xilinx.com/ipcenter/fft/software_requirements.htm
[14] http://www.xilinx.com/support/documentation/sw_man
uals/xilinx11/sim.pdf
[15] K. C. Chang, “Digital systems design with VHDL and synthesis”.
IEEE computer society press, 1999.‫‏‬

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