Vl390 For Ubtx: Clock Gen SLG8LP625

1
VL390 FOR uBTX CPU:

AMD AM3
Cover Sheet 1
BLOCK DIAGRAM 2
GPIO Configuration 3
Clock Distribution 4
Power Deliver Chart 5 System Chipset:
AMD - RS780(North Bridge)
VRM Intersil 6323 3 Phase 6
AMD - SB710 (South Bridge)
AMD Socket AM3 7~9
On Board Chipset:
DDR III DIMM 1 & 2 & 3 & 4 10 ~ 11
BIOS - SPI
Clock Gen SLG8LP625 12 Azalia CODEC - Realtek ALC662(Default)/888
AMD - RS780 13 ~ 16 LPC Super I/O -- ITE8720
CLOCK GEN --SLG8LP625
AMD - SB710 17 ~ 21
LAN-Realtek 8111CP
A
DVI / VGA Connector 22 TMP - INFINEON/SLB9635T A
SATA/KB/ FAN Control 23

LAN-Realtek 8111CP 24
LPC I/O ITE8720 25
Main Memory:
ACPI UPI & SYS POWER 26
DDR III * 4
Core Power & DDR Power 27
Expansion Slots:
Azalia CODEC ALC662/888 28
PCI Express X16 Slot * 1
USB CONNECTORS 29 PCI Express X1 Slot * 1
PCI EXPRESS X16 & X 1 SLOT 30 PCI 2.3 Slot * 2
PCI Slot 1&2 31 Intersil PWM:
TMP 32 Controller - Intersil 6323 3 Phase
ATX & Front Panel 33
Auto BOM Manual 34
History 35
MICRO-START INT'L CO.,LTD.
History 36 Title
COVER SHEET
Size Document Number Rev
Custom VL390 0A
Date: Tuesday, September 09, 2008 Sheet 1 of 37
1
5 4 3 2 1
Project RS-780 BLOCK DIAGRAM
DDRIII 800~1333 UNBUFFERED UNBUFFERED

AMD AM3 128bit DDRIII DIMM1 10 DDRIII DIMM3 11
D D
AM3 SOCKET DDRIII 800~1333 UNBUFFERED UNBUFFERED

7,8,9 128bit DDRIII DIMM2 10 DDRIII DIMM4 11
OUT
DDRIII FIRST LOGICAL DIMM DDRIII SECOND LOGICAL DIMM
HyperTransport LINK 16x16 2.6GHZ(HT3)
IN
Display Port
ATI NB - RS780
HyperTransport LINK0 CPU I/F
1 16X PCIE VIDEO I/F
1 4X PCIE I/F WITH SB
PCIE GFX x16 PCIE x16
31 2 1X PCIE I/F
C C
4X1 PCIE INTERFACE

13,14,15,16
Gbit ETHERNET
IEEE-1394 8039/8056 PCIE x1 SLOT1,2
23 /8071/8075 25 31
A-LINK
4X PCIE
USB-5 USB-4 USB-3 USB-2 USB-1 USB-0 HD AUDIO HDR 29

REAR REAR REAR REAR REAR REAR USB 2.0
ATI SB - SB710
AZALIA
30 30 30 30 30 30 USB2.0 (12)
AZALIA CODEC 29
SATA2 (4 PORTS)
USB-9 USB-8 USB-7 USB-6 AC97 2.3
HDR HDR HDR HDR
HD AUDIO 1.0
30 30 30 30
ACPI 1.1 SERIAL ATA 2.0 SATA#0 SATA#1 SATA#2 SATA#3
B B
SPI I/F 24 24 24 24
PCI/PCI BRIDGE
ASF
PCI BUS
SPI Bus SPI ROM 8M
19
17,18,19,20,21
PCI SLOT
30
CPU CORE POWER

ACPI CONTROLLER NB CORE POWER
Intersil ISL6323 LPC BUS
UPi Intersil ISL6612A 6
27
CPU VLDT Power

CPU VDDR Power TPM
CPU VDDA Power ITE SIO IT8720 33
DUAL POWER 26
NB & SB POWER
A
27 A
DDR3 DRAM POWER

RS780 CORE POWER 28
FLOPPY KBD SERIAL MICRO-START INT'L CO.,LTD.
MOUSE PORT Title
26 24 26 BLOCK Diagram
ATX CON
34 Size Document Number Rev
Custom VL390 0A
5 4 3 2 1
5 4 3 2 1
SB700/710 GPIO Config SIO IT8720 GPIO Config

GPIO Name Type Function description Pin GPIO Name Type Function description Pin
CLK_REQ0#/SATA_IS3#/GPIO0 3.3V Not connected(internal pull-down) VDIMM_STR_EN / PCIRST3#/GP10 3.3V Not connected(internal pull-down)
SPKR/GPIO2 SPKR SPKR/GPIO2 SPKR
FANOUT0/GPIO3 Not connected (internal PU to +3.3V_S0) FANOUT0/GPIO3 Not connected (internal PU to +3.3V_S0)
SMARTVOLT/SATA_IS2#/GPIO4 CPU_PRESENT#:CPU present detect SMARTVOLT/SATA_IS2#/GPIO4 CPU_PRESENT#:CPU present detect
SHUTDOWN#/GPIO5 R377 10KR to GND SHUTDOWN#/GPIO5 R377 10KR to GND
CLK_REQ3#/SATA_IS1#/GPIO6 Note1 CLK_REQ3#/SATA_IS1#/GPIO6 Note1
D D
DDC1_SDA/GPIO8 Note1 DDC1_SDA/GPIO8 Note1
DDC1_SCL/GPIO9 Note1 DDC1_SCL/GPIO9 Note1
SATA_IS0#/GPIO10 Note1 SATA_IS0#/GPIO10 Note1
SPI_DO/GPIO11 SPI_DATAOUT SPI_DO/GPIO11 SPI_DATAOUT
BMREQ#/REQ5#/GPIO68 SPI_DATAIN BMREQ#/REQ5#/GPIO68 SPI_DATAIN
LAN_RST#/GPIO13 Reserve TP LAN_RST#/GPIO13 Reserve TP
ROM_RST#/GPIO14 Not connected (defaults to output driven low) ROM_RST#/GPIO14 Not connected (defaults to output driven low)
GPIO[30:15]/IDE_D[15:0] Not connected GPIO[30:15]/IDE_D[15:0] Not connected
SPI_HOLD#/GPIO31 SPI_HOLD_L SPI_HOLD#/GPIO31 SPI_HOLD_L
SPI_CS#/GPIO32 SPI_CS# SPI_CS#/GPIO32 SPI_CS#
CLK_REQ1#/GPIO39 Not connected (internal pull-down). CLK_REQ1#/GPIO39 Not connected (internal pull-down).
CLK_REQ2#/GPIO40 Not connected (internal pull-down) CLK_REQ2#/GPIO40 Not connected (internal pull-down)
PCICLK5/GPIO41 Terminated with a strapping resistor PCICLK5/GPIO41 Terminated with a strapping resistor
AZ_SDIN0/GPIO42 SDATA_IN_R AZ_SDIN0/GPIO42 SDATA_IN_R
AZ_SDIN1/GPIO43 Not connected (internal pull-down) AZ_SDIN1/GPIO43 Not connected (internal pull-down)
SPI_CLK/GPIO47 SPI_CLK SPI_CLK/GPIO47 SPI_CLK
GPIO[49:48]/ FANOUT[2:1]] Not connected (internal pull-up to +3.3V_S0) GPIO[49:48]/ FANOUT[2:1]] Not connected (internal pull-up to +3.3V_S0)
C C
GPIO[52:50]/ FANIN[2:0] Note1 GPIO[52:50]/ FANIN[2:0] Note1
GPIO[60:53]/ VIN[7:0] Note1 GPIO[60:53]/ VIN[7:0] Note1
GPIO[63:61]/ TEMPIN[2:0] Note1 GPIO[63:61]/ TEMPIN[2:0] Note1
GPIO64/ TALERT#/ TEMPIN3 TALERT# GPIO64/ TALERT#/ TEMPIN3 TALERT#
GPIO65/ BMREQ#/ REQ5# Note1 GPIO65/ BMREQ#/ REQ5# Note1
GPIO66/ LLB# LC_SENSE GPIO66/ LLB# LC_SENSE
GPIO67/ SATA_ACT# SATA_LED# GPIO67/ SATA_ACT# SATA_LED#
GPIO68/ LDRQ1#/ GNT5# Reserve TP54 GPIO68/ LDRQ1#/ GNT5# Reserve TP54
GPIO[71:70]/ REQ[4:3]# Not connected (internal pull-up to +3.3V_S0) GPIO[71:70]/ REQ[4:3]# Not connected (internal pull-up to +3.3V_S0)
GPIO[73:72]/ GNT[4:3]# Not connected (defaults to output HIGH). GPIO[73:72]/ GNT[4:3]# Not connected (defaults to output HIGH).
GPOC0#/ SCL0 SCLK GPOC0#/ SCL0 SCLK
GPOC1#/ SDA0 SDATA GPOC1#/ SDA0 SDATA
GPOC2#/ SCL1 SCLK1 GPOC2#/ SCL1 SCLK1
GPOC3#/ SDA1 SDATA1 GPOC3#/ SDA1 SDATA1
USB_OC[5:0]#/GPM[5:0]# OC#[6::1] USB_OC[5:0]#/GPM[5:0]# OC#[6::1]
SYS_RESET#/GPM7# FP_RST# SYS_RESET#/GPM7# FP_RST#
AZ_DOCK_RST#/GPM8# Not connected (internal pull-up to +3.3V_S5). AZ_DOCK_RST#/GPM8# Not connected (internal pull-up to +3.3V_S5).
SLP_S2/GPM9# GFX16_PCIERST# SLP_S2/GPM9# GFX16_PCIERST#
B B
NOTE1
Configured for one of these options:
"10-k? 5% pull-up resistor to +3.3V_S0.
"10-k? 5% pull-down resistor.
"Configured GPIO to output mode.
"Configured for internal pull-up or pull-down resistor.
A A

Title
GPIO Configuration
C VL390 0A
5 4 3 2 1
5 4 3 2 1
DIMM3 DIMM4
D D
CPU_HT_CLK
DIMM1 DIMM2 PCI CLK0
PCI SLOT 0 33MHz
NB_HT_CLK 33MHZ
PCI CLK1
2 PAIR MEM CLK

2 PAIR MEM CLK
2 PAIR MEM CLK
2 PAIR MEM CLK

25M_48M_66M_OSC 33MHZ
AMD SB PCI CLK2

SB700 33MHZ
PCI CLK3
HT REFCLK AMD NB NB_DISP_CLK 33MHZ SUPER IO IT8720
100MHz DIFF(RX780/RS780) RS780/RS740
AM3 CPU 1 PAIR CPU CLK
200MHZ PCI CLK4
AM3SOCKET TPM 33MHz
33MHZ
NB-OSCIN GPP_CLK3
14.318MHZ
NB ALINK PCIE CLK PCIE_RCLK/ PCI CLK5

C NB_LNK_CLK C
100MHZ 33MHZ
SB ALINK PCIE CLK

100MHZ
LPC_CLK0
EXTERNAL
33MHZ
CLK GEN. NB GFX PCIE CLK
100MHZ
LPC CLK1
33MHZ
PCIE GFX CLK SLT_GFX_CLK

100MHZ PCIE GFX SLOT 1 - 16 LANES
SB_BITCLK
PCIE GPP CLK HD AUDIO
GPP_CLK0 48MHZ
100MHZ PCIE GPP SLOT 1 - 1 LANE ALC 662/888
25MHz
PCIE GPP CLK 25MHZ GPP_CLK1
100MHZ
LAN
PCIE GPP SLOT 2 - 1 LANES OSC
INPUT
PCIE GPP CLK Y2 GPP_CLK2
14.318MHz
100MHZ PCIE GBE
Y6
B B
PCIE GPP CLK

100MHZ PCIE IEEE1394 Y4 USB_CLK
24.576MHZ
OSC INPUT
24.576MHz
1394 Y5
USB CLK
48MHZ
32.768KHz
SIO CLK
48MHZ
Y3
Y1
25MHz SATA
14.31818MHz
External clock mode

A A
Internal clock mode

Title
Clock Distribution Chart
Custom VL390 0A
5 4 3 2 1
5 4 3 2 1
Power Deliver Chart
AMD AM2r2 CPU

VDDA25 (S0, S1)
2.5V Shunt VDDA 2.5V 0.2A
Regulator
VDDCORE
0.8-1.55V 110A
VRM SW VCCP (S0, S1) / VCC_NB (S0, S1)
CPU REGUALTOR
D ATX P/S WITH 1A STBY CURRENT PW D
VCC_DDR (S0, S1, S3) DDR2 MEM I/F
5VSB 5V 3.3V 12V -12V 12V VDD MEM 1.8V 10A
+/-5% +/-5% +/-5% +/-5% +/-5% +/-5% VTT_DDR (S0, S1, S3)
VTT MEM 0.9V 2A
0.9V VTT_DDR
DDRII DIMMX4
REGULATOR VLDT 1.2V 0.5A
VDD MEM 12A
5VDIMM Linear 1.8V VDD SW VTT_DDR 2A
REGULATOR REGULATOR
NB_VCC1P1 (S0, S1)
1.1V VCC Linear
REGULATOR
NB RS780
VDDHT/RX 1.1V 1.2A
VCC_1V2 (S0, S1)
1.8V VCC Linear 1.2V VCC Linear VDDHTTX 1.2V 0.5A
REGULATOR REGULATOR
VDDPCIE 1.1V 2A
NB CORE VDDC 7A
1.1V
+1.8V_S0 (S0, S1)
VDDA18PCIE 1.8V 0.9A
PLLs 1.8V 0.1A
VDD18/VDD18_MEM
1.8V 0.01A
VDD_MEM 1.8V/1.5V0.5A
AVDD 3.3V 0.135A
C C
SB700
X4 PCI-E 0.8A
VCC3_SB Linear
REGULATOR
ATA I/O 0.5A
ATA PLL 0.01A
VCC3_SB (S0, S1, S3, S5) PCI-E PVDD 80mA
SB CORE 0.6A
CLOCK
+1.2VSB (S0, S1)
1.2V_SB Linear
REGULATOR 1.2V S5 PW 0.22A
VCC3_SB (S0, S1, S3, S5)
3.3V S5 PW 0.01A
USB CORE I/O 0.2A

VCC3 (S0, S1)
3.3V I/O 0.45A
+5VA Linear
B REGULATOR B
AUDIO CODEC
5VDUAL Linear
REGULATOR 3.3V CORE 0.1A
+5VA (S0, S1)
5V ANALOG 0.1A
SUPER I/O
VCC3_SB (S0, S1, S3, S5)
+3.3VDUAL (S3) 0.01A
+3.3V (S0, S1) 0.01A
+5V (S0, S1) 0.1A
PCI Slot (per slot) X1 PCIE per X16 PCIE per USB X4 FR USB X6 RL 2XPS/2
ENTHENET IEEE-1394 x1
5V 5.0A 3.3V 3.0A 3.3V 3.0A VDD VDD 5VDual 3.3V (S3) 0.1A 3.3V (S0, S1) 0.1A
A A
3.3V 7.6A 12V 0.5A 12V 5.5A 5VDual 5VDual 0.5A 3.3V (S0, S1) 0.5A 12V (S0, S1) 1.1A
12V 0.5A 3.3Vaux 0.1A 3.3VDual 0.1A 2.0A 3.0A
3.3VDual 0.375A
-12V 0.1A

Title
Power Deliver Chart
C VL390 0A
5 4 3 2 1
5 4 3 2 1
Intersil 6323 3 Phase

+12VIN
VCC_DDR VCC3
Make sure +12vin
R38
connect plug in
VCC5_SB 10KR0402
R584 R580
4.7KR0402 10KR0402
R637 VIN
VCC5
C20 C0.1U16Y0402
10KR0402
R36
B
1KR0402 +12VIN
VCORE_EN# R636 10KR0402 B C101 C96
D 26 VCORE_EN# D
Q97 R39 LDT_PWRGD E C VRM_PWROK
7,17 LDT_PWRGD
N-MMBT3904 2.2R0805 C1U16X5 C10u16Y1206
E
R51
2.2R0805 Q100 U_G1 R137 1R0805 D
G
N-MMBT3904 S
R136 Q14
C32 10KR0402 N-NTD4809NT4G_DPAK3-RH CH-0.25u40A0.65m-RH
VCC5 C4.7U10Y0805 C35 CHOKE2
PHASE1 1 2 VCCP
C1U16X5
Q17
N-NTD4806NT4G_DPAK3-RH
7X7 QFN Q16
10
R63 U1 N-NTD4806NT4G_DPAK3-RH R138
1
D D
10KR0402 29 L_G1 2.2R1%0805
VCC
G G
0.85V Threshold PVCC1_2
24 EN S S
37 31 R52 2.2R1%0805 C41 C0.1U25X CP41 CP40
26 VRM_GD VDDPWRGD BOOT1
R206 X_0R0402 VRM_PWROK 34
15,26 NB_PWRGD
2
TP8 VR_VID5 PWROK U_G1 C133
9 VID5 UGATE1 32
TP9 VR_VID4 8 33 PHASE1 C1000P50X0402
VID4 PHASE1 L_G1
7 VID3_SVC 7 VID3/SVC LGATE1 30
6 PHASE11
7 VID2_SVD VID2/SVD
7 VID1_SEL 5 VID1/SEL
TP10 VR_FIXEN 4 20 ISEN1+ R33 200R1%0402 ISEN1 ISEN1
VID0/VFIXEN ISEN1+ VCCP
C6
C0.1U16Y0402
X_C680P50X0402 C0.01U16X0402 21 ISEN1-
CPU_VDDNB C42 R69 ISEN1- PHASE11 R32 C5
1 2
R57 1.2KR1%0402 C48 48 4.32KR1%0402
X_470R1%0402 COMP_NB C0.1U16Y0402 VIN EC29
R59 C44 C10P50N0402 1 FB_NB BOOT2 27 R46 2.2R1%0805 C27 C0.1U25X 1+ 2
R58 360R1%0402
100R0402 ISEN_NB_A 26 U_G2 CD820u2.5SO-RH
C40 R53 0R0402 UGATE2 PHASE2 C140 C149
PHASE2 25
X_C0.1U16Y0402 2 28 L_G2 EC33
7 V_NB VSEN_NB LGATE2
R54 X_0R0402 C1U16X5 C10u16Y1206 1+ 2
C39 3
C38 RGND_NB ISEN2+ R31 150R1%0402 ISEN2 U_G2 R151 1R0805 D
CD820u2.5SO-RH
ISEN2+ 22 G
C4
C0.1U16Y0402
X_C0.1U16Y0402 X_C0.1U16Y0402 23 ISEN2- C3 S
ISEN2- PHASE22 R30 R152 Q20 EC34
7 V_GND
1.2KR1%0402 C0.01U16X0402 4.32KR1%0402 10KR0402 N-NTD4809NT4G_DPAK3-RH CH-0.25u40A0.65m-RH 1+ 2
C VCCP R34 1 2 C23 18 C0.1U16Y0402 CHOKE4 C
R50 X_470R1%0402 COMP PWM3 PHASE2 CD820u2.5SO-RH
PWM3 35 1 2 VCCP
100R0402 R18 C7 C33P50N0402
Q22
C8 44 ISEN3+ R65 0R0402 ISEN3 Q21 EC36
ISEN3+
C55
C0.1U16Y0402
X_C1000P50X0402 17 FB ISEN3- 43 ISEN3- C54 N-NTD4806NT4G_DPAK3-RH
D D
R153 1+ 2
R5 560R1%0402-RH C19 C0.01U16X0402 PHASE33 R64 L_G2 G G 2.2R1%0805
1
100R0402 R4 2 1 15 4.32KR1%0402 S S CD820u2.5SO-RH
R17 RCOMP C0.1U16Y0402 CP43 CP42
7 COREFB+
1.3KR1%0402 36 EC41
PWM4 C207 1+ 2
2
C26 COREFB+ 13 46 Disable PWM4 Use 3phase C1000P50X0402
X_C0.1U16Y0402 VSEN ISEN4+ CD820u2.5SO-RH
ISEN4- 45 VCC5
COREFB- 12 PHASE22
7 COREFB- RGND ISEN2 EC42
C24 C30 C0.1U16Y0402 1+ 2
R42 C22 42 R70 2.2R1%0805 +12VIN
100R0402 R16 PVCC_NB CD820u2.5SO-RH
X_C0.1U16Y0402 4.99KR1%0402 C52 C1U25X0805
X_C0.1U16Y0402 40 R68 C51 C0.1U25X +12VIN VIN EC43
BOOT_NB
19 APA
2.2R1%0805 1+ 2
C587 C0.1U10X0402 39 UGATE_NB
R37 56KR1%0402 VRM_SET UGATE_NB PHASE_NB CD820u2.5SO-RH
VCC5 16 RESET PHASE_NB 38
41 LGATE_NB R191 C211 C223
LGATE_NB 2.2R0805 EC45
VCC5 R19 59KR1%0402 OFS 14 OFS
C1U16X5 C10u16Y1206 1+ 2
47 R75 X_6.2KR1%0402 U11
GND
ISEN_NB U_G3 R176 1R0805 D

CD820u2.5SO-RH
VCC5 11 FS 6 VCC UGATE 1 G
R28 R47 7 2 R175 S
X_10KR0402 X_100KR0402 PHASE_NB_A ISEN_NB_A PVCC BOOT R186 C260 10KR0402 Q23
49
R62 C53 2.2R1%0805 C0.1U25X N-NTD4809NT4G_DPAK3-RH CH-0.25u40A0.65m-RH

R45 ISL6323CRZ_QFN48-RH 5.6KR1%0402 C0.1U16Y0402 C271 8 CHOKE6
120KR1%0402 C1U25X0805 PHASE PHASE3 1 2 VCCP
4 GND
Q27
Q28
N-NTD4806NT4G_DPAK3-RH R180
D D
BOTTOM PAD PWM3 3 5 L_G3 G G 2.2R1%0805
PWM LGATE
1
CONNECT TO GND ISL6612ACBZT_SOIC8-RH
S S
CP45 CP44
B B
Through 8 VIAs
C264
2
C1000P50X0402
PHASE33
ISEN3
Modify 0902
VIN
5
JPW1
VCC_DDR R66 X_300R0402
GND
12V
+12VIN 3 1
C56 C59
Q6
N-NTD4809NT4G_DPAK3-RH C1U16X5 C10u16Y1206
12V
GND
4 2
R340 X_27R0402 VID1_SEL CPU_VDDNB
7 CPU_CORE_TYPE D
LOW FOR SVID UGATE_NB R120 1R0805 G
C283 PWR-2X2M_natural-RH S EC51
X_C0.01u25X0402 R118 CHOKE1 1+ 2
10KR0402 CH-0.5u40A0.81m-RH
R78 CD820u2.5SO-RH
300R0402 PHASE_NB 2 1 CPU_VDDNB
Q7 EC53
D D
R101 1+ 2
LGATE_NB R77 1R0805 G G Q9 2.2R1%0805
1
CHOKE7 S S CD820u2.5SO-RH
CH-1.1u27A2.5m-RH VIN CP39 CP38
R94 1R0805
1 2 C60
+12VIN
2
C1000P50X0402
C284
X_C0.01u25X0402
EC10
CD1000U16EL20-2
EC28
CD1000U16EL20-2
EC17
CD1000U16EL20-2
EC6
X_CD1000U16EL20-2
C270
C0.1U16Y0402
1
PHASE_NB_A
+
A A
ISEN_NB_A
2
TP125 VCC5 MICRO-START INT'L CO.,LTD.

Title
TP126 VIN Intersil 6323 3 Phase
C VL390 0A
5 4 3 2 1
5 4 3 2 1
HT_CADIN_H[15..0]
13 HT_CADIN_H[15..0] VCC_1V2
HT_CADIN_L[15..0]
13 HT_CADIN_L[15..0] RS740 R442 VCC_DDR
X_51R1%0402 HT_CTLIN_H1
HT_CADOUT_H[15..0] RS740 R599 X_51R1%0402 HT_CTLIN_L1 VDDA25 VDDA_25 VDDA25
13 HT_CADOUT_H[15..0] Note: Change the PU
CPU_CORE_TYPE R80 1KR0402
HT_CADOUT_L[15..0] L5 resister to 1KR
13 HT_CADOUT_L[15..0]
1 2 VID3_SVC R72 1KR0402
C84 C77 C69 C89 C74 47n300mA_0805-RH-2 VID2_SVD R71 1KR0402
D C3900P50X D
CPU1D
12 CPU_CLK
CPU1A MISC
HYPERTRANSPORT C10 VDDA1 KEY/VSS1 H22Remove H22,AE9
N6 AD5 R121 C0.22U16X C1U10Y D10 AE9 change pin F2 from
13 HT_CLKIN_H1 L0_CLKIN_H(1) L0_CLKOUT_H(1) HT_CLKOUT_H1 13 VDDA2 KEY/VSS2 PLATFORM_TYPE to RSVD
P6 AD4 C91 169R1%0402 C4.7U10Y0805 C3300P50X0402
13 HT_CLKIN_L1 L0_CLKIN_L(1) L0_CLKOUT_L(1) HT_CLKOUT_L1 13
N3 AD1 C3900P50X CPUCLKIN A8 F2 CPU_PF_TYPE TP2
13 HT_CLKIN_H0 L0_CLKIN_H(0) L0_CLKOUT_H(0) HT_CLKOUT_H0 13 CLKIN_H PLATFORM_TYPE
N2 AC1 CPUCLKIN# B8 G5 CPU_CORE_TYPE
13 HT_CLKIN_L0 L0_CLKIN_L(0) L0_CLKOUT_L(0) HT_CLKOUT_L0 13 12 CPU_CLK# CLKIN_L CORE_TYPE CPU_CORE_TYPE 6
V4 Y6 LDT_PWRGD C9 D2 VID5 TP5
13 HT_CTLIN_H1 L0_CTLIN_H(1) L0_CTLOUT_H(1) HT_CTLOUT_H1 13 6,17 LDT_PWRGD PWROK VID(5)
V5 W6 LDT_STOP# D8 D1 VID4 TP6
13 HT_CTLIN_L1 L0_CTLIN_L(1) L0_CTLOUT_L(1) HT_CTLOUT_L1 13 15,17 LDT_STOP# LDTSTOP_L VID(4)
U1 W2 LDT_RST# C7 C1 VID3_SVC
13 HT_CTLIN_H0 L0_CTLIN_H(0) L0_CTLOUT_H(0) HT_CTLOUT_H0 13 15,17 LDT_RST# RESET_L SVC/VID(3) VID3_SVC 6
V1 W3 E3 VID2_SVD
13 HT_CTLIN_L0 L0_CTLIN_L(0) L0_CTLOUT_L(0) HT_CTLOUT_L0 13 SVD/VID(2) VID2_SVD 6
E2 VID1_SEL
PVIEN/VID(1) VID1_SEL 6
HT_CADIN_H15 U6 Y5 HT_CADOUT_H15 CPU_PRESENT_L AL3 E1 VRFIXEN TP7
HT_CADIN_L15 L0_CADIN_H(15) L0_CADOUT_H(15) HT_CADOUT_L15 CPU_PRESENT_L VID(0)
V6 L0_CADIN_L(15) L0_CADOUT_L(15) Y4
HT_CADIN_H14 T4 AB6 HT_CADOUT_H14 CPU_SIC AL6 AG9
L0_CADIN_H(14) L0_CADOUT_H(14) SIC THERMDC THERMDC_CPU 25,32
HT_CADIN_L14 T5 AA6 HT_CADOUT_L14 CPU_SID AK6 AG8
L0_CADIN_L(14) L0_CADOUT_L(14) SID THERMDA THERMDA_CPU 25,32
HT_CADIN_H13 R6 AB5 HT_CADOUT_H13 CPU_ALERT# AL4 AK7 CPU_THRIP_L#
HT_CADIN_L13 L0_CADIN_H(13) L0_CADOUT_H(13) HT_CADOUT_L13 R146 0R0402 ALERT_L THERMTRIP_L PROCHOT_L R102 0R0402
T6 L0_CADIN_L(13) L0_CADOUT_L(13) AB4 AK4 SA0 PROCHOT_L AL7 CPU_PROCHOT# 17
HT_CADIN_H12 P4 AD6 HT_CADOUT_H12
HT_CADIN_L12 L0_CADIN_H(12) L0_CADOUT_H(12) HT_CADOUT_L12 CPU_TDI CPU_TDO
P5 L0_CADIN_L(12) L0_CADOUT_L(12) AC6 AL10 TDI TDO AK10
HT_CADIN_H11 M4 AF6 HT_CADOUT_H11 CPU_TRST_L AJ10
HT_CADIN_L11 L0_CADIN_H(11) L0_CADOUT_H(11) HT_CADOUT_L11 CPU_TCK TRST_L
M5 L0_CADIN_L(11) L0_CADOUT_L(11) AE6 AH10 TCK
HT_CADIN_H10 L6 AF5 HT_CADOUT_H10 CPU_TMS AL9
HT_CADIN_L10 L0_CADIN_H(10) L0_CADOUT_H(10) HT_CADOUT_L10 TMS
M6 L0_CADIN_L(10) L0_CADOUT_L(10) AF4
HT_CADIN_H9 K4 AH6 HT_CADOUT_H9 CPU_DBREQ_L A5 B6 CPU_DBRDY
HT_CADIN_L9 L0_CADIN_H(9) L0_CADOUT_H(9) HT_CADOUT_L9 DBREQ_L DBRDY
K5 L0_CADIN_L(9) L0_CADOUT_L(9) AG6
HT_CADIN_H8 J6 AH5 HT_CADOUT_H8 COREFB+ G2 AK11 R163 100R0402
L0_CADIN_H(8) L0_CADOUT_H(8) VCC_DDR 6 COREFB+ VDD_FB_H VDDIO_FB_H DDR_FB 27
HT_CADIN_L8 K6 AH4 HT_CADOUT_L8 COREFB- G1 AL11 TP4
L0_CADIN_L(8) L0_CADOUT_L(8) 6 COREFB- VDD_FB_L VDDIO_FB_L
VDDNB_FB_H G4 V_NB 6
C HT_CADIN_H7 U3 Y1 HT_CADOUT_H7 G3 C
L0_CADIN_H(7) L0_CADOUT_H(7) VDDNB_FB_L V_GND 6
HT_CADIN_L7 U2 W1 HT_CADOUT_L7
HT_CADIN_H6 L0_CADIN_L(7) L0_CADOUT_L(7) HT_CADOUT_H6 R162 TP1 CPU_VDDR_SENSE VCC_1V2
R1 L0_CADIN_H(6) L0_CADOUT_H(6) AA2 E12 VTT_SENSE PSI_L F1 CPU_PSI_L TP3
HT_CADIN_L6 T1 AA3 HT_CADOUT_L6 39.2R1%0402 CPU_M_VREF
HT_CADIN_H5 L0_CADIN_L(6) L0_CADOUT_L(6) HT_CADOUT_H5 HTREF1 R168 44.2R1%
R3 L0_CADIN_H(5) L0_CADOUT_H(5) AB1 F12 M_VREF HTREF1 V8
HT_CADIN_L5 R2 AA1 HT_CADOUT_L5 CPU_STRAP_HI_E11 AH11 V7 HTREF2 R171 44.2R1%
HT_CADIN_H4 L0_CADIN_L(5) L0_CADOUT_L(5) HT_CADOUT_H4 CPU_STRAP_LO_F11 M_ZN HTREF0
N1 L0_CADIN_H(4) L0_CADOUT_H(4) AC2 AJ11 M_ZP
HT_CADIN_L4 P1 AC3 HT_CADOUT_L4
HT_CADIN_H3 L0_CADIN_L(4) L0_CADOUT_L(4) HT_CADOUT_H3 CPU_TEST25_H R123 X_80.6R1%0402
L1 L0_CADIN_H(3) L0_CADOUT_H(3) AE2 A10 TEST25_H TEST29_H C11
HT_CADIN_L3 M1 AE3 HT_CADOUT_L3 R160 CPU_TEST25_L B10 D11
HT_CADIN_H2 L0_CADIN_L(3) L0_CADOUT_L(3) HT_CADOUT_H2 39.2R1%0402 R534 X_300R0402 TEST25_L TEST29_L Keep trace < 1" from CPU.
L3 L0_CADIN_H(2) L0_CADOUT_H(2) AF1 F10 TEST19
HT_CADIN_L2 L2 AE1 HT_CADOUT_L2 R564 X_300R0402 E9
HT_CADIN_H1 L0_CADIN_L(2) L0_CADOUT_L(2) HT_CADOUT_H1 TEST18
J1 L0_CADIN_H(1) L0_CADOUT_H(1) AG2 AJ7 TEST13
HT_CADIN_L1 K1 AG3 HT_CADOUT_L1 F6
HT_CADIN_H0 L0_CADIN_L(1) L0_CADOUT_L(1) HT_CADOUT_H0 TEST9
J3 L0_CADIN_H(0) L0_CADOUT_H(0) AH1
HT_CADIN_L0 J2 AG1 HT_CADOUT_L0 TP19 D6 AK8 TP28 TP27
L0_CADIN_L(0) L0_CADOUT_L(0) TP20 TEST17 TEST24 TP24
E7 TEST16 TEST23 AH8
TP23 F8 AJ9 R567 300R0402
TP18 TEST15 TEST22 R531 300R0402
C5 TEST14 TEST21 AL8
Note: CRB Reserved TP25 AH9 AJ8
VCC_DDR TEST12 TEST20 TP26
E5 TEST7 TEST28_H J10
CPU_DBREQ_L R294 X_1KR0402 AJ5 H9
CPU_TCK R281 X_1KR0402 TEST6 TEST28_L
TEST27 AK9
CPU_TMS R249 X_1KR0402 AK5 R165 X_300R0402 VCC_DDR
CPU_TDI R247 X_1KR0402 TEST26
AH7 TEST3 TEST10 G7
CPU_TRST_L R240 X_1KR0402 AJ6 D4
TEST2 TEST8
LDT_STOP# C801 X_C180p50N0402

LDT_RST# C802 X_C180p50N0402
B LDT_PWRGD C803 X_C180p50N0402 B
AMD REQUEST
VCC_DDR
VCC3 VCC_DDR VCC_DDR

CPU_M_VREF
Modify 0902 R110
VCC3 15R1%
Q102
R22 R21
X_1KR0402 X_4.7KR0402 CPU_SIC S1 R169 R166
G1 D1 R182 0R0402 300R0402 4.7KR0402
AMD_TSI_C 25
R184 CPU_SID S2 R109 C86 C92
B
20KR1%0402 G2 D2 R178 0R0402

AMD_TSI_D 25
B
SW1 X_SW-TACT4PS X_100R0402 15R1% C1000P50X0402
1 3 R8 LDT_RST_L E C LDT_RST# CPU_FETGATE C0.1U16Y0402
Q1 NN-2N7002DW-7-F_SOT363-6-RH CPU_THRIP_L#
2 4 Q103 E C CPU_THRIP# 18
X_N-MMBT3904_NL_SOT23 Q24
R174 CPU_ALERT# S1 N-MMBT3904_NL_SOT23
C255 G1 D1 R183 X_0R0402
VCC_DDR J1
TALERT# 19
X_39.2KR1%0402 CPU_PRESENT_L
C0.1U16Y0402 S2
1 2 G2 D2 CPU_PRESENT# 18
3 4
5 6 TP135 CPU_CLK
CPU_DBREQ_L
NN-2N7002DW-7-F_SOT363-6-RH TP136 CPU_CLK#
7 8
CPU_DBRDY 9 10
CPU_TCK 11 12 For SIC/SID
CPU_TMS 13 14 TP137 LDT_PWRGD
A A
CPU_TDI 15 16 VCC_DDR
CPU_TRST_L 17 18 TP138 LDT_RST#
CPU_TDO 19 20 CPU_ALERT# R177 1KR0402
21 22
23 24 LDT_RST_L CPU_SID R231 1KR0402 VCC_DDR
26 CPU_SIC R167 1KR0402
KEY
CPU_PRESENT_L R170 10KR0402
LDT_STOP#
LDT_RST#
R106
R105
300R0402
300R0402
HTREF1 C227 X_C1000P50X0402
X_H2X13[25]_black CPU_TEST25_H R111 510R0402 LDT_PWRGD R107 300R0402 HTREF2 C228 X_C1000P50X0402 Title
PROCHOT_L R103 300R0402 CPU AM2 HT I/F,CTRL&DEBUG
CPU_TEST25_L R119 510R0402 LDT_RST# C67 X_C1000P50X0402
Custom VL390 0A
5 4 3 2 1
5 4 3 2 1
10,11 MEM_MA_DQS_L[7..0]
10,11 MEM_MA_DQS_H[7..0] 10,11 MEM_MB_DQS_L[7..0]
10,11 MEM_MA_DM[7..0] 10,11 MEM_MB_DQS_H[7..0]
10,11 MEM_MA_CHECK[7..0] 10,11 MEM_MB_DM[7..0]

D 10,11 MEM_MB_CHECK[7..0] D
Pin naming for memory pins indicate
"DDR3"/"DDR2" connections.
CPU1B CPU1C
MEMORY INTERFACE A MEM_MA_DATA[63..0] 10,11
AG21 AE14 MEM_MA_DATA63
MA0_CLK_H(2) MA_DATA(63) MEMORY INTERFACE B MEM_MB_DATA[63..0] 10,11
AG20 AG14 MEM_MA_DATA62 AJ19 AH13 MEM_MB_DATA63
MA0_CLK_L(2) MA_DATA(62) MEM_MA_DATA61 MB0_CLK_H(2) MB_DATA(63) MEM_MB_DATA62
G19 MA0_CLK_H(1) MA_DATA(61) AG16 AK19 MB0_CLK_L(2) MB_DATA(62) AL13
H19 AD17 MEM_MA_DATA60 A18 AL15 MEM_MB_DATA61
MEM_MA1_CLK_H1 MA0_CLK_L(1) MA_DATA(60) MEM_MA_DATA59 MB0_CLK_H(1) MB_DATA(61) MEM_MB_DATA60
11 MEM_MA1_CLK_H1 U27 MA0_CLK_H(0) MA_DATA(59) AD13 A19 MB0_CLK_L(1) MB_DATA(60) AJ15
MEM_MA1_CLK_L1 U26 AE13 MEM_MA_DATA58 MEM_MB1_CLK_H1 U31 AF13 MEM_MB_DATA59
11 MEM_MA1_CLK_L1 MA0_CLK_L(0) MA_DATA(58) 11 MEM_MB1_CLK_H1 MB0_CLK_H(0) MB_DATA(59)
AG15 MEM_MA_DATA57 MEM_MB1_CLK_L1 U30 AG13 MEM_MB_DATA58
MA_DATA(57) 11 MEM_MB1_CLK_L1 MB0_CLK_L(0) MB_DATA(58)
MEM_MA0_CS_L1 AC25 AE16 MEM_MA_DATA56 AL14 MEM_MB_DATA57
10 MEM_MA0_CS_L1 MA0_CS_L(1) MA_DATA(56) MB_DATA(57)
MEM_MA0_CS_L0 AA24 AG17 MEM_MA_DATA55 MEM_MB0_CS_L1 AE30 AK15 MEM_MB_DATA56
10 MEM_MA0_CS_L0 MA0_CS_L(0) MA_DATA(55) 10 MEM_MB0_CS_L1 MB0_CS_L(1) MB_DATA(56)
AE18 MEM_MA_DATA54 MEM_MB0_CS_L0 AC31 AL16 MEM_MB_DATA55
MA_DATA(54) 10 MEM_MB0_CS_L0 MB0_CS_L(0) MB_DATA(55)
MEM_MA0_ODT0 AC28 AD21 MEM_MA_DATA53 AL17 MEM_MB_DATA54
10 MEM_MA0_ODT0 MA0_ODT(0) MA_DATA(53) MB_DATA(54)
AG22 MEM_MA_DATA52 MEM_MB0_ODT0 AD29 AK21 MEM_MB_DATA53
MA_DATA(52) 10 MEM_MB0_ODT0 MB0_ODT(0) MB_DATA(53)
AE20 AE17 MEM_MA_DATA51 AL21 MEM_MB_DATA52
MA1_CLK_H(2) MA_DATA(51) MEM_MA_DATA50 MB_DATA(52) MEM_MB_DATA51
AE19 MA1_CLK_L(2) MA_DATA(50) AF17 AL19 MB1_CLK_H(2) MB_DATA(51) AH15
G20 AF21 MEM_MA_DATA49 AL18 AJ16 MEM_MB_DATA50
MA1_CLK_H(1) MA_DATA(49) MEM_MA_DATA48 MB1_CLK_L(2) MB_DATA(50) MEM_MB_DATA49
G21 MA1_CLK_L(1) MA_DATA(48) AE21 C19 MB1_CLK_H(1) MB_DATA(49) AH19
MEM_MA0_CLK_H0 V27 AF23 MEM_MA_DATA47 D19 AL20 MEM_MB_DATA48
10 MEM_MA0_CLK_H0 MA1_CLK_H(0) MA_DATA(47) MB1_CLK_L(1) MB_DATA(48)
MEM_MA0_CLK_L0 W27 AE23 MEM_MA_DATA46 MEM_MB0_CLK_H0 W29 AJ22 MEM_MB_DATA47
10 MEM_MA0_CLK_L0 MA1_CLK_L(0) MA_DATA(46) 10 MEM_MB0_CLK_H0 MB1_CLK_H(0) MB_DATA(47)
AJ26 MEM_MA_DATA45 MEM_MB0_CLK_L0 W28 AL22 MEM_MB_DATA46
MA_DATA(45) 10 MEM_MB0_CLK_L0 MB1_CLK_L(0) MB_DATA(46)
MEM_MA1_CS_L1 AD27 AG26 MEM_MA_DATA44 AL24 MEM_MB_DATA45
11 MEM_MA1_CS_L1 MA1_CS_L(1) MA_DATA(44) MB_DATA(45)
MEM_MA1_CS_L0 AA25 AE22 MEM_MA_DATA43 MEM_MB1_CS_L1 AE29 AK25 MEM_MB_DATA44
11 MEM_MA1_CS_L0 MA1_CS_L(0) MA_DATA(43) 11 MEM_MB1_CS_L1 MB1_CS_L(1) MB_DATA(44)
AG23 MEM_MA_DATA42 MEM_MB1_CS_L0 AB31 AJ21 MEM_MB_DATA43
MA_DATA(42) 11 MEM_MB1_CS_L0 MB1_CS_L(0) MB_DATA(43)
MEM_MA1_ODT0 AC27 AH25 MEM_MA_DATA41 AH21 MEM_MB_DATA42
11 MEM_MA1_ODT0 MA1_ODT(0) MA_DATA(41) MB_DATA(42)
AF25 MEM_MA_DATA40 MEM_MB1_ODT0 AD31 AH23 MEM_MB_DATA41
MA_DATA(40) 11 MEM_MB1_ODT0 MB1_ODT(0) MB_DATA(41)
AJ28 MEM_MA_DATA39 AJ24 MEM_MB_DATA40
C MEM_MA_CAS_L MA_DATA(39) MEM_MA_DATA38 MB_DATA(40) MEM_MB_DATA39 C
10,11 MEM_MA_CAS_L AB25 MA_CAS_L MA_DATA(38) AJ29 MB_DATA(39) AL27
MEM_MA_WE_L AB27 AF29 MEM_MA_DATA37 MEM_MB_CAS_L AC29 AK27 MEM_MB_DATA38
10,11 MEM_MA_WE_L MA_WE_L MA_DATA(37) 10,11 MEM_MB_CAS_L MB_CAS_L MB_DATA(38)
MEM_MA_RAS_L AA26 AE26 MEM_MA_DATA36 MEM_MB_WE_L AC30 AH31 MEM_MB_DATA37
10,11 MEM_MA_RAS_L MA_RAS_L MA_DATA(36) 10,11 MEM_MB_WE_L MB_WE_L MB_DATA(37)
AJ27 MEM_MA_DATA35 MEM_MB_RAS_L AB29 AG30 MEM_MB_DATA36
MA_DATA(35) 10,11 MEM_MB_RAS_L MB_RAS_L MB_DATA(36)
MEM_MA_BANK2 N25 AH27 MEM_MA_DATA34 AL25 MEM_MB_DATA35
10,11 MEM_MA_BANK2 MA_BANK(2) MA_DATA(34) MB_DATA(35)
MEM_MA_BANK1 Y27 AG29 MEM_MA_DATA33 MEM_MB_BANK2 N31 AL26 MEM_MB_DATA34
10,11 MEM_MA_BANK1 MA_BANK(1) MA_DATA(33) 10,11 MEM_MB_BANK2 MB_BANK(2) MB_DATA(34)
MEM_MA_BANK0 AA27 AF27 MEM_MA_DATA32 MEM_MB_BANK1 AA31 AJ30 MEM_MB_DATA33
10,11 MEM_MA_BANK0 MA_BANK(0) MA_DATA(32) 10,11 MEM_MB_BANK1 MB_BANK(1) MB_DATA(33)
E29 MEM_MA_DATA31 MEM_MB_BANK0 AA28 AJ31 MEM_MB_DATA32
MA_DATA(31) 10,11 MEM_MB_BANK0 MB_BANK(0) MB_DATA(32)
MEM_MA_CKE1 L27 E28 MEM_MA_DATA30 E31 MEM_MB_DATA31
10,11 MEM_MA_CKE1 MA_CKE(1) MA_DATA(30) MB_DATA(31)
MEM_MA_CKE0 M25 D27 MEM_MA_DATA29 MEM_MB_CKE1 M31 E30 MEM_MB_DATA30
10,11 MEM_MA_CKE0 MA_CKE(0) MA_DATA(29) 10,11 MEM_MB_CKE1 MB_CKE(1) MB_DATA(30)
C27 MEM_MA_DATA28 MEM_MB_CKE0 M29 B27 MEM_MB_DATA29
MA_DATA(28) 10,11 MEM_MB_CKE0 MB_CKE(0) MB_DATA(29)
MEM_MA_ADD15 M27 G26 MEM_MA_DATA27 A27 MEM_MB_DATA28
MEM_MA_ADD14 MA_ADD(15) MA_DATA(27) MEM_MA_DATA26 MEM_MB_ADD15 MB_DATA(28) MEM_MB_DATA27
N24 MA_ADD(14) MA_DATA(26) F27 N28 MB_ADD(15) MB_DATA(27) F29
MEM_MA_ADD13 AC26 C28 MEM_MA_DATA25 MEM_MB_ADD14 N29 F31 MEM_MB_DATA26
MEM_MA_ADD12 MA_ADD(13) MA_DATA(25) MEM_MA_DATA24 MEM_MB_ADD13 MB_ADD(14) MB_DATA(26) MEM_MB_DATA25
N26 MA_ADD(12) MA_DATA(24) E27 AE31 MB_ADD(13) MB_DATA(25) A29
MEM_MA_ADD11 P25 F25 MEM_MA_DATA23 MEM_MB_ADD12 N30 A28 MEM_MB_DATA24
Y25 MA_ADD(10) MA_DATA(22) E25 P29 MB_ADD(11) MB_DATA(23) A25
MEM_MA_ADD9 N27 E23 MEM_MA_DATA21 MEM_MB_ADD10 AA29 A24 MEM_MB_DATA22
R24 MA_ADD(8) MA_DATA(20) D23 P31 MB_ADD(9) MB_DATA(21) C22
MEM_MA_ADD7 P27 E26 MEM_MA_DATA19 MEM_MB_ADD8 R29 D21 MEM_MB_DATA20
R25 MA_ADD(6) MA_DATA(18) C26 R28 MB_ADD(7) MB_DATA(19) A26
MEM_MA_ADD5 R26 G23 MEM_MA_DATA17 MEM_MB_ADD6 R31 B25 MEM_MB_DATA18
R27 MA_ADD(4) MA_DATA(16) F23 R30 MB_ADD(5) MB_DATA(17) B23
MEM_MA_ADD3 T25 E22 MEM_MA_DATA15 MEM_MB_ADD4 T31 A22 MEM_MB_DATA16
U25 MA_ADD(2) MA_DATA(14) E21 T29 MB_ADD(3) MB_DATA(15) B21
MEM_MA_ADD1 T27 F17 MEM_MA_DATA13 MEM_MB_ADD2 U29 A20 MEM_MB_DATA14
10,11 MEM_MA_ADD[15..0] MA_ADD(1) MA_DATA(13) MB_ADD(2) MB_DATA(14)
MEM_MA_ADD0 W24 G17 MEM_MA_DATA12 MEM_MB_ADD1 U28 C16 MEM_MB_DATA13
MA_ADD(0) MA_DATA(12) 10,11 MEM_MB_ADD[15..0] MB_ADD(1) MB_DATA(13)
G22 MEM_MA_DATA11 MEM_MB_ADD0 AA30 D15 MEM_MB_DATA12
MEM_MA_DQS_H7 MA_DATA(11) MEM_MA_DATA10 MB_ADD(0) MB_DATA(12) MEM_MB_DATA11
AD15 MA_DQS_H(7) MA_DATA(10) F21 MB_DATA(11) C21
MEM_MA_DQS_L7 AE15 G18 MEM_MA_DATA9 MEM_MB_DQS_H7 AK13 A21 MEM_MB_DATA10
MEM_MA_DQS_H6 MA_DQS_L(7) MA_DATA(9) MEM_MA_DATA8 MEM_MB_DQS_L7 MB_DQS_H(7) MB_DATA(10) MEM_MB_DATA9
AG18 MA_DQS_H(6) MA_DATA(8) E17 AJ13 MB_DQS_L(7) MB_DATA(9) A17
B MEM_MA_DQS_L6 MEM_MA_DATA7 MEM_MB_DQS_H6 MEM_MB_DATA8 B
AG19 MA_DQS_L(6) MA_DATA(7) G16 AK17 MB_DQS_H(6) MB_DATA(8) A16
MEM_MA_DQS_H5 AG24 E15 MEM_MA_DATA6 MEM_MB_DQS_L6 AJ17 B15 MEM_MB_DATA7
MEM_MA_DQS_L5 MA_DQS_H(5) MA_DATA(6) MEM_MA_DATA5 MEM_MB_DQS_H5 MB_DQS_L(6) MB_DATA(7) MEM_MB_DATA6
AG25 MA_DQS_L(5) MA_DATA(5) G13 AK23 MB_DQS_H(5) MB_DATA(6) A14
MEM_MA_DQS_H4 AG27 H13 MEM_MA_DATA4 MEM_MB_DQS_L5 AL23 E13 MEM_MB_DATA5
AG28 MA_DQS_L(4) MA_DATA(3) H17 AL28 MB_DQS_H(4) MB_DATA(4) F13
MEM_MA_DQS_H3 D29 E16 MEM_MA_DATA2 MEM_MB_DQS_L4 AL29 C15 MEM_MB_DATA3
C29 MA_DQS_L(3) MA_DATA(1) E14 D31 MB_DQS_H(3) MB_DATA(2) A15
MEM_MA_DQS_H2 C25 G14 MEM_MA_DATA0 MEM_MB_DQS_L3 C31 A13 MEM_MB_DATA1
MEM_MA_DQS_L2 MA_DQS_H(2) MA_DATA(0) MEM_MB_DQS_H2 MB_DQS_L(3) MB_DATA(1) MEM_MB_DATA0
D25 MA_DQS_L(2) C24 MB_DQS_H(2) MB_DATA(0) D13
MEM_MA_DQS_H1 E19 J28 MEM_MA_DQS_H8 MEM_MB_DQS_L2 C23
MA_DQS_H(1) MA_DQS_H(8) MEM_MA_DQS_H8 10,11 MB_DQS_L(2)
MEM_MA_DQS_L1 F19 J27 MEM_MA_DQS_L8 MEM_MB_DQS_H1 D17 J31 MEM_MB_DQS_H8
MA_DQS_L(1) MA_DQS_L(8) MEM_MA_DQS_L8 10,11 MB_DQS_H(1) MB_DQS_H(8) MEM_MB_DQS_H8 10,11
MEM_MA_DQS_H0 F15 MEM_MB_DQS_L1 C17 J30 MEM_MB_DQS_L8
MA_DQS_H(0) MB_DQS_L(1) MB_DQS_L(8) MEM_MB_DQS_L8 10,11
MEM_MA_DQS_L0 G15 J25 MEM_MA_DM8 MEM_MB_DQS_H0 C14
MA_DQS_L(0) MA_DM(8) MEM_MA_DM8 10,11 MB_DQS_H(0)
MEM_MB_DQS_L0 C13 J29 MEM_MB_DM8
MB_DQS_L(0) MB_DM(8) MEM_MB_DM8 10,11
MEM_MA_DM7 AF15 K25 MEM_MA_CHECK7
MEM_MA_DM6 MA_DM(7) MA_CHECK(7) MEM_MA_CHECK6 MEM_MB_DM7 MEM_MB_CHECK7
AF19 MA_DM(6) MA_CHECK(6) J26 AJ14 MB_DM(7) MB_CHECK(7) K29
MEM_MA_DM5 AJ25 G28 MEM_MA_CHECK5 MEM_MB_DM6 AH17 K31 MEM_MB_CHECK6
MEM_MA_DM4 MA_DM(5) MA_CHECK(5) MEM_MA_CHECK4 MEM_MB_DM5 MB_DM(6) MB_CHECK(6) MEM_MB_CHECK5
AH29 MA_DM(4) MA_CHECK(4) G27 AJ23 MB_DM(5) MB_CHECK(5) G30
MEM_MA_DM3 B29 L24 MEM_MA_CHECK3 MEM_MB_DM4 AK29 G29 MEM_MB_CHECK4
E24 MA_DM(2) MA_CHECK(2) K27 C30 MB_DM(3) MB_CHECK(3) L29
MEM_MA_DM1 E18 H29 MEM_MA_CHECK1 MEM_MB_DM2 A23 L28 MEM_MB_CHECK2
H15 MA_DM(0) MA_CHECK(0) H27 B17 MB_DM(1) MB_CHECK(1) H31
MEM_MB_DM0 B13 G31 MEM_MB_CHECK0
MB_DM(0) MB_CHECK(0)
Add For ECC 0829 Add For ECC 0829

A A

Title
CPU AM2 DDR MEMORY I/F
Custom VL390 0A
5 4 3 2 1
5 4 3 2 1
CPU AM2 PWR & GND

VCCP CPU_VDDNB VCCP CPU1I
VCCP VCC_1V2
CPU1F CPU1G CPU1H VDDIO
VDD1 VDD2 VDD3 AJ4 H6 VLDT_RUN_B
VLDT_A1 VLDT_B1
A4 VDDNB1 VSS1 A3 L14 VDD1 VSS1 AK20 AA20 VDD1 VSS1 N17 AJ3 VLDT_A2 VLDT_B2 H5
A6 A7 L16 AK22 AA22 N19 AJ2 H2 C120
VDDNB2 VSS2 VDD2 VSS2 VDD2 VSS2 CPU_VDDR VLDT_A3 VLDT_B3 CPU_VDDR C116
B5 VDDNB3 VSS3 A9 L18 VDD3 VSS3 AK24 AB13 VDD3 VSS3 N21 AJ1 VLDT_A4 VLDT_B4 H1
B7 A11 M2 AK26 AB15 N23 CPU_VDDR@4A X_C0.01U25Y
VDDNB4 VSS4 VDD4 VSS4 VDD4 VSS4
C6 VDDNB5 VSS5 AA4 M3 VDD5 VSS5 AK28 AB17 VDD5 VSS5 P2 D12 VTT1 VTT5 AK12
C8 AA5 M7 AK30 AB19 P3 C12 AJ12 C10u6.3X50805
VDDNB6 VSS6 VDD6 VSS6 VDD6 VSS6 VTT2 VTT6 near (1900,-4700)*3, near C116*2
D7 VDDNB7 VSS7 AA7 M9 VDD7 VSS7 AL5 AB21 VDD7 VSS7 P8 B12 VTT3 VTT7 AH12
D9 AA9 M11 B4 AB23 P10 VCC_DDR A12 AG12
VDDNB8 VSS8 VDD8 VSS8 VDD8 VSS8 VTT4 VTT8
D
E8 VDDNB9 VSS9 AA11 M13 VDD9 VSS9 B9 AC12 VDD9 VSS9 P12 VTT9 AL12 D
E10 VDDNB10 VSS10 AA13 M15 VDD10 VSS10 B11 AC14 VDD10 VSS10 P14 AB24 VDDIO1
F9 VDDNB11 VSS11 AA15 M17 VDD11 VSS11 B14 AC16 VDD11 VSS11 P16 AB26 VDDIO2 VSS1 K24
F11 VDDNB12 VSS12 AA17 M19 VDD12 VSS12 B16 AC18 VDD12 VSS12 P18 AB28 VDDIO3 VSS2 K26
G10 VDDNB13 VSS13 AA19 N8 VDD13 VSS13 B18 AC20 VDD13 VSS13 P20 AB30 VDDIO4 VSS3 K28
G12 VDDNB14 VSS14 AA21 N10 VDD14 VSS14 B20 AC22 VDD14 VSS14 P22 AC24 VDDIO5 VSS4 K30
VSS15 AA23 N12 VDD15 VSS15 B22 AD11 VDD15 VSS15 R7 AD26 VDDIO6 VSS5 L7
AA8 AB2 N14 B24 AD23 R9 AD28 L9 VCCP
VDD3 VSS16 VDD16 VSS16 VDD16 VSS16 VDDIO7 VSS6 EMI_0B
AA10 VDD4 VSS17 AB3 N16 VDD17 VSS17 B26 AE12 VDD17 VSS17 R11 AD30 VDDIO8 VSS7 L11
AA12 VDD5 VSS18 AB8 N18 VDD18 VSS18 B28 AF11 VDD18 VSS18 R13 AF30 VDDIO9 VSS8 L13
AA14 VDD6 VSS19 AB10 P7 VDD19 VSS19 B30 L20 VDD19 VSS19 R15 M24 VDDIO10 VSS9 L15
AA16 AB12 P9 C3 L22 R17 M26 L17 C788 C789 C790 C791 C792
VDD7 VSS20 VDD20 VSS20 VDD20 VSS20 VDDIO11 VSS10
AA18 VDD8 VSS21 AB14 P11 VDD21 VSS21 D14 M21 VDD21 VSS21 R19 M28 VDDIO12 VSS11 L19
AB7 VDD9 VSS22 AB16 P13 VDD22 VSS22 D16 M23 VDD22 VSS22 R21 M30 VDDIO13 VSS12 L21
AB9 VDD10 VSS23 AB18 P15 VDD23 VSS23 D18 N20 VDD23 VSS23 R23 P24 VDDIO14 VSS13 L23
AB11 VDD11 VSS24 AB20 P17 VDD24 VSS24 D20 N22 VDD24 VSS24 T8 P26 VDDIO15 VSS14 M8
AC4 AB22 P19 D22 P21 T10 P28 M10 X_C0.1U16Y0402 X_C0.1U16Y0402
VDD12 VSS25 VDD25 VSS25 VDD25 VSS25 VDDIO16 VSS15 X_C0.1U16Y0402 X_C0.1U16Y0402 X_C0.1U16Y0402
AC5 VDD13 VSS26 AC7 R4 VDD26 VSS26 D24 P23 VDD26 VSS26 T12 P30 VDDIO17 VSS16 M12
AC8 VDD14 VSS27 AC9 R5 VDD27 VSS27 D26 R22 VDD27 VSS27 T14 T24 VDDIO18 VSS17 M14
AC10 VDD15 VSS28 AC11 R8 VDD28 VSS28 D28 T23 VDD28 VSS28 T16 T26 VDDIO19 VSS18 M16
AD2 VDD16 VSS29 AC13 R10 VDD29 VSS29 D30 U22 VDD29 VSS29 T18 T28 VDDIO20 VSS19 M18
AD3 VDD17 VSS30 AC15 R12 VDD30 VSS30 E11 V23 VDD30 VSS30 T20 T30 VDDIO21 VSS20 M20
AD7 VDD18 VSS31 AC17 R14 VDD31 VSS31 F4 W22 VDD31 VSS31 T22 V25 VDDIO22 VSS21 M22
AD9 VDD19 VSS32 AC19 R16 VDD32 VSS32 F14 Y23 VDD32 VSS32 U4 V26 VDDIO23 VSS22 N4
AE10 VDD20 VSS33 AC21 R18 VDD33 VSS33 F16 VSS33 U5 V28 VDDIO24 VSS23 N5
AF7 VDD21 VSS34 AC23 R20 VDD34 VSS34 F18 VSS34 U7 V30 VDDIO25 VSS24 N7
AF9 VDD22 VSS35 AD8 T2 VDD35 VSS35 F20 VSS35 U9 Y24 VDDIO26 VSS25 N9
AG4 VDD23 VSS36 AD10 T3 VDD36 VSS36 F22 VSS36 U11 Y26 VDDIO27 VSS26 N11
AG5 VDD24 VSS37 AD12 T7 VDD37 VSS37 F24 VSS37 U13 Y28 VDDIO28 VSS27 N13
AG7 VDD25 VSS38 AD14 T9 VDD38 VSS38 F26 5 GND VSS38 U15 Y29 VDDIO29 VSS28 N15
AH2 AD16 T11 F28 Change to 6 U17
VDD26 VSS39 VDD39 VSS39 Passive GND VSS39
AH3 VDD27 VSS40 AD20 T13 VDD40 VSS40 F30 Pin 7 GND VSS40 U19
B3 VDD28 VSS41 AD22 T15 VDD41 VSS41 G9 8 GND VSS41 U21
C2 VDD31 VSS42 AD24 T17 VDD42 VSS42 G11 VSS42 U23
C4 VDD32 VSS43 AE4 T19 VDD43 VSS43 H8 VSS43 V2
D3 VDD35 VSS44 AE5 T21 VDD44 VSS44 H10 VSS44 V3
D5 U8 H12 V10 CPU1E
VDD36 VDD45 VSS45 VSS45
E4 VDD39 VSS46 AE11 U10 VDD46 VSS46 H14 VSS46 V12
C E6 VDD40 VSS47 AF2 U12 VDD47 VSS47 H16 1 GND VSS47 V14 INTERNAL MISC E C
F5 VDD43 VSS48 AF3 U14 VDD48 VSS48 H18 2 GND VSS48 V16 L25 RSVD1 RSVD17 E20MEM_MA_RESET# MEM_MA_RESET# 10,11
F7 VDD44 VSS49 AF8 U16 VDD49 3 GND VSS49 V18 L26 RSVD2 RSVD18 B19MEM_MB_RESET# MEM_MB_RESET# 10,11
G6 VDD47 VSS50 AF10 U18 VDD50 VSS50 H24 VSS50 V20 L31 RSVD3
G8 VDD48 VSS51 AF12 U20 VDD51 VSS51 H26 VSS51 V22 L30 RSVD4
H7 VDD51 VSS52 AF14 V9 VDD52 VSS52 H28 VSS52 W9
H11 AF16 V11 H30 W11 MEM_MA1_CLK_H0 W26 AK3
VDD52 VSS53 VDD53 VSS53 VSS53 11 MEM_MA1_CLK_H0 RSVD5 RSVD21
H23 AF18 V13 J4 W13 MEM_MA1_CLK_L0 W25
VDD53 VSS54 VDD54 VSS54 VSS54 11 MEM_MA1_CLK_L0 RSVD6
J8 AF20 V15 J5 W15 MEM_MA1_ODT1 AE27
VDD54 VSS55 VDD55 VSS55 VSS55 11 MEM_MA1_ODT1 RSVD7
J12 AF22 V17 J7 W17 MEM_MA0_CLK_H1 U24
VDD55 VSS56 VDD56 VSS56 VSS56 10 MEM_MA0_CLK_H1 RSVD8
J14 AF24 V19 J9 W19 MEM_MA0_CLK_L1 V24 F3 CPU_VDDIO_PWRGD
VDD56 VSS57 VDD57 VSS57 VSS57 10 MEM_MA0_CLK_L1 RSVD9 RSVD23
J16 AF26 V21 J11 W21 MEM_MA0_ODT1 AE28
VDD57 VSS58 VDD58 VSS58 VSS58 10 MEM_MA0_ODT1 RSVD10
J18 VDD58 VSS59 AF28 W4 VDD59 VSS59 J13 VSS59 W23
J20 AG10 W5 J15 Y8 MEM_MB1_CLK_H0 Y31 Add pin B2 as NP/RSVD
VDD59 VSS60 VDD60 VSS60 VSS60 11 MEM_MB1_CLK_H0 RSVD11
J22 AG11 W8 J17 Y10 MEM_MB1_CLK_L0 Y30
VDD60 VSS61 VDD61 VSS61 VSS61 11 MEM_MB1_CLK_L0 RSVD12
J24 AH14 W10 J19 Y12 MEM_MB1_ODT1 AG31
VDD61 VSS62 VDD62 VSS62 VSS62 11 MEM_MB1_ODT1 RSVD13
K7 AH16 W12 J21 W7 MEM_MB0_CLK_H1 V31 AD25
VDD62 VSS63 VDD63 VSS63 VSS63 10 MEM_MB0_CLK_H1 RSVD14 RSVD27
K9 AH18 W14 J23 Y20 MEM_MB0_CLK_L1 W31 AE24
VDD63 VSS64 VDD64 VSS64 VSS64 10 MEM_MB0_CLK_L1 RSVD15 RSVD28
K11 AH20 W16 K2 Y22 MEM_MB0_ODT1 AF31 AE25
VDD64 VSS65 VDD65 VSS65 VSS65 10 MEM_MB0_ODT1 RSVD16 RSVD29
K13 VDD65 VSS66 AH22 W18 VDD66 VSS66 K3 RSVD30 AJ18
K15 AH24 W20 K8 AD18 AJ20 VCC_DDR
VDD66 VSS67 VDD67 VSS67 KEY1 RSVD31 DG use 1KR PU
K17 VDD67 VSS68 AH26 Y2 VDD68 VSS68 K10 AD19 KEY2 RSVD32 C18
K19 VDD68 VSS69 AH28 Y3 VDD69 VSS69 K12 AE7 KEY3 RSVD33 C20
K21 AH30 Y7 K14 Remove pin H3, H4, H21, AD18, AD19, AE8;AE8 G24 R300 301R0402
VDD69 VSS70 VDD70 VSS70 change pin H20, AE7 to NP/VSS KEY4 RSVD34 R423 301R0402
K23 VDD70 VSS71 AK2 Y9 VDD71 VSS71 K16 H3 KEY5 RSVD35 G25
L4 VDD71 VSS72 AK14 Y11 VDD72 VSS72 K18 H4 KEY6 RSVD36 H25
L5 VDD72 VSS73 AK16 Y13 VDD73 VSS73 K20 H20 KEY7 RSVD37 V29 MEM_MB_EVENT# MEM_MB_EVENT# 10,11
L8 VDD73 VSS74 AK18 Y15 VDD74 VSS74 K22 H21 KEY8 RSVD38 W30 MEM_MA_EVENT# MEM_MA_EVENT# 10,11
L10 VDD74 VSS240 Y14 Y21 VDD75 VSS75 Y18
L12 VDD75 VSS241 Y16
Y17 EVENT pins are for future AM3r2
VDD150
Y19 VDD151
Layout: Route as 60 ohms
with 5/10 W/S from CPU pins.
CPU_VDDIO_PWRGD generater circuit

B VCCP VCC_DDR 100ns after VCC_DDR valid VCC3_SB B
VCC_DDR
Bottom side Bottom side
C685 C713 C698 C706 C689 C688 C700 C704 C693 C701 C694 C681 C697 C702 C684 C712 C705 C687 C690 C714 C768 VCC3_SB R472 R199
X_5.6KR1%0402 X_4.7KR0402
R172 CPU_VDDIO_PWRGD
C22u6.3X1206 C22u6.3X1206 C22u6.3X1206 C22u6.3X1206 C22u6.3X1206 C22u6.3X1206 C22u6.3X1206 C22u6.3X1206 C0.22U16X C0.01u16X-1 C10u6.3X50805 X_4.7KR0402
C
C22u6.3X1206 C22u6.3X1206 C22u6.3X1206 C22u6.3X1206 C22u6.3X1206 C22u6.3X1206 C22u6.3X1206 C0.01u16X-1 C180p50N C0.22U16X
VCC_DDR R661 B Q43
X_10KR0402 X_N-MMBT3904 R662
C
X_4.7KR0402 C855
E
VCCP VCC_DDR R635 B Q39 X_C1U10Y
Bottom side Place along the VCC_DDR/VSS plane splite X_10KR0402 X_N-MMBT3904
E
If the distance between the processor
C114 C682 C709 C686 C680 C703 C691 C711 C715 C710 C695 C699 C707 C696 C239 C131 C132 C774 C234 C819 C243 keepout and the keepout of the first DIMM
C210 C220 is less than 2.5 inches, there are four
additional 180-pF capacitors instead of two.
C0.22U16X C10u6.3X50805 C10u6.3X50805 C10u6.3X50805 C10u6.3X50805 C4.7U10Y0805 C4.7U10Y0805 C4.7U10Y0805 C4.7U10Y0805 C180P50N0402 C180P50N0402
C0.01u16X-1 C0.22U16X C10u6.3X50805 C10u6.3X50805 C10u6.3X50805 C0.01u16X-1 C4.7U10Y0805 C180P50N0402 C4.7u6.3X5 C4.7u6.3X5 C180P50N0402 C180P50N0402
CPU_VDDR VTT_DDR
Bottom side Place behind the DIMM Slot VCC_DDR
CPU_VDDNB
Bottom side TOP side, place close to CPU socket
1
C50 C224 C716 C246 C287 C267 C65 C130
1 +
1
C72 C683 C679 C107 C81 C108 C79 C80 C111 C110 C241 VCCP CPU_VDDNB EC20
2
.CD1000U6.3EL11.5 TP129 VCCP
2
C88 C2.2u10Y-RH C22u6.3X1206 C0.01u16X-1 X_C4.7U10Y0805 X_C4.7U10Y0805
2
C0.22U16X C0.01U16X0402 C4.7U10Y0805 C4.7U10Y0805 TP130 VCC_1V2

C22u6.3X1206 C10u6.3X50805 C0.22U16X C4.7U10Y0805 C0.01U16X0402
C22u6.3X1206 C0.01u16X-1 C10u6.3X50805 X_C0.22U16X C0.01U16X0402 C180P50N0402 TP131 CPU_VDDR
A CPU_VDDR A
Place between the DIMM Slot TP132 VCC_DDR
1
VCC_1V2 C68 C90 C66 C76 C233 C252 C61 C57 C258 C331 C262 C263 C261 C276
2
Bottom side
C0.22u10Y0402 C0.22u10Y0402 C4.7U10Y0805 C4.7U10Y0805 C10u6.3X50805 C4.7U10Y0805 C4.7U10Y0805
C104 C723 C105 C236 C229 C249 C237 VCC_DDR VCCP C0.22u10Y0402 C0.22u10Y0402 C0.01U16X0402 C4.7U10Y0805 C4.7U10Y0805 C4.7U10Y0805 C4.7U10Y0805
C708 C2.2u10Y-RH MICRO-START INT'L CO.,LTD.

Title
C10u6.3X50805 C4.7U10Y0805 C180P50N0402 C692 C2.2u10Y-RH CPU AM2 PWR & GND
C10u6.3X50805 C10u6.3X50805 C4.7U10Y0805 C180P50N0402
C VL390 0A
5 4 3 2 1
5 4 3 2 1
8,11 MEM_MA_DQS_H[7..0] VTT_DDR 8,11 MEM_MB_DQS_H[7..0] VTT_DDR

VCC_DDR VCC3 VCC_DDR VCC3
8,11 MEM_MA_DQS_L[7..0] 8,11 MEM_MB_DQS_L[7..0]
MEM_MA_EVENT# MEM_MB_EVENT#
MEM_MA_EVENT# 9,11 MEM_MB_EVENT# 9,11
8,11 MEM_MA_CHECK[7..0] 8,11 MEM_MB_CHECK[7..0]
170
173
176
179
182
183
186
189
191
194
197
236
120
240
167
187
198
170
173
176
179
182
183
186
189
191
194
197
236
120
240
167
187
198
51
54
57
60
62
65
66
69
72
75
78
68
53
79
48
49
51
54
57
60
62
65
66
69
72
75
78
68
53
79
48
49
DIMM1 DIMM2
VTT
VTT
NC/ERR_OUT
NC/TEST4
FREE1
FREE2
FREE3
FREE4
VTT
VTT
FREE1
FREE2
FREE3
FREE4
NC/ERR_OUT
NC/TEST4
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDSPD
NC/PAR_IN
RSVD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDSPD
NC/PAR_IN
RSVD
8,11 MEM_MA_DATA[63..0]
MEM_MA_DATA0 3 188 MEM_MA_ADD0 MEM_MB_DATA0 3 188 MEM_MB_ADD0
DQ0 A0 MEM_MA_ADD[15..0] 8,11 8,11 MEM_MB_DATA[63..0] DQ0 A0 MEM_MB_ADD[15..0] 8,11
MEM_MA_DATA2 DQ1 A1 MEM_MA_ADD2 MEM_MB_DATA2 DQ1 A1 MEM_MB_ADD2
9 DQ2 A2 61 9 DQ2 A2 61
122 DQ4 A4 59 122 DQ4 A4 59
D MEM_MA_DATA5 MEM_MA_ADD5 MEM_MB_DATA5 MEM_MB_ADD5 D
123 DQ5 A5 58 123 DQ5 A5 58
129 DQ7 A7 56 129 DQ7 A7 56
13 DQ9 A9 175 13 DQ9 A9 175
MEM_MA_DATA11 DQ10 A10/AP MEM_MA_ADD11 MEM_MB_DATA11 DQ10 A10/AP MEM_MB_ADD11
19 DQ11 A11 55 19 DQ11 A11 55
132 DQ13 A13 196 132 DQ13 A13 196
138 DQ15 A15 171 138 DQ15 A15 171
MEM_MA_DATA16 21 MEM_MB_DATA16 21
MEM_MA_DATA17 DQ16 MEM_MA_CHECK0 MEM_MB_DATA17 DQ16 MEM_MB_CHECK0
22 DQ17 CB0 39 22 DQ17 CB0 39
MEM_MA_DATA18 27 40 MEM_MA_CHECK1 MEM_MB_DATA18 27 40 MEM_MB_CHECK1
MEM_MA_DATA19 DQ18 CB1 MEM_MA_CHECK2 MEM_MB_DATA19 DQ18 CB1 MEM_MB_CHECK2
28 DQ19 CB2 45 28 DQ19 CB2 45
141 158 141 158
MEM_MA_DATA22
MEM_MA_DATA23
146
147
DQ21
DQ22
CB4
CB5 159
164
MEM_MA_CHECK5
MEM_MA_CHECK6
Add For ECC 0829 MEM_MB_DATA22
MEM_MB_DATA23
146
147
DQ21
DQ22
CB4
CB5 159
164
MEM_MB_CHECK5
MEM_MB_CHECK6
Add For ECC 0829
30 DQ24 CB7 165 30 DQ24 CB7 165
MEM_MA_DATA26 DQ25 MEM_MA_DQS_H0 MEM_MB_DATA26 DQ25 MEM_MB_DQS_H0
36 DQ26 DQS0 7 36 DQ26 DQS0 7
MEM_MA_DATA27 37 6 MEM_MA_DQS_L0 MEM_MB_DATA27 37 6 MEM_MB_DQS_L0
MEM_MA_DATA28 DQ27 DQS0# MEM_MA_DQS_H1 MEM_MB_DATA28 DQ27 DQS0# MEM_MB_DQS_H1
149 DQ28 DQS1 16 149 DQ28 DQS1 16
155 DQ30 DQS2 25 155 DQ30 DQS2 25
81 DQ32 DQS3 34 81 DQ32 DQS3 34
87 DQ34 DQS4 85 87 DQ34 DQS4 85
200 DQ36 DQS5 94 200 DQ36 DQS5 94
C MEM_MA_DATA37 MEM_MA_DQS_L5 MEM_MB_DATA37 MEM_MB_DQS_L5 C
201 DQ37 DQS5# 93 201 DQ37 DQS5# 93
MEM_MA_DATA38 206 103 MEM_MA_DQS_H6 MEM_MB_DATA38 206 103 MEM_MB_DQS_H6
MEM_MA_DATA39 DQ38 DQS6 MEM_MA_DQS_L6 MEM_MB_DATA39 DQ38 DQS6 MEM_MB_DQS_L6
207 102 207 102
MEM_MA_DATA40
MEM_MA_DATA41
90
91
DQ39
DQ40
DQS6#
DQS7 112
111
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MB_DATA41
90
91
DQ39
DQ40
DQS6#
DQS7 112
111
MEM_MB_DQS_H7
MEM_MB_DQS_L7 Add For ECC 0829
96 DQ42 DQS8 43 MEM_MA_DQS_H8 8,11 96 DQ42 DQS8 43 MEM_MB_DQS_H8 8,11
MEM_MA_DQS_L8 8,11 MEM_MB_DQS_L8 8,11
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
209
210
215
DQ43
DQ44
DQ45
DQ46
DDR3 DQS8#
DM0/DQS9
NC/DQS9#
125
126
MEM_MA_DM0
MEM_MA_DM[7..0] 8,11
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
209
210
215
DQ43
DQ44
DQ45
DQ46
DDR3 DQS8#
DM0/DQS9
NC/DQS9#
125
126
MEM_MB_DM0
MEM_MB_DM[7..0] 8,11
MEM_MA_DATA47 216 134 MEM_MA_DM1 MEM_MB_DATA47 216 134 MEM_MB_DM1
MEM_MA_DATA48 DQ47 DM1/DQS10 MEM_MB_DATA48 DQ47 DM1/DQS10
99 DQ48 NC/DQS10# 135 99 DQ48 NC/DQS10# 135
105 DQ50 NC/DQS11# 144 105 DQ50 NC/DQS11# 144
218 DQ52 NC/DQS12# 153 218 DQ52 NC/DQS12# 153
224 DQ54 NC/DQS13# 204 224 DQ54 NC/DQS13# 204
108 DQ56 NC/DQS14# 213 108 DQ56 NC/DQS14# 213
114 222 114 222
MEM_MA_DATA59
MEM_MA_DATA60
115
227
DQ58
DQ59
NC/DQS15#
DM7/DQS16 230
231
MEM_MA_DM7 MEM_MB_DATA59
MEM_MB_DATA60
115
227
DQ58
DQ59
NC/DQS15#
DM7/DQS16 230
231
MEM_MB_DM7 Add For ECC 0829
MEM_MA_DATA61 DQ60 NC/DQS16# MEM_MA_DM8 MEM_MB_DATA61 DQ60 NC/DQS16# MEM_MB_DM8
228 161 228 161
MEM_MA_DATA62
MEM_MA_DATA63
233
234
DQ61
DQ62
DM8/DQS17
NC/DQS17# 162
MEM_MA_DM8 8,11
MEM_MB_DATA63
233
234
DQ61
DQ62
DM8/DQS17
NC/DQS17# 162
MEM_MB_DM8 8,11
DQ63 MEM_MA0_ODT0 DQ63 MEM_MB0_ODT0

ODT0 195 MEM_MA0_ODT0 8 ODT0 195 MEM_MB0_ODT0 8
2 77 MEM_MA0_ODT1 2 77 MEM_MB0_ODT1
VSS ODT1 MEM_MA0_ODT1 9 VSS ODT1 MEM_MB0_ODT1 9
5 50 MEM_MA_CKE0 5 50 MEM_MB_CKE0
VSS CKE0 MEM_MA_CKE0 8,11 VSS CKE0 MEM_MB_CKE0 8,11
11 193 MEM_MA0_CS_L0 11 193 MEM_MB0_CS_L0
B VSS CS0# MEM_MA0_CS_L0 8 VSS CS0# MEM_MB0_CS_L0 8 B
VSS CS1# MEM_MA0_CS_L1 8 VSS CS1# MEM_MB0_CS_L1 8
17 71 MEM_MA_BANK0 17 71 MEM_MB_BANK0
VSS BA0 MEM_MA_BANK0 8,11 VSS BA0 MEM_MB_BANK0 8,11
26 VSS 26 VSS
29 73 MEM_MA_WE_L 29 73 MEM_MB_WE_L
VSS WE# MEM_MA_WE_L 8,11 VSS WE# MEM_MB_WE_L 8,11
32 192 MEM_MA_RAS_L 32 192 MEM_MB_RAS_L
VSS RAS# MEM_MA_RAS_L 8,11 VSS RAS# MEM_MB_RAS_L 8,11
35 74 MEM_MA_CAS_L 35 74 MEM_MB_CAS_L
VSS CAS# MEM_MA_CAS_L 8,11 VSS CAS# MEM_MB_CAS_L 8,11
38 168 MEM_MA_RESET# 38 168 MEM_MB_RESET#
VSS RESET# MEM_MA_RESET# 9,11 VSS RESET# MEM_MB_RESET# 9,11
41 VSS 41 VSS
De-coupling Caps For DIMMs 44 184 MEM_MA0_CLK_H0 44 184 MEM_MB0_CLK_H0
VSS CK0 MEM_MA0_CLK_H0 8 VSS CK0 MEM_MB0_CLK_H0 8
47 185 MEM_MA0_CLK_L0 47 185 MEM_MB0_CLK_L0
VSS CK0# MEM_MA0_CLK_L0 8 VSS CK0# MEM_MB0_CLK_L0 8
80 63 MEM_MA0_CLK_H1 80 63 MEM_MB0_CLK_H1
VSS CK1(NU) MEM_MA0_CLK_H1 9 VSS CK1(NU) MEM_MB0_CLK_H1 9
VSS CK1#(NU) MEM_MA0_CLK_L1 9 VSS CK1#(NU) MEM_MB0_CLK_L1 9
86 VSS 86 VSS
Place close to DIMM1 89 1 MEM_VREF_DQ MEM_VREF_DQ 89 1 MEM_VREF_DQ MEM_VREF_DQ
VCC_DDR VSS VREFDQ MEM_VREF_CA VSS VREFDQ MEM_VREF_CA
92 VSS VREFCA 67 MEM_VREF_CA 92 VSS VREFCA 67 MEM_VREF_CA
95 118 SCLK 95 118 SCLK
VSS SCL SCLK 11,12,18,26 VSS SCL
C806 C2.2u10Y-RH 98 238 SDATA 98 238 SDATA
VSS SDA SDATA 11,12,18,26 VSS SDA
C807 C2.2u10Y-RH 101 237 101 237
VSS SA1 VSS SA1
MEC1
MEC2
MEC3
MEC1
MEC2
MEC3
C808 C2.2u10Y-RH 104 117 104 117 VCC3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C810 C220p25N0402 VSS SA0 VSS SA0
DDRIII-240P_BLUE-RH DDRIII-240P_BLANK-RH
107
110
113
116
119
121
124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
199
202
205
208
211
214
217
220
223
226
229
232
235
239
MEC1
MEC2
MEC3
107
110
113
116
119
121
124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
199
202
205
208
211
214
217
220
223
226
229
232
235
239
MEC1
MEC2
MEC3
Place close to DIMM1
with DIMM2 VCC_DDR VCC_DDR
VCC_DDR
C809 C2.2u10Y-RH
MEM_VREF_DQ
A
DIMM1(CHANNEL-A A0) MEM_VREF_CA
DIMM2(CHANNEL-B B0) A
R48 C382 R44 C34
Place close to DIMM2 ADDRESS=0:0(SA1:SA0) 15R1% C0.1U16Y0402 15R1% C0.1U16Y0402 ADDRESS=0:1(SA1:SA0)
VCC_DDR
C811 C0.1U16Y0402
C582
C0.1U16Y0402
C805
C1000P50X0402
C804
C1000P50X0402
C36
C0.1U16Y0402
C785
C1000P50X0402
C772
C1000P50X0402
C812 C0.1U16Y0402
VCC_DDR R568 R55
VCC3
C235 X_C0.1U16Y0402
15R1% 15R1%
TP133 MEM_VREF_DQ MICRO-START INT'L CO.,LTD.
C813 C2.2u10Y-RH C242 X_C0.1U16Y0402 Title
TP134 MEM_VREF_CA FIRST LOGICAL DDR DIMM
Custom VL390 0A
5 4 3 2 1
5 4 3 2 1
8,10 MEM_MB_DQS_H[7..0]
8,10 MEM_MA_DQS_H[7..0]
VTT_DDR 8,10 MEM_MB_DQS_L[7..0] VTT_DDR
VCC_DDR VCC3 VCC_DDR VCC3
8,10 MEM_MA_DQS_L[7..0]
8,10 MEM_MB_CHECK[7..0]
MEM_MA_EVENT# MEM_MB_EVENT#
8,10 MEM_MA_CHECK[7..0] MEM_MA_EVENT# 9,10 MEM_MB_EVENT# 9,10
170
173
176
179
182
183
186
189
191
194
197
236
120
240
167
187
198
170
173
176
179
182
183
186
189
191
194
197
236
120
240
167
187
198
51
54
57
60
62
65
66
69
72
75
78
68
53
79
48
49
51
54
57
60
62
65
66
69
72
75
78
68
53
79
48
49
DIMM3 DIMM4
VTT
VTT
NC/TEST4
FREE1
FREE2
FREE3
FREE4
NC/ERR_OUT
VTT
VTT
NC/TEST4
FREE1
FREE2
FREE3
FREE4
NC/ERR_OUT
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDSPD
NC/PAR_IN
RSVD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDSPD
NC/PAR_IN
RSVD
8,10 MEM_MA_DATA[63..0]
DQ0 A0 MEM_MA_ADD[15..0] 8,10 8,10 MEM_MB_DATA[63..0] DQ0 A0 MEM_MB_ADD[15..0] 8,10
9 DQ2 A2 61 9 DQ2 A2 61
D MEM_MA_DATA3 MEM_MA_ADD3 MEM_MB_DATA3 MEM_MB_ADD3 D
10 DQ3 A3 180 10 DQ3 A3 180
123 DQ5 A5 58 123 DQ5 A5 58
129 DQ7 A7 56 129 DQ7 A7 56
13 DQ9 A9 175 13 DQ9 A9 175
MEM_MA_DATA11 DQ10 A10/AP MEM_MA_ADD11 MEM_MB_DATA11 DQ10 A10/AP MEM_MB_ADD11
19 DQ11 A11 55 19 DQ11 A11 55
132 DQ13 A13 196 132 DQ13 A13 196
138 DQ15 A15 171 138 DQ15 A15 171
MEM_MA_DATA17 DQ16 MEM_MA_CHECK0 MEM_MB_DATA17 DQ16 MEM_MB_CHECK0
22 DQ17 CB0 39 22 DQ17 CB0 39
28 45 28 45
MEM_MA_DATA20
MEM_MA_DATA21
140
141
DQ19
DQ20
CB2
CB3 46
158
MEM_MA_CHECK3
MEM_MA_CHECK4 Add For ECC 0829
MEM_MB_DATA20
MEM_MB_DATA21
140
141
DQ19
DQ20
CB2
CB3 46
158
MEM_MB_CHECK3
MEM_MB_CHECK4
Add For ECC 0829
146 DQ22 CB5 159 146 DQ22 CB5 159
30 DQ24 CB7 165 30 DQ24 CB7 165
MEM_MA_DATA26 DQ25 MEM_MA_DQS_H0 MEM_MB_DATA26 DQ25 MEM_MB_DQS_H0
36 DQ26 DQS0 7 36 DQ26 DQS0 7
149 DQ28 DQS1 16 149 DQ28 DQS1 16
155 DQ30 DQS2 25 155 DQ30 DQS2 25
81 DQ32 DQS3 34 81 DQ32 DQS3 34
87 DQ34 DQS4 85 87 DQ34 DQS4 85
C MEM_MA_DATA35 MEM_MA_DQS_L4 MEM_MB_DATA35 MEM_MB_DQS_L4 C
88 DQ35 DQS4# 84 88 DQ35 DQS4# 84
201 DQ37 DQS5# 93 201 DQ37 DQS5# 93
MEM_MA_DATA39
MEM_MA_DATA40
207
90
DQ38
DQ39
DQS6
DQS6# 102
112
MEM_MA_DQS_L6
MEM_MA_DQS_H7 Add For ECC 0829
MEM_MB_DATA39
MEM_MB_DATA40
207
90
DQ38
DQ39
DQS6
DQS6# 102
112
MEM_MB_DQS_L6
MEM_MB_DQS_H7
Add For ECC 0829
91 DQ41 DQS7# 111 91 DQ41 DQS7# 111
DQ42 DQS8 MEM_MA_DQS_H8 8,10 DQ42 DQS8 MEM_MB_DQS_H8 8,10
MEM_MA_DQS_L8 8,10 MEM_MB_DQS_L8 8,10
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
209
210
215
DQ43
DQ44
DQ45
DQ46
DDR3 DQS8#
DM0/DQS9
NC/DQS9#
125
126
MEM_MA_DM0
MEM_MA_DM[7..0] 8,10
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
209
210
215
DQ43
DQ44
DQ45
DQ46
DDR3 DQS8#
DM0/DQS9
NC/DQS9#
125
126
MEM_MB_DM0
MEM_MB_DM[7..0] 8,10
99 DQ48 NC/DQS10# 135 99 DQ48 NC/DQS10# 135
105 DQ50 NC/DQS11# 144 105 DQ50 NC/DQS11# 144
218 DQ52 NC/DQS12# 153 218 DQ52 NC/DQS12# 153
224 DQ54 NC/DQS13# 204 224 DQ54 NC/DQS13# 204
108 DQ56 NC/DQS14# 213 108 DQ56 NC/DQS14# 213
114 222 114 222
MEM_MA_DATA59
MEM_MA_DATA60
115
227
DQ58
DQ59
NC/DQS15#
DM7/DQS16 230
231
MEM_MA_DM7 Add For ECC 0829 MEM_MB_DATA59
MEM_MB_DATA60
115
227
DQ58
DQ59
NC/DQS15#
DM7/DQS16 230
231
MEM_MB_DM7 Add For ECC 0829
MEM_MA_DATA61 DQ60 NC/DQS16# MEM_MA_DM8 MEM_MB_DATA61 DQ60 NC/DQS16# MEM_MB_DM8
228 DQ61 DM8/DQS17 161 MEM_MA_DM8 8,10 228 DQ61 DM8/DQS17 161 MEM_MB_DM8 8,10
MEM_MA_DATA62 233 162 MEM_MB_DATA62 233 162
MEM_MA_DATA63 DQ62 NC/DQS17# MEM_MB_DATA63 DQ62 NC/DQS17#
234 DQ63 234 DQ63
195 MEM_MA1_ODT0 195 MEM_MB1_ODT0
ODT0 MEM_MA1_ODT0 8 ODT0 MEM_MB1_ODT0 8
2 77 MEM_MA1_ODT1 2 77 MEM_MB1_ODT1
VSS ODT1 MEM_MA1_ODT1 9 VSS ODT1 MEM_MB1_ODT1 9
B VSS CKE0 MEM_MA_CKE0 8,10 VSS CKE0 MEM_MB_CKE0 8,10 B
26 VSS 26 VSS
29 73 MEM_MA_WE_L 29 73 MEM_MB_WE_L
VSS WE# MEM_MA_WE_L 8,10 VSS WE# MEM_MB_WE_L 8,10
32 192 MEM_MA_RAS_L 32 192 MEM_MB_RAS_L
VSS RAS# MEM_MA_RAS_L 8,10 VSS RAS# MEM_MB_RAS_L 8,10
35 74 MEM_MA_CAS_L 35 74 MEM_MB_CAS_L
VSS CAS# MEM_MA_CAS_L 8,10 VSS CAS# MEM_MB_CAS_L 8,10
38 168 MEM_MA_RESET# 38 168 MEM_MB_RESET#
VSS RESET# MEM_MA_RESET# 9,10 VSS RESET# MEM_MB_RESET# 9,10
41 VSS 41 VSS
VSS CK0 MEM_MA1_CLK_H0 9 VSS CK0 MEM_MB1_CLK_H0 9
VSS CK0# MEM_MA1_CLK_L0 9 VSS CK0# MEM_MB1_CLK_L0 9
VSS CK1(NU) MEM_MA1_CLK_H1 8 VSS CK1(NU) MEM_MB1_CLK_H1 8
VSS CK1#(NU) MEM_MA1_CLK_L1 8 VSS CK1#(NU) MEM_MB1_CLK_L1 8
86 VSS 86 VSS
89 1 MEM_VREF_DQ MEM_VREF_DQ 89 1 MEM_VREF_DQ MEM_VREF_DQ
VSS VREFDQ MEM_VREF_CA VSS VREFDQ MEM_VREF_CA
92 VSS VREFCA 67 MEM_VREF_CA 92 VSS VREFCA 67 MEM_VREF_CA
De-coupling Caps For DIMMs 95 118 SCLK 95 118 SCLK
VSS SCL SCLK 10,12,18,26 VSS SCL
98 238 SDATA 98 238 SDATA
VSS SDA SDATA 10,12,18,26 VSS SDA
101 VSS SA1 237 VCC3 101 VSS SA1 237
MEC1
MEC2
MEC3
MEC1
MEC2
MEC3
104 117 104 117 VCC3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS SA0 VSS SA0
Place close to DIMM3 DDRIII-240P_BLUE-RH DDRIII-240P_BLANK-RH

107
110
113
116
119
121
124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
199
202
205
208
211
214
217
220
223
226
229
232
235
239
MEC1
MEC2
MEC3
107
110
113
116
119
121
124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
199
202
205
208
211
214
217
220
223
226
229
232
235
239
MEC1
MEC2
MEC3
VCC_DDR
C814 C2.2u10Y-RH
A Place close to DIMM3 A
with DIMM4 DIMM3(CHANNEL-A A1) DIMM2(CHANNEL-B B1)

VCC_DDR
ADDRESS=1:0(SA1:SA0) ADDRESS=1:1(SA1:SA0)
C821 C0.1U16Y0402
C822 C0.1U16Y0402
C829 C0.1U16Y0402
Vref-DQ : Reference voltage for DQ0每DQ63, CB0每CB7 and PAR_IN. When in single ended mode used for
DQS0每DQS7. MICRO-START INT'L CO.,LTD.
VCC3 Title
Vref-CA : Reference
RESET#(Output) voltage for A0-A15,
: A synchronously forces BA0每BA2, RAS#, output
all registered CAS#, WE#, S0#, RESET#
LOW when S01#, CKE0, CKE1, ODT0 and ODT1.
is LOW. SECOND LOGICAL DDR DIMM
C824 C2.2u10Y-RH
This signal can be used during power up to ensure that CKE is LOW and DQs are High-Z. Size Document Number Rev
Custom VL390 0A
5 4 3 2 1
5 4 3 2 1
NB CLOCK INPUT TABLE * RS780 can be used as clock buffer to output two PCIE referecence clocks
Clock Gen SLG8LP625 NB CLOCKS RS740
By deault, chip will configured as input mode, BIOS can program it to output mode.
RS780
HT_REFCLKP
66M SE(SE) 100M DIFF
HT_REFCLKN NC 100M DIFF
CLK_VDD 150 MILS WIDTH
L21 REFCLK_P
Place Close to PIN.33,40,48,28,11,14,21 14M SE (3.3V) 14M SE (1.1V) 100M DIFF
VCC3 REFCLK_N NC vref
600L500mA-300_0805 C364 C371 C358 C354 C333 C324 C363 C368 C369 100M DIFF
GFX_REFCLK 100M DIFF 100M DIFF(IN/OUT)*
D D
GPP_REFCLK NC 100M DIFF(OUT)
C22u6.3X1206 C0.1U16Y0402 C0.1U16Y0402 C0.1U16Y0402 C0.1U16Y0402 GPPSB_REFCLK 100M DIFF 100M DIFF
C0.1U16Y0402 C0.1U16Y0402 C0.1U16Y0402 C0.1U16Y0402
L25 15 MILS WIDTH U15

CLK_VDDA
VCC3 CLK_VDDA 36 VDD_A CPU_K8_0 42 CPU_CLK 7
600L500mA-300_0805 C348 C343 C347 35 41 CPU_CLK# 7 To CPU
VSS_A CPU_K8_0#
CPU_K8_1 38
CLK_VDDREF 52 37
VDD_REF CPU_K8_1#
53 VSS_REF
32 NB_GXF_CLK_R R265 0R0402 NB_GXF_CLK 15
C2.2u10Y-RH C22u6.3X1206 CLK_VDD48 ATIGCLK_0 NB_GXF_CLK#_R R268 0R0402
56 VDD_48 ATIGCLK_0# 31 NB_GXF_CLK# 15 To North Bridge GXF
C0.1U16Y0402 3 30
CLK_VDD VSS_48 ATIGCLK_1
ATIGCLK_1# 29
L20 12 MILS WIDTH CLK_VDD 33 26 PE16_GXF_CLK_R R250 0R0402 PE16_GXF_CLK 30
CLK_VDDREF VDD ATIGCLK_2 PE16_GXF_CLK#_R R267 0R0402
34 VSS ATIGCLK_2# 25 PE16_GXF_CLK# 30 To PCI-E x16 Slot 100MHz
600L500mA-300_0805 C321 40
Place Close to PIN.52 VDD_CPU
39 VSS_CPU
C2.2u10Y-RH 23 NB_SBREF_CLK_R R261 0R0402 NB_SBREF_CLK 15
SB_SRC_0 NB_SBREF_CLK#_R R274 0R0402
48 VDD_HTT SB_SRC_0# 22 NB_SBREF_CLK# 15 To North Bridge SB Reference clock
45 19 SB_LINK_CLK_R R269 0R0402 SB_LINK_CLK 17
VSS_HTT SB_SRC_1 SB_LINK_CLK#_R R266 0R0402
SB_SRC_1# 18 SB_LINK_CLK# 17 To South Bridge Link clock
L19 12 MILS WIDTH 28
CLK_VDD48 VDD_ATIGCLK
VCC3
11 VDD_SRC
600L500mA-300_0805 C335 Place Close to PIN.56 14 VDD_SRC
C 21 VDD_SB_SRC
C
C2.2u10Y-RH 17 PE1_GPP_CLK1_R R264 0R0402 PE1_GPP_CLK1 30
C319 C27p50N0402 SRC_0 PE1_GPP_CLK1#_R R263 0R0402
24 VSS_ATIGCLK SRC_0# 16 PE1_GPP_CLK1# 30 PCIEx1 Slot-1 GPP
27 VSS_ATIGCLK SRC_1 13
SRC_1# 12
2
10 9 LAN_CLK_R R504 0R0402 LAN_CLK 24

Y1 R216 VSS_SRC SRC_2 LAN_CLK#_R R505 0R0402
15 VSS_SRC SRC_2# 8 LAN_CLK# 24 PCIE LAN 100MHz GPP
14.318MHZ16P_D-RH X_1MR0402 20 7
1
VSS_SB_SRC SRC_3
SRC_3# 6
54 XTAL_IN
C338 C22P50N0402 55 XTAL_OUT
R210 4.7KR0402 CLK_RST# 44 47 NBHTT_CLK_R R208 0R0402 NBHTT_CLK 15 NB HTT 100M Clock(RS780)
VCC3 RESTORE# HTT_0/66M_0 NBHTT_CLK#_R R209 0R0402
HTT_0#/66M_1 46 NBHTT_CLK# 15 NB HTT 66M Clock (RS740)
R496 4
10,11,18,26 SCLK SCL
R494 X_0R0402 R582 5 2 SIO_48M_CLK_R R223 33R0402 SIO_48M_CLK 25 Super I/O 48MHz Clock
18,26,34 FP_RST# 10,11,18,26 SDATA SDA 48MHz_0
1 USB_48M_CLK_R R222 33R0402 USB_48M_CLK 18 USB 48MHz Clock
R211 1KR0402 CLK_PD# 48MHz_1
CLK_VDD 43 PD#
51 REF_0/SEL_HTT66
CLK_VDD
50 Clock chip has internal serial terminations Place close to Clock GEN
REF_1
49
for differencial pairs, external resistors are CPU_CLK
R510 3.3V REF_2 reserved for debug purpose. CPU_CLK#
X_8.2KR0402
SLG8LP625TTR_TSSOP56-RH SIO_48M_CLK
HWM_14M_RR USB_48M_CLK
R656 X_110R1%0402 OSC14M_REFOUT
17 SB_OSC_14M
R207 158R1%0402 NB_OSC_14M_R C780 C779 C815 C816
B 15 NB_OSC_14M B
X_C5P50N0402
X_C5P50N0402
X_C5P50N0402
1- PLACE ALL THE SERIES TERMINATION RESISTORS AS CLOSE AS U6 AS POSSIBLE
C5P50N0402
R224 R205
R207and R198 have X_75R1%0402 R198 8.2KR0402 2- ROUTE ALL CPUCLK/#, NBSRCCLK/#, GPPCLK/# AS DIFFERENT PAIR RULE
90.9R1%0402
been change value 3- PUT DECOUPLING CAPS CLOSE TO U15 POWER PIN
for support RS780
4-Enabled spread spectrum on all high frequency clocks; set to 0.5% down spread, for EMI reasons
2007/08/07 MS-7500
OSC_14M_NB R207/R198
RS780 (Single-ended) 1.1V 200R/100R
RS740 3.3V 33R Serial
Silego CRB Suggested
VCC3_SB
clock generator should not be enable before

+1.2v(VCC_1V2 is this design) is ready.
R665
10KR0402 TP110 CLK_VDD
VCC5_SB
TP111 CLK_VDDA
1.2V_PWRGD D48 CLK_PD#
R663 TP112 CLK_VDD48
4.7KR0402 S-RB751V-40_SOD323-RH
D
A TP113 CLK_VDDREF A
1.2V_PWRGD_R G Q98
N-2N7002_SOT23
VCC_1V2
C
R664 10KR0402 B REF_0/SEL_HTT66 (Pin51) HTT_0/66M_0 & HTT_0#/66M_1 (Pin 46,47)

Q96
N-MMBT3904
E
RS780 Title
0 Configure as differential 100MHz output
C853 Clock Gen ICS9LPR472
C1U10Y
RS740 Size Document Number Rev
1 Configure as single-ended 66MHz output Custom VL390 0A
5 4 3 2 1
5 4 3 2 1
RS780-HT LINK I/F
D HT_CADIN_H[15..0] D
7 HT_CADIN_H[15..0]
HT_CADIN_L[15..0]
7 HT_CADIN_L[15..0]
HT_CADOUT_H[15..0]
7 HT_CADOUT_H[15..0]
HT_CADOUT_L[15..0]
7 HT_CADOUT_L[15..0]
U14A U14D
HT_CADOUT_H0 Y25 D24 HT_CADIN_H0 PAR 4 OF 6
HT_CADOUT_L0 HT_RXCAD0P HT_TXCAD0P HT_CADIN_L0
HT_CADOUT_H1
Y24 HT_RXCAD0N PART 1 OF 6 HT_TXCAD0N D25
HT_CADIN_H1
AB12 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA18
V22 HT_RXCAD1P HT_TXCAD1P E24 AE16 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) AA20
HT_CADOUT_L1 V23 E25 HT_CADIN_L1 V11 AA19
HT_CADOUT_H2 HT_RXCAD1N HT_TXCAD1N HT_CADIN_H2 MEM_A2(NC) MEM_DQ2/DVO_DE(NC)
V25 HT_RXCAD2P HT_TXCAD2P F24 AE15 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) Y19
HT_CADOUT_L2 V24 F25 HT_CADIN_L2 AA12 V17
HT_CADOUT_H3 HT_RXCAD2N HT_TXCAD2N HT_CADIN_H3 MEM_A4(NC) MEM_DQ4(NC)
U24 HT_RXCAD3P HT_TXCAD3P F23 AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17
HT_CADOUT_L3 U25 F22 HT_CADIN_L3 AB14 AA15
HT_RXCAD3N HT_TXCAD3N MEM_A6(NC) MEM_DQ6/DVO_D2(NC)
HYPER TRANSPORT CPU I/F

HT_CADOUT_H4 T25 H23 HT_CADIN_H4 AD14 Y15
HT_CADOUT_L4 HT_RXCAD4P HT_TXCAD4P HT_CADIN_L4 MEM_A7(NC) MEM_DQ7/DVO_D4(NC)
T24 HT_RXCAD4N HT_TXCAD4N H22 AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20
HT_CADOUT_H5 P22 J25 HT_CADIN_H5 AD15 AD19
SBD_MEM/DVO_I/F
P23 HT_RXCAD5N HT_TXCAD5N J24 AC16 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) AE22
HT_CADOUT_H6 P25 K24 HT_CADIN_H6 AE13 AC18
C P24 HT_RXCAD6N HT_TXCAD6N K25 AC14 MEM_A12(NC) MEM_DQ12(NC) AB20 C
HT_CADOUT_H7 N24 K23 HT_CADIN_H7 Y14 AD22
N25 HT_RXCAD7N HT_TXCAD7N K22 MEM_DQ14/DVO_D10(NC) AC22
AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
HT_CADOUT_H8 AC24 F21 HT_CADIN_H8 AE17
HT_CADOUT_L8 HT_RXCAD8P HT_TXCAD8P HT_CADIN_L8 MEM_BA1(NC)
AC25 HT_RXCAD8N HT_TXCAD8N G21 AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
HT_CADOUT_H9 AB25 G20 HT_CADIN_H9 W18
HT_CADOUT_L9 HT_RXCAD9P HT_TXCAD9P HT_CADIN_L9 MEM_DQS0N/DVO_IDCKN(NC)
AB24 HT_RXCAD9N HT_TXCAD9N H21 W12 MEM_RASb(NC) MEM_DQS1P(NC) AD20
HT_CADOUT_H10 AA24 J20 HT_CADIN_H10 Y12 AE21
HT_CADOUT_L10 HT_RXCAD10P HT_TXCAD10P HT_CADIN_L10 MEM_CASb(NC) MEM_DQS1N(NC)
AA25 HT_RXCAD10N HT_TXCAD10N J21 AD18 MEM_WEb(NC)
HT_CADOUT_H11 Y22 J18 HT_CADIN_H11 AB13 W17
HT_CADOUT_L11 HT_RXCAD11P HT_TXCAD11P HT_CADIN_L11 MEM_CSb(NC) MEM_DM0(NC)
Y23 HT_RXCAD11N HT_TXCAD11N K17 AB18 MEM_CKE(NC) MEM_DM1/DVO_D8(NC) AE19
HT_CADOUT_H12 W21 L19 HT_CADIN_H12 V14 CP49
HT_CADOUT_L12 HT_RXCAD12P HT_TXCAD12P HT_CADIN_L12 MEM_ODT(NC)
W20 HT_RXCAD12N HT_TXCAD12N J19 IOPLLVDD18(NC) AE23 1 2 +1.8V_S0
HT_CADOUT_H13 V21 M19 HT_CADIN_H13 V15 AE24 1 2 NB_VCC1P1
HT_CADOUT_L13 HT_RXCAD13P HT_TXCAD13P HT_CADIN_L13 MEM_CKP(NC) IOPLLVDD(NC)
V20 HT_RXCAD13N HT_TXCAD13N L18 W14 MEM_CKN(NC)
HT_CADOUT_H14 U20 M21 HT_CADIN_H14 AD23 CP50 1.2V(RS740)
HT_CADOUT_L14 HT_RXCAD14P HT_TXCAD14P HT_CADIN_L14 IOPLLVSS(NC)
U21 HT_RXCAD14N HT_TXCAD14N P21 AE12 MEM_COMPP(NC)
HT_CADOUT_H15 U19 P18 HT_CADIN_H15 AD12 AE18
HT_CADOUT_L15 HT_RXCAD15P HT_TXCAD15P HT_CADIN_L15 MEM_COMPN(NC) MEM_VREF(NC)
U18 HT_RXCAD15N HT_TXCAD15N M18
AMD-215-0674028-A13
7 HT_CLKOUT_H0 T22 HT_RXCLK0P HT_TXCLK0P H24 HT_CLKIN_H0 7
7 HT_CLKOUT_L0 T23 HT_RXCLK0N HT_TXCLK0N H25 HT_CLKIN_L0 7
7 HT_CLKOUT_H1 AB23 HT_RXCLK1P HT_TXCLK1P L21 HT_CLKIN_H1 7
B 7 HT_CLKOUT_L1 AA22 HT_RXCLK1N HT_TXCLK1N L20 HT_CLKIN_L1 7 B
7 HT_CTLOUT_H0 M22 HT_RXCTL0P HT_TXCTL0P M24 HT_CTLIN_H0 7

7 HT_CTLOUT_L0 M23 HT_RXCTL0N HT_TXCTL0N M25 HT_CTLIN_L0 7
7 HT_CTLOUT_H1 R21 HT_RXCTL1P HT_TXCTL1P P19 HT_CTLIN_H1 7
7 HT_CTLOUT_L1 R20 HT_RXCTL1N HT_TXCTL1N R18 HT_CTLIN_L1 7
R197 RS780 301R0402 HT_RXCALP C23 B24 HT_TXCALP R196 301R0402
HT_RXCALN A24 HT_RXCALP HT_TXCALP HT_TXCALN
HT_RXCALN HT_TXCALN B25
NB_VCC1P1
AMD-215-0674028-A13
1.2V(RS740) RS740 R436 X_49.9R1%0402
RS740 R443 X_49.9R1%0402
RX780/RS740/RS780 difference table (HT LINK)

SIGNALS RS740 RS780
HT_RXCALP 49.9R (GND)

301R
HT_RXCALN 49.9R (VDDHT)
HT_TXCALP
A Decoupling Cap for HT. 100R 301R A
HT_TXCALN
VCC_1V2 C784 MICRO-START INT'L CO.,LTD.

VCCP
Title
X_C0.1U16Y0402 RS780-HT LINK I/F
B VL390 0A
5 4 3 2 1
A B C D E
RS780-PCIE I/F
4 4
U14B
30 GFX_RX0P D4 GFX_RX0P GFX_TX0P A5 GFX_TXC_0P 33
30 GFX_RX0N C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5 GFX_TXC_0N 33
30 GFX_RX1P A3 GFX_RX1P GFX_TX1P A4 GFX_TXC_1P 33
30 GFX_RX1N B3 GFX_RX1N GFX_TX1N B4 GFX_TXC_1N 33
30 GFX_RX2P C2 GFX_RX2P GFX_TX2P C3 GFX_TXC_2P 33
30 GFX_RX2N C1 GFX_RX2N GFX_TX2N B2 GFX_TXC_2N 33
30 GFX_RX3P E5 GFX_RX3P GFX_TX3P D1 GFX_TXC_3P 33
30 GFX_RX3N F5 GFX_RX3N GFX_TX3N D2 GFX_TXC_3N 33
30 GFX_RX4P G5 GFX_RX4P GFX_TX4P E2 GFX_TXC_4P 30
30 GFX_RX4N G6 GFX_RX4N GFX_TX4N E1 GFX_TXC_4N 30
30 GFX_RX5P H5 GFX_RX5P GFX_TX5P F4 GFX_TXC_5P 30
30 GFX_RX5N H6 GFX_RX5N GFX_TX5N F3 GFX_TXC_5N 30
30 GFX_RX6P J6 GFX_RX6P GFX_TX6P F1 GFX_TXC_6P 30
30 GFX_RX6N J5 GFX_RX6N GFX_TX6N F2 GFX_TXC_6N 30
30 GFX_RX7P J7 GFX_RX7P GFX_TX7P H4 GFX_TXC_7P 30
J8 H3
PCIE I/F GFX

30 GFX_RX7N GFX_RX7N GFX_TX7N GFX_TXC_7N 30
30 GFX_RX8P L5 GFX_RX8P GFX_TX8P H1 GFX_TXC_8P 30
30 GFX_RX8N L6 GFX_RX8N GFX_TX8N H2 GFX_TXC_8N 30
30 GFX_RX9P M8 GFX_RX9P GFX_TX9P J2 GFX_TXC_9P 30
30 GFX_RX9N L8 GFX_RX9N GFX_TX9N J1 GFX_TXC_9N 30
30 GFX_RX10P P7 GFX_RX10P GFX_TX10P K4 GFX_TXC_10P 30
3 30 GFX_RX10N M7 GFX_RX10N GFX_TX10N K3 GFX_TXC_10N 30 3
30 GFX_RX11P P5 GFX_RX11P GFX_TX11P K1 GFX_TXC_11P 30
30 GFX_RX11N M5 GFX_RX11N GFX_TX11N K2 GFX_TXC_11N 30
30 GFX_RX12P R8 GFX_RX12P GFX_TX12P M4 GFX_TXC_12P 30
30 GFX_RX12N P8 GFX_RX12N GFX_TX12N M3 GFX_TXC_12N 30
30 GFX_RX13P R6 GFX_RX13P GFX_TX13P M1 GFX_TXC_13P 30
30 GFX_RX13N R5 GFX_RX13N GFX_TX13N M2 GFX_TXC_13N 30
30 GFX_RX14P P4 GFX_RX14P GFX_TX14P N2 GFX_TXC_14P 30
30 GFX_RX14N P3 GFX_RX14N GFX_TX14N N1 GFX_TXC_14N 30
30 GFX_RX15P T4 GFX_RX15P GFX_TX15P P1 GFX_TXC_15P 30
30 GFX_RX15N T3 GFX_RX15N GFX_TX15N P2 GFX_TXC_15N 30
AE3 AC1 GPP_TX0P
30 GPP_RX0P GPP_RX0P GPP_TX0P GPP_TX0P 30
AD4 AC2 GPP_TX0N
30 GPP_RX0N GPP_RX0N GPP_TX0N GPP_TX0N 30
AE2 GPP_RX1P GPP_TX1P AB4
AD3 GPP_RX1N GPP_TX1N AB3
AD1 GPP_RX2P GPP_TX2P AA2
RX_LANP0
AD2 GPP_RX2N PCIE I/F GPP GPP_TX2N AA1
TX_LANP0 C392 C0.1U10X0402
24 RX_LANP0 V5 GPP_RX3P GPP_TX3P Y1 TXLANP 24
RX_LANN0 W6 Y2 TX_LANN0 C390 C0.1U10X0402
24 RX_LANN0 GPP_RX3N GPP_TX3N TXLANN 24
U5 GPP_RX4P GPP_TX4P Y4
U6 GPP_RX4N GPP_TX4N Y3
U8 GPP_RX5P GPP_TX5P V1
U7 GPP_RX5N GPP_TX5N V2
2 2
AA8 AD7 A_TX0P_C C365 C0.1U10X0402
17 A_RX0P SB_RX0P SB_TX0P A_TX0P 17
Y8 AE7 A_TX0N_C C362 C0.1U10X0402
17 A_RX0N SB_RX0N SB_TX0N A_TX0N 17
AA7 AE6 A_TX1P_C C367 C0.1U10X0402
Y7 AD6 A_TX1N_C C375 C0.1U10X0402
AA5 PCIE I/F SB AB6 A_TX2P0 C366 C0.1U10X0402
AA6 AC6 A_TX2N0 C372 C0.1U10X0402
W5 AD5 A_TX3P0 C384 C0.1U10X0402
Y5 AE5 A_TX3N0 C377 C0.1U10X0402
AC8 R236 1.27KR1%0402
PCE_CALRP(PCE_BCALRP) R243 2KR1%0402
PCE_CALRN(PCE_BCALRN) AB8 NB_VCC1P1
AMD-215-0674028-A13 1.2V (RS740) 1.1V(RS780)
RS780/RS740 GPP difference table RS780/RS740 GPP Routing table

RS740 RS780 RS740 RX780/RS780
1 PCE_CALRP 562R (GND) 1.27K (GND) PCIE1_X1 CONNECTOR GPP0 GPP0 1
GPP4 NC GPP4 PCIE1_X2 CONNECTOR GPP1 GPP1
GPP5 NC GPP5 GIGABIT ETHERNET GPP3 GPP3 MICRO-START INT'L CO.,LTD.

Title
RS780-PCIE I/F
B VL390 0A
A B C D E
5 4 3 2 1
RS780-SYSTEM I/F
U14C
Stuff For RS780 AVDD F12 A22 Stuff For RS780
AVDD1(NC) TXOUT_L0P(NC) CP17 +1.8V_S0
E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22
VCC3 AVDDDI F14 A21 1 2
AVDDDI(NC) TXOUT_L1P(NC)
G15 AVSSDI(NC) TXOUT_L1N(NC) B21
L31 220L250mA-600-RH AVDD AVDDQ H15 B20 VDDLTP18 L27 X_220L250mA-600-RH
AVDDQ(NC) TXOUT_L2P(NC)
H14 AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) A20
RS780 C734 A19 C349 C729
TXOUT_L3P(NC)
Button Sdie Button Sdie
CRT/TVOUT
E17 C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) B19
C2.2u10Y-RH F17 C10u10Y0805 C2.2u10Y-RH
RS780 Y(DFT_GPIO2) RS780 RS780
F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18
A18 CP7
CP16 TXOUT_U0N(NC) N-2N7002_SOT23
22 NB_VGA_R G18 RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3) A17 1 2
+1.8V_S0 1 2 G17 B17 Q34 RS780;RS740
D REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) VDDLT18 L17 X_220L250mA-600-RH D
22 NB_VGA_G E18 GREEN(DFT_GPIO1) TXOUT_U2P(NC) D20 +1.8V_S0
S
L26 X_600L350mA-450-RH AVDDDI F18 D21 ONLY single-link DVI is
GREENb(NC) TXOUT_U2N(NC)
G
E19 D18 applicable to the RS780L. C329 C328
RS780
22 NB_VGA_B BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) RS780;RS740
C726 F19 D19 Button Sdie
BLUEb(NC) TXOUT_U3N(NC) C0.1U16Y0402 C4.7U10Y0805 R214 4.7KR0402
Button Sdie +12V
C0.1U16Y0402 HSYNC A11 B16 RS780 RS780
RS780
22 HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1)
22 VSYNC VSYNC B11 A16
DACSDA DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3)
22 DAC_SDA E8 DAC_SDA(PCE_TCALRN) TXCLK_UP(PCIE_RESET_GPIO4) D16
22 DAC_SCL DACSCL F8 D17 R213 X_4.7KR0402
+1.8V_S0 DAC_SCL(PCE_RCALRN) TXCLK_UN(PCIE_RESET_GPIO1) +12V
CP13
R220 RS780 715R1%0402 G14 1 2
L22 220L250mA-600-RH AVDDQ DAC_RSET(PWM_GPIO1) VDDLTP18
VDDLTP18(NC) A13
G
PLLVDD RS780 A12 B13 VDDLT33 L23 X_220L250mA-600-RH VCC3
S
PLLVDD(NC) VSSLTP18(NC)
D
RS780 C722 PLLVDD18 RS780 D14
LVTM
PLLVDD18(NC) VDDLT18 C344 C725 Q35
Button Sdie B12 A15
PLL PWR
C2.2u10Y-RH PLLVSS(NC) VDDLT18_1(NC) X_N-2N7002_SOT23
VDDLT18_2(NC) B15 Button Sdie
RS780 VDDA18HTPLL H17 A14 VDDLT33 X_C0.1U16Y0402 X_C2.2u10Y-RH
VDDA18HTPLL VDDLT33_1(NC)
VDDLT33_2(NC) B14
VDDA18PCIEPLL D7 Stuff For RS740
NB_VCC1P1 VDDA18PCIEPLL1
E7 VDDA18PCIEPLL2 VSSLT1(VSS) C14
VSSLT2(VSS) D15
L30 220L250mA-600-RH PLLVDD NB_RST#_L D8 C16
SYSRESETb VSSLT3(VSS)
6,26 NB_PWRGD A10 POWERGOOD VSSLT4(VSS) C18
RS780 C731 LDT_STOP_NB# C10
PM
LDTSTOPb VSSLT5(VSS) C20
Button Sdie ALLOW_LDTSTOP C12 E20
C2.2u10Y-RH ALLOW_LDTSTOP VSSLT6(VSS)
VSSLT7(VSS) C22
RS780 C25
12 NBHTT_CLK HT_REFCLKP
12 NBHTT_CLK# C24 HT_REFCLKN
RS740_DFT_GPIO4 1.2V (RS740)
E11
CLOCKs
+1.8V_S0 12 NB_OSC_14M RS780 150R0402 REFCLK_P/OSCIN(OSCIN)
NB_VCC1P1 R244 F11 E9 NB_VCC1P1
220L250mA-600-RH R238 RS780 150R0402 REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) COMM_EN 30,33 RS740
LVDS_BLON(PCE_RCALRP) F7
L28 VDDA18HTPLL T2 G12 L52 X_220L250mA-600-RH
12 NB_GXF_CLK GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) R323
12 NB_GXF_CLK# T1 GFX_REFCLKN R338
RS780 C724 C728
Button Sdie TP38 U1
C2.2u10Y-RH C2.2u10Y-RH TP39 GPP_REFCLKP +1.8V_S0
U2 GPP_REFCLKN X_1.27KR1%0402
Stuff For RS780
C RS780 RS780 RS780 C
X_1.27KR1%0402 L38 220L250mA-600-RH VDDA18PCIEPLL
12 NB_SBREF_CLK V4 GPPSB_REFCLKP(SB_REFCLKP)
12 NB_SBREF_CLK# V3 GPPSB_REFCLKN(SB_REFCLKN) C735 C387
I2C_DATA A9 Button Sdie
+1.8V_S0 I2C_CLK I2C_DATA C2.2u10Y-RH C0.1U16Y0402
33 DP_AUX_DP DP_AUX_DP
B9
B8
I2C_CLK MIS. TMDS_HPD(NC) D9
D10 R660 RS740 RS740-DFT_GPIO5
L42 220L250mA-600-RH PLLVDD18 DP_AUX_DN DDC_DATA/AUX0P(NC) HPD(NC) X_0R0402 HPD_DP
33 DP_AUX_DN A8 DDC_CLK/AUX0N(NC) HPD_DP 33
RS740_DFT_GPIO0
RS780 C797
SWAP RS740_DFT_GPIO2
B7
A7
AUX1P(NC) TVCLKIN(PWM_GPIO5) D12
R537 10KR0402
AUX1N(NC)
Button Sdie THERMALDIODE_P AE8
C2.2u10Y-RH STRP_DATA B10 AD8
STRP_DATA THERMALDIODE_N
RS780 RS740_DFT_GPIO3 G11 D13 R219 1.8KR0402 NB_RST#_L C820 X_C180p50N0402
RSVD TESTMODE NB_PWRGD C823 X_C180p50N0402
RS740_DFT_GPIO1 C8 AUX_CAL(NC)
AMD-215-0674028-A13
RS740/RS780 difference table (Control signal)
NB_OSC_14M C370 C22P50N0402
RS740 RS780
NB_PWRGD 3.3V IN 1.8V IN

IN
ALLOW_LDTSTOP OD OD/3.3V IN
OUT(default)/IN
LDT_STOP# 3.3V IN 3.3V IN/OD Stuff For RS740
IN(default)/OUT
SYSTEMRESETb 3.3V IN 3.3V IN VCC3
IN RS740/RS780: STRAP_DEBUG_BUS_GPIO_ENABLE
R275 RS740 X_39.2KR1%0402 I2C_CLK
VSYNC R232 RS780 3KR0402
VCC3 RS740 X_39.2KR1%0402
R283 I2C_DATA
R230 X_3KR0402 Enables the Test Debug Bus using GPIO and/or memory IO
1 : Disable (RS740); Enable (RX780/RS780) R251 RS740 X_10KR0402 STRP_DATA
VCC3 0 : Enable (RS740); Disable(RX780/RS780)

RS740: pin DFT_GPIO5
B +1.8V_S0 B
RS740-DFT_GPIO5 R237 RS740 X_3KR0402 RS780: pin VSYNC
R305
X_4.7KR0402
RS780
G
DFT_GPIO[4:2]: STRAP_PCIE_GPP_CFG[2:0]
RS780
Q48
S D NB_RST#_L RS740_DFT_GPIO2 R297 X_3KR0402 These pin straps are used to configure PCI-E GPP mode.
7,17 LDT_RST#
111: register defined (register default to Config E) default
X_N-FDV301N_SOT23-3-RH RS740_DFT_GPIO3 R290 X_3KR0402 110: 4-0-0-0-0 Config A
R570 RS780 X_0R0402 RS740_DFT_GPIO4 R262 X_3KR0402 101: 4-4-0-0-0 Config B
100: 4-2-2-0-0 Config C
R571 0R0402 011: 4-2-1-1-0 Config D
17 PE_NB_RST#
010: 4-1-1-1-1 Config E
R159 others: register defined (default to Config E)
X_100R0402
Patch the timing of SYSRESET# & LDT_RST#
& LDT_STOP# (ER_RS780B6)
RS740/RS780: LOAD_EEPROM_STRAPS
VCC3 RS740_DFT_GPIO1 R291 RS780 150R1%0402 Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
+1.8V_S0 0 : I2C Master can load strap values from EEPROM if connected, or use
R277 default values if not connected
4.7KR0402 RS740: pin DFT_GPIO1
TP139 NB_OSC_14M
RS780: pin SUS_STAT#
G
TP140 NB_GXF_CLK
TP141 NB_GXF_CLK#
Q40
S D LDT_STOP_NB#
7,17 LDT_STOP# TP142 NB_SBREF_CLK
A N-FDV301N_SOT23-3-RH RS740/RS780: SIDE-PORT MEMORY ENABLE TP143 NB_SBREF_CLK# A
RS740;RS780 & DDR3 based CPU:
Level shifted and pulled up to 3.3V_S0 HSYNC R227 RS780 3KR0402
through a 4.7-k resistor on the Northbridge side VCC3
Enables Side port memory
R225 X_3KR0402 1. Disable (RS740/RS780)
+1.8V_S0 RS740_DFT_GPIO0 R292 X_3KR0402 0 : Enable (RS740/RS780)
RS740: pin DFT_GPIO0
RS780: pin HSYNC
R350
1KR0402
Title
RS780-SYSTEM I/F
ALLOW_LDTSTOP
17 ALLOW_LDTSTOP Size Document Number Rev
C VL390 0A
5 4 3 2 1
5 4 3 2 1
RS740/RX780/RS780 POWER DIFFERENCE TABLE
AE14
AC3
AC4
M11
AA4
AB5
AB1
AB7
AE1
AE4
AB2
D11
E14
E15
K14
L15
J15
J12
W1
W2
W4
W7
W8
M6
G1
G2
G4
G8
D3
D5
H7
R7
N4
R1
R2
R4
U4
A2
B1
E4
P6
V7
V8
V6
Y6
L1
L2
L4
L7
J4
PIN NAME RS740 RX780 RS780 PIN NAME RS740 RX780 RS780
U14F
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
AMD-215-0674028-A13 VDDHT NC +1.1V +1.1V IOPLLVDD +1.2V NC +1.1V
VDDHTRX NC +1.1V +1.1V AVDD +3.3V NC +3.3V
VDDHTTX +1.2V +1.2V +1.2V AVDDDI +1.8V NC +1.8V

D D
PART 6/6
GROUND VDDA18PCIE NC +1.8V +1.8V AVDDQ +1.8V NC +1.8V
VDD18 +1.8V +1.8V +1.8V PLLVDD +1.2V NC +1.1V
VDD18_MEM NC NC +1.8V PLLVDD18 +1.8V NC +1.8V
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
VDDPCIE +1.2V +1.1V +1.1V VDDA18PCIEPLL +1.2V +1.8V +1.8V
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VDDC +1.2V +1.1V +1.1V VDDA18HTPLL +1.8V +1.8V +1.8V
VDD_MEM +1.8V NC +1.8V(DDR2) VDDLTP18 +1.8V NC +1.8V

+1.5V(DDR3)
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VDD33 +3.3V NC +3.3V VDDLT18 +1.8V NC +1.8V
IOPLLVDD18 +1.8V NC +1.8V VDDLT33 +3.3V NC NC
NB_VCC1P1 L39 NB_VDDPCIE

X_30L3_15_0805
1 2
120 MILS WIDTH 1 2
NB_VDDPCIE
C
L16 Bottom side U14E Bottom side 300 MILS WIDTH CP21
C
NB_VCC1P1
RS780 VDDHTRXNB J17 A6
VDDHT_1 VDDPCIE_1
220L2A-50-RH C305 C301 C312 C721
K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6
C736 C389 C393 C394 C395
L16 VDDHT_3 VDDPCIE_3 C6
M16 VDDHT_4 VDDPCIE_4 D6
P16 VDDHT_5 VDDPCIE_5 E6
R16 VDDHT_6 VDDPCIE_6 F6
C0.1U16Y0402 C0.1U25Y T16 G7 C0.1U25Y C1U10Y C4.7U10Y0805
C4.7U10Y0805 C0.1U16Y0402 VDDHT_7 VDDPCIE_7 C0.1U16Y0402 C1U10Y
VDDPCIE_8 H8
H18 VDDHTRX_1 VDDPCIE_9 J9
70 MILS WIDTH Bottom side G19 K9
VDDHTRX_2 VDDPCIE_10
F20 VDDHTRX_3 VDDPCIE_11 M9
E21 VDDHTRX_4 VDDPCIE_12 L9
C308 C302 C304 C303 C720 D22 P9
VDDHTRX_5 VDDPCIE_13
B23 VDDHTRX_6 VDDPCIE_14 R9
A23 VDDHTRX_7 VDDPCIE_15 T9
VDDPCIE_16 V9
C4.7U10Y0805 C0.1U16Y0402 C0.1U25Y AE25 VDDHTTX_1 VDDPCIE_17 U9 Bottom side NB_VCC1P1
C0.1U16Y0402 X_C0.1U16Y0402 AD24 300 MILS WIDTH
VDDHTTX_2
AC23 VDDHTTX_3 VDDC_1 K12
AB22 VDDHTTX_4 VDDC_2 J14
AA21 U16 C727 C309 C311 C317 C310 C316 C315 C306 C307
Bottom side VDDHTTX_5 VDDC_3
Y20 VDDHTTX_6 VDDC_4 J11
L14 1 2 X_200L400_350_0805 VDDHTTXNB 45 MILS WIDTH W19 K15
POWER
VCC_1V2 VDDHTTX_7 VDDC_5
1 2 V18 VDDHTTX_8 VDDC_6 M12
CP6 C292 C297 C298 C299 C296 C719 U17 L14 C0.1U25Y C0.1U16Y0402 C0.1U16Y0402 C0.1U16Y0402 C10u10Y0805
VDDHTTX_9 VDDC_7 C0.1U16Y0402 C0.1U16Y0402 C0.1U16Y0402 C10u10Y0805
T17 VDDHTTX_10 VDDC_8 L11
R17 VDDHTTX_11 VDDC_9 M13
P17 VDDHTTX_12 VDDC_10 M15
C0.1U16Y0402 C0.1U16Y0402 C0.1U25Y M17 N12
L29 C4.7U10Y0805 X_C0.1U16Y0402 C0.1U16Y0402 VDDHTTX_13 VDDC_11
VDDC_12 N14
B RS780 VDD18NB 20 MILS WIDTH J10 P11 B
+1.8V_S0 VDDA18PCIE_1 VDDC_13
P10 VDDA18PCIE_2 VDDC_14 P13
220L2A-50-RH C350 C351 C352 C353 C360 C733 K10 P14
VDDA18PCIE_3 VDDC_15
M10 VDDA18PCIE_4 VDDC_16 R12
L10 VDDA18PCIE_5 VDDC_17 R15
W9 VDDA18PCIE_6 VDDC_18 T11
C4.7U10Y0805 C0.1U16Y0402 C0.1U25Y H9 T15
C4.7U10Y0805 C0.1U16Y0402 C0.1U16Y0402 VDDA18PCIE_7 VDDC_19
T10 VDDA18PCIE_8 VDDC_20 U12
R10 VDDA18PCIE_9 VDDC_21 T14
Y9 VDDA18PCIE_10 VDDC_22 J16
Bottom side AA9 VDDA18PCIE_11
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10
1 2 VDDG18 AD9 AA11 RS780 without Side-port:
+1.8V_S0 VDDA18PCIE_13 VDD_MEM2(NC)
CP52 15 MILS WIDTH AE9 Y11 Connected to GND plane
C730 VDDA18PCIE_14 VDD_MEM3(NC)
U10 VDDA18PCIE_15 VDD_MEM4(NC) AD10
VDD_MEM5(NC) AB10
C1U10Y F9 AC10
VDDG18_1(VDD18_1) VDD_MEM6(NC)
G9 VDDG18_2(VDD18_2) Bottom side VCC3
AE11 VDD18_MEM1(NC) VDDG33_1(NC) H11
RS780 without Side-port: AD11 H12 15 MILS WIDTH RS780 TP107 VDDHTRXNB
Connected to GND plane VDD18_MEM2(NC) VDDG33_2(NC)
AMD-215-0674028-A13 TP108 VDDHTTXNB
C732 C391
C0.1U16Y0402 C0.1U16Y0402 TP109 VDD18NB
VDDC 1.1V@13A
VDD18 1.8V@10 mA (Pin G9,F9)
VDD33 3.3 V at 60 mA (Pin H11,H12)
VDDA18PCIE 1.8 V at 700 mA
R143 X_0R0805 VDDA18PCIEPLL 1.8 V (RS780/RX780) or 1.2 V (RS740) at 120 mA.(Pin D7,E7)
/N VDDHT 1.1 V at 600 mA
A R144 0R0805 VDDHTRX 1.1 V at 700 mA A
+1.8V_S0 VDDHTTX 1.2 V at 400 mA
Z
VDDA18HTPLL 1.8 V at 20 mA (Pin H17)

PLLVDD18 1.8 V at 20 mA (Pin D14) Combine with H17
VCC3 X Y X Y PLLVDD 1.2 V (RS740) or 1.1 V (RS780) at 65 mA (Pin A12)
AVDD 3.3 V at 110 mA (Pin E12,F12)
D39 /N AVDDQ 1.8 V at 4 mA (Pin H15)
D38
BAV99-7-F_SOT23-LF BAV99-7-F_SOT23-LF AVDDDI 1.8 V at 20 mA(Pin F14) MICRO-START INT'L CO.,LTD.
VDDLT33 3.3 V at 180 mA (Pin A14,B14) RS740 only
Title
VDDLT18 1.8 V at 300 mA (Pin A15,B15)
VDDLTP18 1.8 V at 15 mA (Pin A13) RX780-POWER
Custom VL390 0A
5 4 3 2 1
A B C D E
PE_LAN_RST# R593 33R0402 U23A Place close to South Bridge

24 PE_LAN_RST#
PE_GF_RST# R587 33R0402
30 PE_GF_RST#
PE_NB_RST# R441 33R0402 A_RST# R594 0R0402 ARST# N2
SB700 P4 PCI_CLK0_R R440 22R0402 PCI_CLK0 Chasiss Intrusion
15 PE_NB_RST# A_RST# PCICLK0 PCI_CLK0 31
Part 1 of 5 P3 PCI_CLK1_R R446 22R0402 PCI_CLK1
PCI CLKS
PCICLK1 PCI_CLK1 31
C467 C0.1U10X0402 A_RX0P_C V23 P1 PCI_CLK2_R R478 22R0402 PCI_CLK2
4 14 A_RX0P PCIE_TX0P PCICLK2 PCI_CLK2 21 VBAT_IN 4
C468 C0.1U10X0402 A_RX0N_C V22 P2 SIO_PCLK_R R426 22R0402 SIO_PCLK
14 A_RX0N PCIE_TX0N PCICLK3 SIO_PCLK 21,25
C465 C0.1U10X0402 A_RX1P_C V24 T4 PCI_CLK4_R R438 22R0402 PCI_CLK4
14 A_RX1P PCIE_TX1P PCICLK4 PCI_CLK4 21,32 PCICLK5/GPIO41 power up default
C466 C0.1U10X0402 A_RX1N_C V25 T3 PCI_CLK5_R R491 22R0402 PCI_CLK5
14 A_RX1N PCIE_TX1N PCICLK5/GPIO41 PCI_CLK5 21 A11:PCICLK5 A12:GPIO41
C464 C0.1U10X0402 A_RX2P_C U25 JCI1
14 A_RX2P PCIE_TX2P
C463 C0.1U10X0402 A_RX2N_C U24 1 Chasiss R416 1MR0402
14 A_RX2N PCIE_TX2N Place close to South Bridge
C412 C0.1U10X0402 A_RX3P_C T23 2
14 A_RX3P PCIE_TX3P
C413 C0.1U10X0402 A_RX3N_C T22 N1 SB_PCIRST# R657 0R0402 PCIRST# R425 33R0402 N32-1020391-A10
14 A_RX3N PCIE_TX3N PCIRST# PCIRST_SLOT1# 31 CO-LAY
R430 33R0402
PCI EXPRESS INTERFACE

AD[31..0] PCIRST_SIO# 25 N31-1020011-C09
U22 R456 33R0402 _BH1X2_white-3.5mm-RH
14 A_TX0P PCIE_RX0P AD[31..0] 31 PCIRST_TPM# 32
U21 U2 AD0
14 A_TX0N PCIE_RX0N AD0
U19 P7 AD1
14 A_TX1P PCIE_RX1P AD1
V19 V4 AD2
R20 T1 AD3 INTRUDER_ALERT# R519 0R0402 Chasiss
14 A_TX2P PCIE_RX2P AD3
R21 V3 AD4
14
14
A_TX2N
A_TX3P R18
R17
PCIE_RX2N
PCIE_RX3P
AD4
AD5 U1
V1
AD5
AD6
Modify 0829 R517 X_1MR0402
Internal 50K PU
VBAT_IN
V2 AD7
R345 562R1%0402 T25 AD7 AD8
PCIE_CALRP AD8 T2
VCC_SB_1V2 R344 2.05KR1%0402 T24 W1 AD9
PCIE_VDDR PCIE_CALRN AD9
T9 AD10
L40 PE_PVDD 40mA P24 AD10 AD11
PCIE_PVDD AD11 R6
R7 AD12 VCC3
220L250mA-600-RH AD12 AD13
P25 PCIE_PVSS AD13 R5
U8 AD14
C407 C410 AD14 AD15
AD15 U5
C2.2u10Y-RH X_C0.1U16Y0402 Y7 AD16
AD16 AD17 R672 R673
AD17 W8
V9 AD18
AD18
X_4.7KR0402
X_4.7KR0402
Y8 AD19
AD19 AD20 U32
AD20 AA8
3 AD21 ARST# A_RST# 3
AD21 Y4 1 A1 Y1 6
Y3 AD22
AD22 AD23
AD23 Y2 2 GND VCC 5
AA2 AD24
AD24 AD25 SB_PCIRST# PCIRST#
AD25 AB4 3 A2 Y2 4
N25 AA1 AD26
12 SB_LINK_CLK PCIE_RCLKP/NB_LNK_CLKP AD26
N24 AB3 AD27 X_NC7WZ07P6X_SC70-6
12 SB_LINK_CLK# PCIE_RCLKN/NB_LNK_CLKN AD27
AB2 AD28
AD28
PCI INTERFACE
TP33 K23 AC1 AD29
TP32 NB_DISP_CLKP AD29 AD30
K22 NB_DISP_CLKN AD30 AC2
AD1 AD31 C_BE#[3..0]
AD31 C_BE#[3..0] 31
M24 W2 C_BE#0
NB_HT_CLKP CBE0# C_BE#1
M25 NB_HT_CLKN CBE1# U7
AA7 C_BE#2
CBE2# C_BE#3
P17 CPU_HT_CLKP CBE3# Y1
M18 AA6 PCI_CLK0 C569 C22P50N0402
CPU_HT_CLKN FRAME# FRAME# 31
DEVSEL# W5 DEVSEL# 31
M23 SLT_GFX_CLKP IRDY# AA5 IRDY# 31
M22 SLT_GFX_CLKN TRDY# Y5 TRDY# 31
PAR U6 PAR 31
J19 GPP_CLK0P STOP# W6 STOP# 31
J18 W4 SIO_PCLK C555 C22P50N0402
GPP_CLK0N PERR# PERR# 31
SERR# V7 SERR# 31
L20 GPP_CLK1P REQ0# AC3 PREQ#0 31
L19 GPP_CLK1N CLOCK GENERATOR REQ1# AD4 PREQ#1 31
AB7 TP42 Place close to device
REQ2# TP43
M19 GPP_CLK2P REQ3#/GPIO70 AE6
Reserve cystal for A14 to solve the system time lag issue; TP21
Also can connect the 14M from clock gen to 14M_X1
M20 GPP_CLK2N REQ4#/GPIO71 AB6
AD2
For EMI
and leace 14M_X2 NC, 1.2V level shift may needed GNT0# PGNT#0 31
N22 AE4 PGNT#1
2 GPP_CLK3P GNT1# PGNT#1 31 2
P22 AD5 PGNT#2 TP29
GPP_CLK3N GNT2# PGNT#3 TP37
GNT3#/GPIO72 AC6
L18 AE5 PGNT#4 TP17
R659 X_0R0402 25M_48M_66M_OSC GNT4#/GPIO73
12 SB_OSC_14M CLKRUN# AD6 PCI_CLKRUN# 32
LOCK# V5 LOCK# 31
C817 X_C22P50N0402 14M_X1 R658 X_0R0402 SB_14M J21 25M_X1
INTE#/GPIO33 AD3 PCI_INTA# 31
2
INTF#/GPIO34 AC4 PCI_INTB# 31

Y6 R572 AE2
INTG#/GPIO35 PCI_INTC# 31
X_14.318MHZ16P_D X_10MR0402 14M_X2 J20 AE3 PCI_INTD# 31
1
25M_X2 INTH#/GPIO36
14M_X2
C818 X_C22P50N0402 G22 LPC_CLK0
LPCCLK0 LPC_CLK0 21
E22 LPC_CLK1
LPCCLK1 LPC_CLK1 21
32K_X1 A3 H24
X1 LAD0 LPC_AD0 25,32
LAD1 H23 LPC_AD1 25,32
RTC XTAL
LAD2 J25 LPC_AD2 25,32

J24
LPC
LAD3 LPC_AD3 25,32

32K_X2 B3 H25
X2 LFRAME# LPC_FRAME# 25,32
32K_X1 H22
LDRQ0# LPC_DRQ#0 25 TP114
AB8 LDRQ#1 TP54 VBAT_IN
LDRQ1#/GNT5#/GPIO68 TP56
BMREQ#/REQ5#/GPIO65 AD7
Y5 V15
SERIRQ SERIRQ 25,32 TP144
32.768KHZ12.5P_D-1 SB_14M
2 1 32K_X2 F23 SB700 has an internal 15k PU
15 ALLOW_LDTSTOP ALLOW_LDTSTP VBAT_IN
F24 C3 RTCCLK TP36
7 CPU_PROCHOT# PROCHOT# RTCCLK INTRUDER_ALERT#
RTC
6,7 LDT_PWRGD F22 C2

4
3
LDT_PG INTRUDER_ALERT#
CPU
G25 B2 R303 510R0402

7,15 LDT_STOP# LDT_STP# VBAT
7,15 LDT_RST# G24 LDT_RST# C380 C383 BAT1
1 R400 20MR 1
AMD-218S7EBLA12FG-A12-RH C1U10Y C0.1U16Y0402
BAT-2P-RH-1
C541 C540 Note: LDT_PG, LDT_STP# & LDT_RST# are OD
C18p50N0402 C18p50N0402 and require a PU to the CPU I/O rail. They are
also in the S5 domain to prevent glitching at Put C308 & C383 Close to B2 pin
power up. MICRO-START INT'L CO.,LTD.
PLACE THESE COMPONENTS CLOSE TO Title
U600, AND USE GROUND GUARD FOR SB700 PCIE/PCI/CPU/LPC
32K_X1 AND 32K_X2
Custom VL390 0A
A B C D E
A B C D E
R418,R422,R212,R565,R655 may be removed

U23D
VCC3
SB700 Part 4 of 5
31 PCI_PME# E1 PCI_PME#/GEVENT4#
KBRST# R382 1KR0402 RI# E2 C8 USB_48M_CLK USB_48M_CLK 12 USB_48M_CLK
RI#/EXTEVNT0# USBCLK/14M_25M_48M_OSC
30 GFX16_PCIERST# H7 SLP_S2/GPM9#
SDATA_IN_R R428 10KR0402 F5 G8 USB_RCOMP R409 11.8KR1%0402 C536
USB MISC
25,26 SLP_S3# SLP_S3# USB_RCOMP
26,27 SLP_S5# G1 SLP_S5#
ACPI / WAKE UP EVENTS

SCLK R375 2.2KR0402 SB_PWRON# H2 C22P50N0402
25 SB_PWRON# PWR_BTN#
26 SB_PWRGD H1 PWR_GOOD
SDATA R374 2.2KR0402 SUS_STAT# K3 Place close
4 SB_TEST2 SUS_STAT# to SB 4
H5 TEST2 USB_FSDP13+ E6
SUS_STAT# R565 X_10KR0402 SB_TEST1 H4 E7
SB_TEST0 TEST1 USB_FSDM13-
H3 TEST0
USB 1.1
CPU_THRIP# R212 4.7KR0402 A20GATE Y15 F7
25 A20GATE GA20IN/GEVENT0# USB_FSDP12+
KBRST# W15 E8
25 KBRST# KBRST#/GEVENT1# USB_FSDM12-
LC_SENSE R469 X_10KR0402 K4
25 LPC_PME# LPC_PME#/GEVENT3#
VCC3_SB LPC_SMI# K24 H11
25 LPC_SMI# LPC_SMI#/EXTEVNT1# USB_HSDP11+
S3_STATE F1 J10
27 S3_STATE S3_STATE/GEVENT5# USB_HSDM11-
SCLK1 R427 2.2KR0402 J2
12,26,34 FP_RST# SYS_RESET#/GPM7#
24,30 WAKE# H6 WAKE#/GEVENT8# USB_HSDP10+ E11
SDATA1 R439 2.2KR0402 F2 F11
NB_PWRGD CPU_THRIP# BLINK/GPM6# USB_HSDM10-
7 CPU_THRIP# J6 SMBALERT#/THRMTRIP#/GEVENT2#
RSMRST# R413 10KR0402 A12 Open Drain WD_PWRGD W14 A11
A11 Push pull 26 WD_PWRGD NB_PWRGD USB_HSDP9+ USB9+ 29
USB_HSDM9- B11 USB9- 29
RI# R418 10KR0402 IO_RSMRST# R412 0R0402 RSMRST# D3
25 IO_RSMRST# RSMRST#
C10 USB8+ 29
SUS_STAT# R424 10KR0402 RSMRST# not de-asserted until at least 10 ms C547 X_C1000P50X0402 USB_HSDP8+
D10 USB9 FRONT PANEL
after S5_3.3V is valid. USB_HSDM8- USB8- 29
RSMRST# ramp up time (10% to 90%) ≒ 50 ms
USB8 FRONT PANEL
SB_PWRON# R422 1KR0402 AE18 G11
SATA_IS0#/GPIO10 USB_HSDP7+ USB7+ 29 USB7 FRONT PANEL
AD18 CLK_REQ3#/SATA_IS1#/GPIO6 USB_HSDM7- H12 USB7- 29
LPC_SMI# R655 X_10KR0402 R522 0R0402 AA19 USB6 FRONT PANEL
7 CPU_PRESENT# SMARTVOLT/SATA_IS2#/GPIO4
W17 E12 USB6+ 29
V17
CLK_REQ0#/SATA_IS3#/GPIO0 USB_HSDP6+
E14 USB5 STACK4 USB4
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 USB_HSDM6- USB6- 29
W20 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40 USB4 STACK4 USB3
SB_GPIO5 R377 10KR0402 W21 C12
USB 2.0
34 SPKR SPKR/GPIO2 USB_HSDP5+ USB5+ 29 USB3 STACK4 USB2
SCLK AA18 D12
10,11,12,26 SCLK SCL0/GPOC0# USB_HSDM5- USB5- 29
SDATA W18 USB2 STACK4 USB1
10,11,12,26 SDATA SDA0/GPOC1#
SCLK1 K1 B12
24,30,31,32 SCLK1
SDATA1 K2
SCL1/GPOC2# USB_HSDP4+
A12
USB4+ 29 USB1 LAN USB BOTTOM
GPIO
24,30,31,32 SDATA1 SDA1/GPOC3# USB_HSDM4- USB4- 29
3
AA20 DDC1_SCL/GPIO9 USB0 LAN USB TOP 3
SB_PWRGD C825 X_C180p50N0402 Y18 G12
19 SPI_WP# DDC1_SDA/GPIO8 USB_HSDP3+ USB3+ 29
LC_SENSE C1 G14
LLB#/GPIO66 USB_HSDM3- USB3- 29
SB_GPIO5 Y19 SHUTDOWN#/GPIO5
G5 DDR3_RST#/GEVENT7# USB_HSDP2+ H14 USB2+ 29
USB_HSDM2- H15 USB2- 29
USB_HSDP1+ A13 USB1+ 29

SCLK C484 X_C22P50N0402 B13 VCC3_SB
USB_HSDM1- USB1- 29
SDATA C483 X_C22P50N0402 VCC3
USB_HSDP0+ B14 USB0+ 29
SCLK1 C584 X_C22P50N0402 TP34 B9 A14
USB_OC6#/IR_TX1/GEVENT6# USB_HSDM0- USB0- 29
SDATA1 C573 X_C22P50N0402 OC#6 B8 USB_OC5#/IR_TX0/GPM5# GPIO8 R360 R367 R361
A8 A18
USB OC
29 OC#5 USB_OC4#/IR_RX0/GPM4# KSO_16/EC_GPIO8
29 OC#4 A9 USB_OC3#/IR_RX1/GPM3# KSO_17/EC_GPIO9 B18 ISOLATEBR 2410KR0402 10KR0402 X_10KR0402
E5 F21 R941
29 OC#3 USB_OC2#/GPM2# EC_PWM0/EC_GPIO10
F8 D21 GPIO8 DSM_GPO# 24
29 OC#2 USB_OC1#/GPM1# SCL2/EC_GPIO11
AZ_BIT_CLK C585 X_C22P50N0402 E4 F19
29 OC#1 USB_OC0#/GPM0# SDA2/EC_GPIO12
E20 X_0R0402
AZ_BITCLK_R SCL3_LV/EC_GPIO13
M1 AZ_BITCLK SDA3_LV/EC_GPIO14 E21
RN33 8P4R-22R0402 AZ_SDATA_OUT_R M2 E19
AZ_SDATA_OUT_R SDATA_IN_R AZ_SDOUT EC_PWM1/EC_GPIO15
28 AZ_SDOUT 1 2 J7 AZ_SDIN0/GPIO42 EC_PWM2/EC_GPO16 D19 SB_GP16 21
HD AUDIO
AZ_BITCLK_R
28 AZ_BIT_CLK 3
5
4
6 AZ_SYNC_R
J8
L8
AZ_SDIN1/GPIO43 EC_PWM3/EC_GPO17 E18 SB_GP17 21 Add 0902
28 AZ_SYNC AZ_SDIN2/GPIO44
7 8 SDATA_IN_R M3 G20 STRAP pin to define
28 AZ_SDIN AZ_SDIN3/GPIO46 KSI_0/EC_GPIO18
R429 22R0402 AZ_RST_R AZ_SYNC_R L6 G21
21,28 AZ_RST#
AZ_RST_R M4
AZ_SYNC KSI_1/EC_GPIO19
D25
use LPC or SPI ROM
AZ_RST# KSI_2/EC_GPIO20
L5 AZ_DOCK_RST#/GPM8# KSI_3/EC_GPIO21 D24
KSI_4/EC_GPIO22 C25
KSI_5/EC_GPIO23 C24
KSI_6/EC_GPIO24 B25
2 C23 2
KSI_7/EC_GPIO25
KSO_0/EC_GPIO26 B24
KSO_1/EC_GPIO27 B23
EMBEDDED CTRL
KSO_2/EC_GPIO28 A23
KSO_3/EC_GPIO29 C22
KSO_4/EC_GPIO30 A22
KSO_5/EC_GPIO31 B22
VCC3_SB B21
KSO_6/EC_GPIO32
KSO_7/EC_GPIO33 A21
RN11 8P4R-10KR0402 H19 D20
OC#1 PS2_DAT/EC_GPIO0 KSO_8/EC_GPIO34
1 2 H20 PS2_CLK/EC_GPIO1 KSO_9/EC_GPIO35 C20
EMBEDDED CTRL
3 4 OC#2 H21 A20
OC#3 SPI_CS2#/EC_GPIO2 KSO_10/EC_GPIO36
5 6 F25 IDE_RST#/F_RST#/EC_GPO3 KSO_11/EC_GPIO37 B20
7 8 OC#4 B19
KSO_12/EC_GPIO38
D22 PS2KB_DAT/EC_GPIO4 KSO_13/EC_GPIO39 A19
R574 10KR0402 OC#5 E24 D18
R591 10KR0402 OC#6 PS2KB_CLK/EC_GPIO5 KSO_14/EC_GPIO40
E25 PS2M_DAT/EC_GPIO6 KSO_15/EC_GPIO41 C18
D23 PS2M_CLK/EC_GPIO7 TP145 USB_48M_CLK
AMD-218S7EBLA12FG-A12-RH
VCC3_SB VCC3_SB VCC3_SB
R444 R419 R420
X_2.2KR0402 X_2.2KR0402 X_2.2KR0402

1 SB_TEST2 1
SB_TEST1
SB_TEST0
R437 R417 R421

X_10KR0402 X_10KR0402 X_10KR0402 Title
SB700 ACPI/GPIO/USB/AUDIO
Custom VL390 0A
A B C D E
5 4 3 2 1
VCC3_SB VCC3_SB
U23B
D D
SATA_TX0+ AD9
SB700 AA24 C487 C574
23 SATA_TX0+ SATA_TX0+ IDE_IORDY
SATA_TX0- AE9 Part 2 of 5 AA25 R364 C10u10Y0805
23 SATA_TX0- SATA_TX0- IDE_IRQ
Y22 R386 R390 10KR0402
SATA_RX0- IDE_A0 1KR0402 C0.1U16Y0402
23 SATA_RX0- AB10 SATA_RX0- IDE_A1 AB23 10KR0402 U22
SATA_RX0+ AC10 Y23
23 SATA_RX0+ SATA_RX0+ IDE_A2
AB24 SPI_CS# 1 8
SATA_TX1+ IDE_DACK# SPI_DATAIN CS# VCC SPI_HOLD# R358 X_0R0402 SPI_HOLD_L
23 SATA_TX1+ AE10 SATA_TX1+ IDE_DRQ AD25 2 DO HOLD# 7
SATA_TX1- AD10 AC25 SPI_WP 3 6 SPI_CLK
23 SATA_TX1- SATA_TX1- IDE_IOR# 18 SPI_WP# WP# CLK
AC24 R388 4 5 SPI_DATAOUT
SATA_RX1- IDE_IOW# 0R0402 GND DIO
23 SATA_RX1- AD11 SATA_RX1- IDE_CS1# Y25
SATA_RX1+ AE11 Y24 W25X16AVSSIG-RH
23 SATA_RX1+ SATA_RX1+ IDE_CS3#
SATA_TX2+ AB12 AD24 16M
23 SATA_TX2+ SATA_TX2+ IDE_D0/GPIO15
SATA_TX2- AC12 AD23
23 SATA_TX2- SATA_TX2- IDE_D1/GPIO16
ATA 66/100/133
IDE_D2/GPIO17 AE22
SATA_RX2- AE12 AC22
23 SATA_RX2- SATA_RX2- IDE_D3/GPIO18 VCC3_SB
SATA_RX2+ AD12 AD21
23 SATA_RX2+ SATA_RX2+ IDE_D4/GPIO19
IDE_D5/GPIO20 AE20
SATA_TX3+ AD13 AB20
SERIAL ATA
23 SATA_TX3+ SATA_TX3+ IDE_D6/GPIO21
SATA_TX3- AE13 AD19 JSPI1
AE19 SPI_CS# 1 2
SATA_RX3- IDE_D8/GPIO23 SPI_DATAOUT 3 SPI_HOLD#
23 SATA_RX3- AB14 SATA_RX3- IDE_D9/GPIO24 AC20 4
SATA_RX3+ AC14 AD20 SPI_WP 5 6 SPI_CLK
23 SATA_RX3+ SATA_RX3+ IDE_D10/GPIO25
AE21 7 8 SPI_DATAIN
SATA_TX4+ IDE_D11/GPIO26
23 SATA_TX4+ AE14 SATA_TX4+ IDE_D12/GPIO27 AB22
SATA_TX4- AD14 AD22 H2X4M_BLACK-RH
IDE_D14/GPIO29 AE23
SATA_RX4- AD15 AC23
23 SATA_RX4- SATA_RX4- IDE_D15/GPIO30
C 23 SATA_RX4+
SATA_RX4+ AE15 SATA_RX4+ C
AB16 SATA_TX5+
Add ESATA 0901 AC16 SATA_TX5-
G6 SPI_DATAIN
SPI_DI/GPIO12 SPI_DATAOUT
AE16 SATA_RX5- SPI_DO/GPIO11 D2
AD16 D1 SPI_CLK
SATA_RX5+ SPI_CLK/GPIO47 SPI_HOLD_L
F4
SPI ROM
R392 1KR1%0402 SATA_CAL SPI_HOLD#/GPIO31 SPI_CS#
V12 SATA_CAL SPI_CS#/GPIO32 F3
SATA_X1 Y12 U15 TP44

SATA_X1 LAN_RST#/GPIO13
ROM_RST#/GPIO14 J1
SATA_X2 AA12 SATA_X2
FANOUT0/GPIO3 M8
SATA_LED# W11 M5
34 SATA_LED# SATA_ACT#/GPIO67 FANOUT1/GPIO48
FANOUT2/GPIO49 M7
VCC3
SATA PWR
PLLVDD_SATA AA11 PLLVDD_SATA_1 FANIN0/GPIO50 P5

FANIN1/GPIO51 P8
XTLVDD_SATA W12 XTLVDD_SATA FANIN2/GPIO52 R8
C6 R566 X_0R0402
TEMP_COMM R394
TEMPIN0/GPIO61 B6
A6 R403 10KR0402 VCC3_SB 10KR0402
HW MONITOR
TEMPIN1/GPIO62
TEMPIN2/GPIO63 A5
B5 CLR_COMS1
TEMPIN3/TALERT#/GPIO64 TALERT# 7
1 CMOS CLEAR JUMPER
A4 CLR_COMS 2 CLR_COMS Clear CMOS
VIN0/GPIO53 1-2 Normal
VIN1/GPIO54 B4 3
C4 CLR_COMS 2-3 Clear CMOS
VIN2/GPIO55 N31-1030151+N33-1020271-RH
D4
B VIN3/GPIO56
VIN4/GPIO57 D5 B
VIN5/GPIO58 D6
VIN6/GPIO59 A7
VIN7/GPIO60 B7
AVDD_HWM
X_30L3_15_0805
F6 L49 1 2 VCC3_SB
AVDD
G7 CP36 X_CP
AVSS
C550 C553
AMD-218S7EBLA12FG-A12-RH X_C2.2u10Y-RH C0.1U16Y0402
NS_VIA CONNECTS
HWM_AGND TO GND
SATA_X1 C526 C10P50N0402

VCC_SB_1V2 PLLVDD_SATA VCC3 XTLVDD_SATA
1
A R391
10MR0402
Y3
25MHZ18P_D-4
L47 L46
A
2
220L250mA-600-RH 220L250mA-600-RH
SATA_X2 C502 C10P50N0402 C527 C530 C520
C2.2u10Y-RH X_C0.1U16Y0402 C1U10Y

Title
SB600 SATA/IDE/HWM/SPI
Custom VL390 0A
5 4 3 2 1
5 4 3 2 1
VCC3 U23C VCC_SB_1V2 U23E

100 MILS WIDTH L41
SB700 VDD12SB
L9
M9
VDDQ_1
Part 3 of 5
VDD_1 L15
M12
1 2 SB700 A2
C451 C543 C461 C511 C566 C567 C568 VDDQ_2 VDD_2 C738 C749 C747 C743 C742 C739 30L3_15_0805 VSS_1
T15 VDDQ_3 VDD_3 M14 VSS_2 A25
U9 N13 B1
CORE S0
C22u6.3X1206 VDDQ_4 VDD_4 C0.1U16Y0402 C1U10Y C1U10Y C1U10Y C10u16Y1206 VSS_3
U16 P12 D7
PCI/GPIO I/O
D VDDQ_5 VDD_5 VSS_4 D
U17 VDDQ_6 VDD_6 P14 T10 AVSS_SATA_1 VSS_5 F20
X_C1U10Y X_C1U10Y C0.1U16Y0402 V8 R11 C0.1U16Y0402 U10 G19
X_C1U10Y C0.1U16Y0402 C0.1U16Y0402 VDDQ_7 VDD_7 AVSS_SATA_2 VSS_6
W7 VDDQ_8 VDD_8 R15 U11 AVSS_SATA_3 VSS_7 H8
Y6 VDDQ_9 VDD_9 T16 U12 AVSS_SATA_4 VSS_8 K9
AA4 VDDQ_10 V11 AVSS_SATA_5 VSS_9 K11
AB5 VDDQ_11 V14 AVSS_SATA_6 VSS_10 K16
AB21 VDDQ_12 W9 AVSS_SATA_7 VSS_11 L4
Y9 AVSS_SATA_8 VSS_12 L7
CP25 Y11 L10
VCC_SB_1V2 AVSS_SATA_9 VSS_13
Y14 AVSS_SATA_10 VSS_14 L11
CP48 50 MILS WIDTH 30 MILS WIDTH Y17 L12
CKVDD12SB AVSS_SATA_11 VSS_15
VCC3 Y20 VDD33_18_1 CKVDD_1.2V_1 L21 1 2 AA9 AVSS_SATA_12 VSS_16 L14
L43 X_30L3_15_0805
IDE/FLSH I/O
CLKGEN I/O
AA21 VDD33_18_2 CKVDD_1.2V_2 L22 AB9 AVSS_SATA_13 VSS_17 L16
C744 C471 C462 AA22 L24 C460 C458 AB11 M6
IDE Interface Not Implemented: VDD33_18_3 CKVDD_1.2V_3 AVSS_SATA_14 VSS_18
AE25 VDD33_18_4 CKVDD_1.2V_4 L25 AB13 AVSS_SATA_15 VSS_19 M10
Decoupling caps not used. AB15 M11
AVSS_SATA_16 VSS_20
AB17 AVSS_SATA_17 VSS_21 M13
C1U10Y C0.1U16Y0402 C2.2u10Y-RH C2.2u10Y-RH AC8 M15
X_C0.1U16Y0402 AVSS_SATA_18 VSS_22
AD8 AVSS_SATA_19 VSS_23 N4
AE8 AVSS_SATA_20 VSS_24 N12
VSS_25 N14
P6
VCC_SB_1V2 PCIE_VDDR
POWER VSS_26
VSS_27 P9
100 MILS WIDTH VSS_28 P10
A15 AVSS_USB_1 VSS_29 P11
L58 220L250mA-600-RH P18 B15 P13
PCIE_VDDR_1 VCC3_SB AVSS_USB_2 VSS_30
P19 PCIE_VDDR_2 C14 AVSS_USB_3 VSS_31 P15
A-LINK I/O
C411 C450 C408 C457 C740 P20 40 MILS WIDTH D8 R1
PCIE_VDDR_3 AVSS_USB_4 VSS_32
P21 PCIE_VDDR_4 S5_3.3V_1 A17 D9 AVSS_USB_5 VSS_33 R2
C4.7U10Y0805 R22 A24 D11 R4
C PCIE_VDDR_5 S5_3.3V_2 C558 C494 C486 AVSS_USB_6 VSS_34 C
R24 B17 D13 R9
3.3V_S5 I/O
PCIE_VDDR_6 S5_3.3V_3 AVSS_USB_7 VSS_35
GROUND
X_C1U10Y C0.1U16Y0402 R25 J4 D14 R10
C1U10Y C0.1U16Y0402 PCIE_VDDR_7 S5_3.3V_4 X_C22u6.3X1206 AVSS_USB_8 VSS_36
S5_3.3V_5 J5 D15 AVSS_USB_9 VSS_37 R12
S5_3.3V_6 L1 E15 AVSS_USB_10 VSS_38 R14
L2 C2.2u10Y-RH F12 T11
VCC_SB_1V2 S5_3.3V_7 C2.2u10Y-RH AVSS_USB_11 VSS_39
F14 AVSS_USB_12 VSS_40 T12
50 MILS WIDTH G9 AVSS_USB_13 VSS_41 T14
L57 220L250mA-600-RH AVDDSATA_SB AA14 +1.2VSB H9 U4
AVDD_SATA_1 AVSS_USB_14 VSS_42
AB18 AVDD_SATA_4
15 MILS WIDTH H17 AVSS_USB_15 VSS_43 U14
C489 C474 C746 C538 C537 AA15 J9 V6
SATA I/O
AVDD_SATA_2 AVSS_USB_16 VSS_44
AA17 G2 J11 Y21
CORE S5
C22u6.3X1206 AVDD_SATA_3 S5_1.2V_1 C544 C548 AVSS_USB_17 VSS_45
AC18 AVDD_SATA_5 S5_1.2V_2 G4 J12 AVSS_USB_18 VSS_46 AB1
AD17 AVDD_SATA_6 J14 AVSS_USB_19 VSS_47 AB19
C1U10Y C0.1U16Y0402 AE17 C1U10Y C1U10Y J15 AB25
C1U10Y C0.1U16Y0402 AVDD_SATA_7 CP33 AVSS_USB_20 VSS_48
K10 AVSS_USB_21 VSS_49 AE1
A10 +1.2VSB K12 AE24
USB_PHY_1.2V_1 AVSS_USB_22 VSS_50
USB_PHY_1.2V_2 B10 K14 AVSS_USB_23
USB12SB 15 MILS WIDTH R399 X_0R K15 AVSS_USB_24
PCIE_CK_VSS_9 P23
C524 C525 C534 R16
VCC3_SB PCIE_CK_VSS_10
PCIE_CK_VSS_11 R19
C0.1U16Y0402 C10u10Y0805 T17
PCIE_CK_VSS_12
50 MILS WIDTH PCIE_CK_VSS_13 U18
L55 220L2A-50-RH AVDDTX_SB A16 AE7 V5_VREF C0.1U16Y0402 H18 U20
AVDDTX_0 V5_VREF PCIE_CK_VSS_1 PCIE_CK_VSS_14
B16 AVDDTX_1 J17 PCIE_CK_VSS_2 PCIE_CK_VSS_15 V18
C519 C518 C773 C516 C515 C517 C16 J16 AVDDCK_33 10 MILS WIDTH J22 V20
AVDDTX_2 AVDDCK_3.3V R406 1KR0402 PCIE_CK_VSS_3 PCIE_CK_VSS_16
D16 AVDDTX_3 VCC5 K25 PCIE_CK_VSS_4 PCIE_CK_VSS_17 V21
D17 K17 AVDDCK_12 M16 W19
PLL
AVDDTX_4 AVDDCK_1.2V PCIE_CK_VSS_5 PCIE_CK_VSS_18
E17 M17 W22
Y
AVDDTX_5 PCIE_CK_VSS_6 PCIE_CK_VSS_19
USB I/O
C10u10Y0805 C1U10Y X_C0.1U16Y0402 F15 E9 AVDDC_33 M21 W24
B C10u10Y0805 C1U10Y X_C1U10Y AVDDRX_0 AVDDC PCIE_CK_VSS_7 PCIE_CK_VSS_20 B
F17 AVDDRX_1 P16 PCIE_CK_VSS_8 PCIE_CK_VSS_21 W25
F18 Z D21
AVDDRX_2 S-BAT54C_SOT23
G15 AVDDRX_3 F9 AVSSC AVSSCK L17
G17 C542 Part 5 of 5
AVDDRX_4
G18
X
AVDDRX_5 C1U10Y AMD-218S7EBLA12FG-A12-RH
VCC3
AMD-218S7EBLA12FG-A12-RH
15 MILS WIDTH
15 MILS WIDTH 15 MILS WIDTH
VCC3 L45 AVDDCK_33
L48 AVDDC_33 VCC_SB_1V2 L56 AVDDCK_12
VCC3_SB
220L250mA-600-RH C745
220L250mA-600-RH C529 C531 220L250mA-600-RH C741
C2.2u10Y-RH
C2.2u10Y-RH TP115 VCC3
Bottom side TP116 AVDDTX_SB

C2.2u10Y-RH C0.1U16Y0402 Bottom side
TP117 VDD12SB
TP118 USB12SB
VCC5
VCC3
A
For EMI VCC3
A
For EMI
C764 C758 C757 C765 C763 C771 C767 C777
C760 C750
X_C0.1U16Y0402
C648 C755 C756
Title
SB700 POWER & DECOUPLING
X_C0.1U16Y0402X_C0.1U16Y0402 X_C0.1U16Y0402 X_C0.1U16Y0402 X_C0.1U16Y0402
X_C0.1U16Y0402 X_C0.1U16Y0402 X_C0.1U16Y0402 X_C0.1U16Y0402 Size Document Number Rev
VCC5 X_C0.1U16Y0402 X_C0.1U16Y0402 Custom VL390 0A
X_C0.1U16Y0402
5 4 3 2 1
5 4 3 2 1
REQUIRED STRAPS
D D
VCC3 VCC3_SB VCC3_SB
R464 R453 R530

X_10KR0402 X_10KR0402 2.2KR0402
17 PCI_CLK2
17,25 SIO_PCLK
17,32 PCI_CLK4
17 PCI_CLK5
17 LPC_CLK0
17 LPC_CLK1
C 18,28 AZ_RST# C
18 SB_GP16
18 SB_GP17
R452 R451 R447 R434 R357 R454 R353 R372

10KR0402 10KR0402 X_10KR0402 X_10KR0402 10KR0402 10KR0402 10KR0402 2.2KR0402
PCI_CLK2 PCI_CLK3
PCI_CLK4 PCI_CLK5 LPC_CLK0 LPC_CLK1 RTC_CLK AZ_RST# GP17 GP16
SIO_PCLK
B ENABLE PCI IMC ROM TYPE: B
Watchdog Debug TPM CLOCK RESERVED MEM BOOT (A11) Internal ENABLED (A11)
timer on straps Clock INTERNAL H, H = Reserved
IMC ENABLE PCI
NB_PWGRD Generator RTC
ENABLED (A12) MEM BOOT (A12) H, L = SPI ROM DEFAULT
L, H = LPC ROM
PULL HIGH ENABLED ENABLED ENABLED ENABLED ENABLED
(VCC3) (VCC3) (VCC3_SB) (VCC3_SB) L, L = FWH ROM
NC IS EXT.
PULL LOW DISABLED DISABLED DISABLED DISABLED RTC DISABLED
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
A A

Title
SB700 STRAPS
B VL390 0A
5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
VCC5
VGA CONNECTOR C219 D11

C1U10Y BAV99-7-F_SOT23-LF
CLOSE TO VGA Connector Y X
CLOSE TO GMCH
Z
L9 0.12U300m-1 L77 47n250mA-RH
15 NB_VGA_R
VCC5 VCC5
APnote:AN_RS780G1 R503 APnote:AN_RS780G1 R158 C214 C215 C856

RS780 A12 and Earlier:R503,R158 150R;A13:140RRS780 140R1%0402 140R1%0402 X_C5p50N0402 C3p50N0402-RH X_C5p50N0402
Y
D10
D7 D5 BAV99-7-F_SOT23-LF
BAV99-7-F_SOT23-LF Z Z BAV99-7-F_SOT23-LF Y X
Z
CLOSE TO MCH L8 0.12U300m-1 L78 47n250mA-RH
15 NB_VGA_G
X
DDC_DATA R147 33R0402 5VDDCDA R502 R157 C204 C205 C857

RS780 150R1%0402 150R1%0402 X_C5p50N0402 C3p50N0402-RH X_C5p50N0402
DDC_CLK R141 33R0402 5VDDCCL D9
BAV99-7-F_SOT23-LF
Y X VGAGND
B B
Z
L7 0.12U300m-1 L79 47n250mA-RH
15 NB_VGA_B
R501 R154 C196 C197 C858

RS780 150R1%0402 150R1%0402 X_C5p50N0402 C3p50N0402-RH X_C5p50N0402
VCC5
FS2
VDD_VGA
VCC3 VCC3 VCC5
F-MICROSMD110F-RH VGAGND
C191 C190
C0.1U16Y0402 C0.1U16Y0402
R108
X_4.7KR0402 R122 6.8K (RS740)
RS740 4.7KR0402 4.7K (RS780)
17
16
G
S D DDC_CLK VCC5
15 DAC_SCL
5VDDCCL 15 5
Q11 RS740 D6 10
X_N-2N7002_SOT23 VCC5 C179 BAV99-7-F_SOT23-LF VSYNC_C 14 4
X_C0.1U16Y0402 Y X 9
R179 0R0402 1 2 HSYNC_C 13 3 BLUE
8
Z
5
RS780 CLOSE TO MCH 5VDDCDA 12 2 GREEN

1 R145 7
VSYNC_C RED
C100P50N0402
C100P50N0402
C100P50N0402
C100P50N0402
4 11 1
C167
C171
C174
C183
VSYNC R234 0R0402 2 6
15 VSYNC
U7 47R0402
NC7WZ08
3
VGA1
A VCC3 VCC3 VCC5 R142 X_0R0402 D8 DSUB-VGAF_BLUE-RH-2 A
BAV99-7-F_SOT23-LF
VCC5 Y X N51-15F0391-F02
Z
5
R126 R130 6.8K (RS740)

X_4.7KR0402 RS740 4.7KR0402 4.7K (RS780) 1 R149
G
4 HSYNC_C
S D DDC_DATA HSYNC R226 0R0402 2
15 DAC_SDA 15 HSYNC
U8 47R0402
Q12 RS740 NC7WZ08
3
X_N-2N7002_SOT23
Title
R221 0R0402 R148 X_0R0402 DVI CONNECTOR
RS780 Size Document Number Rev
C VL390 0A
8 7 6 5 4 3 2 1
5 4 3 2 1
SERIAL ATA CONNECTOR BLOCK

PS2 KEYBOARD & MOUSE CONNECTOR
SATA 1 Blue SATA 3 Orange SATA2,4 Black
SATA3 SATA1
Default 10nF , Default 10nF , SVCC2
GND
GND
D Option 0 ohm 9 Option 0 ohm 9 D
GND
GND
1 1
TX+
TX+
SATA_TX0+ C589 1 2 C0.01U16X0402 ST_TX0 2 SATA_TX2+ C493 1 2 C0.01U16X0402 ST_TX2 2
19 SATA_TX0+ 19 SATA_TX2+
TX- RX-
TX- RX-
SATA_TX0- C586 1 2 C0.01U16X0402 ST_TX#0 3 SATA_TX2- C488 1 2 C0.01U16X0402 ST_TX#2 3 C9 R20
19 SATA_TX0- 19 SATA_TX2-
GND
GND
4 4
2
4
6
8
19 SATA_RX0- SATA_RX0- C571 1 2 C0.01U16X0402 ST_RX#0 5 19 SATA_RX2- SATA_RX2- C482 1 2 C0.01U16X0402 ST_RX#2 5 X_C0.1U25Y X_1KR1%0402
SATA_RX0+ C565 1 2 C0.01U16X0402 ST_RX0 SATA_RX2+ C479 1 2 C0.01U16X0402 ST_RX2 RN1
RX+
RX+
19 SATA_RX0+ 6 19 SATA_RX2+ 6
GND
GND
7 7 8P4R-2.2KR
16
17
GND
GND
8 8
1
3
5
7
KBMS1
25 MSDATA MSDATA FB1 300L600m_150 7 10
SATA7PM_ORANGE-P CONN-SATA2P_blue 8
25 MSCLK MSCLK FB2 300L600m_150 11
SATA4 SATA2 12 9
MS
GND
GND
9 9 25 KBDATA KBDATA FB3 300L600m_150 1 4
GND
GND
1 1 2
TX+
TX+
SATA_TX1+ C577 1 2 C0.01U16X0402 ST_TX1 2 SATA_TX3+ C514 1 2 C0.01U16X0402 ST_TX3 2 25 KBCLK KBCLK FB4 300L600m_150 5
19 SATA_TX1+ 19 SATA_TX3+
TX- RX-
TX- RX-
SATA_TX1- C572 1 2 C0.01U16X0402 ST_TX#1 3 SATA_TX3- C508 1 2 C0.01U16X0402 ST_TX#3 3 6 3
19 SATA_TX1- 19 SATA_TX3-
KB
GND
GND
4 4
19 SATA_RX1- SATA_RX1- C557 1 2 C0.01U16X0402 ST_RX#1 5 19 SATA_RX3- SATA_RX3- C499 1 2 C0.01U16X0402 ST_RX#3 5 C33 CONN-MiniDIN2X12P-RH
13
14
15
SATA_RX1+ C552 1 2 C0.01U16X0402 ST_RX1 SATA_RX3+ C496 1 2 C0.01U16X0402 ST_RX3 C180P50N
RX+
RX+
19 SATA_RX1+ 6 19 SATA_RX3+ 6
GND
GND
7 7 C31
C180P50N
GND
GND
8 8
C25
C180P50N
SATA7PM_BLACK-P-RH SATA7PM_BLACK-P-RH C21
C180P50N
For e-SATA
BLACK:N5N-07M0221-H06
VCC5
C604
X_C0.1U16Y0402
C C
ESATA1 PWM FAN CONTROL

1 GND G1 G1
SATA_TX4+ C583 1 2 C0.01U16X0402 ST_TX4 2 G2
19 SATA_TX4+ TX+ G2
SATA_TX4- C575 1 2 C0.01U16X0402 ST_TX#4 3 G3
19 SATA_TX4- TX- G3
4 GND G4 G4
SATA_RX4- C564 1 2 C0.01U16X0402 ST_RX#4 5
19 SATA_RX4- RX-
SATA_RX4+ C554 1 2 C0.01U16X0402 ST_RX4 6
19 SATA_RX4+ RX+
7 GND M1 M1
M2 VCC3 VCC5 VCC3 CPU FAN
M2
+12V
ESATA7PM_BLUE-P-RH
R117 R113 D3
4.7KR0402 X_4.7KR0402 X_1N4148W-F D1 1N4148W-F_SOD123-RH R6 27KR0402 CPUFAN_TAC 25
R9 4.7KR0402
Add ESATA 0901 CPU_FAN1
25 CPUFAN_PWM CPUFAN_PWM R92 100R0402 R7
4
3 22KR0402
2
C28 1
BH1X4B_BROWN-RH
C0.1U16Y0402 Default is 4-Pin FAN
1
EC3
+
B B
CD100u16EL11-RH
2
SYSTEM FAN
+12V
SYSFAN1
3
2
1
BH1X3_White
1
C895
+
EC88
CD470u16EL11.5
2 X_C0.1u16Y0402
A A

Title
SATA & COM1 & LPT
C VL390 0A
5 4 3 2 1
5 4 3 2 1
VDD33
R810
0R/8
VDD33
C860 C861 LINK_UP
D C22u6.3X1206 R666 330R/6 LINK_100 C868 C27p50N D
C0.1u25Y0402-RH R723 330R/6 LINK_1G XTAL1
VDD33
R677 R679
Y7 3.6K/6/1% 10K/4
CHOKE10 close to 25MHz/18pf/HC49S VDD33
U30 Pin 1 within 0.5cm U31
R668 Place near XTAL2 EECS 1 8
R811 R818 EESK CS VCC
Pin64 of U30 2 SK NC 7
0R/8 0R/6 C869 C27p50N EEDI_LAN 3 6
CH/4.7uH/4.0x4.3x2.0mm/1.24A FB12 EEDO DI NC
2.49k for 8111CP ? DSM_GPO# 18 4 DO GND 5
CHOKE10 AVDD18
CTRL15/VDD33
R812 R668
0R/8
Pay attention to the This Pin C889
4K/93C66/10ms-SOIC8
DVDD15
AVDD33
DVDD15
DVDD15
VDD33
XTAL2
XTAL1
CTRL18 1 2
2.49K/4/1% 8111CP uses 93C66 and keep R607 C0.1u25Y0402-RH
C862 C863
C22u6.3X1206 U30
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
C0.1u25Y0402-RH
LED0
LED1
LED2
LED3
GND
RSET
VCTRL15
CKTAL2
CKTAL1
AVDD33
VDD15
VDD33
VDD15
VDD15
GVDD
OGPIO
NC
C862 , C863 CTRL18 1 48 EESK
AVDD33 VCTRL18 EESK EEDI_LAN
CLOSE TO CHOKE1 2 AVDD33 EEDI/AUX 47
MDI_0+ 3 46 VDD33
MDI_0- MDIP0 VDD33 EEDO
4 MDIN0 EEDO 45
MDIx+/- FB12 5 44 EECS
MDI_1+ AVDD18 EECS DVDD15
Reference to GND plan. 6 MDIP1 VDD15 43
MDI_1- 7 42
C AVDD18 MDIN1 NC4 C
8 AVDD18 VDD1 41
C864 MDI_2+ 9 40
C0.01u25X0402 MDI_2- MDIP2 NC6
10 MDIN2 NC7 39
AVDD18 11 38 DVDD15
MDI_3+ AVDD18 VDD15 VDD33
12 MDIP3 VDD33 37
C864 use 0.01uF MDI_3- 13 36 ISOLATEB R671 1K/4
MDIN3 ISOLATEB VCC3
for better EMI performace. AVDD18 14 35 R670 15K/4
DVDD15 AVDD18 NC8
15 34
C
VDD33 VDD15 NC9
16 33
LANWAKEB
REFCLK_N
VDD33 CLKREQB
REFCLK_P
B R82 ISOLATEBR 18
SMDATA
PERSTB
EVDD18
EVDD18
R724 X_10K/4 AVDD18 VDD33

SBCLK
VDD15
VDD15
EGND
HSON
EGND
HSOP
Q99 C893 C894

HSIN
HSIP
X_0R/4
E
X_2N3904_SOT23
DVDD15 BIOS pull high/low on Pin36 C1000p50X0402 C1000p50X0402
R815 ISOLATE to leave/enter DSM.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RTL8111CP-VB-GR R725 R726

VL1_2 DVDD15 X_0R/4 330R/6
R385 33R0402
DVDD15
B06-8111C3C-R09
DVDD15
EVDD18
EVDD18
18,30,31,32 SCLK1
0R/8 R387 33R0402 LAN_USB1B
EGND
EGND
18,30,31,32 SDATA1 R813 YELLOW+

LAN_ACTLED 19 19
EGND LINK_UP 20 YELLOW- Left => YELLOW
13 PWR
0R/8 MDI_0+ 18 TD1+
MDI_0- 12 TD1- 20
C890 MDI_1+ 17 TD2+
R669 0R/4 C867 C0.1u10X0402 MDI_1- 11 TD2-
17 PE_LAN_RST#
RX_LANN0_C C866 C0.1u10X0402 C680p50X0402-RH MDI_2+ 16 TD3+
RX_LANN0 14 TD3-
RX_LANP0_C MDI_2- 10 21
RX_LANP0 14 TD4+
MDI_3+ 15
LAN_CLK# 12 TD4-
MDI_3- 9 Right => Orange / Green
LAN_CLK 12 GND
TXLANN 14 R727 0R/4 14
B LINK_100 GR/OR+ B
TXLANP 14 21 22
VCC3_SB VDD33 WAKE# LINK_1G 22 GR/OR-
AVDD33 WAKE# 18,30
R808 R809
C865 RJ45_USBX2_LEDX2_TX-GIGA-RH-1
VDD33 AVDD33 C891 C892
C0.1u25Y0402-RH
+1
0R/8 0R/8 C1000p50X0402

EC77 C870 C871
C1000p50X0402
N58-22F0181-F02
2
100uf/16v/6.3x5/2.5mm C0.1u25Y0402-RH C0.1u25Y0402-RH

VCC3
EVDD18 D30
R814 AVDD18 IP4220/SOT457
5
VL1_2 EVDD18 DVDD15
C874 C0.1u25Y0402-RH C885 C0.1u25Y0402-RH MDI_3+ 6 4 MDI_2+
0R/8
C873 C872 C875 C0.1u25Y0402-RH C886 C0.1u25Y0402-RH MDI_3- 1 3 MDI_2-
C0.1u25Y0402-RH C0.1u25Y0402-RH C876 C0.1u25Y0402-RH C887 C0.1u25Y0402-RH
2
C888 C0.1u25Y0402-RH
VDD33
C877 C0.1u25Y0402-RH C881 C0.1u25Y0402-RH
C878 C0.1u25Y0402-RH C882 C0.1u25Y0402-RH

VCC3
C879 C0.1u25Y0402-RH C883 C0.1u25Y0402-RH
A A
C880 C0.1u25Y0402-RH C884 C0.1u25Y0402-RH D40
IP4220/SOT457
5
MDI_1+ 6 4 MDI_0+
MDI_1- 1 3 MDI_0-
2
Title
LAN 8111CP
Custom VL390 0A
5 4 3 2 1
5 4 3 2 1
SERIAL PORT 1
LPC I/O IT8720 VCC5 1+
EC23 2CD47u10EL7-1 C0.1U16Y0402
C635
Super I/O Chasiss
NOT USED
L2 C157 C0.1U16Y0402 U36 BAS32L_LL34
20 1 +12COM_1 D26 +12V
30L3_15_0805 VCCH CP1 X_CP R326 VCC5 NRIA VCC VDD RIA#
VCC5_SB 2 RA1 RY1 19
10KR0402 NCTSA# 3 18 CTSA#
C62 C63 C158 L1 X_30L3A-15_0805-RH C633 NDSRA# RA2 RY2 DSRA#
4 RA3 RY3 17
X_C0.1U16Y0402
C0.1U16Y0402 NSINA SINA CHASSIS R23 1KR0402
C0.1U16Y0402
C0.1U16Y0402
7 RA4 RY4 14
1
EC2 JMAT_MODE1 NDCDA# DCDA#
+
9 RA5 RY5 12
R324 1KR0402 BIOS_SELECT1 1
CD47u10EL7-1 VCC5 2 RTSA# 16 5 NRTSA
2
BIOS_SELECT2 G DTRA# DA1 DY1 NDTRA
3 15 DA2 DY2 6
SOUTA NSOUTA BAS32L_LL34
35
99
67
D 13 DA3 DY3 8 D
4
U3 N31-1030151+N33-1020271-RH 11 10 -12COM_1 D53
GND VSS -12V
VCC
VCC
AVCC
VCCH
DCDA# 127 116 RND7 GD75232_SSOP20 C677 C0.1U16Y0402
RIA# DCD1# PD7/GP77/BUSSO2 RND6 R280
128 115
CTSA# 1
RI1# PD6/GP76/BUSSO1
114 RND5 10KR0402
FLOPPY CONNECTOR
DTRA# CTS1# PD5/GP75/BUSSO0 RND4
126 DTR1#/JP4 PD4/GP74/BUSSI2 113
RTSA#
DSRA#
122 RTS1#/JP2 PD3/GP73/BUSSI1 112 RND3
RND2
NRTSA
NDSRA#
C638
C642
C330p50X
C330p50X
JCOM1 CONNECTOR VCC5
123 DSR1# PD2/GP72/BUSSI0 111
SOUTA 124 110 RND1 NCTSA# C632 C330p50X
SINA SOUT1/JP3 PD1/GP71 RND0 NRIA C630 C330p50X WP_#
125 SIN1 PD0/GP70 109 1 2
DCDB# 26 108 PRSTB# INDEX# 3 4 RN2
RIB# VIDO1/GP21/DCD2# STB#/GP87/SMBC_M PRAFD# NDCDA# C737 C330p50X TRACK0# 8P4R-1KR0402
28 VIDO6/GP17/RI2# AFD#/GP86/SMBC_R 107 5 6
CTSB# PRERR# NSOUTA C748 C330p50X RDDATA#
12
27 VIDO0/GP20/CTS2# ERR# 106 7 8
DTRB# 29 105 PRINIT# NSINA C676 C330p50X R43
RTSB# VIDO7/GP16/DTR2#/JP6 INIT#/GP85/SMBD_M LPT_SLIN# NDTRA C653 C330p50X JCOM1 DSKCHG# 1KR0402
23 VIDO2/FAN_TAC5/GP24/RTS2# SLIN#/GP84/SMBD_R 104 10
DSRB# 22 103 PRACK# VCC3 NDCDA# 1 6 NDSRA#
SOUTB VIDO3/FAN_TAC4/GP25/DSR2# ACK#/GP83 PRBUSY NSINA NRTSA
21 VIDO4/GP26/SOUT2 BUSY/GP82 102 2 7
SINB 20 101 PRPE NSOUTA 3 8 NCTSA#
VIDO5/GP27/SIN2 PE/GP81 PRSLCT NDTRA NRIA FDD1
SLCT/GP80 100 4 9
C787 5
48 78 R26 10KR0402 VCC5_SB X_C0.1U16Y0402 1 2 DRVDEN0
MB_ID0 SO/GP50 PWROK2/GP41 R27 X_0R0402 DSUB-COMM_GREEN-RH-6
25 GP22/SCK SUSC#/GP53 77 LPC_SMI# 18 3
MB_ID1 24 76 ATX_PSON# 26,34
11
GP23/SI PSON#/GP42 INDEX#
PANSWH#/GP43 75 PSIN 34 7 8
IT8720F-RH 72 SB_PWRON# 18 9 10 MOA#
PWRON#/GP44 SLP_S3#
71 SLP_S3# 18,26 EMI_0B 11 12
SUSB# DSA#
5 13 14
6
VCORE_EN/VID7/GP64 SERIAL PORT 2 15 16
VCORE_GOOD/VID6/GP63 IO30 Delay 60 ms from VCC5_SB ramp up to 4V VCC5 DIR#
CE_N/RESETCON#/CIRTX1 30 17 18
85 IO_RSMRST# IO_RSMRST# 18 C0.1U16Y0402 19 20 STEP#
RSMRST#/CIRRX1/GP55 C645 WRDATA#
IRTX/GP47 66 BOM Option: 10/100 /N 21 22
70 PWR_LED PWR_LED 34 U34 23 24 WE#
DRVDEN0 GP46/IRRX CHASSIS C793 +12COM_1 TRACK0#
51 DENSEL# COPEN# 68 VCC5 20 VCC VDD 1 25 26
C INDEX# SUS_LED X_C0.1U16Y0402 NRIB RIB# WP_# C
63 INDEX# 3VSBSW#/GP40 79 SUS_LED 34 2 RA1 RY1 19 27 28
MOA# 52 IO3 NCTSB# 3 18 CTSB# 29 30 RDDATA#
AMD_TSI_C MTRA# C64 NDSRB# RA2 RY2 DSRB# HEAD#
7 AMD_TSI_C 55 PECI/AMDTSI_C/DRVB# 4 RA3 RY3 17 31 32
DSA# 54 3 R229 4.7KR0402 VCC3_SB C0.1U16Y0402 NSINB 7 14 SINB 33 34 DSKCHG#
AMD_TSI_D DRVA# PCIRSTIN#/CIRTX2/SVD/GP15 VCC3 NDCDB# RA4 RY4 DCDB#
7 AMD_TSI_D 53 SST/AMDTSI_D/PECI_AVA/MTRB# PCIRST3#/GP10/VDIMM_STR_EN 84 USB_EN 29 9 RA5 RY5 12
DIR# 57 34 EMI_0B
STEP# DIR# PCIRST2#/GP11 R97 10KR0402 Placement RTSB# NRTSB
58 STEP# PWROK1/GP13 32 VCC5 16 DA1 DY1 5 BH2X17[4][5][6]_BLACK-RH
WRDATA# 56 33 close to C630 DTRB# 15 6 NDTRB
WE# WDATA# PCIRST1#/GP12 SOUTB DA2 DY2 NSOUTB
60 WGATE# 13 DA3 DY3 8
TRACK0# 62 11 10 -12COM_1
WP_# TRK0# VIN0 GND VSS
64 WPT# VIN0 98
RDDATA# 61 97 VIN1 GD75232_SSOP20 C678 C0.1U16Y0402
HEAD# 59
RDATA# VIN1
96 VIN2 Thermal Resistor
DSKCHG# HDSEL# VIN2 VIN3
65 DSKCHG# VIN3/ATXPG 95
94 VIN4 VCC5
VIN4/VLDT_12 R286
93 VIN5 NRTSB C649 C330p50X
PCIRST_SIO# VIN5/VDDA_25 C10 COM_GPIO2 NDSRB# C650 C330p50X
17 PCIRST_SIO# 37 LRESET# VIN6/VDIMM_STR 92
17 LPC_DRQ#0 LPC_DRQ#0 38 C1U10Y NCTSB# C651 C330p50X VCCP R13 47R0402 VIN4
LDRQ#/JP1
17,32 SERIRQ SERIRQ
LPC_FRAME#
39 SERIRQ VREF 91 HM_VREF
10KR0402 COM2 HEADER NRIB C652 C330p50X
C17 C0.1U16Y0402 HW_AGND
17,32 LPC_FRAME# 40 LFRAME# TMPIN1 90
LPC_AD0 LPC_AD0 41 89 VR_TEMP_DA NDCDB# C674 C330p50X
LPC_AD1 LAD0 TMPIN2 SIO_THERMDA_CPU COM2 NSOUTB C752 C330p50X
LPC_AD1 42 LAD1 TMPIN3 88
LPC_AD2 LPC_AD2 43 2 R95 X_0R0402 NDCDB# 1 2 NSINB NSINB C672 C330p50X VCC3 R10 10KR1%0402 VIN0
LPC_AD3 LAD2 FAN_CTL5/CIRRX2/GP16 R96 X_0R0402 NSOUTB NDTRB NDTRB C675 C330p50X
LPC_AD3 44 LAD3 FAN_CTL4/VID_TURBO 121 3 4
47 12 5 6 NDSRB# C13 C0.1U16Y0402 HW_AGND
PCICLK FAN_CTL3/GP36 NRTSB NCTSB#
17,21 SIO_PCLK FAN_TAC3/GP37 11 7 8
12 SIO_48M_CLK 49 10 NRIB 9
CLKIN FAN_CTL2/GP51 COM_GPIO2 C794 C0.1U16Y0402 R14 47R0402 VIN5
18 LPC_PME# 73 PME#/GP54 FAN_TAC2/GP52 9 VCC_DDR
8 CPUFAN_PWM CPUFAN_PWM 23 H2X5[10]_white-RH
FAN_CTL1 C18 C0.1U16Y0402 HW_AGND
FAN_TAC1 7 CPUFAN_TAC 23 Close to COM PORT header
18 KBRST# KBRST# 45 19 MB_ID2
A20GATE KRST#/GP62 VID0/GP30
18 A20GATE 46 GA20/JP5 VID1/GP31 18
23 KBDATA KBDATA 80 17 COM_GPIO2 VCC5 R1 6.81KR1%0402 VIN1
B KBCLK KDAT/GP61 VID2/GP32 B
81 16
23
23
KBCLK
MSDATA MSDATA 82
KCLK/GP60 VID3/GP33
15
TEMP SENSOR C14 C0.1U16Y0402 HW_AGND
MSCLK MDAT/GP57 GNDD BIOS_SELECT1
23 MSCLK 83 MCLK/GP56 VID4/GP34 14
13 BIOS_SELECT2 VR_TEMP_DA R11 10KR1%0402
VID5/GP35 Add 0902 VCC3_SB
SIO_THERMDA_CPU R535 0R0402
C
THERMDA_CPU 7,32
Y
31 87 SIO_THERMDC_CPU C2
SVC/PECI_RQT/GP14 TS_D- C2200p50X0402 Place close R2 6.81KR1%0402 VIN2
118 GP67/CPU_PG B VCC5_SB
119 69 Z D25 to VRM C1
GP66/VLDT_EN VBAT
GNDD
GNDD
GNDD
GNDA
120 36 S-BAT54C_SOT23 Q66 C2200p50X0402 C15 C0.1U16Y0402 HW_AGND
E
GP65/VDDA_EN VIDVCC SIO_THERMDC_CPU VR_TEMP_DC N-MMBT3904_NL_SOT23
VBAT_IO
C12 R12 10KR1%0402
X
C1U10Y Place close to SIO side CP8 X_CP SIO_THERMDC_CPU R536 0R0402
VBAT_IN THERMDC_CPU 7,32
50
74
117
86
SLP_S3# R25 X_10KR0402 VCC3_SB VCC3 CP2 X_CP +12V R3 30.1KR1%0402 VIN3
LPC_PME# R24 10KR0402 VCC5_SB SIO_48M_CLK HW_AGND R98 X_10KR0402 VCC5_SB C16 C0.1U16Y0402 HW_AGND
MB_ID0 R86 10KR0402 D54
C43 CP3 L3 VCC5 R15 10KR1%0402
X_CP X_120L600mA-250 R523 X_10KR0402 VCC5_SB
AMD_TSI_C R378 2.2KR0402 X_C22P50N0402 10/100 Giga MB_ID1 R87 X_10KR0402 RN47 8P4R-2.7KR0402
BAS32L_LL34
VCC3
MB_ID0 0 1 RND0 1 2
AMD_TSI_D R379 2.2KR0402 Place close MB_ID1 R553 X_10KR0402 RND1 3 4 CN4 8p4C-220p50N TP119 VCC5
VCC5
to SIO MB_ID2 MB_ID2 R239 X_10KR0402 RND2 RND0
26
5 6 LPT1 1 2
RND3 7 8 RND1 3 4 TP120 VCCH
PRSTB# 1 2 PRAFD# RND2 5 6
RN48 8P4R-2.7KR0402 RND0 3 4 PRERR# RND3 7 8 TP127 +12COM_1
Power On Strapping Options RND4 1 2 RND1 5 6 PRINIT# CN5 8p4C-220p50N
SUPER I/O STRAPPING RESISTOR RND5 3 4 RND2 7 8 LPT_SLIN# RND4 1 2 TP128 -12COM_1
Symbol PIN value Description RND6 5 6 RND3 9 10 RND5 3 4
VCC3 VCC3 RND7 7 8 RND4 11 12 RND6 5 6
Flashseg1_EN 38 1 Disabled. RND5 13 14 RND7 7 8
LPC_FRAME#R115 X_10KR0402 LPC_DRQ#0 R336 10KR0402 (LPC_DRQ#0) 0 Flash I/F Address Segment 1 (FFFE_0000h~FFFF_FFFFh, 000F_0000h~000F_FFFFh) is enabled RN49 8P4R-2.7KR0402 RND6 15 16 CN6 8p4C-220p50N
SERIRQ R116 X_10KR0402 RTSA# R61 10KR0402 VIDO_EN (RTSA#) 122 1 Disable VIDOUT pins(except VIDO6 & VIDO7) PRSLCT 1 2 RND7 17 18 PRSLCT 1 2 TP149 PCIRST_SIO#
A DTRA# R470 10KR0402 0 Enable VIDOUT pins PRPE 3 4 PRACK# 19 20 PRPE 3 4 A
DTRB# R74 10KR0402 CHIP_SEL (SOUTA) 124 -- Chip selection in configuration. PRBUSY 5 6 PRBUSY 21 22 PRBUSY 5 6 TP150 SIO_PCLK
/N K8PWR_EN 126 1 K8 POWER SEQUENCE FUNCION IS DISABLED PRACK# 7 8 PRPE 23 24 PRACK# 7 8
RN4 X_8P4R-10KR0402 (DTRA#) 0 K8 POWER SEQUENCE FUNCION IS ENABLED PRSLCT 25 28 C898 TP151 SIO_48M_CLK
LPC_AD3 1 2 VCC3 11 The default value of EC Index 15h / 16h / 17h is 40h (50%) RN46 8P4R-2.7KR0402 PRSTB#
LPC_AD2 3 4 FAN_CTL_SEL 10 The default value of EC Index 15h / 16h / 17h is 7Fh(Fan off ) LPT_SLIN# 1 2
27
LPC_AD1 5 6 R356 10KR0402 (SOUTA/A20GATE) 124/46 01 The default value of EC Index 15h / 16h / 17h is 00h(Fan full speed ) PRINIT# 3 4 C220p25N0402
LPC_AD0 7 8 SOUTA R347 X_680R0402-RH 00 The default value of EC Index 15h / 16h / 17h is 20h(75%) PRERR# 5 6
VCC3
IO30 R89 10KR0402
SVID_EN
(DTRB#)
29 1
0
Parallel VIDOutput(Only for Parallel VID input)
Serial VIDOutput(Only for Parallel VID input)
PRAFD#
PRSTB#
7 8 DSUB-PRINTERF_BURGUNDY-RH-4
IO3 R84 10KR0402 R348 1KR0402 WDT_EN 46 1 Disable WDT to reset PWROK Title
A20GATE R91 X_680R0402-RH (A20GATE) 0 Enable WDT to reset PWROK R942 2.7KR0402
C899 LPC I/O IT8720
C0.1u25Y0402-RH
RIA# R112 X_10KR0402 Size Document Number Rev
Reserve For No COM port For Lenovo FAN Speed Control Custom VL390 0A
50% Power On default
5 4 3 2 1
LPC_DRQ#0
5 4 3 2 1
REFERENCE VOLTAGE 0.9V_REF 1.2V_REF

0.9V_REF +12V VCC3
*Reference sinking/sourcing 100uA ???NEW rev UPI/uP6264BMA8 I34-0626419-U33 ???
*Reference ramp-up 5mS G
D
Q80 ATX_PSON# G
D
Q82
5VDIMM 25,34 ATX_PSON#
S N-2N7002_SOT23 S N-2N7002_SOT23 R609
*5VSB > 4.2V POR VCC5_SB VCC5 10KR0402 0.9V
8
R934 X_10R U49B
*Pin8 > 1.4V Enable +1.8V_S0_REF 5 AZ358M-E1_SOIC8-RH
1.8V@2A
*Pin8 < 0.4V Disable VCC5_SB + D
7 G
R902 +1.8V_S0_FB 6 S Q53 +1.8V_S0
R933 10R C839 C0.1u16Y0402 R903 X_11KR1%0402 - N-P0903BD_TO252
X_11KR1%0402 C837
4
R611
1
U26 VCC5 VCC3 VCC5_SB 20KR1%0402
R909 3 7
5VSB
10,11,12,18 SCLK SCL 1.5V 1.5V_REF
D C0.1u16Y0402 D
1
R910 EC8 EC38 EC63 C836 EC39
+
10,11,12,18 SDATA 4 SDA R610 100R0402 Place Close to U18 R612 1KR1%0402
X_C10u6.3X50805
6 0.9V_REF
.CD1000U6.3EL11.5
0.9V
GND
.CD1000U6.3EL11.5
.CD1000U6.3EL11.5
.CD1000U6.3EL11.5
2
2
6 VRM_GD R615 0R0402 EN_HT 8 5 R614 100R0402 1.2V_REF
EN 1.2V R613
Enable 0.9VREF and 1.25REF UP6264AMA8_SOT23-8-RH 1KR1%0402
2
C840 C841 C842
X_C0.1u16Y0402
C0.1u16Y0402
C0.1u16Y0402
VCC5_SB
5VDIMM FOR DDR VCC5_SB CPU VDDA_25 POWER VCC5_SB VCORE_EN# 6

R621
VCC5 10KR0402
VDDA_25
D
VCC5_SB
U44
2.5V/150mA R622 G Q88
S
VCC5 R912 510R0402 5VDIMM_5V R914 10R0402 UP7707M5-00_SOT23-5 4.7KR0402 N-2N7002_SOT23
D
G 1 5
S
R913 10KR0402 C87 X_C0.1u16Y0402 5VDIMM VIN VOUT VCC_DDR Q83
27,34 ATX_PWROK G
Q10 C146 C147 EC30 N-2N7002_SOT23
C
D
1
P06P03LCG_SOT89 R595 C143 D42
+
GND
S
C828 2.1KR1%0402 R620 4.7KR0402
FB
3 B
C10u10Y0805
X_C1U10Y0402-RH
EN ATX_PWROK 27,34
1
2
U16 R2 Q87
X_C10u10Y0805
CD100u16EL11-RH
X_C0.1u16Y0402
2
5 7 5VSBDRV1 C843 C18000p16X0402 N-MMBT3904 S-RB751V-40_SOD323-RH
5VCC
5VSB
18,25 SLP_S3#
E
2
4
S3# 5VSB_DRV R648 C154
18,27 SLP_S5# 6 S5#
X_4.7KR0402 C4.7U10Y0805
VCC5_SB VDDA_25
C844
GND
C
D
R915 X_4.7KR0402 MODE 4 8 5VDRV1 G Q32 X_C0.1u16Y0402
MODE 5VCC_DRV R596 R619 10KR0402
S B
R916 R597 10KR0402 1KR1%0402 Q86
27,34 ATX_PWROK
3
0R0402 UP7501M8_SOT23-8-RH R917 C93 N-APM3023_TO252-RH Vo=0.8*(R1+R2)/R1 N-MMBT3904

R1
E
1.5KR-RH R649
C0.022u16X0402-RH
C R911 4.7KR0402 C830 C

200KR0402 C0.1u16Y0402
CRB: MODE Low support S0/S3 CPU_VDDR POWER
Hi support S0/S3/S5 +12V
VCC5 1.2V_REF +12V VCC_DDR
5VDRV1_EN 29 VCC3_SB
R644
10KR0402 SB700 & RS780 POWER GOOD CIRCUIT
8
U51A
CPU_VDDR_REF 3 AZ358M-E1_SOIC8-RH
1.2V@4A R623
For special PSU sequence R325 +
1 G
D
10KR0402
56KR1%0402 CPU_VDDR_FB 2 S Q45 CPU_VDDR
VCC3 VCC5_SB - N-P0903BD_TO252 D44 S-RB751V-40_SOD323-RH R617 0R0402 SYS_PWRGD
27,34 ATX_PWROK
C850
4
5VDIMM_5V R645 D45 S-RB751V-40_SOD323-RH SLP_S3#
12,18,34 FP_RST#
20KR1%0402
R918 R927 D43 S-RB751V-40_SOD323-RH
D
X_1KR0402 X_47KR1%0402-RH C0.1u16Y0402 VCC5_SB
1
C849 EC58 Q89 use Slp_s3# control SYS_PWRGD
+
D
G
Q31 R646 0R0402 N-2N7002_SOT23 refer to AMD reference
X_C10u6.3X50805
G
R624 circuit
.CD1000U6.3EL11.5
S
S
2
D
G C94 X_N-2N7002_SOT23 4.7KR0402
S X_C0.1u16Y0402 R647
Q33 X_270R1%0402
R931
X_4.7KR0402 X_N-2N7002_SOT23 NB_VCC1P1
C
R625 10KR0402 B
Q90
N-MMBT3904
E
1.2V_REF
VCC_1V2 POWER C848 VCC3 +1.8V_S0
R650 X_10KR0402 X_C1U10Y
3VDUAL POWER VCC3_SB
RS740 RS780
R638 R642
VCC3 1.2V_REF +12V VCC_DDR X_1KR0402 4.7KR0402
B U20 B
VCC5_SB SYS_PWRGD 1 6
VCC5_SB A1 Y1 NB_PWRGD 6,15
S
R922 10R C845 C1U10Y 5VDRV1 R600 SPEC. 2 5 VCC3_SB
G
GND VCC
10KR0402
D
H :0.7VCC
8
Q42 VCC3_SB U49A

N-APM3023NUC-TRL_TO252-RH VCC_1V2_REF 3 AZ358M-E1_SOIC8-RH
1.2V@2A L: 0.3VCC
3 A2 Y2 4
4
U18 + D
R643
1 G X_NC7WZ07P6X_SC70-6
1 VCC_1V2_FB 2 Q44 VCC_1V2 X_4.7KR0402
VCTRL
S
POK - N-P0903BD_TO252
VOUT 6
2 C833 SB_PWRGD 18
4
EN R601
1
C846 R924 EC40

+
3 VIN 20KR1%0402
X_C0.015u16X0402 10KR0402
X_.CD1000U6.3EL11.5
1
EC32
C0.1u16Y0402 C832 SYS_PWRGD R629 0R0402 SB_PWRGD
+
7
GND
GND
.CD1000U6.3EL11.5
2
R618 X_0R0402 FB
X_C10u6.3X50805
5 VREF R926 200KR0402 5VDRV1 R602 0R0402 18 WD_PWRGD WD_PWRGD R667 0R0402 NB_PWRGD
2
UP7706U8_PSOP8-RH
8
SB_PWRGD
C847 R925 R603 rise time ≒ 50 ms; fall time ≒ 1 ms
C10u10Y0805 3.3KR0402 X_270R1%0402 ER_RS780E1.pdf de-asserted at least 80 ns before VDD drops 5% from nominal value.
from 1.35V change to normal 1.2V de-asserted at least 1 ns before RSMRST# is asserted when entering G3 state.
VCC5
ATHLON64 PWRGD & ENABLECIRCUIT
VCC_SB_1V2 POWER
1.2VDUAL POWER For SB +1.2V_S5 Power Rail VCC5_SB
R628
For SB +1.2V_SUS Power Rail 0.9V_REF 1.2V_REF +12V VCC_DDR
X_10KR0402
South bridge All Power Rails: EN_HT
Ramp time is less than 40 ms.
D46 R626
R608 R604 X_S-RB751V-40_SOD323-RH X_10KR0402
D
VCC3_SB 10KR0402 X_10KR0402 SLP_S3#
8
+1.2VSB U51B Q91

U42 +1.2VSB_REF AZ358M-E1_SOIC8-RH
1.2V@1.9A G
X_N-2N7002_SOT23
UP7707M5-00_SOT23-5
1.2V@1.5A 5 +
7
D
C
G
R627
S
A A
1 5 +1.2VSB_FB 6 S Q84 VCC_SB_1V2
VIN VOUT - N-P0903BD_TO252
6 VRM_GD B
C835 Q92
4
R605 X_N-MMBT3904
GND
E
R616 X_4.7KR0402
3 R2
FB
EN 20KR1%0402
1
C854 C151
+
1KR1%0402
X_C0.015u16X0402 EC37 C0.1u16Y0402
2
C834 EC79
+
X_C10u10Y0805
CD100u16EL5-RH
2
C150 R606 1KR1%0402

X_C10u6.3X50805
C10u10Y0805
CD820u2.5SO-RH-1
2
R598 R607
Vo=0.8*(R1+R2)/R1
R1 Title
2KR1%0402 3KR1%0402
ACPI Controller UPI
Custom VL390 0A
5 4 3 2 1
5 4 3 2 1
VTT_DDR POWER DDR III 1.5V POWER 5VDIMM
CHOKE3
CH-1.2u15A3.0m-RH
0.75V@2A +12V
5VDIMM_IN 1 2
D VTT_DDR VCC_DDR Y D
Z
1
C85
+
X
X
C268 X_C0.1U16Y0402 VCC5_SB C71 C123 EC11 EC64 EC14
D37
X_C0.1u16Y0402
C10u10Y0805
CD470u6.3SO-RH
.CD1000U6.3EL11.5
.CD1000U6.3EL11.5
S-BAT54C_SOT23 Z D35
R190 U12 X_S-BAT54A_SOT23 X_C0.1u16Y0402
1KR1%0402 1 8 5VDIMM
VIN NC3
2 7
Y
GND NC2 R173
3 REFIN VCNTL 6
4 VOUT NC1 5 2.2R0805
9
1.5V@10A+10A
C0.1U16Y0402
.CD1000U6.3EL11.5
GND
1
1.5V_REF
EC27
R588 X_0R C142 C1u25X0805

+
C277
R192 C274 UP7711U8_PSOP8-RH G
Q15 VCC_DDR
1KR1%0402
C0.1U16Y0402
S
2
5
U6 C83 N-NTD4809NT4G_DPAK3-RH CHOKE5
R569 2KR1%0402 DDR_REF 7 1 DDR_BOOT R573 0R C1u25X0805 CH-1.1u27A2.5m-RH
VCC
Vref BOOT
C37 DDR_PHASE
EN_DDR
PHASE 8 1 2
R583 2 DDR_HG
GND
DDR_FB UG DDR_LG D
6 4
C0.1u16Y0402
X_12.1KR1%0402
G
FB LG Q18
S
1
UP6103S8_SOP8-RH N-NTD4806NT4G_DPAK3-RH R589
+
3
R640 2.2R0805 C206 EC22 EC25 EC21
X_27KR0402 C1U10Y
X_.CD1000U6.3EL11.5
.CD1000U6.3EL11.5
.CD1000U6.3EL11.5
R576
Iocp=225/8.5=26.5
X_12.1KR1%0402
VCC5_SB C75
D
C3300p50X0402
R630 4.7KR0402 G Q93
N-2N7002_SOT23
S
C29 X_C10000p10X0402 R586 X_0R0402
7 DDR_FB R577 3.09KR1%0402
C C
C
C
18 S3_STATE R631 4.7KR0402 B B R632 4.7KR0402 ATX_PWROK 26,34
Q94
18,26 SLP_S5# R633 X_4.7KR0402 N-MMBT3904 Q95
E
E
N-MMBT3904
Combining VLDT and VDDR For cost down ;

All capacitors for VLDT and VDDR must be included
NB_VCC1P1 POWER
1.1V@13A FOR RS780 VCC3
CHOKE8
VCC_1V2 CPU_VDDR CH-1.2u15A3.0m-RH
+12V VCC3_IN 1 2
R431 X_0R0805-1
R432 X_0R0805-1 D47
R480 X_0R0805-1 X_S-BAT54ALT1G_SOT23
1
R481 X_0R0805-1 C99
+
Y C103 C124 EC13 EC74
Z
X_C0.1u16Y0402
C10u10Y0805
2
.CD1000U6.3EL11.5
.CD1000U6.3EL11.5
X
B X_C0.1u16Y0402 B
0.9V_REF 1.2V_REF R181

2.2R0805
C145 C1u25X0805
D
1.1V@13A
R675 R402 G
X_1KR1%0402 1KR1%0402 0.8V S Q38 NB_VCC1P1

5
U41 C102 N-NTD4809NT4G_DPAK3-RH CHOKE9

NB__REF 7 1 NB_BOOT R575 0R C1u25X0805 CH-1.2u15A1.7m-RH
VCC
Vref BOOT
8 NB_PHASE 1 2
C838 PHASE NB_HG
2
GND
R578 NB_FB UG NB_LG D

6 FB LG 4 G
2KR1%0402 C0.1u16Y0402 S EC61 EC31
1
UP6103S8_SOP8-RH Q41 R674 EC35
+
3
N-NTD4806NT4G_DPAK3-RH 2.2R0805
CD100u16EL5-RH
CD100u16EL5-RH
R641 C208
X_.CD1000U6.3EL11.5
2
2
Combining VCC_1V2 andVCC_SB_1V2 For cost down R678 X_10KR1%0402 C1U10Y
8.06KR1%0402
Iocp=150/8.5=17.65 C100
C3300p50X0402
VCC_1V2 VCC_SB_1V2
R651 X_0R0805-1
R652 X_0R0805-1
R653 X_0R0805-1 C98 X_C10000p10X0402 R639 X_0R0402
R654 X_0R0805-1
R634 3.09KR1%0402
A A

Title
NB Core Power & DDR Power
Custom VL390 0A
5 4 3 2 1
5 4 3 2 1
Rear Phone Jack

Audio Codec ALC662 (ALC888)
Layout Follow Route AUDIO1A
Default is ALC662 PIN.36 PIN.25 EC46 75R0402 120L600mA-250 3 16
LINE1-IN-R 1+ 2 L_INR_1 R560 L_INR_0 L37 L_INR_2 10
Reference resistor PIN.37 PIN.24 LINE1-JD 11 14
for Jack EC47
CD10u16EL5 75R0402 120L600mA-250 12
LINE1-IN-L 1+ 2 L_INL_1 R561 L_INL_0 L36 L_INL_2 13 15
Detection(close to
1
the codec) PIN.46 CD10u16EL5 JACK-AUDIOX3F_PK/GR/BU-RH-4 LINE_OUT
(front
Spilt by DGND PIN.47 LINE IN(A) channel)
AVDD5 PIN.48 PIN.13
HP_SNS R484 39.2KR1%0402 Analog Area In order to meet the
2
C0.1U16Y0402 input/output performance of R260
MIC_SNS R485 20KR1%0402 C616 PIN.1 PIN.12 Digital Area Vista Premium requirement, 22KR0402 D16 35mm
D D
10uF DIP caps. and 22K R282 ESD-SFI/SFI0603ML080C-LF SURROUND
LINE OUT(B)
20KR1%0402
AC_HP_SNS R559 47R1%0402 pull-down resistors. 22KR0402 D18 or
ESD-SFI/SFI0603ML080C-LF LINE_IN
FRONT-R
FRONT-L
Sense_B
For Standby Mode/De-pop
R463 CENTER-LEF
SURRBACK_LR506 0R0402
AVDD5 MIC IN(C) or
R471
X_10KR0402 MIC INPUT
SURRBACK_RR507 0R0402
EC57 R257 AUDIO1B
33
34
35
36
37
38
39
40
41
42
43
44
R529 R550 U28 CD100u16EL5-RH 75R0402 120L600mA-250 AUDIO PANEL
X_22KR0402 X_22KR0402 FRONT-R 1+ 2 F_R_0 F_R_1 L34 F_R_2 6 AUDIO1
FRONT-L
AVDD2
SURR-L
JDREF
AVSS2
NC
Sense B
FRONT-R
SURR-R
LFE
CENTER
PIN37-VREFO
FRONT-JD 7
120L600mA-250 8
21 MIC1-IN-L FRONT-L 1+ 2 F_L_0 F_L_1 L35 F_L_2 9
ALC888/ALC662 Desktop Configuation(5.1
MIC1-L MIC1-IN-R
MIC1-R 22 EC56 Channel solution)
1
2 1 45 CD100u16EL5-RH R258 JACK-AUDIOX3F_PK/GR/BU-RH-4
FRONT-JD R449 5.1KR1%0402 EC82 2
+ SIDE-L LINE1-IN-L
+1CD10U16EL5
46 SIDE-R LINE1-L 23 75R0402
(3 Jacks at rear panel , 2 jacks
EC83 CD10U16EL5
47 24 LINE1-IN-R
LINE1-JD R450 10KR1%0402 SPDIFI/EAPD LINE1-R
48 SPDIFO
25 C588 C0.1U16Y0402
AVDD5 at front panel)
2
MIC1-JD R448 20KR1%0402 Sense_A AVDD1 R259
13 Sense A AVSS1 26
HP_OUT-L
HP_OUT-R
14
15
LINE2-L
LINE2-R
REALTEK VREF 27 C610 C10u6.3X50805
22KR0402
R256
D15
ESD-SFI/SFI0603ML080C-LF Pin Assignment Location Re-tasking
MIC_IN-L 16 28 MIC1-VREFO-L 22KR0402 D14
MIC_IN-R 17
18
MIC2-L
MIC2-R
CD-L
ALC888 MIC1-VREFO-L
LINE1-VREFO 29
ESD-SFI/SFI0603ML080C-LF LINE1 (pin-23/24)
FRONT(pin-35/36)
Rear Panel
Rear Panel
line input
AMP output
19 MIC1 (pin-21/22) Rear Panel MIC input
GPIO1/DMIC-DATA
CD-GND
GPOI0/DMIC-CLK
JD resistors should be placed 30 MIC2-VREFO

MIC2-VREFO
as close as possible to the 20 CD-R
SURR (pin-39/41) Rear RCA Jack Line output
LINE2-VREFO
SDATA-OUT
LINE2-VREFO 31
sense pin of CODEC. MIC1-VREFO-R CEN/LFE (pin-43/44) N/A Line output
SDATA-IN
32
DVDD-IO
MIC1-VREFO-R
PCBEEP
RESET#
SIDE-SURR (pin-45/46) N/A Line output
DVDD1
DVSS1
DVSS2
SYNC
BCLK
MIC1-VREFO-L R254 4.7KR0402 LINE2 (pin-14/15) Front Panel AMP output

C FMIC (pin-16/17) Front Panel Stereo MIC input C
ALC888-GR-A2-RH MIC1-VREFO-R R253 4.7KR0402
1
2
3
4
5
6
7
8
9
10
11
12
AUDIO1C
EC49 75R0402 120L600mA-250
MIC1-IN-R 1+ 2 M_INR_1 R562 M_INR_0L32 M_INR_2 1 18
AZ_RST# AZ_RST# 18,21 MIC1-JD 2
VCC3 AZ_SYNC 18 EC48
CD10u16EL5 75R0402 120L600mA-250 4 17
R459 22R0402 AZ_SDIN 18 MIC1-IN-L 1+ 2 M_INL_1 R563 M_INL_0 L33 M_INL_2 5
R460 22R0402 AZ_BIT_CLK AZ_BIT_CLK 18
1
AZ_SDOUT 18 CD10u16EL5 JACK-AUDIOX3F_PK/GR/BU-RH-4
In order to meet the input/output
C609 C608 C607 performance of Vista Premium
requirement, 10uF DIP caps. and 22K
C0.1U16Y0402 C0.1U16Y0402 C22p50N0402 AZ_RST# C591 X_C100P50N0402 pull-down resistors.
2
AZ_BIT_CLK C603 X_C1000P50X0402 D13
R252 ESD-SFI/SFI0603ML080C-LF
22KR0402 D12
R255 ESD-SFI/SFI0603ML080C-LF
22KR0402
Front Audio Jack JSPK_OUT HEADER

D29
S-BAT54A_SOT23
Y R131 4.7KR0402
MIC2-VREFO Z
X R132 4.7KR0402
AVDD5
Y R133 4.7KR0402 AVDD5

LINE2-VREFO Z 1/16W, 2.5V,
X R139 4.7KR0402 max:25mA JSPK_OUT
SURRBACK_L 1 2 SURRBACK_R
3 4
D33 R528 C646 5
S-BAT54A_SOT23 JAUD1 X_10KR0402 X_C0.1U16Y0402
B B
1 2 H2X3[6]_green-RH
MIC_IN-R C851 C4.7u6.3X50805 MIC_R 3 4 R508
MIC_IN-L C852 C4.7u6.3X50805 MIC_L 5 6 MIC_SNS 33R0402
HP_OUT-R EC60 1+ 2 CD100u16EL5-RH HP_R_1 AC_HP_SNS 7
HP_OUT-L EC50 1+ 2 CD100u16EL5-RH HP_L_1 HP_L 9 10 HP_SNS
R488
1
ESD CAP R558 _H2X5[8]_green-2.6mm-RH-1 20KR1%0402

1KR0402
R557 R486
1KR0402 39.2KR1%0402
R487
2
75R0402
R498
75R0402
R497 R482
D28 22KR0402 22KR0402
ESD-SFI/SFI0603ML080C-LF R493 R483 c610 change to X5R;C591 leave empty;R449 change to 1%
D31
ESD-SFI/SFI0603ML080C-LF
D27
22KR0402 22KR0402
Modify 0828 EC61,EC62 change to C851,C8524.7uX5R;R557,R558 change to 1KR;
D33,,R139,R133,R482,R483 leave empty;
R253,R254 change to 4.7KR and connect to M_INR_0/M_INL_0; Add for NEC spec0828
Analog Area Digital Area
ESD-SFI/SFI0603ML080C-LF R256,R259 connect to F_R_0/F_L_0
D32
ESD-SFI/SFI0603ML080C-LF
Audio Power EMI
VCC5_SB 1 2 CP47
Digital Area Sense_B
Analog Area 1 2 CP46
Trace Width 40mils. MIC_R LINE1-IN-R C578 X_C100P50N0402
D22 AVDD5 LINE1-IN-L C579 X_C100P50N0402
D23 R901 U27 S-1N5817_DO214AC MIC_L C658 TP124 AVDD5
BAS32L_LL34 10R0805 LT1087S_SOT89 FRONT-R C614 X_C100P50N0402 C0.1U16Y0402
+12V 3 2 FRONT-L C613 X_C100P50N0402
VIN VOUT
A A
1
EC52 C590 HP_L MIC1-IN-R C580 X_C100P50N0402

+
ADJ
R462 MIC1-IN-L C581 X_C100P50N0402

1
CD100u16EL5-RH EC59 C615

+
100R1%0402
2
C673 C663 C660 C751 For EMI

1
CD100u16EL5-RH C0.1U16Y0402 Placement close to Codec chip Tied at one point only
2
C0.1U16Y0402
under the codec or near
the codec
R461 C381 C1000P50X0402
324R1%0402 X_C1000P50X0402 X_C1000P50X0402 X_C0.1U16Y0402
X_C1000P50X0402 MICRO-START INT'L CO.,LTD.
Title
ALC888
Analog Area
Digital Area Custom VL390 0A
5 4 3 2 1
E D C B A
POWER CIRCUIT FOR USB PORT 2,3,4,5 Rear

POWER CIRCUIT FOR USB PORT 6,7 Front
VCC5 VCC5
EC68 VCC5
EC73
2 + 1
VCC5_SB VCC5_SB 2 + 1
X_.CD1000U6.3EL11.5 VCC5_SB
SVCC1 SVCC2
X_.CD1000U6.3EL11.5
1
2
1
2
U40 U45 SVCC4
1
2
5 5 U46
5VCC
5VCC
5VSB
5VSB
26 5VDRV1_EN S3# 26 5VDRV1_EN S3#
6 7 6 7 5
5VCC
5VSB
18 OC#1 OC# VOUT1 18 OC#2 OC# VOUT1 26 5VDRV1_EN S3#
18 OC#4 6 OC# VOUT1 7
EC67 C266 EC69 C513
8 8 EC81 C522
GND
GND
VOUT2 VOUT2
1
+
+
4 4 8
GND
4 25 USB_EN 25 USB_EN 4
.CD1000U6.3EL11.5
.CD1000U6.3EL11.5
EN EN VOUT2
1 +
4
C0.1U16Y0402
C0.1U16Y0402
25 USB_EN
.CD1000U6.3EL11.5
UP7533AM8_SOT23-8-RH UP7533AM8_SOT23-8-RH EN
C0.1U16Y0402
3
2
UP7533AM8_SOT23-8-RH
2
POWER CIRCUIT FOR USB PORT 8,9 Front
POWER CIRCUIT FOR USB PORT 0,1
VCC5 VCC5
Rear
SVCC1 SVCC2 SVCC3 SVCC4 SVCC5
VCC5_SB VCC5_SB
SVCC3 SVCC5
1
2
1
2
C717
C251
C656
C654
C655
U48 U47
X_C0.01U16X0402
X_C0.01U16X0402
X_C0.01U16X0402
X_C0.01U16X0402
X_C0.01U16X0402
1
1
5 5
5VCC
5VCC
5VSB
5VSB
26 5VDRV1_EN S3# 26 5VDRV1_EN S3#
18 OC#3 6 OC# VOUT1 7 18 OC#5 6 OC# VOUT1 7
2
EC87 C637 EC85 C631
8 8
GND
GND
VOUT2 VOUT2
1
1
+
+
25 USB_EN 4 25 USB_EN 4
.CD1000U6.3EL11.5
.CD1000U6.3EL11.5
EN EN
C0.1U16Y0402
C0.1U16Y0402
UP7533AM8_SOT23-8-RH UP7533AM8_SOT23-8-RH
3
2
For EMI
Placement close to ESD doide power pin.
3 3
REAR PANEL USB CONNECTOR FOR USB PORT 2,3,4,5
FRONT PANEL USB CONNECTOR FOR USB PORT 6,7
22 / 7.5 / 7.5 / 7.5 / 22 / 7.5 / 7.5 / 7.5 / 22
NEAR USB CONNECTOR
NEAR USB CONNECTOR 22 / 7.5 / 7.5 / 7.5 / 22 / 7.5 / 7.5 / 7.5 / 22
SVCC2 SVCC4
SBD3+
18 USB3+
1
SBD6+
18 USB6+ 40 mils
4
U9 L72 U29 SVCC4
ESD-IP4220 X_CMC-L02-9008034-M09 ESD-IP4220 L62
5
5
X_CMC-L02-9008034-M09
SBD2+ 6 4 SBD3+ SVCC2 SBD7+ 6 4 SBD6+
SBD3- USB1B
18 USB3-
2
SBD2- 1 3 SBD3- 16 SBD7- 1 3 SBD6- SBD6- C625

18 USB6-
3
SBD2+ 15 21
13
SBD2- 14 22 SBD7+ C0.1U16Y0402
18 USB7+
2
4
18 USB2+
SBD2+ 13 UP JUSB1
1
12 L61 EMI
L73 SBD3+ SBD7- 1 2 SBD6-
11 X_CMC-L02-9008034-M09 3 4
X_CMC-L02-9008034-M09 SBD3- 10 9 SBD7+ SBD6+
5 6
9 SECOND 7 8
USB6- SBD6- SBD7-
18 USB7-
3
USB3+ SBD3+ SBD2- USBAX4M_BLACK-RH-3 USB6+ SBD6+ 10
18 USB2-
2
USB3- SBD3- USB7- SBD7- _H2X5[9][10]_yellow-RH

USB2+ SBD2+ USB7+ SBD7+
USB2- SBD2-
Modify USB Pinhead

SVCC2
U10
ESD-IP4220 SBD5+
18 USB5+
5
2 2
SBD5- 6 4 SBD4- L74 SVCC1
X_CMC-L02-9008034-M09 USB1A
SBD5+ 1 3 SBD4+ 8 17
SBD4+
SBD5- SBD4-
7
6
5
18
19
USB CARD READER + IR MODULE FOR USB PORT 8,9
18 USB5-
2
5 THIRD 20
SVCC5
4
SBD4+ SBD5+ 3
18 USB4+
1
SBD5- 2 1
L75 1 U35
USB5+ SBD5+ X_CMC-L02-9008034-M09 DOWN ESD-IP4220
5
USB5- SBD5- USBAX4M_BLACK-RH-3 SBD9+
18 USB9+
4
USB4+ SBD4+ SBD8+ 6 4 SBD9+
USB4- SBD4- SBD4- L63
18 USB4-
2
SBD8- 1 3 SBD9- X_CMC-L02-9008034-M09
2
SBD9-
18 USB9-
3
SBD8+
18 USB8+
4
USB9- SBD9- L64
USB9+ SBD9+ X_CMC-L02-9008034-M09
40 mils SVCC5
USB8- SBD8-
USB8+ SBD8+
REAR PANEL USB CONNECTOR FOR USB PORT 0,1 SBD8-
18 USB8-
3
SVCC3
C629
SBD1+ SVCC3
18 USB1+
1
U13 C0.1U16Y0402
ESD-IP4220 L76 X_C0.1U16Y0402 JUSB2
5
X_CMC-L02-9008034-M09 C718
1 2
EMI
SBD1- 6 4 SBD0- SBD9- SBD8-
LAN_USB1A SBD9+ 3 4 SBD8+
SBD1+ SBD0+ SBD1- 5 6
1 3 18 USB1- 5 23
2
PWR GND 7 8
SBD0- 6 USB- GND 24
SBD0+ 10
7 USB+ GND 25
2
1 1
8 26 _H2X5[9][10]_yellow-RH
SBD0+
GND UP GND
18 USB0+
1
1 PWR GND 27
L80 SBD1- 2 GND 28
USB-
X_CMC-L02-9008034-M09 SBD1+ 3 GND 29
USB+DOWN
4 GND GND 30
SBD0- RJ45_USBX2_LEDX2_TX-GIGA-RH-1
18 USB0-
2
USB1+ SBD1+
USB1- SBD1-
USB0+
USB0-
SBD0+
SBD0- MICRO-START INT'L CO.,LTD.
Title
USB CONNECTORS
Custom VL390 0A
E D C B A
8 7 6 5 4 3 2 1
PCI Express Slot x16/x1

VCC3
PESW_1.8V
PCI EXPRESS x16 Slot PCI EXPRESS 1 Slot-1
R332 X_4.7KR0402 DP_AUX1P_CON
+12V PESW_1.8V PESW_1.8V
R328 X_4.7KR0402 PE_TMS +12V PCIE16_X1 R473 +12V PCIE1_X1 +12V
X2 4.7KR0402
R369 X_4.7KR0402 PE_TCK X2 R407 R474 VCC3
B1 12V#B1 PRSNT1# A1 COMM_EN 15,33
B2 A2 4.7KR0402 4.7KR0402 B1 A1
R329 X_4.7KR0402 TMDS_HPD1_CON 12V#B2 12V VCC3_SB 12V PRSNT1_#
B3 RSVD#B3 12V#A3 A3 B2 12V#B2 12V#A2 A2
G
D B4 A4 SLI_SWITCH B3 A3 D
SLI_SWITCH 33
S
GND#B4 GND RSVD 12V#A3
D
SCLK1 B5 A5 PE_TCK B4 A4
18,24,31,32 SCLK1 SMCLK JTAG2 GND GND#A4 VCC3
SDATA1 B6 A6 DP_AUX1P_CON SCLK1 B5 A5
18,24,31,32 SDATA1 SMDAT JTAG3 Q110 SMCLK JTAG2
B7 A7 SDATA1 B6 A6
GND#B7 JTAG4 PE_TMS N-2N7002_SOT23 SMDATA JTAG3
VCC3 B8 3.3V#B8 JTAG5 A8 B7 GND#B7 JTAG4 A7
TMDS_HPD1_CON B9 A9 B8 A8
JTAG1 3.3V VCC3 3.3V JTAG5
VCC3_SB
WAKE#
B10
B11
3.3VAUX 3.3V#A10 A10
A11 PE_GF_RST#_A
Modify 0901 B9
B10
JTAG1 3.3V#A9 A9
A10
18,24 WAKE# WAKE# PWRGD 3.3VAUX 3.3V#A10
WAKE# B11 A11 PE_GF_RST#_A
WAKE_# PWRGD
X1 X1
B12 RSVD#B12 GND#A12 A12 From Clock Gen
B13 A13 PE16_GXF_CLK B12 A12
GND#B13 REFCLK+ PE16_GXF_CLK 12 RSVD#B12 GND#A12
SW_GFX_TXC_0P
C415 C0.1U10X0402 EXP_A_TXP_0_C B14 A14 PE16_GXF_CLK# B13 A13
33 SW_GFX_TXC_0P HSOP0 REFCLK- PE16_GXF_CLK# 12 GND#B13 REFCLK+ PE1_GPP_CLK1 12
SW_GFX_TXC_0N
C414 C0.1U10X0402 EXP_A_TXN_0_C B15 A15 C402 C0.1U10X0402 GPP_TX0P_C B14 A14
33 SW_GFX_TXC_0N HSON0 GND#A15 14 GPP_TX0P HSOP0+ REFCLK- PE1_GPP_CLK1# 12
B16 A16 GFX_RX0P C404 C0.1U10X0402 GPP_TX0N_C B15 A15
GND#B16 HSIP0 GFX_RX0P 14 14 GPP_TX0N HSOP0- GND#A15
B17 A17 GFX_RX0N B16 A16
PRSNT2# HSIN0 GFX_RX0N 14 GND#B16 HSIP0+ GPP_RX0P 14
B18 GND#B18 GND#A18 A18 B17 PRSNT2_# HSIP0- A17 GPP_RX0N 14
B18 GND#B18 GND#A18 A18
X2 X2
SW_GFX_TXC_1P
C424 C0.1U10X0402 EXP_A_TXP_1_C B19 A19
33 SW_GFX_TXC_1P HSOP1 RSVD
SW_GFX_TXC_1N
C420 C0.1U10X0402 EXP_A_TXN_1_C B20 A20
33 SW_GFX_TXC_1N HSON1 GND#A20
B21 A21 GFX_RX1P
GND#B21 HSIP1 GFX_RX1P 14
B22 A22 GFX_RX1N
GND#B22 HSIN1 GFX_RX1N 14
SW_GFX_TXC_2P
C421 C0.1U10X0402 EXP_A_TXP_2_C B23 A23 SLOT-PCI36_WHITE-2PITCH-RH-4
33 SW_GFX_TXC_2P HSOP2 GND#A23
SW_GFX_TXC_2N
C425 C0.1U10X0402 EXP_A_TXN_2_C B24 A24
B25 A25 GFX_RX2P
B26 A26 GFX_RX2N
SW_GFX_TXC_3P
C426 C0.1U10X0402 EXP_A_TXP_3_C B27 A27
33 SW_GFX_TXC_3P HSOP3 GND#A27
SW_GFX_TXC_3N
C422 C0.1U10X0402 EXP_A_TXN_3_C B28 A28
B29 A29 GFX_RX3P
B30 A30 GFX_RX3N
C RSVD#B30 HSIN3 GFX_RX3N 14 C
B31 PRSNT2##B31 GND#A31 A31
B32 GND#B32 RSVD#A32 A32
GFX_TXC_4P C427 C0.1U10X0402 EXP_A_TXP_4_C B33 A33

14 GFX_TXC_4P HSOP4 RSVD#A33
GFX_TXC_4N C428 C0.1U10X0402 EXP_A_TXN_4_C B34 A34
14 GFX_TXC_4N HSON4 GND#A34
B35 A35 GFX_RX4P
B36 A36 GFX_RX4N
14 GFX_TXC_5P HSOP5 GND#A37
B39 A39 GFX_RX5P
B40 A40 GFX_RX5N
B43 A43 GFX_RX6P
B44 A44 GFX_RX6N
B47 A47 GFX_RX7P
B48 A48 GFX_RX7N
PRSNT2##B48 HSIN7 GFX_RX7N 14
B49 GND#B49 GND#A49 A49

14 GFX_TXC_8P HSOP8 RSVD#A50
B52 A52 GFX_RX8P
B53 A53 GFX_RX8N
B56 A56 GFX_RX9P
B57 A57 GFX_RX9N
B GND#B57 HSIN9 GFX_RX9N 14 B
GFX_TXC_10PC438 C0.1U10X0402 EXP_A_TXP_10_C B58 A58
GFX_TXC_10NC439 C0.1U10X0402 EXP_A_TXN_10_C B59 A59
B60 A60 GFX_RX10P
B61 A61 GFX_RX10N
B64 A64 GFX_RX11P
B65 A65 GFX_RX11N
B68 A68 GFX_RX12P
B69 A69 GFX_RX12N
B72 A72 GFX_RX13P
GND#B72 HSIP13 GFX_RX13P 14 VCC3 TP152
B73 A73 GFX_RX13N PE_GF_RST#_A
GND#B73 HSIN13 GFX_RX13N 14 Connected to A_RST# ANDed with
14 GFX_TXC_14P HSOP14 GND#A74 Southbridge GPIO (S5 domain). TP153
GFX_TXC_14NC417 C0.1U10X0402 EXP_A_TXN_14_C B75 A75 U54 PE16_GXF_CLK
14 GFX_TXC_14N HSON14 GND#A75 TP154
B76 A76 GFX_RX14P NC7SZ08M5X_SOT23-5-RH PE16_GXF_CLK#
5
B77 A77 GFX_RX14N
GFX_TXC_15PC418 C0.1U10X0402 EXP_A_TXP_15_C B78 A78 1
VCC
14 GFX_TXC_15P HSOP15 GND#A78 18 GFX16_PCIERST# A
GFX_TXC_15NC419 C0.1U10X0402 EXP_A_TXN_15_C B79 A79 4 PE_GF_RST#_A
14 GFX_TXC_15N HSON15 GND#A79 Y
B80 A80 GFX_RX15P 2
GND#B80 HSIP15 GFX_RX15P 14 17 PE_GF_RST# B
TP156
B81 A81 GFX_RX15N PE1_GPP_CLK1
PRSNT2##B81 HSIN15 GFX_RX15N 14 GND
TP157
B82 A82 PE1_GPP_CLK1#
3
RSVD#B82 GND#A82
X1 X1
SLOT-PCI164P_BLACK-2PITCH-RH-13
R299 X_0R0402
A A
+12V VCC3 VCC3_SB +12V VCC3 VCC3_SB
1
C521 C403 C400 C523 C401 C448 C492 EC44 C490 C447 C446
+
C0.1U16Y0402 MICRO-START INT'L CO.,LTD.

2
C0.1U16Y0402 Title
X_C0.1u16Y0402 C0.1U16Y0402 X_C0.1u16Y0402 C0.1U16Y0402 PCI EXPRESS X16 & X1 SLOT
C0.1U16Y0402 C0.1U16Y0402
X_C0.1u16Y0402 CD470u16EL11.5-RH X_C0.1u16Y0402 Size Document Number Rev
Placement Between at PCIE_X1 Placement Close To PCIE16_X1 Custom VL390 0A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI SLOT 1 (PCI VER: 2.3 COMPLY) PCI SLOT 2 (PCI VER: 2.3 COMPLY)
AD[31..0] AD[31..0]
17 AD[31..0] -12V 17 AD[31..0] -12V
+12V +12V
C_BE#[3..0] PCI1 C_BE#[3..0] PCI2
17 C_BE#[3..0] 17 C_BE#[3..0]
B1 -12V TRST# A1 B1 -12V TRST# A1
B2 TCK +12V A2 B2 TCK +12V A2
B3 GND#B3 TMS A3 B3 GND#B3 TMS A3
B4 TDO TDI A4 VCC5 B4 TDO TDI A4 VCC5
VCC5 B5 +5V#B5 +5V A5 VCC5 B5 +5V#B5 +5V A5
B6 A6 PCI_INTA# B6 A6 PCI_INTB#
PCI_INTB# +5V#B6 INTA# PCI_INTC# PCI_INTC# +5V#B6 INTA# PCI_INTD#
B7 INTB# INTC# A7 B7 INTB# INTC# A7
D PCI_INTD# B8 A8 PCI_INTA# B8 A8 D
INTD# +5V#A8 INTD# +5V#A8
B9 PRSNT#1 RESERVED A9 B9 PRSNT#1 RESERVED A9
B10 RESERVED#B10 +5V(I/O) A10 B10 RESERVED#B10 +5V(I/O) A10
B11 A11 VCC3 B11 A11 VCC3
VCC3 PRSNT#2 RESERVED#A11 VCC3 PRSNT#2 RESERVED#A11
B12 GND#B12 GND A12 B12 GND#B12 GND A12
B13 GND#B13 GND#A13 A13 B13 GND#B13 GND#A13 A13
B14 RESERVED#B14 3.3VAUX A14 VCC3_SB B14 RESERVED#B14 3.3VAUX A14 VCC3_SB
B15 A15 PCIRST_SLOT1# B15 A15 PCIRST_SLOT1#
GND#B15 RST# PCIRST_SLOT1# 17 GND#B15 RST#
17 PCI_CLK0 B16 CLK +5V(I/O)#A16 A16 17 PCI_CLK1 B16 CLK +5V(I/O)#A16 A16
B17 GND#B17 GNT# A17 PGNT#0 17 B17 GND#B17 GNT# A17 PGNT#1 17
PREQ#0 B18 A18 PREQ#1 B18 A18
17 PREQ#0 REQ# GND#A18 17 PREQ#1 REQ# GND#A18
B19 A19 PCI_PME# B19 A19 PCI_PME#
+5V(I/O)#B19 PME# PCI_PME# 18 +5V(I/O)#B19 PME# PCI_PME# 18
AD31 B20 A20 AD30 AD31 B20 A20 AD30
AD29 AD31 AD30 AD29 AD31 AD30
B21 AD29 +3.3V A21 B21 AD29 +3.3V A21
B22 A22 AD28 B22 A22 AD28
AD27 GND#B22 AD28 AD26 AD27 GND#B22 AD28 AD26
B23 AD27 AD26 A23 B23 AD27 AD26 A23
AD25 B24 A24 AD25 B24 A24
AD25 GND#A24 AD24 AD25 GND#A24 AD24
B25 +3.3V#B25 AD24 A25 B25 +3.3V#B25 AD24 A25
C_BE#3 B26 A26 R458 330R0402 AD16 C_BE#3 B26 A26 R466 330R0402 AD17
AD23 C/BE#3 IDSEL AD23 C/BE#3 IDSEL
B27 AD23 +3.3 A27 B27 AD23 +3.3 A27
B28 A28 AD22 B28 A28 AD22
AD21 GND#B28 AD22 AD20 AD21 GND#B28 AD22 AD20
B29 AD21 AD20 A29 B29 AD21 AD20 A29
AD19 B30 A30 AD19 B30 A30
B31 +3.3V#B31 AD18 A31 B31 +3.3V#B31 AD18 A31
AD17 B32 A32 AD16 AD17 B32 A32 AD16
FRAME# C_BE#2 AD17 AD16 C_BE#2 AD17 AD16
17 FRAME# B33 C/BE#2 +3.3V#A33 A33 B33 C/BE#2 +3.3V#A33 A33
IRDY# B34 A34 FRAME# B34 A34 FRAME#
17 IRDY# DEVSEL# IRDY# GND#B34 FRAME# IRDY# GND#B34 FRAME#
17 DEVSEL# B35 IRDY# GND#A35 A35 B35 IRDY# GND#A35 A35
TRDY# B36 A36 TRDY# B36 A36 TRDY#
17 TRDY# +3.3V#B36 TRDY# +3.3V#B36 TRDY#
DEVSEL# B37 A37 DEVSEL# B37 A37
DEVSEL# GND#A37 STOP# DEVSEL# GND#A37 STOP#
B38 GND#B38 STOP# A38 B38 GND#B38 STOP# A38
C SERR# LOCK# B39 A39 LOCK# B39 A39 C
17 SERR# LOCK# +3.3V#A39 LOCK# +3.3V#A39
PERR# PERR# B40 A40 SCLK1 PERR# B40 A40 SCLK1
17 PERR# PERR# SMBCLK SCLK1 18,24,30,32 PERR# SMBCLK SCLK1 18,24,30,32
LOCK# B41 A41 SDATA1 B41 A41 SDATA1
17 LOCK# +3.3V#B41 SMBDAT SDATA1 18,24,30,32 +3.3V#B41 SMBDAT SDATA1 18,24,30,32
STOP# SERR# B42 A42 SERR# B42 A42
17 STOP# SERR# GND#A42 SERR# GND#A42
B43 A43 PAR B43 A43 PAR
+3.3V#B43 PAR PAR 17 +3.3V#B43 PAR PAR 17
C_BE#1 B44 A44 AD15 C_BE#1 B44 A44 AD15
PCI_INTD# AD14 C/BE#1 AD15 AD14 C/BE#1 AD15
17 PCI_INTD# B45 AD14 +3.3V#A45 A45 B45 AD14 +3.3V#A45 A45
PCI_INTC# B46 A46 AD13 B46 A46 AD13
17 PCI_INTC# GND#B46 AD13 GND#B46 AD13
PCI_INTA# AD12 B47 A47 AD11 AD12 B47 A47 AD11
17 PCI_INTA# AD12 AD11 AD12 AD11
PCI_INTB# AD10 B48 A48 AD10 B48 A48
17 PCI_INTB# AD10 GND#A48 AD10 GND#A48
B49 A49 AD9 B49 A49 AD9
GND#B49 AD9 GND#B49 AD9
X1 X1 X2 X2 X1 X1 X2 X2
AD8 B52 A52 C_BE#0 AD8 B52 A52 C_BE#0

AD7 AD8 C/BE#0 AD7 AD8 C/BE#0
B53 AD7 +3.3V#A53 A53 B53 AD7 +3.3V#A53 A53
B54 A54 AD6 B54 A54 AD6
AD5 +3.3V#B54 AD6 AD4 AD5 +3.3V#B54 AD6 AD4
B55 AD5 AD4 A55 B55 AD5 AD4 A55
AD3 B56 A56 AD3 B56 A56
B57 GND#B57 AD2 A57 B57 GND#B57 AD2 A57
AD1 B58 A58 AD0 AD1 B58 A58 AD0
AD1 AD0 AD1 AD0
B59 +5V(I/O)#B59 +5V(I/O)#A59 A59 B59 +5V(I/O)#B59 +5V(I/O)#A59 A59
ACK#64 B60 A60 REQ#64 ACK#64 B60 A60 REQ#64
ACK64# REQ64# ACK64# REQ64#
B61 +5V#B61 +5V#A61 A61 B61 +5V#B61 +5V#A61 A61
B62 +5V#B62 +5V#A62 A62 B62 +5V#B62 +5V#A62 A62
VCC3
SLOT-PCI120_white-RH SLOT-PCI120_white-RH
ACK#64 R445 8.2KR0402
REQ#64 R433 8.2KR0402
PCI PULL-UP / DOWN RESISTORS
IDSEL = AD16 IDSEL = AD17
B MASTER = PREQ#0 MASTER = PREQ#1 B
PCI_INT A, B, C, D PCI_INT B, C, D, A
PCI SLOT DECOUPLING CAPACITORS
VCC5 VCC3 VCC5 VCC3 VCC3_SB
1+ 2 EC54 1+ 2 EC55 C561

C500 .CD1000U6.3EL11.5 X_.CD1000U6.3EL11.5 C0.1U16Y0402
X_C0.1U16Y0402 C563 C600 C592
C562 C0.1U16Y0402 C0.1U16Y0402 C0.1U16Y0402
X_C0.1U16Y0402 C601 C595 C599
C0.1U16Y0402 C0.1U16Y0402 X_C0.1U16Y0402
C624 C598
X_C0.1U16Y0402 X_C0.1U16Y0402
C622 C597
C0.1U16Y0402 X_C0.1U16Y0402 TP161 PCI_CLK0
C596 C594
X_C0.1U16Y0402 X_C0.1U16Y0402 TP162 PCIRST_SLOT1#
A A
+12V -12V
C560 C623
C0.1U16Y0402 C0.1U16Y0402
C602 C559
X_C0.1U16Y0402
C593
X_C0.1U16Y0402
X_C0.1U16Y0402 Title
PCI SLOT 1
Custom VL390 0A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
TPM - Security Controller

VCC3
C668 C664
X_C0.1U16Y0402 X_C0.1U16Y0402
VCC3 C665
C0.1U16Y0402
U25
VCC3_SB
LPC_AD0 26 10
17,25 LPC_AD0 LAD0 VDD
R532 LPC_AD1 23 19
10KR0402 LPC_AD2 20 24
LPC_AD3 17
17,25 LPC_AD3 LAD3
TPMLPCPD# 21 4
C 17,21 PCI_CLK4 LCLK GND C
LPC_FRAME# 22 11 C669
17,25 LPC_FRAME# LFRAME# GND
PCIRST_TPM# 16 18 C0.1U16Y0402
17 PCIRST_TPM# LRESET# GND
TPMLPCPD# 28 25
SERIRQ LPCPD# GND
17,25 SERIRQ 27 SERIRQ
VSB 5
R546 X_0R0402 9
R533 4.7KR0402 TESTBI/BADD
15 CLKRUN#
PP 7
6 GPIO
R552 R551 2
X_0R0402 GPIO2
0R0402 XTALI 13
VCC3 1 14
NC XTALO
4
3
17 PCI_CLKRUN#
12
NC
NC TESTI 8
Y8
CPU Thermo Sense
32.768KHZ12.5P_D-LF
B0C-0963512(SLB9635TT1.2-RH)
3
C659 C671
C12P50N0402 C12P50N0402
U37
B VCC3 1 8 SCLK1 B
VCC SCL SCLK1 18,24,30,31
7,25 THERMDA_CPU R524 X_0R0402 HWM_D+ 2 7 SDATA1

D+ SDA SDATA1 /N18,24,30,31
7,25 THERMDC_CPU R525 X_0R0402 HWM_D- 3 6 TALERT1# R526 X_1KR0402 VCC3
/N D- ALERT#
VCC3 R527 X_1KR0402 TALERT2# 4 5
THERM# GND
X_SNSR-F75383S-LF
HWM_D+
/N
Place close to C782 VCC3 C781 X_C10u6.3X50805
F75383.
X_C3300P50X0402
HWM_D-
A A
TP163 PCIRST_TPM# MICRO-START INT'L CO.,LTD.

Title
TP164 PCI_CLK4 TMP/Asset ID/HWM W83201G
B VL390 0A
8 7 6 5 4 3 2 1
5 4 3 2 1
PESW_1.8V
DISPLAYPORT1
DPC_LINE0_DP 1 ML_LANE_0P
2 GND 21 21
DPC_LINE0_DN
13
18
20
30
40
42
U24 3 ML_LANE_0N 22 22
5
8
DPC_LINE1_DP 4 23
ML_LANE_1P 23
5 24
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
SW_DPC_LINE0_DN DPC_LINE1_DN GND 24
D
0B1 38 6 ML_LANE_1N
D
37 SW_DPC_LINE0_DP DPC_LINE2_DP 7
1B1 ML_LANE_2P
8 GND
GFX_TXC_0N 2 36 SW_DPC_LINE1_DN DPC_LINE2_DN 9
14 GFX_TXC_0N A0 2B1 ML_LANE_2N
GFX_TXC_0P 3 35 SW_DPC_LINE1_DP DPC_LINE3_DP 10
14 GFX_TXC_0P A1 3B1 ML_LANE_3P
11 GND
GFX_TXC_1N 6 34 SW_GFX_TXC_0N DPC_LINE3_DN 12
14 GFX_TXC_1N A2 0B2 SW_GFX_TXC_0N 30 ML_LANE_3N
GFX_TXC_1P 7 33 SW_GFX_TXC_0P 13
14 GFX_TXC_1P A3 1B2 SW_GFX_TXC_0P 30 GND
14 GND
32 SW_GFX_TXC_1N DPC_AUX_DP 15
2B2 SW_GFX_TXC_1N 30 AUX_CHP
31 SW_GFX_TXC_1P 16
3B2 SW_GFX_TXC_1P 30 GND
SLI_SWITCH 9 DPC_AUX_DN 17
30 SLI_SWITCH SEL SW_DPC_LINE2_DN DPC_HPD AUX_CHN
GND 4B1 29
28 SW_DPC_LINE2_DP FS3
18
19
HOT PLUG DETECT
5B1 DP_PWR RETURN DP_PWR
VCC3 A C 1 2 20 DP_PWR
GFX_TXC_2N 11 27 SW_DPC_LINE3_DN
14 GFX_TXC_2N A4 6B1
GFX_TXC_2P 12 26 SW_DPC_LINE3_DP D19 1.1A/6V/0.21ohm
14 GFX_TXC_2P A5 7B1 S-1N5817_DO214AC DISPO20PM_BLACK-RH
GFX_TXC_3N 15 25 SW_GFX_TXC_2N
14 GFX_TXC_3N A6 4B2 SW_GFX_TXC_2N 30
GFX_TXC_3P 16 24 SW_GFX_TXC_2P
14 GFX_TXC_3P A7 5B2 SW_GFX_TXC_2P 30
SW_DPC_LINE0_DP C176 C0.1U16X0402 DPC_LINE0_DP
23 SW_GFX_TXC_3N
6B2 SW_GFX_TXC_3N 30
SW_GFX_TXC_3P R310
22 Switch circuit for secondary displayport
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
7B2 SW_GFX_TXC_3P 30
X_1KR/4
SW_DPC_LINE0_DN C172 C0.1U16X0402 DPC_LINE0_DN
C C
PI2PCIE2412ZHE_TQFN42-RH
1
4
10
14
17
19
21
39
41
43
DPC_AUX_DP_C
SW_DPC_LINE1_DP C173 C0.1U16X0402 DPC_LINE1_DP
R311 Q107 R943

D
X_1KR/4 G X_0R0402
SW_DPC_LINE1_DN C166 C0.1U16X0402 DPC_LINE1_DN S
N-2N7002_SOT23
DP_AUX_DP
DP_AUX_DP 15
SW_DPC_LINE2_DP C164 C0.1U16X0402 DPC_LINE2_DP DPC_AUX_DN_C
R312 Q108
D
X_1KR/4 G R944
N-2N7002_SOT23
SW_DPC_LINE2_DN C162 C0.1U16X0402 DPC_LINE2_DN S X_0R0402
DP_AUX_DN
+12V DP_AUX_DN 15
SW_DPC_LINE3_DP C161 C0.1U16X0402 DPC_LINE3_DP DPC_HPD
R314 Q109
D
X_1KR/4 R939 G R940
SW_DPC_LINE3_DN C155 C0.1U16X0402 DPC_LINE3_DN 100KR0402 S X_0R0402
N-2N7002_SOT23
HPD_DP
VCC3 HPD_DP 15
C337 C0.1U16X0402
DPC_AUX_DP DPC_AUX_DP_C Q106
D
B G B
C336 C0.1U16X0402 S
DPC_AUX_DN DPC_AUX_DN_C N-2N7002_SOT23
R937
10KR0402 R938
R285 R284
100KR/2 100KR/2 Q105 4.7KR0402
D
G
S
N-2N7002_SOT23
VCC3 Q104
D
COMM_EN G
15,30 COMM_EN
S
PESW_1.8V C472 C0.1u16X0402-2 PESW_1.8V C478 C0.1u16X0402-2 N-2N7002_SOT23
PESW_1.8V C473 C0.1u16X0402-2 C480 C0.1u16X0402-2 R936

4
VCC5 U33 10KR0402

500mA C475 C0.1u16X0402-2 C481 C0.1u16X0402-2
ADJ/GND
4
3 VIN VOUT 2
C476 C0.1u16X0402-2 C396 C0.1u16X0402-2
C4.7u6.3X5
C0.1u16X0402-2
C469 C459 C477 C0.1u16X0402-2 C449 C0.1u16X0402-2

C456
C470
C4.7u6.3X5 C0.1u16X0402-2 AMS1117_SOT223-3 R455

1
240R1%0402 C405 C0.1u16X0402-2 C454 C0.1u16X0402-2

A A
REG_CTRL C452 C0.1u16X0402-2 C399 C0.1u16X0402-2
C453 C0.1u16X0402-2 C455 C0.1u16X0402-2

R457
100R1%0402 C398 C0.1u16X0402-2 C409 C0.1u16X0402-2 Title
<Title>
C397 C0.1u16X0402-2 C406 C0.1u16X0402-2
Custom<Doc> <RevCode

5 4 3 2 1
8 7 6 5 4 3 2 1
ATX CONNECTOR
C0.1U16Y0402
C232
25
VCC5_SB ATX1 VCC3 VCC5
13 1
25
VCC3 3.3V 3.3V VCC3
1 2 1 2
14 2 3 4 RN38 3 4 RN40
-12V -12V 3.3V
R188 C346 5 6 X_8P4R-10R 5 6 X_8P4R-10R
D 10KR0402 C253 C0.1U16Y0402 D
15 GND GND 3 7 8 7 8
C0.1U16Y0402 1 2 1 2
R187 0R0402 16 4 3 4 RN39 3 4 RN41
25,26 ATX_PSON# P_ON 5V VCC5 VCC5 5 6 X_8P4R-10R 5 6 X_8P4R-10R
17 GND GND 5 7 8 7 8
C265 C257
18 6 C0.1U16Y0402 VCC5_SB R307 X_1KR0402 VCC5_SB R549 X_1KR0402
X_C1000P50X0402 GND 5V R195
19 7 4.7KR0402 G2 D2 G2 D2
GND GND
S2 S2
20 8 VCC_DDR R547 X_1KR0402 G1 D1 VCC_DDR R548 X_1KR0402 G1 D1
-5V POK ATX_PWROK 26,27
S1 S1
VCC5 21 9 C289 C799 Q69 C800 Q70
5V 5VSB VCC5_SB
C1000P50X0402
22 10 X_C0.1U16Y0402 X_NN-2N7002DW-7-F_SOT363-6-RH X_C0.1U16Y0402 X_NN-2N7002DW-7-F_SOT363-6-RH
5V +12V +12V
C273
23 11 C322 C294
C0.1U16Y0402 5V +12V D02-0390479-D07 D02-0390479-D07
24 12 C0.1U16Y0402 D02-0390479-O05 D02-0390479-O06
GND 3.3V C0.1U16Y0402
PWRCONN24P_WHITE-1
VCC3
C231
C C
C0.1U16Y0402
NEC Front Panel Connector POWER LED

VCC5_SB
Modify 0829 SUSLED
C647 R516 300R
C
VCC3_SB X_C0.1U16Y0402
JFP1
POWER BUTTON C628 B
Q68
R514 4.7KR0402 SUS_LED
SUS_LED 25
R499 330R N-MMBT3904_NL_SOT23
E
HDD+ 1 2 PWR_LED VCC5_SB
VCC5 HDD+ PLED PWR_LED 25
HDD- 3 4 SUS_LED X_C0.1U16Y0402 VCC5_SB
HDD- SLED SUS_LED 25
R320 PWRLED
4.7KR0402 RESET- 5 6 PWRSW+ R475 R515 300R
C
RESET- PWSW+ R476 8.2KR0402
B R479 33R/4 RESET+ 7 8PWRSW- 33R0402 C627 B R513 4.7KR0402 PWR_LED B
12,18,26 FP_RST# RESET+ PWSW- PWR_LED 25
PWRSW+ Q67
PSIN 25
C661 9 N-MMBT3904_NL_SOT23
E
R500 NC R490 C626
X_C0.1U16Y0402 300R
0R/4 HEADER,2*5(10)_Black C0.1U16Y0402 X_C0.1U16Y0402
D50 R489 X_4.7KR0402

VCC3
S-BAT54A_SOT23
Y SATA_LED#
SATA_LED# 19
HDD- Z
X
D24 VCC5
BUZZER BAS32L_LL34
R467 220R 1
R465 220R SPK1 2
BZ1
C
BUZZER-RH
A R468 10KR0402 B A
18 SPKR
C612
C0.1U16Y0402
E

Title
Q62 ATX & FRONT PANEL
N-MMBT3904_NL_SOT23
B VL390 0A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
HEAT SINK
U14_X1 U23_X1
9
1
9
1
9
1
9
1
XX1 XX1 XX1 XX1 MH1 MH2 MH3 MH4
D D
7 2 7 2 7 2 7 2
6 3 6 3 6 3 6 3
X_MH001 X_MH001 X_MH001 X_MH001
4
XX2 XX2 XX2 XX2
9
1
9
1
9
1
9
1
MH5 MH6 MH7 MH8
NB_HEATSINK SB_HEATSINK 7 2 7 2 7 2 7 2
6 3 6 3 6 3 6 3
X_MH001 X_MH001 X_MH001 X_MH001
4
MANUAL PART Simulation
C C
AVL: X_JS1
D06-0100161-F52
D06-0100101-P01 VCC5
SIM1
X_PIN1*2
BAT1_X1
BAT-BCR2032P-RH
X_JS2
SIM2
PCB1
P30-073890A-E48 X_PIN1*2
P30-073890A-G37
P30-073890B-E48
P30-073890B-G37
P30-073890C-E48
P30-073890C-G37
P30-0737711-E48
B B
Optics Orientation Holes
FM16 FM2 FM12 FM8
X_FM120 X_FM120 X_FM100 X_FM100

FM1 FM15 FM9 FM11
X_FM120 X_FM120 X_FM100 X_FM100

FM18 FM17 FM5 FM14
A A
X_FM120 X_FM120 X_FM100 X_FM100

FM19 FM20 FM3 FM10 MICRO-START INT'L CO.,LTD.
Title
Auto BOM Mnaual
X_FM120 X_FM120 X_FM100 X_FM100 Size Document Number Rev
B VL390 0A
8 7 6 5 4 3 2 1
5 4 3 2 1
MODIFY HISTORY
1,(page 7,8,9)change to AM3 socket :(Have to apply AM3 library and footprint)
(1) add pin B2 as NP/RSVD
(2) change pin F3 from RSVD to M_VDDIO_PWRGD
(3) change pin W30 from RSVD to MA_EVENT#
(4) change pin V29 from RSVD to MB_EVENT#
(5) change pin A12,B12,C12,D12,AG12,AH12,AJ12,AK12,AL12 from VTT to VDDR
(6) change pin H20, AE7 to NP/VSS
AM3 (7) remove pin H3, H4, H21, H22, AD18, AD19, AE8, AE9
(8) change pin F2 from PLATFORM_TYPE to RSVD
2,(page 7)
PWROK(Pin C9) (1) CPU_CORE_TYPE PU reister change to 1KR refer to CRB
(2) Reserve R567 300R to cnnetct TEST22 to GND
D (3) Reserve R240,R247,R249,R281,R294 HDT PU resisters D
(4) Reserve C801,C802,C803

(5) Reserve R442,R599 for RS740 HT1.0
AM3
3,(page 8,9) change to DDR3
(1) W26,W25 change to MEM_MA1_CLK0;U24,V24 change to MEM_MA0_CLK1 LDT_RST#
RESET_L(Pin C7)
(2) Y31,Y30 change to MEM_MB1_CLK0;V31,W31 change to MEM_MB0_CLK1
(3) AE27 change to MEM_MA1_ODT1;AE28 change to MEM_MA0_ODT1
(4) AG31 change to MEM_MB1_ODT1;AF31 change to MEM_MB0_ODT1
(5) E20 change to MEM_MA_RESET#; B19 change to MEM_MB_RESET#
RS780 (6) Reserve MEM_MA_DQS_8 , MEM_MA_DM8 and MEM_MB_DQS_8,MEM_MB_DM8
POWERGOOD(Pin A10) NB_PWRGD 4,(page 10,11,) change to DDR3

(1) Placement A0,B0,A1,B1
(2) DIMM1,DIMM3 PN:N13-2400421-L06(Blue);DIMM2,DIMM4 PN:N13-2400631-F02 (GREEN)
5,(pag 6) Modify VRM_EN circuit;Reserve LDT_PWRGD to VRM_PWROK,VID_SEL circuit;Add C587
6,(page 12) Remove the termination resisters and decouping caps
LDT_PG(Pin F22) LDT_PWRGD
7,(page 13) R196,R197 change to 301R1%;Reserve R436,R443 for RS740
7,(page 14) Lan TX/RX pairs connect to GPP3 to co-lay RS740 RS780
SB700 8,(page 15) SYSRESETb(Pin D8) NB_RST#_L
(1) ball B8 is RS780 (DDC_DATA0) and RS740 (BMREQ#),
PE_NB_RST#
PWR_BTN#(Pin H2)
SLP_S3#(Pin F5) PWR_GD#(Pin H1) SB_PWRGD
ball A8 as it is used as DDC_CLK0 for RS780 and DDC_DATA for RS740
(2) Reserve LDT_RST#,LDT_STOP# level-shift circuit for RS740;
LDT_RST#
Reserve R570,R571,R159,to Patch the timing of SYSRESET# & LDT_RST#
& LDT_STOP# (Errata:ER_RS780B6 ERN # RS780-024))
(3) Add R472 and power rail VDDG_NB;R305 change to 1KR PE_NB_RST#
(4) Reserce L52 to pin7,D7 for RS740;Remove CP20
*
(5) Leave empty R275,R283,R251 for RS740 only NB_RST# circuit
(6) Add L42,C797;leave empty R246 PCIE 16X slot A_RST#(Pin N2) LDT_RST#(Pin G24)
C (7)modify the I2C_CLK/I2C_DATA,SDA0_AUX0P/SCL0_AUX0N Pull-up and level shift topology PCIE 1X slot 1 C
SLP_S3# SUSB#(Pin 71) (8) COMM_EN connect to Pin F9 PCIE 1X slot 2
PCIE LAN
SB_PWRON# PWRON# (Pin72) 9,(page 16) PCIE 1394
(1) For RS780 without Side-port:For VDDMEMNB stuff R723=0R and leave the LC filter empty;
SB700
(2) Reserve CP29,R529 for RS740 co-lay PCIRST#(Pin N1) PCI Slot 1
(3) Stuff D38,R144 for POWER UP SEQUENCE KBRST#(Pin W15) Super IO
(4) Remove VDDMEMNB LC filers,remove R529,C326 with no side-port memory Super IO TPM
ATX1 (5) Remove CP8,L18 and short NB_VCC1P1 to SB VDDC pins SYS_RESET#(Pin J2)
PSON# (Pin76) PS_ON# 10,(page 17)

Pin16 (1) Reserve cystal circuit(Y6,C817,C818,R572) for A14 to solve the system time lag issue;
PANSWH# (Pin75)
(2) Modify A_RST# topology:add R441,R587,R590,R591,R592,R593
ATX_PWROK U2 (UP7501) 5VDIMM (3) Remove R432,R442,C575,C556,C570(PCI_CLK1 & CK_P_33M_1394)
Pin8 U4 (UP7707) VDDA_25 (4) Reserve PGNT#1,PGNT#2 as TP
11,(pag 18)
CLOCK GEN FP_RST#
(1) USB OC[0::6]# PU RN11,R574; * F_PANEL1
PSIN F_PANEL1
(2) Pin D3 RSMRST# connect to SIO Pin 85; (Reserve:remove R412,stuff R413=22KR,C547=2.2uF
to meet timing requirement);
(3) KRRST# PU resister R382 change to 1KR;Reserve R655(ITE suggest)
(4) Add R117;Reserve R212,R655
SYS_PWRGD Circuit
UP6264 12,(pag 19) Reserve C574;SPI rom change to M31-25X1613-W03
+1.8V_S0 MEANS OPTION
VRM_GD VCC_1V2 12,(pag 20) Modify the SB power rail from VCC_1V2 to VCC_SB_1V2 *
ATX_PWROK VDDPWRGD(Pin 37) SYSTEM POWER REF. +1.2VSB
VDDA_25 VCORE_EN 13,(page 22)
VCC_DDR EN(Pin 24) VCC_DDR (1) Change termination R on RED channel R158,R503 to 140R follow AN_RS780G1(For A13)
VRM U1 ISL6323 NB_VCC1P1
NB_PWRGD
(2) add R179,R221,leave R108,R126,Q11,Q12 empty ,R122,R130 change to 4.7KR;
PWROK(Pin 34) (For RS 780 level shifter not requried )
(3) the VGA1 PN change from N51-15F0391-F02 to N51-15F0391-A10(the pin is same but outside of board different)
LDT_PWRGD# (4) leave empty Q8,Q13,C95 for RS740 only and R104,R128 change to 4.7KR
* (5) Add Q59,Leave empty D2,reserve R203,R81 change to10KR,R85 change to 200KR
B
(6) Leave shunt R empty R204,R201,R215,R218,R538,R540,R539 B
14,(pag 23) Clock Gen change to SLG8LP625
15,(pag 24) Remove LPT1 circuit;SATA4 change to black N5N-07M0221-H06 for e-SATA
ATX_PWROK NB_PWRGD
NB_VCC1P1 SYS_PWRGD 16,(pag 25) LAN change to Broadcom BCM5784/5764/5906(all co-lay),defualt 5906 M
FP_RST#
SLP_S3# SB_PWRGD 17,(pag 26) Super IO change to IT8720;Floppy leave empty default;COM1 header change to Rear COM port SB700 CPU_SIC/CPU_SID
DIMM1,2,3,4
18,(pag 27) The ACPI solution change to UPI;System power generater circuit;the NB,SB PWRGD sequence VCC3 PU SCLK UP6264
WD_PWRGD SDATA CLOCK Gen
* 19,(pag 28) The VCC_DDR (PWM)and NB_VCC1P1 (Linear) circuit;CPU_VDDR(1.2V) generater Asset ID Chipset
20,(pag 29) Remove the CD-IN header;ADD SPIDIF OUT header

PCIE 16X
21,(pag 30) PCIE 1X
(1) USB power regulater modify to UP7533; VCC3_SB PU SCLK1 PCI
ACTIVE SDATA1 TPM
(2) Stuff Common choke L12-181D017-CA8 and L12-900D017-CA8
22,(pag 31) ADD PCIE1_X2 Slot;Reserve R579,R581 for RS740
ENABLE
23,(pag 32) Remove PCI2 slot ;Add PREQ#2 PU R528
PWROK 24,(pag 34) Remove U20 circuit;Add D36 and leave R478 empty
metal_VID metal_VID 24,(pag 35) NB heatsink change to HS_43_44X31_24
V_SVI
VDD&VDDNB
NOTICE
PWRGD
3,(page 18)
Configer GPIO5 to output mode or internal PU/PD can Leave R377 empty ;??
R360,R367 can leave empty
VCC 4,(page 17,22)
A A
(1) PCICLK5/GPIO41 power up default&enabled register changed between A11 and A12
1.5V
(2) LPC_CLK0&AZ_RST# the straps for the PCI ROM BOOT and IMC enable should be verified
6ms 15~30 ms
5,(page 23) Make sure NB&SB PCIE PHY 100M REF CLOCK from the SRC PLLs rather than SB_SRC PLL
EN Follow APnote PA_RS7X0A2
3ms 3ms
0.9V
6ms 6ms
1.2V 10 ms 10 ms MICRO-START INT'L CO.,LTD.

6ms 6ms Title
BOM HISTORY
1, No AM3 socket PN,in the sche use AM2 PN N12-9400040-F02 Size Document Number Rev
Custom VL390 0A
2, CHIPSET: RS780 Ver A13PN. B01-RS78085-A08 ㄛSB700 Ver A12 PN. B01-SB70035-A082
5 4 3 2 1
5 4 3 2 1
BOM
For AMD check
6R165,R534,R564l eave empty

9stuff
C713,C706,C688,C704,C694,C680,C703,C691,C711,C696,C682,C72,C81,C108,C110,C702,C684,C714,C210,C132,C712,C768,C50,C252,C57,C66,C236,C249
Add C239,C241,C819,C243,C261,C246,C104,C105,C723
remove C242,C244
16stuff C307,C309,C311,C316,C797L29,L31,L22,L42
12Add 369L19,L20L21,L25
1, page 22 D9,D10,D11 placed close to CRT connector;
Stuff U7,U8 and leave emtpy R142,R148
D remve RX780 parts D
6,reserve Q9
17,remove Q58,Q60,Q61,R466,R464,R408,C546
31,modify all the PU to 8.2KR to VCC3;leave empty PREQ#[0:5] PU R
17~19,Remove Reserved R378,R383,R506,R507,R508,R509,R401
18,remove R117,R385 duplicate with R638,R642

Remove WAKE ON LAN Circuit
15,remove VDDG_NB power(R472,R479) and use VCC3,remove R301,R246,R241,R298,R217
23,remove W83391TG,RN8,FS1
25,Modify SYS_TEM to VR_TEMP_DA(remove RT1,R35,C11 chagne to 2200pF)

Remove BIOS WRITE PROTECT Circuit
15,remove DISPLAY PORT
9,Modify CPU_VDDIO_PWRGD
7,VDDIO_FB R163 connect to DDR_FB
12,clock generator should not be enable before VCC_1V2 is ready.
25, Add AMDTSI circuit
C C
B B
VCC
A A
EN

Title
HISTORY
Custom VL390 0A
5 4 3 2 1

Vl390 For Ubtx: Clock Gen SLG8LP625

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Vl390 For Ubtx: Clock Gen SLG8LP625

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1

VL390 FOR uBTX CPU:

SATA/KB/ FAN Control 23

Project RS-780 BLOCK DIAGRAM

DDRIII 800~1333 UNBUFFERED UNBUFFERED

AM3 SOCKET DDRIII 800~1333 UNBUFFERED UNBUFFERED

4X1 PCIE INTERFACE

USB-5 USB-4 USB-3 USB-2 USB-1 USB-0 HD AUDIO HDR 29

CPU CORE POWER

CPU VLDT Power

DDR3 DRAM POWER

SB700/710 GPIO Config SIO IT8720 GPIO Config

MICRO-START INT'L CO.,LTD.

2 PAIR MEM CLK

2 PAIR MEM CLK

2 PAIR MEM CLK

AMD SB PCI CLK2

NB ALINK PCIE CLK PCIE_RCLK/ PCI CLK5

SB ALINK PCIE CLK

PCIE GFX CLK SLT_GFX_CLK

PCIE GPP CLK

External clock mode

MICRO-START INT'L CO.,LTD.

Power Deliver Chart

AMD AM2r2 CPU

ATA PLL 0.01A

VCC3_SB (S0, S1, S3, S5) PCI-E PVDD 80mA

USB CORE I/O 0.2A

+3.3V (S0, S1) 0.01A

+5V (S0, S1) 0.1A

MICRO-START INT'L CO.,LTD.

Intersil 6323 3 Phase

ISEN_NB U_G3 R176 1R0805 D

R62 C53 2.2R1%0805 C0.1U25X N-NTD4809NT4G_DPAK3-RH CH-0.25u40A0.65m-RH

TP125 VCC5 MICRO-START INT'L CO.,LTD.

LDT_STOP# C801 X_C180p50N0402

VCC3 VCC_DDR VCC_DDR

20KR1%0402 G2 D2 R178 0R0402

10,11 MEM_MA_DQS_H[7..0] 10,11 MEM_MB_DQS_L[7..0]

10,11 MEM_MA_DM[7..0] 10,11 MEM_MB_DQS_H[7..0]

10,11 MEM_MA_CHECK[7..0] 10,11 MEM_MB_DM[7..0]

Add For ECC 0829 Add For ECC 0829

MICRO-START INT'L CO.,LTD.

CPU AM2 PWR & GND

CPU_VDDIO_PWRGD generater circuit

C50 C224 C716 C246 C287 C267 C65 C130

.CD1000U6.3EL11.5 TP129 VCCP

C0.22U16X C0.01U16X0402 C4.7U10Y0805 C4.7U10Y0805 TP130 VCC_1V2

C708 C2.2u10Y-RH MICRO-START INT'L CO.,LTD.

8,11 MEM_MA_DQS_H[7..0] VTT_DDR 8,11 MEM_MB_DQS_H[7..0] VTT_DDR

DQ63 MEM_MA0_ODT0 DQ63 MEM_MB0_ODT0

Place close to DIMM3 DDRIII-240P_BLUE-RH DDRIII-240P_BLANK-RH

A Place close to DIMM3 A

with DIMM4 DIMM3(CHANNEL-A A1) DIMM2(CHANNEL-B B1)

L25 15 MILS WIDTH U15

10 9 LAN_CLK_R R504 0R0402 LAN_CLK 24

clock generator should not be enable before

R664 10KR0402 B REF_0/SEL_HTT66 (Pin51) HTT_0/66M_0 & HTT_0#/66M_1 (Pin 46,47)

RS780-HT LINK I/F

HYPER TRANSPORT CPU I/F

7 HT_CTLOUT_H0 M22 HT_RXCTL0P HT_TXCTL0P M24 HT_CTLIN_H0 7

RX780/RS740/RS780 difference table (HT LINK)

HT_RXCALP 49.9R (GND)