(1)Consider the 2-bit multiplexer (MUX) shown in the figure.

For OUTPUT to be the XOR of C

and D, the values for A0, A1, A2 and A3 are ?

(2)The Boolean expression F implemented by the circuit i

(3) A four-variable Boolean function is realized using 4 × 1 multiplexers as shown in the figure

The minimized expression for F(U, V, W, X) is

(4) Signals A,B,C,D and D(bar) are available. Using a single 8 - to - 1 multiplexer and no other
gate, implement the Boolean function.
f ( A , B , C , D , D)=BC+AB D + A C D

(5) A ROM is to be used to implement the Boolean functions given below:

F1(A,B,C,D)=ABCD+ A BC D

F1(A,B,C,D)=(A+B)+( A¿+ B+C)¿

F1(A,B,C,D)=∑ 3,5 , +∑ 13,15

(a) What is the minimum size of the ROM required?

(b) Determine the data in each location of the ROM

(6)In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays.
The present input condition is: P = Q = "0‟. If the input condition is changed simultaneously to P
= Q = "1", the outputs X and Y are

7) for the circuit shown, the clock frequency is f0 and the duty cycle is 25%. For the signal at the
Q output of the Flip-Flop, 
(8) A 4-bit shift register circuit configured for right-shift operation is Din→A,A→B,B→C,C→D, is
shown. If the present state of the shift register is ABCD = 1101, the number of clock cycles
required to reach the state ABCD = 1111 is

(9) A sequence generator is shown in figure. The counter status (Q0 Q1 Q3) is intialized to 010
using preset/clear inputs.
The Clock has a period of 50ns and transitions take place at the rising clock edge.
(a) Give the sequence generated at Q0 till it repeats.
(b) What is the repetition rate for the generated sequence?
(10)all FF conversions