6.

The output F of the multiplexer circuit shown in the given figure can be
represented by

A. AB + BC + CA + BC

B. A ⊕ B ⊕ C

C. A ⊕ B

D. ABC + AB C + A BC

Correct Option: D

7. The output ƒ of the 4-to-1 MUX shown in the given figure is

 A. xy + x

B. x + y

C. x + y

D. xy + x

Correct Option: B

8. In time division multiplexing

A. time is doubled between bits of a byte

 B. time slicing at CPU level takes place

C. total time available in the channel is divided bet ween sever al user s
and each user s is allotted a time slice

D. none of these

Correct Option: C

9. The logic realized by the circuit shown in the figure below, is

A. F = A ⊙ C

B. F = A ⊕ C

C. F = B ⊙ C
 D. F = B ⊕ C
Correct Option: B
F=ABC+ABC+ABC
= A C (B + B) + A C (B + B)
=AC+AC
=A⊕C

10. Digital multiplexer is basically a combinational logic circuit to

perform the operation

A. AND – AND

B. OR – OR

C. AND – OR

D. OR – AND
 Correct Option: C

11. The combinational logic circuit shown in the given figure has an
output Q which is

A. A B C

B. A + B + C

C. A ⊕ B ⊕ C

D. A ⊙ B ⊙ C

Correct Option: B

From the K-map,

Q=A+B+C
 12. The mod-number of the asynchronous counter shown in the figure
is

1.
A. 24

B. 48

C. 25

D. 36

Correct Option: A

It is a 5 bit ripple counter. At 11000, output of NAND gate is LOW. This will clear all FF. So it is
a Mod – 24 counter.
Note that when 11000 occur, the CLR input is activated and all FF are immediately cleared. So
it is a MOD 24 counter not MOD 25.
 13. The circuit shown in the figure converts

1.
A. BCD to binary code

B. Binary to excess – 3 code

C. Excess – 3 to Gray code

D. Gray to Binary code

Correct Option: A

All BCD combination can be convert into binary code except 1000 & 1001. Hence best possible
answer is (a).

14. The circuit shown in the figure given below Output

 A. is an oscillating circuit and its output is a square wave

B. is one whose output remains stable in ‘1’ state

C. is one having output semains stable ‘0’ state

D. having a single pulse of 3 times propagation delay

Correct Option: A

15. How many gates (minimum) are needed for a 3-bit up-counter
using standard binary and using T flip-flops? Assume unlimited fan-in.

A. 4

B. 3

C. 2
 D. 1

Correct Option: C

NA

2. Schmitt trigger is shown in the figure. The upper and lower threshold
voltage-are-respectively

A. 2 V, – 4 V

B. 2 V, – 2 V

C. 4 V, – 4 V

D. 4 V, – 2 V

Correct Option: C

Upper crossover voltage when V0 = + 10 V At upper threshold point

 5 5 20
(10) = (2) + VTL
5 + 20 10 + 20 10 + 20

2 2
⇒ VTH = 2 - ⇒ VTH = 2V
3 3

Lower crossover voltage when V0 = – 10 V

5 10 20
(-10) = (2) = VTL
5 + 20 10 + 20 10 + 20

⇒ VTL = – 4V

2. A retrigger able moonshot is one which

A. can be triggered only once

B. has two quasi-stable states

C. cannot be triggered until full pulse has been

D. is capable of being triggered while the output is being

Correct Option: D

NA
 3. The 8-to-1 multiplexer shown in the figure, realize which of the
following Boolean expression?

1.
A. wxz + wxz + wyz + xyz

B. wxz + wyz + wyz + wxy

C. wxz + wyz + wyz + wxz

D. MUX is not enable

Correct Option: C

Let z = 0
Then ƒ = wxy + wxy + wxy + wxy = wx + wy
If we put z = 0 in given option, then
(a) = wx + xy (b) = wy + wxy (c) = wx + wy
Since MUX is enable.
 4. The output of the 4 × 1 multiplexer shown in the figure, is

1.
A. X + Y

B. X + Y

C. XY + X

D. XY

Correct Option: A

Z = XY + XY + XY,
Z=X+Y
3. A sequential multiplexer is connected as shown in the figure. Each time
the multiplexer receivers the clock, it switches to the next cannel (from 6
it goes to 1) if input signals are

A.5 cos (2π (4 × 10³t)

B. 2 cos 2π (3.8 × 10³t)

C. 6 cos 2π (2.2 × 10³t)

D. 4 cos 2π (17 × 10³t)

Correct Option: D

NA

Copyright 2018 InterviewMania.com - All rights reserved.

21. A pulse train with a frequency of 1 MHz is counted using a modulo

1024 ripple-counter built with J-K flip-flops. For proper operation of the
counter the maximum permissible propagation delay per flip-flop stage
is
 A. 100 n sec

B. 50 n sec

C. 20 n sec

D. 10 n sec

Correct Option: A

Maximum frequency of 1 MHz corresponds to minimum time = 1/1 × 10 6 = 1 microsecond = 100

nanoseconds.

22. For a flip-flop formed from two NAND gates as shown in the given
figure, the unusable state corresponds to

1.
A. X = 0, Y = 0

B. X = 0, Y = 1
 C. X = 1, Y = 0

D. X = 1, Y = 1

Correct Option: A

NA

23. In a sequential circuit, the outputs at any instant of time depends

A. only on the inputs present at that instant of time

B. on past outputs as well as present inputs

C. only on the past inputs

D. only on the present outputs

Correct Option: B

NA

24. Meta stability in D-Flip Flop occurs when

A. set up time of input data is not met

 B. clock period is too large

C. set and reset are active simultaneously

D. D and Q pins are shortened.

Correct Option: A

NA

25. A 4– bit modulo– 16 ripple counter used JK flipflop. If progression

delay of each FF is 50 ms, then maximum clock frequency is equal to

A. 20 MHz

B. 10 MHz

C. 5 MHz

D. 4 MHz

Correct Option: C

1 1
ƒmax = =
N:Td 4 × 50 × 10-12
= 5 MHZ.

26. A switch-tail ring counter is made by using a single D-FF. The

resulting circuit is

A. SR flip-flop

B. JK flip-flop

C. D – FF

D. T – FF

Correct Option: D

In a switch– tail ring counter, using D-FF, the complementary output Q is connected to D input
for a single D-FF it becomes a T-FF.

27. A 4-bit-synchronous counter uses flip-flops with pr opagation

delay time of 25 ns each. The maximum possible time required for
change of state will be

A. 25 ns

B. 50 ns
 C. 75 ns

D. 100 ns

Correct Option: A

NA

28. The type of gate shown in the given figure is

A. OR

B. NOR

C. NAND

D. EX-OR
 E. EX-NOR

Correct Option: D

NA

29. The output of the circuit will be

A. ABCD + ABCD + ABCD + ABC D D

B. ABCD + ABCD + ABCD + ABCD

C. ABCD + ABCD + ABCD + ABCD

D. ABCD + ABCD + ABCD + ABCD

 Correct Option: D

NA

30. The following arrangement of master-slave flip flops has the initial
state
31. Of-P,-Q-as-0,-1respectively.

Clock After three clock cycles, the output state P, Q respectively are

A. 1,0

B. 1,1

C. 0,0

D. 0,1

Correct Option: A

NA
31. For the circuit shown in the figure below, what is the frequency of
the-output-Q?

A. Twice the input clock frequency

B. Half the input clock frequency

C. Same as the input clock frequency

D. Inverse of the propagation delay of the FF

Correct Option: B

NA

32. For the circuit shown in figure, output F = 0, when

 A. both ƒ2 and ƒ3 are 1

B. both ƒ2 and ƒ3 are 0

C. ƒ2 is 1 and ƒ3 is zero

D. ƒ2 is 1 and ƒ3 is one
Correct Option: A

NA

33. For the circuit shown in figure

A. F = A + B

B. F = AB

C. F = A + B
 D. F = AB

Correct Option: A

NA

34. Consider the following expressions

1. Y = ƒ (A, B, C, D) = ∑ (1, 2, 4, 7, 8, 11, 13, 14)
2. Y = ƒ (A, B, C, D) = ∑ (3, 5, 7, 10, 11, 12, 13, 14)
3. Y = ƒ (A, B, C, D) = ∑ (0, 3, 5, 6, 9, 10, 12, 15)
4. Y = ƒ (A, B, C, D) = ∑ (0, 1, 2, 4, 5, 8, 9, 15)
Which of these expressions are equivalent to the expression Y = A ⊕
B ⊕ C ⊕ D?

A. 2 and 3

B. 1 and 4

C. 2 and 4

D. 1 and 3

Correct Option: D

NA
35. A full-adder can be implemented with half-adders and OR gates.
A 4-bit parallel full adder without any initial carry requires

A.8 half-adders,4-OR gates

B. 8 half-adders, 3-OR gates

C. 7 half-adders, 4-OR gates

D. 7 half-adders, 3-OR gates

Correct Option: D

The circuit of a 4-bit full adder using half adders and OR gates is shown in the figure
From the figure, it is apparent that 4-bit full adder required seven half adders and 3-OR gates.
36. The figure given below shows the circuit of which one of the
following-is

A. Bi-stable multi-vibrator

B. Schmitt trigger

C. Mono-stable multi-vibrator

D. A Stable multi-vibrator

Correct Option: C

NA
37. Output Y of the circuit shown in the figure is

A. (A + B) C + DE

B. AB + C (D + E)

C. (A + B) C + D + E

D. (AB + C). DE

38. I n the given network of AND and OR gates, ƒ can be written as

 A. x0 x1 x2... xn + x1 x2... xn + x2 x3... xn .... xn

B. x0 x1 + x2 x3 +... + xn–1. xn

C. x0 + x1 + x2 +... + xn

D. x0 x1 x3... xn–1 + x2 x3 x5... xn – 1 +... + xn– 2 xn– 1 + xn

Correct Option: D

In terms of Boolean operations

Output of 1 is x0 x1
Output of 2 is (x0 x1 + x2)
Output of 3 is (x0 x1 + x2) x3 = x0 x1 x3 + x2 x3
Output of 4 is x0 x1 x3 + x2 x3 + x4
Output of 5 would be x0 x1 x3 x5 + x2 x3 x5 + x4 x5
Output of 6 would be x0 x1 x3 x5 + x2 x3 x5 + x4 x5 x6
Thus for n gates connected as shown, the output would be
 x0 x1 x3 ...................... xn– 1
+ x2 x3 x5 ...................... xn– 1
+ x4 x5 x7 ...................... xn– 1
+ xh – 2 xn– 1
+ xn .

39. A carry look ahead adder is frequently used for addition because
it

A. is faster

B. is more accurate

C. uses fewer gates

D. costs less

40. Output of the circuit shown in the figure is equal to

 A.0

B. 1

C. AB + AB

D. (A*B) * (A*B)

Correct Option: A

The gates are XNOR

F = (A ⊕ B) ⊕ (A ⊕ B) = (AB + AB) ⊕ (AB + AB)
= (AB + AB) ⊕ (A B + AB)
= (AB + AB) ⊕ (AB + AB)
=0