OCC Simulation Report.

1) Functional Mode.
Drivers-
scan_en=0;
capture_cycle_width[1:0]=2'bz;
scan_in=z;
fast_capture_mode=z;
test_mode=0;

Testbench-
`timescale 1ps / 1p
module tb_occ();
reg fast_clock;
reg scan_clk;
reg scan_enable_i;
reg test_mode;
reg fast_capture_mode;
reg [1:0] capture_cycle_width;
reg shift_only_mode;
reg scan_in;
wire scan_out;
wire clock_out;
tap_two_counter_edt_top_occ_core_tessent_occ d1 (
fast_clock , //i
scan_clk , //i
scan_enable_i , //i
test_mode , //i
fast_capture_mode , //i
capture_cycle_width , //i
shift_only_mode , //i
clock_out , //o
scan_in , //i
scan_out //o
);

initial
begin

scan_clk = 0;
fast_clock = 0;

// setting design in functional mode

scan_enable_i = 1'b0;
scan_in = 1'bz;
capture_cycle_width = 2'bz;
fast_capture_mode = 1'bz;
test_mode = 1'b0;
// shift_only_mode = 1'b1;
#100 $stop;
end
initial
begin
forever
#1 fast_clock = ~fast_clock;
end
initial
begin
forever
#5 scan_clk = ~scan_clk;
end
endmodule

Waveform-
2) Stuck At Mode.
Drivers-
1)Shift.
scan_en=1;
capture_cycle_width[1:0]=2'bz;
scan_in=enable;
fast_capture_mode=z;
test_mode=1;

2)Slow Capture.
scan_en=0;
capture_cycle_width[1:0]=2'bxx;
scan_in=z;
fast_capture_mode=0;
test_mode=1;

3)Shift.
scan_en=1;
capture_cycle_width[1:0]=2’bz;
scan_in=enable;
fast_capture_mode=z;
Test_mode=1;

Testbench-
`timescale 1ps / 1ps
module tb_occ_v2();
reg fast_clock;
reg scan_clk;
reg scan_enable_i;
reg test_mode;
reg fast_capture_mode;
reg [1:0] capture_cycle_width;
reg shift_only_mode;
reg scan_in;
wire scan_out;
wire clock_out;
tap_two_counter_edt_top_occ_core_tessent_occ d1 (
fast_clock , //i
scan_clk , //i
scan_enable_i , //i
test_mode , //i
fast_capture_mode , //i
capture_cycle_width , //i
shift_only_mode , //i
 clock_out , //o
scan_in , //i
scan_out //o
);
initial
begin
scan_clk = 0;
fast_clock = 0;
//Simulation for Stuck At Mode.
// setting design in shift
scan_enable_i = 1'b1;
scan_in = 1'b1;
capture_cycle_width = 2'bz;
fast_capture_mode = 1'bz;
test_mode = 1'b1;
// shift_only_mode = 1'b1;
#100
//setting design in Slow Capture
scan_enable_i = 1'b0;
scan_in = 1'bz;
capture_cycle_width = 2'bxx;
fast_capture_mode = 1'b0;
test_mode = 1'b1;
// shift_only_mode = 1'b1;
#100
// setting design in shift
scan_enable_i = 1'b1;
scan_in = 1'b1;
capture_cycle_width = 2'bz;
fast_capture_mode = 1'bz;
test_mode = 1'b1;
// shift_only_mode = 1'b1;

#100 $stop;
end

initial
begin
forever
#1 fast_clock = ~fast_clock;
end
initial
begin
forever
#5 scan_clk = ~scan_clk;
end
endmodule
Waveform-
3) At Speed Mode.
Drivers-
1) Shift
scan_en=1;
capture_cycle_width[1:0]=2’bz;
scan_in=enable;
fast_capture_mode=z;
Test_mode=1;

2) Fast Capture
scan_en=0;
capture_cycle_width[1:0]=2'bxx;
scan_in=z;
fast_capture_mode=1;
test_mode=1;

Testbench-
`timescale 1ps / 1ps
module tb_occ_v3();
reg fast_clock;
reg scan_clk;
reg scan_enable_i;
reg test_mode;
reg fast_capture_mode;
reg [1:0] capture_cycle_width;
reg shift_only_mode;
reg scan_in;
wire scan_out;
wire clock_out;
tap_two_counter_edt_top_occ_core_tessent_occ d1 (
fast_clock , //i
scan_clk , //i
scan_enable_i , //i
test_mode , //i
fast_capture_mode , //i
capture_cycle_width , //i
shift_only_mode , //i
clock_out , //o
scan_in , //i
scan_out //o
);

initial
begin

scan_clk = 0;
fast_clock = 0;
 //Simulation for At Speed Mode

// setting design in Shift

scan_enable_i = 1'b1;
scan_in = 1'b1;
capture_cycle_width = 2'bz;
fast_capture_mode = 1'bz;
test_mode = 1'b1;
// shift_only_mode = 1'b1;
#100
// setting design in Fast Capture
scan_enable_i = 1'b0;
scan_in = 1'bz;
capture_cycle_width = 2'b11;
fast_capture_mode = 1'b1;
test_mode = 1'b1;
// shift_only_mode = 1'b1;
#100 $stop
end
initial
begin
forever
#1 fast_clock = ~fast_clock;
end
initial
begin
forever
#5 scan_clk = ~scan_clk;
end
endmodule
Waveform-