Multicycle Path Between Two Clock Domains

Multicycle Path Between Two Clock
Domains
Products:
Tempus
Innovus Implementation System
Encounter Digital Implementation (EDI)
Encounter Timing System (ETS)
July 12, 2017

Multicycle Path Between Two Clock Domains
Copyright Statement
© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are
registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective
holders.
Learn more at Cadence Online Support - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 2
Table of Contents
Purpose ....................................................................................................................... 4
Multi-Cycle Paths Introduction ..................................................................................... 5
Clock edge movement in multicycle path..................................................................... 6
Defining Multicycle path for Single Clock Domain ....................................................... 7

CASE 1: No MCP: Setup multiplier - 1, Hold multiplier - 0 ....................................... 7
CASE 2: Setup multiplier - 4, Hold multiplier - Default ............................................. 8
CASE 3: Setup multiplier - 4, Hold multiplier - 3 ....................................................... 9
Defining Multicycle path for Slow clock domain to Fast clock domain ....................... 10
CASE 1: No MCP: Setup multiplier - 1, Hold multiplier - 0 ..................................... 10
CASE 2: Setup multiplier - 2, Hold multiplier - Default ........................................... 11
CASE 3: Setup multiplier - 2, Hold multiplier - 1 ..................................................... 11
CASE 4: Setup multiplier 2, Hold multiplier 1 ......................................................... 12
Defining Multicycle path for Fast clock domain to Slow clock domain ....................... 13
CASE 1: No MCP: Setup multiplier 1, Hold multiplier 0 .......................................... 13
CASE 2: Setup multiplier 2, Hold multiplier – Default ............................................. 14
CASE 3: Setup multiplier 2, Hold multiplier 1 ......................................................... 14
CASE 4: Different launching and capturing clock edge .......................................... 15
Support ...................................................................................................................... 17
Feedback ................................................................................................................... 17

Purpose
This document explains how to specify multicycle path exception between two clock
domains of different frequencies.

Multi-Cycle Paths Introduction

By default, all paths are considered as one cycle paths for setup and hold check
evaluation. The set_multicycle_path command lets you specify additional cycles for the
paths.
When set_multicycle_path is defined, following cycle adjusting rules will be applied:
For setup checks:
 The default launching and capturing clock edges are defined to be the pair of edges with the
smallest positive difference between the capturing clock edge and the launching clock edge. The
default active edges are the propagated versions of the clock edges, measured at the launch and
capture registers.
 By default, or if the -end option is specified, the setup multiplier specified with -setup option is
interpreted with respect to the capture clock, and it affects the capturing clock edge. Instead of
the default capturing clock edge, the edge which arrives (setup multiplier - 1) cycles later is used.
 If the -start option is specified, the setup multiplier specified with -setup option is interpreted with
respect to the launch clock, and it affects the launching clock edge. Instead of the default
launching clock edge, the edge which arrives (setup multiplier -1) cycles earlier is used.
For hold checks:
 For all paths affected by a set_multicycle_path command, the default hold edge pair is chosen by
considering two hold conditions with respect to the adjusted setup edge pair. If no setup
adjustments have been made, the default setup edges are used. The following two hold
conditions are checked, and the one with the least hold slack is chosen for hold check.
- Data triggered by the current launch clock cycle must not be latched by the previous capture
clock cycle. This condition defines a hold edge pair where the hold launching clock edge is
the same as the setup launching clock edge and the hold capturing edge is one clock cycle
earlier than the setup capturing clock edge.
- Data triggered by the next launch clock cycle must not be latched by the current capture
cycle. This condition defines a hold edge pair where the hold launching clock edge is one
cycle later than the setup launching clock edge, and the hold capturing clock edge is the
same as the setup capturing clock edge.
 By default, or if -start option is specified, the hold multiplier specified with -hold option is
interpreted with respect to the launch clock, and it affects the launching clock edge. Instead of
using the default launch edge, the launching edge which arrives hold multiplier cycles later is
used.
 If -end option is specified, the hold multiplier specified with –hold option is interpreted with
respect to the capture clock, and it affects the capturing clock edge. Instead of using the default
capturing clock edge, the capturing edge which arrives hold multiplier cycles earlier is used.
So, for setup check, you can either move the capturing clock edge forward or the launching clock edge
backward and for hold checks, you can either move the launching clock edge forward or the capturing
clock edge backward.

Clock edge movement in multicycle path

Launching Clock Edge Capturing Clock Edge
Setup Check  
Hold Check  
 Blue Color arrow is the default clock edge movement in setup and hold checks.
Above diagram shows how the check points for setup and hold checks are moved backward or forward
depending on the -start/-end option and number of cycles for that path.
By default, set_multicycle_path moves the capturing clock edge for setup check and the launching clock
edge for hold check. You can control the movement by using the -end and -start options of the
set_multicycle_path command.
For a single clock domain path, there is no need to specify -end or -start option. These options have no
effect in single clock domain path.
But for a clock domain crossing path, moving the launching clock edge forward by one cycle is not equal
to moving the capturing clock edge backward by one cycle. The different options give different results.
In this document:
Red color arrow in the clock waveform is launching -> capturing clock edge pair for setup check.
Red color dotted arrow in the clock waveform is ignored launching -> capturing clock edge pair for setup
check.
Blue color arrow in the clock waveform is launching -> capturing clock edge pair for hold check.
Blue color dotted arrow in the clock waveform is ignored launching -> capturing clock edge pair for hold
check.

Defining Multicycle path for Single Clock Domain

FF1 FF2
CK1 CK2
create_clock -name CK1 -period 2 -waveform { 0 1 } [get_ports {ck1}]

CASE 1: No MCP: Setup multiplier - 1, Hold multiplier - 0

set_multicycle_path -setup 1 -from CK1 -to CK2
set_multicycle_path -hold 0 -from CK1 -to CK2
CK1 0 1 2 3 4 5 6 7 8 9 10
S
CK2
0 1 2 3 4 5 6 7 8 9 10
Setup 1, Hold 0
In this case, setup check will be done between the launching edge in first cycle and capturing clock edge
in the next cycle. The hold check will be done in between the launching edge in first cycle and capturing
edge in the same cycle so that the data launched by the setup launching edge is not captured by the
previous capturing edge.
Setup Report:
Path 1: MET Setup Check with Pin F2/CK

Endpoint: F2/D (v) checked with leading edge of 'CK2'
Beginpoint: F1/Q (v) triggered by leading edge of 'CK1'
Other End Arrival Time 0.000
- Setup 0.121
+ Phase Shift 2.000
+ Cycle Adjustment 0.000
= Required Time 1.879
- Arrival Time 0.166
= Slack Time 1.713
Clock Rise Edge 0.000
+ Clock Network Latency (Ideal) 0.000
= Beginpoint Arrival Time 0.000

+---------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival | Required |
| | | | | Time | Time |
|----------+-------------+---------+-------+---------+----------|
| F1 | CK ^ | | | 0.000 | 1.713 |
| F1 | CK ^ -> Q v | DFFHQX1 | 0.107 | 0.107 | 1.820 |
| B2 | A v -> Y v | BUFX2 | 0.059 | 0.166 | 1.879 |
| F2 | D v | DFFHQX1 | 0.000 | 0.166 | 1.879 |
+---------------------------------------------------------------+
Hold Report:
Path 1: MET Hold Check with Pin F2/CK

Endpoint: F2/D (^) checked with leading edge of 'CK2'
Beginpoint: F1/Q (^) triggered by leading edge of 'CK1'
Other End Arrival Time 0.000
+ Hold -0.021
+ Phase Shift 0.000
- Cycle Adjustment 0.000
= Required Time -0.021
Arrival Time 0.168
Slack Time 0.189
Clock Rise Edge 0.000
+ Clock Network Latency (Ideal) 0.000
= Beginpoint Arrival Time 0.000
+---------------------------------------------------------------+
| Instance | Arc | Cell | Delay | Arrival | Required |
| | | | | Time | Time |
|----------+-------------+---------+-------+---------+----------|
| F1 | CK ^ | | | 0.000 | -0.189 |
| F1 | CK ^ -> Q ^ | DFFHQX1 | 0.120 | 0.120 | -0.069 |
| B2 | A ^ -> Y ^ | BUFX2 | 0.048 | 0.168 | -0.021 |
| F2 | D ^ | DFFHQX1 | 0.000 | 0.168 | -0.021 |
+---------------------------------------------------------------+
CASE 2: Setup multiplier - 4, Hold multiplier - Default

CK1 0 1 2 3 4 5 6 7 8 9 10
S
H
CK2
0 1 2 3 4 5 6 7 8 9 10
Setup 4, Hold Default
In this case, setup check will be done between the launching edge in first cycle and capturing edge after
four cycles. Changing the setup relationship implicitly changes the hold relationship as well because all
hold relationships are based on the valid setup relationships. The hold check can be done in between the
launching edge in first cycle and capturing edge after three cycles (previous to setup capturing edge) or in
between the launching edge in second cycle and capturing edge after three cycle (setup capturing edge).
From Setup Report:
+ Phase Shift 2.000

From Hold Report:
+ Phase Shift 0.000

- Cycle Adjustment -6.000
CASE 3: Setup multiplier - 4, Hold multiplier - 3

set_multicycle_path -hold 3 -from CK1 -to CK2
CK1 0 1 S 2 3 4 5 6 7 8 9 10
CK2
0 1 2 3 4 5 6 7 8 9 10
Setup 4, Hold 3
In this case, the setup check will be done between the launching edge in first cycle and capturing edge
after four cycles. The hold multiplier 3 specified with -hold will move the launch edge forward by three
clock cycles with respect to the default position (relative to the valid setup relationship) or capture edge
backward by three clock cycles with respect to the default position.
From Setup Report:
+ Phase Shift 2.000

From Hold Report:
+ Phase Shift 0.000

If you specify only setup multiplier and do not specify hold multiplier, tool by default assumes one clock
cycle before setup check for hold check as in CASE 2. This may not be the correct behavior for the
design. To get the desired behavior, you can move the hold check back towards the start of the multicycle
period by specifying hold multiplier = (setup multiplier -1) with ‘-hold’ option as in CASE 3.
In general, if your setup multiplier is X, use the multiplier of X-1 for hold:
set_multicycle_path -setup X -from CK1 -to CK2

set_multicycle_path -hold X-1 -from CK1 -to CK2

Defining Multicycle path for Slow clock domain to Fast

clock domain
FF1 FF2
CK1 (Slow Clock) CK2 (Fast Clock)

CASE 1: No MCP: Setup multiplier - 1, Hold multiplier - 0

set_multicycle_path 1 -setup -from CK1 -to CK2
set_multicycle_path 0 -hold -from CK1 -to CK2
CK1 0 1 2 3 4 5 6 7 8 9 10
S
H
CK2
0 1 2 3 4 5 6 7 8 9 10
No MCP: Setup 1, Hold 0
In this case, the closest capturing edge that occurs after the launching edge is selected for setup check.
Hence, 0 -> 2 edge pair is selected for setup check.
The closest capturing edge that occurs at or before the launching edge is selected for hold check. In this
case, the possible edge pairs are 0 -> 0 and 4 -> 2 and 0 -> 0 edge pair is selected for hold check.
From Setup Report:
+ Phase Shift 2.000

From Hold Report:
+ Phase Shift 0.000


CASE 2: Setup multiplier - 2, Hold multiplier - Default
CK1 0 1 2 3 4 5 6 7 8 9 10
H S
CK2
0 1 2 3 4 5 6 7 8 9 10
Setup 2 (-end), Default Hold
In this case, setup multiplier is set to 2 and hold multiplier is not specified. So the capturing clock edge is
moved forward (Using the default -end) for setup check. In this case even multicycle for the hold is not
specified, the hold check is updated upon the setup check. The default hold edge pair is chosen by
considering two hold conditions with respect to the adjusted setup edge pair. In this case, the possible
edge pairs are 0 -> 2 and 4 -> 4. The 0 -> 2 edge pair minimizes the hold slack and hence chosen for
hold check.
From Setup Report:
+ Phase Shift 2.000

From Hold Report:
+ Phase Shift 0.000

CASE 3: Setup multiplier - 2, Hold multiplier - 1

CK1 0 2 4 6 8 10
S H
CK2
0 1 2 3 4 5 6 7 8 9 10
Setup 2 (-end), Hold 1 (-start)

In this case, setup multiplier is set to 2 and hold multiplier is set to 1, so for hold check launch clock edge
(Using the default -start) is moved forward by one clock cycle.
This may not be a correct check. The correct hold check should be done at the first capturing clock edge
relative to first launching clock edge. Please see the next case to see the correct check.
From Setup Report:
+ Phase Shift 2.000

From Hold Report:
+ Phase Shift 0.000

CASE 4: Setup multiplier 2, Hold multiplier 1
set_multicycle_path 2 -setup -from CK1 -to CK2 -end

set_multicycle_path 1 -hold -from CK1 -to CK2 -end
CK1 0 2 4 6 8 10
S
H
CK2
0 1 2 3 4 5 6 7 8 9 10
Setup 2 (-end), Hold 1 (-end)
In this case, setup multiplier is set to 2 and hold multiplier is set to 1 relative to the capturing clock, CK2
(Using the -end option). So, the hold check is moved one clock backward relative to capturing clock,
CK2.
From Setup Report:
+ Phase Shift 2.000

From Hold Report:
+ Phase Shift 0.000

This is the correct check in this scenario.
In general, for defining multicycle path between slow clock to fast clock path, please use following:
set_multicycle_path X -setup -from CK1 -to CK2 -end

set_multicycle_path X-1 -hold -from CK1 -to CK2 -end

Defining Multicycle path for Fast clock domain to Slow

clock domain
FF1 FF2
CK1 (Fast Clock) CK2 (Slow Clock)

CASE 1: No MCP: Setup multiplier 1, Hold multiplier 0

CK1 0 1 2 3 4 5 6 7 8 9 10
S H
CK2
0 2 4 6 8 10
No MCP: Setup 1, Hold 0
In this case, the closest capturing edge that occurs after the launching edge is selected for setup check.
Hence, 2 -> 4 pair is selected for setup check.
The closest capturing edge that occurs at or before the launching edge is selected for hold check. Hence,
0 -> 0 or 4 -> 4 pair is selected for hold check.
From Setup Report:
+ Phase Shift 2.000

From Hold Report:
+ Phase Shift 0.000


CASE 2: Setup multiplier 2, Hold multiplier – Default

set_multicycle_path 2 -setup -from CK1 -to CK2 -start
CK1 0 1 2 3 4 5 6 7 8 9 10
S H
CK2
0 2 4 6 8 10
Setup 2 (-start), Default Hold
In this case, setup multiplier is 2 relative to launch clock and hold multiplier is not defined. So the
launching clock edge is moved backward (Using the –start option) for setup check. In this case even
though the user is not writing the multicycle for the hold, the hold check is updated upon the setup check.
The default hold edge pair is chosen by considering two hold conditions with respect to the adjusted
setup edge pair. In this case, the possible edge pairs are 0 -> 0 and 2 -> 4. The 2 -> 4 edge pair
minimizes the hold slack and hence chosen for hold check.
From Setup Report:
+ Phase Shift 2.000

From Hold Report:
+ Phase Shift 0.000

CASE 3: Setup multiplier 2, Hold multiplier 1

set_multicycle_path 2 -setup -from ck1 -to ck2 -start
set_multicycle_path 1 -hold -from ck1 -to ck2 -start
CK1 0 1 2 3 4 5 6 7 8 9 10
S H
CK2
0 2 4 6 8 10
Setup 2 (-start), Hold 1 (-start)
In this case, setup multiplier is set to 2 relative to the launching clock edge (Using -start option), and the
hold multiplier is set to 1 relative to the launching clock edge (Using the default -start option). In this case
the hold check was moved one clock forward relative to launch clock, CK1.

From Setup Report:
+ Phase Shift 2.000

From Hold Report:
+ Phase Shift 0.000

This is the correct check in this scenario.
In general, for defining multicycle path between fast clock to slow clock path, please use following:
set_multicycle_path X -setup -from CK1 -to CK2 -start

set_multicycle_path X-1 -hold -from CK1 -to CK2 -start
CASE 4: Different launching and capturing clock edge

CK1 0 5 10 15 20 25 30
H
S
CK2
0 7 12 22 27 37
No MCP: Setup 1, Hold Default
In this case, the possible combination for launching - capturing edge pairs are 0 -> 7 and 20 -> 22 for
setup check. The closest capturing edge that occurs after the launching edge is selected for setup check.
Hence, 20 -> 22 pair are selected for setup check.
But, timer references the start of the launch/capture clock paths from the first relevant edge i.e. 0 for CK1
and 7 for CK2. To make the edge-to-edge relationship same as the 20 -> 22 pair, it has to subtract 5
from the capturing clock, which yields 0 -> 2, which from a magnitude standpoint is the same at the 20-
>22 time allotment. This subtracted value of 5 is reported as phase shift.
The possible combination for launching - capturing edge pairs are 10 -> 7 and 30 -> 22 for hold check.
The closest capturing edge that occurs at or before the launching edge is selected for hold check. Hence,
10 -> 7 pair are selected for hold check.
But, timer references the start of the launch/capture clock paths from the first relevant edge i.e. 0 for CK1
and 7 for CK2. To make the edge-to-edge relationship same as the 10 -> 7 pair, it has to subtract 10
from the capturing clock, which yields 0 -> -3, which from a magnitude standpoint is the same at the 10 -
> 7 time allotment. This subtracted value of 10 is reported as phase shift.

From Setup Report:
+ Phase Shift -5.000

From Hold Report:

set_multicycle_path 2 -setup -from CK1 -to CK2 -start

set_multicycle_path 1 -hold -from CK1 -to CK2 -start
CK1 0 5 10 15 20 25 30
S
CK2
0 7 12 22 27 37
Setup 2 (-start), Hold 1 (-start)
If you apply the above multicycles, the setup launching clock edge will move one clock backward. The
new adjusted setup edge pair will be 10 -> 22 from default setup edge pair of 20 -> 22. The default hold
edge pair is chosen by considering two hold conditions with respect to the adjusted setup edge pair. In
this case, the possible edge pairs are 10 -> 7 and 20 -> 22. The 10 -> 7 edge pair minimizes the hold
slack and hence is chosen for hold check. The hold launching clock edge will move one clock forward
relative to launch clock, CK1 and the adjusted hold edge pair 20 -> 7 is chosen for hold check.
From Setup Report:

From Hold Report:


Support
Cadence Online Support provides access to support resources, including an extensive
knowledge base, access to software updates for Cadence products, and the ability to
interact with Cadence Customer Support. Visit https://support.cadence.com.
Feedback
Email comments, questions, and suggestions to content_feedback@cadence.com.


Multicycle Path Between Two Clock Domains

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Multicycle Path Between Two Clock Domains

Uploaded by

Copyright:

Available Formats

Multicycle Path Between Two Clock

July 12, 2017

Learn more at Cadence Online Support - https://support.cadence.com

Multi-Cycle Paths Introduction ..................................................................................... 5

Clock edge movement in multicycle path..................................................................... 6

Defining Multicycle path for Single Clock Domain ....................................................... 7

Learn more at Cadence Online Support - https://support.cadence.com

Learn more at Cadence Online Support - https://support.cadence.com

Multi-Cycle Paths Introduction

When set_multicycle_path is defined, following cycle adjusting rules will be applied:

For setup checks:

For hold checks:

Learn more at Cadence Online Support - https://support.cadence.com

Clock edge movement in multicycle path

Learn more at Cadence Online Support - https://support.cadence.com

Defining Multicycle path for Single Clock Domain

create_clock -name CK1 -period 2 -waveform { 0 1 } [get_ports {ck1}]

CASE 1: No MCP: Setup multiplier - 1, Hold multiplier - 0

Path 1: MET Setup Check with Pin F2/CK

Learn more at Cadence Online Support - https://support.cadence.com

Path 1: MET Hold Check with Pin F2/CK

CASE 2: Setup multiplier - 4, Hold multiplier - Default

From Setup Report:

+ Phase Shift 2.000

From Hold Report:

+ Phase Shift 0.000

CASE 3: Setup multiplier - 4, Hold multiplier - 3

From Setup Report:

+ Phase Shift 2.000

From Hold Report:

+ Phase Shift 0.000

set_multicycle_path -setup X -from CK1 -to CK2

Learn more at Cadence Online Support - https://support.cadence.com

Defining Multicycle path for Slow clock domain to Fast

CK1 (Slow Clock) CK2 (Fast Clock)

create_clock -name CK1 -period 4 -waveform { 0 2 } [get_ports {ck1}]

CASE 1: No MCP: Setup multiplier - 1, Hold multiplier - 0

From Setup Report:

+ Phase Shift 2.000

From Hold Report:

+ Phase Shift 0.000

Learn more at Cadence Online Support - https://support.cadence.com

CASE 2: Setup multiplier - 2, Hold multiplier - Default

set_multicycle_path 2 -setup -from CK1 -to CK2

From Setup Report:

+ Phase Shift 2.000

From Hold Report:

+ Phase Shift 0.000

CASE 3: Setup multiplier - 2, Hold multiplier - 1

set_multicycle_path 2 -setup -from CK1 -to CK2

Learn more at Cadence Online Support - https://support.cadence.com

From Setup Report:

+ Phase Shift 2.000

From Hold Report:

+ Phase Shift 0.000

CASE 4: Setup multiplier 2, Hold multiplier 1

set_multicycle_path 2 -setup -from CK1 -to CK2 -end

From Setup Report:

+ Phase Shift 2.000

From Hold Report:

+ Phase Shift 0.000

This is the correct check in this scenario.

set_multicycle_path X -setup -from CK1 -to CK2 -end