Conductivity of Silicon and MOSFET Basics

1.
The conductivity of the pure silicon is raised by:
a) Introducing Dopants (impurities)
b) Increasing Pressure
c) Decreasing Temperature
d) Deformation of Lattice
View Answer
Answer: a
: By introducing Dopants free charge carriers increase further increasing the conductivity of silicon.
2. The n-type semiconductor have _______ as majority carriers.
a) Holes
b) Negative ions
c) Electrons
d) Positive ions
View Answer
Answer: c
: In n-type semiconductor the majority charge carriers present are electrons.
3. The majority carriers of p-type semiconductor are:
a) Holes
b) Negative ions
c) Electrons
d) Positive ions
View Answer
Answer: a
: The majority charge carriers of n-type semiconductors are holes.
4. The n-MOS transistor is made up of:
a) N-type source, n-type drain and p-type bulk
b) N-type source, p-type drain and p-type bulk
c) P-type source, n-type drain and n-type bulk
d) P- type source, p-type drain and n-type bulk
View Answer
Answer: a
: n-MOS Transistor consists of n-type source, n-type drain and p-type bulk.
5. The correct representation of n-MOSFET is:
a) Representation of n-MOSFET - option a
b) Representation of n-MOSFET - option b
c) Representation of n-MOSFET - option c
d) None of the mentioned
View Answer
Answer: c
: This is the correct representation of n-MOSFET : Representation of n-MOSFET - option c
6. The correct representation of p-MOSFET is:
a) Representation of p-MOSFET - option a
b) Representation of p-MOSFET - option b
c) Representation of p-MOSFET - option c
d) Representation of p-MOSFET - option d
View Answer
Answer: b
: This is the correct representation of p-MOSFET: Representation of p-MOSFET - option b
7. The oxide layer formed in the MOSFET is:
a) Metal oxide
b) Silicon dioxide
c) Poly Silicon oxide
d) Oxides of Non metals
View Answer
Answer: b
: Silicon Dioxide (Commonly called as glass) is the insulating oxide layer formed in MOSFET.
8. The drain current is varied by:
a) Gate to source voltage
b) Gate current
c) Source Voltage

View Answer
Answer: a
: The Gate to Source voltage acts as input which varies the drain current.
9. The low voltage on the gate of p-MOSFET forms:
a) Channel of negative carriers
b) Channel is not formed
c) Channel is clipped
d) Channel of positive carriers
View Answer
Answer: d
: For a p-MOS low gate voltage forms a conducting channel of positive carriers.
10. The n-MOSFET is working as accumulation mode when:
a) Gate is applied with positive voltage
b) Gate is grounded
c) Gate is applied with negative voltage
d) Gate is connected to source
View Answer
Answer: c
: When the negative voltage is applied to the gate, there develops a presence of negative charge on
the gate. The mobile positively charged holes are attracted to the region beneath the gate. This
explains the formation of accumulation mode.
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1. The current through the n-MOS transistor will flow when:
a) Vgs > Vtreshold, Vds=0
b) Vgd < Vtreshold, Vds=0
c) Vgs > Vtreshold, Vds>0
d) Vgd > Vtreshold, Vds<0
View Answer
Answer: c
: The current flows through the n-MOS transistor when Vgs > Vtreshold, Vds>0.
2. The p-MOS Transistor is said to be in Saturation mode when:

a) Vdsp > Vgsp – Vtp
b) Vgsp < Vdsp –Vtp
c) Vgsp > Vtp
d) Vdsp < Vgsp – Vtp
View Answer
Answer: d
: The pMOS transistor is in Saturation mode when Vdsp < Vgsp – Vtp and Vgsp < Vtp.
3. The Fermi potential of the p-type MOSFET is:
a) φfp = (kT/q)ln(ND/NA)
b) φfp = (kT/q)ln(NA/ND)
c) φfp = (kT/q)ln(NA/ni)
d) φfp = (kT/q)ln(ni/NA)
View Answer
Answer: d
: The Fermi potential of the p-type semiconductor is φfp = (kT/q)ln(ni/NA) where ni denotes the
intrinsic carrier concentration of silicon, NA is acceptor concentration, ND is Donor Concentration.
4. The Fermi potential(φfp) for the n-type MOSFET is:
a) φfp = (kT/q)ln(ND/NA)
b) φfp = (kT/q)ln(NA/ND)
c) φfp = (kT/q)ln(ND/ni)
d) φfp = (kT/q)ln(ni/ND)
View Answer
Answer: c
: The Fermi potential of the p-type semiconductor is φfp = (kT/q)ln(ND/ni) where ni denotes the
intrinsic carrier concentration of silicon, NA is acceptor concentration, ND is Donor Concentration.
5. The principle of the MOSFET operation is:
a) Control the conduction of current between the source and the drain, using the potential
difference applied at the gate voltage as a control variable
b) Control the current conduction between the source and the gate, using the electric field applied
at the drain voltage as a control variable
c) Control the current conduction between the PN junction, using the electric field generated by the
bias voltage as a control variable
d) Control the current conduction between the PN junctions, using the electric potential generated
by the gate voltage as a control variable
View Answer
Answer:a
: By varying the gate voltage the current between the source and drain are varied.
6. The conduction of current IDS depends on:
i) Gate to source voltage
ii) Drain to source voltage
iii) Bulk to source voltage
iv) Threshold voltage
v) Dimensions of MOSFET
a) Only i
b) Only i, ii and iii
c) Only v
d) All of the mentioned
View Answer
Answer: d
: The current depends on Vgs, Vds, Vbs, Vt and dimensions of MOSFET.
7. The impedance at the input of n-MOS transistor circuit is:
a) Lesser than p-MOS transistor
b) Greater than BJT transistor
c) Lesser than JFET transistor
d) Zero
View Answer
Answer: b
: The impedance at the input of n-MOS transistor is more than BJT transistor.
8. The depletion mode n-MOS differs from enhancement mode n-MOS in:
a) Threshold voltage
b) Channel Length
c) Switching time

View Answer
Answer: a
: If n-MOS operates with negative threshold voltage then it is in depletion mode. If n-MOS operates
with positive threshold voltage then it is in enhancement mode.
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1. When the drain voltage in an n-MOSFET is negative, it is operating in
a. active region
b. inactive region
c. ohmic region
d. reactive region
Answer. b
2. The regions of operation of a MOSFET to work as a linear resistor and linear amplifier are
a. cut-off and saturation respectively
b. triode and cut-off respectively
c. triode and saturation respectively
d. saturation and triode respectively
Answer. c
3. Two MOSFETs M[1] and M[2] are connected in parallel to carry a total current of 20A. The drain to
source voltage of M[1] is 2.5V and that of M[2] is 3V. What are the drain currents of M[1] and M[2]
when the current sharing series resistances are each of 0.5Ω?
a. 10.5 A and 9.5 A
b. 9.5 A and 10.5 A
c. 10.5 A and 10.5 A
d. 9.5 A and 9.5
A Answer. a
4. The lower turn off time of MOSFET when compared to BJT can be attributed to which one of the
following?
a. input impedance b. positive temperature coefficient c. absence of minority carriers d. on-state

resistance
Answer. c
5. What is the main difference between MOSFETs and BJTs in terms of their I-V characteristics? a.
current is quadratic with V[GS] for MOSFETs and linear with V[BE] for BJTs b
b. current is linear with V[GS] for MOSFETs and exponential with V[BE] for BJTs
c. current is exponential with V[GS]/V[BE] in both these devices, but rise is faster in MOSFETs d.
current is quadratic with V[GS] for MOSFETs and exponential with V[BE] for BJTs
Answer. d
6. The modified work function of an n-channel MOSFET is -0.85 V. If the interface charge is 3 × 10^-4
C/m^2 and the oxide capacitance is 300 μF/m^2, the flat band voltage is
a. -1.85 V
b. -0.15 V
c. +0.15 V
d. +1.85 V
Answer. d
7. Enhancement mode is connected with which one of the following?
a. tunnel diode b. MOSFET c. photodiode d. varactor diode
Answer. b
8. The MOSFET switch in its on-state may be considered equivalent to
a. resistor b. capacitor c. inductor d. battery
Answer. b
9. Which of the following pair is not correctly matched?
a. MOSFET – unipolar device
b. BJT – switching power loss
c. MOSFET – high ON state conduction power loss
d. IGBT – voltage-controlled device
Answer. b
10. Identify the incorrect statement regarding power MOSFET.
a. these are so constructed as to avoid punch through
b. the channel length is relatively large and the channel width is relatively small
c. these do not experience any minority charge carrier storage
d. these can be put in parallel to handle large currents
Answer. b
11. An E-MOSFET with its gate connected to its drain is an example of
a. a three-terminal device
b. an active load
c. a passive load
d. a switching device
Answer. b
12. Which of the following devices revolutionised the computer industry?
a. JFET
b. D-MOSFET
c. E-MOSFET
d. Power FET
Answer. c
13. A D-MOSFET can operate in the
a. depletion mode only
b. enhancement mode only
c. depletion mode or enhancement mode
d. low impedance mode
Answer. c
14. For operation of depletion type MOSFET the gate voltage is kept
a. positive
b. highly positive
c. zero
d. negative
Answer. d
15. A MOSFET can be used as
a. resistor
b. capacitor
c. switch
d. all the above
Answer. d
16. Most commonly used insulating layer material for MOSFET is
a. GeO[2]
b. Al[2]O[3]
c. As[2]O[5]
d. SiO[2]
Answer. d
17. Dynamic memory cells are constructed using
a. transistors b. flip-flops c. MOSFETs d. FETs
Answer. c
18. MOSFET can be used as
a. current controlled capacitor b. voltage controlled capacitor c. current controlled inductor
d. voltage controlled inductor
Answer. b
19. Which of the following parameters are affected due to short channel MOSFET geometry
i.mobility of carriers ii.threshold voltage iii.drain current
a. only i
b. only ii
c. both i and iii
d. i, ii and iii
Answer. d
20. Which of the following characterisitics does an active loaded MOS differential circuit possess?
a. high CMRR b. low CMRR c. high delay d. high differential gain
Answer. d
21. The MOSFET combines the areas of _______ & _________
a) field effect & MOS technology b) semiconductor & TTL c) mos technology & CMOS technology d)
none of the mentioned
Answer: a : It is an enhancement of the FET devices (field effect) using MOS technology.
22. Which of the following terminals does not belong to the MOSFET?
a) Drain b) Gate c) Base d) Source
Answer: c : MOSFET is a three terminal device D, G & S.
23. Choose the correct statement
a) MOSFET is a uncontrolled device b) MOSFET is a voltage controlled device c) MOSFET is a current

controlled device d) MOSFET is a temperature controlled device
Answer: b : It is a voltage controlled device.
24. Choose the correct statement(s)

i) The gate circuit impedance of MOSFET is higher than that of a BJT ii) The gate circuit impedance of
MOSFET is lower than that of a BJT iii) The MOSFET has higher switching losses than that of a BJT iv)
The MOSFET has lower switching losses than that of a BJT
a) Both i & ii
b) Both ii & iv
c) Both i & iv
d) Only ii
Answer: c : MOSFET requires gate signals with lower amplitude as compared to BJTs & has lower
switching losses.
a) MOSFET is a unipolar, voltage controlled, two terminal device
b) MOSFET is a bipolar, current controlled, three terminal device
c) MOSFET is a unipolar, voltage controlled, three terminal device
d) MOSFET is a bipolar, current controlled, two terminal device
Answer: c : MOSFET is a three terminal device, Gate, source & drain. It is voltage controlled unlike
the BJT & only electron current flows.
26. The arrow on the symbol of MOSFET indicates
a) that it is a N-channel MOSFET b) the direction of electrons c) the direction of conventional current
flow d) that it is a P-channel MOSFET
Answer: b : The arrow is to indicate the direction of electrons (opposite to the direction of
conventional current flow).
27. The controlling parameter in MOSFET is
a) Vds b) Ig c) Vgs d) Is
Answer: b : The gate to source voltage is the controlling parameter in a MOSFET.
28. In the internal structure of a MOSFET, a parasitic BJT exists between the
a) source & gate terminals
b) source & drain terminals
c) drain & gate terminals
d) there is no parasitic BJT in MOSFET
Answer: b : Examine the internal structure of a MOSFET, notice the n-p-n structure between the
drain & source. A p-channel MOSFET will have a p-n-p structure.
29. In the transfer characteristics of a MOSFET, the threshold voltage is the measure of the
a) minimum voltage to induce a n-channel/p-channel for conduction

b) minimum voltage till which temperature is constant
c) minimum voltage to turn off the device
d) none of the above mentioned is true
Answer: a : It is the minimum voltage to induce a n-channel/p-channel which will allow the device to
conduct electrically through its lengt
30.The output characteristics of a MOSFET, is a plot of
a) Id as a function of Vgs with Vds as a parameter
b) Id as a function of Vds with Vgs as a parameter
c) Ig as a function of Vgs with Vds as a parameter
d) Ig as a function of Vds with Vgs as a parameter
Answer: b : It is Id vs Vds which are plotted for different values of Vgs (gate to source voltage).
31. In the output characteristics of a MOSFET with low values of Vds, the value of the on-state
resistance is a) Vds/Ig b) Vds/Id c) 0 d) ∞
Answer: b : The o/p characteristics Is a plot of Id verses Vds, which for low values of Vds is almost
constant. Hence, the onstate resistance is constant & the slop is its constant value
32. At turn-on the initial delay or turn on delay is the time required for the
a) input inductance to charge to the threshold value b) input capacitance to charge to the threshold
value c) input inductance to discharge to the threshold value d) input capacitance to discharge to the
threshold value
Answer: b : It is the time required for the input capacitance to charge to the threshold value, which
depends on the device configuration. The device can start conducting only after this time.
a) MOSFET suffers from secondary breakdown problems
b) MOSFET has lower switching losses as compared to other devices
c) MOSFET has high value of on-state resistance as compared to other devices
Answer: b : MOSFET has lower switching losses due to its unipolar nature & less turn off time. All of
the other statements are false.
34. Which among the following devices is the most suited for high frequency applications? a) BJT b)
IGBT c) MOSFET d) SCR
Answer: c : MOSFET has the least switching losses among the rest of the devices.
a) MOSFET has a positive temperature co-efficient
b) MOSFET has a high gate circuit impedance

c) MOSFET is a voltage controlled device
Answer: d : MOSFETs are voltage controlled devices. They have high gate circuit impedance and are
PTC devices.
36. Consider an ideal MOSFET. If Vgs = 0V, then Id = ?
a) Zero b) Maximum c) Id(on) d) Idd
Answer: a : Gate current = 0 so device is off (ideally).
37. For a MOSFET Vgs=3V, Idss=5A, and Id=2A. Find the pinch of voltage Vp a) 4.08 b) 8.16 c) 16.32
d) 0V
Answer: b : Use Id = Idd x [1-Vgs/Vp] .
38. How does the MOSFET differ from the JFET?
a) JFET has a p-n junction b) They are both the same c) JFET is small in size d) MOSFET has a base
terminal
Answer: a : None.
39. The basic advantage of the CMOS technology is that
a) It is easily available b) It has small size c) It has lower power consumption d) It has better switching
capabilities
Answer: c : Complementary MOS consumes very less power as compared to all the earlier devices.
40. The N-channel MOSFET is considered better than the P-channel MOSFET due to its
a) low noise levels b) TTL compatibility c) lower input impedance d) faster operation
Answer: d : The N-channel are faster than the P-channel type
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1. What is the best choice of IC package used for experimental purpose?
a) DIP package
b) Metal can package
c) Flat pack
d) Transistor pack
View Answer
Answer: a
: DIP package are used as it is easy to mount. The mounting does not require bending or soldering of
the leads.
2. What is the general information specified in ordering an IC?
a) Temperature range
b) Device type
c) Package type
View Answer
Answer: d
: Generally, in ordering an IC, all the three informations must be specified.
3. Find the ordering information for μA741TC.
a) Sprague 741 DIP with Industrial temperature range
b) Intersil 741 DIP with commercial temperature range
c) Fairchilds 741 DIP with commercial temperature range
d) Texas instrument 741 metal can with Industrial temperature range
View Answer
Answer: c
: Here “μA” represents the identifying initials used by Fairchild,
T represents Mini DIP package and C represents Commercial temperature range.
4. How a Motorola IC with plastic DIP and commercial temperature range is ordered?
a) ICLxxxP -> 0o to 75oc
b) CAxxE -> -55o to +125oc
c) LMxxxxA -> -40o to+85oc
d) MCxxxP -> 0o to 70oc
View Answer
Answer: d
: The ordering format for a typical Motorola IC is,
MCxxxx –> Device type
P –> Package type(Plastic DIP)
0o to 70oc –> Temperature range (Commercial).
5. What does the 1-2-3 numbering system used in National Semiconductor IC denotes
a) Validity in years
b) Temperature range
c) Package type
d) Ordering information
View Answer
Answer: c
: In National linear ICs, a 1-2-3 numbering system is used to represent the temperature range.
6. How does an industrial temperature range device in National Semiconductor IC is represented?
a) LM305
b) LM101
c) LM201
View Answer
Answer: c
: In LM201, the number 2 denotes an industrial temperature range device.
8. Dual-In-Line pack is considered to be suitable for mounting because,
a) Easy to handle
b) Fits mounting hardware
c) Inexpensive
View Answer
Answer: c
: DIP pack is easy to handle, fit standard mounting hardware and is inexpensive when moulded on
plastic.
9. What is the use of notch and dot in DIP ICs?
a) Determine the pin configuration
b) Designed to represent device type
c) Represent property of IC
d) Find the pin number
View Answer
Answer: d
: A notch and dot as viewed form top view is used to find the pin terminal. The terminals are
numbered counter clockwise.
10. How an eight pin Dual-In-Line Package is shortly named

a) 8p DIP
b) Maxi DIP
c) Mini DIP
d) ES DIP
View Answer
Answer: c
: An eight pin Dual-In-Line Package is called as Mini DIP as it is used for devices with minimum
number of inputs and outputs.
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1. Which is the reference vector for parallel RC circuits?
None of the above
View Answer =v
2. What is called the power that is measured in volt-amperes?
True power
Reactive power
Apparent power
Impedance power
View Answer =
Apparent power
3. Which of the following statement is true about a series circuit?
The resistor voltage lags the current
The current lags the source voltage.
The current leads the source voltage.
None of the above
View Answer =
The current leads the source voltage.

4. What is the expression of current in the R- C circuit?
i=(V/R)exp⁡(t/RC )
i=(V/R)-exp(⁡t/RC )
i=(V/R)exp⁡(-t/RC )
i=(V/R)-exp⁡(-t/RC )
View Answer =
i=(V/R)exp⁡(-t/RC )
5. What do you mean by an RC circuit ?
a circuit with both a resistor (R) and a capacitor (C)
a resistor (R) and a capacitor (C).
Voltage
Current
View Answer =
a circuit with both a resistor (R) and a capacitor (C)
6. The relationship between change in charge, current and the time interval is:
ΔQ = I Δt
ΔQ = I /Δt
ΔQ = 2I /Δt
None of the above
View Answer =
ΔQ = I Δ
7. Which one is the formula for Voltage, charge and capacitance of a capacitor in RC circuit?
V=Q/C
V=QC
V=2Q/C
None of the above
View Answer =
V=Q/C
8. What does RC circuit stands for?
resistor–capacitor circuit
resistor–conductor circuit
rotator–capacitor circuit
All of the above
View Answer =
resistor–capacitor circuit
9. The two most common RC filters are the ___.
high-pass filters
low-pass filters
Both A and B
None of the above
View Answer =
Both A and B
10. The relationship between the complex impedance, ZC (in ohms) of a capacitor with capacitance C
(in farads) and complex frequency s is ___.
ZC=1/2sC
ZC=1/sC
ZC=2/sC
ZC=1/3sC
View Answer =
ZC=1/sC
11. A complex number represents a phasor quantity.
True
False
View Answer =
True
12. When the frequency of the source voltage decreases, the impedance of a parallel RC circuit:
Decreases to zero
Increases
Does not change
Decreases
View Answer=
Increases
13. When the frequency of the voltage applied to a series RC circuit is increased, the phase angle
____.
increases
decreases
remains the same
becomes erratic
View Answer =
decreases
14. The combination of reactive power and true power in RC circuit is called apparent power.
True
False
View Answer =
True
15. Is Apparent power is measured in the unit of Volt-Amps (VA)?
Yes
No
View Answer =
Yes
16. Total current in an RC circuit always leads the source voltage.
True
False
View Answer =
True
17. In an R-C circuit, when the switch is closed, the response ___.
do not vary with time
decays with time
rises with time
first increases and then decreases
View Answer =decays with time
18. When the frequency of the source voltage decreases, the impedance of a parallel RC circuit ___.
increases
decreases
does not change
decreases to zero
View Answer =increases
19. Positive numbers can be represented by points to the right of the origin on the horizontal axis of
a graph.
True
False
View Answer =
True
20. The time constant τ for an RC circuit is defined as RC.
True
False
View Answer =
True
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1) In accordance to the scaling technology, the total delay of the logic circuit depends on ______
a. The capacitor to be charged
b. The voltage through which capacitance must be charged
c. Available current
d. All of the above
Answer
ANSWER: All of the above
No is available for this question!
2) In CMOS circuits, which type of power dissipation occurs due to switching of transient current and
charging & discharging of load capacitance?
a. Static dissipation
b. Dynamic dissipation
c. Both a and b
d. None of the above

Answer
ANSWER: Dynamic dissipation
3) In high noise margin (NMH), the difference in magnitude between the maximum HIGH output
voltage of driving gate and the maximum HIGH voltage is recognized by the _________gate.
a. Driven
b. Receiving
c. Both a and b
Answer
ANSWER: Receiving
4) Which factor/s play/s a crucial role in determining the speed of CMOS logic gate?
a. Load capacitance
b. Supply voltage
c. Gain factor of MOS
d. All of the above
Answer
5) For complex gate design in CMOS, OR function needs to be implemented by _______

connection/s of MOS.
a. Series
b. Parallel
c. Both series and parallel
Answer
ANSWER: Parallel
:
6) In pull-up network, PMOS transistors of CMOS are connected in parallel with the provision of
conducting path between output node & Vdd yielding _____ output.
a. 1
b. 0
c. Both a and b
Answer
ANSWER: 1
7) In CMOS inverter, the propagation delay of a gate is the/an _________ transition delay time for
the signal during propagation from input to output especially when the signal changes its value.
a. Highest
b. Average
c. Lowest
Answer
ANSWER: Average
8) In DIBL, which among the following is/are regarded as the source/s of leakage?
a. Subthreshold conduction
b. Gate leakage
c. Junction leakage
d. All of the above
Answer
9) In enhancement MOSFET, the magnitude of output current __________ due to an increase in the
magnitude of gate potentials.
a. Increases
b. Remains constant
c. Decreases
Answer
ANSWER: Increases
10) Which type of MOSFET exhibits no current at zero gate voltage?
a. Depletion MOSFET
b. Enhancement MOSFET
c. Both a and b
Answer
ANSWER: Enhancement MOSFET
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1. Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?

Find the circuit in figure (a to d) which is sum-of-products implementation
a) a
b) b
c) c
d) d
View Answer
Answer: d
Explanation: SOP means Sum Of Products form which represents the sum of product terms having
variables in complemented as well as in uncomplemented form. Here, the diagram of d contains the
OR gate followed by the AND gates, so it is in SOP form.
2. Which of the following logic expressions represents the logic diagram shown?
The logic expressions X=A’B’+AB represents the logic diagram
a) X=AB’+A’B
b) X=(AB)’+AB
c) X=(AB)’+A’B’
d) X=A’B’+AB
View Answer
Answer: d
Explanation: 1st output of AND gate is = A’B’
2nd AND gate’s output is = AB and,
OR gate’s output is = (A’B’)+(AB) = AB + A’B’.
3. The device shown here is most likely a ________

The diagram is demultiplexer because it takes single input & gives many outputs
a) Comparator
b) Multiplexer
c) Inverter
d) Demultiplexer
View Answer
Answer: d
Explanation: The given diagram is demultiplexer, because it takes single input & gives many outputs.
A demultiplexer is a combinational circuit that takes a single output and latches it to multiple
outputs depending on the select lines.
4. What type of logic circuit is represented by the figure shown below?
The logic expressions X=A’B’+AB represents the logic diagram
a) XOR
b) XNOR
c) AND
d) XAND
View Answer
Answer: b
Explanation: After solving the circuit we get (A’B’)+AB as output, which is XNOR operation. Thus, it
will produce 1 when inputs are even number of 1s or all 0s, and produce 0 when input is odd
number of 1s.
5. For a two-input XNOR gate, with the input waveforms as shown below, which output waveform is
correct?
Find output waveform for a two-input XNOR gate with the input waveforms shown
a) d
b) a
c) c
d) b
View Answer
Answer: a
Explanation: When both inputs are same then the o/p is high for a XNOR gate.
i.e., A B O/P
001
010
100
1 1 1.
Thus, it will produce 1 when inputs are even number of 1s or all 0s, and produce 0 when input is odd
number of 1s.
6. Which of the following combinations of logic gates can decode binary 1101?
a) One 4-input AND gate
b) One 4-input AND gate, one inverter
c) One 4-input AND gate, one OR gate
d) One 4-input NAND gate, one inverter
View Answer
Answer: b
Explanation: For decoding any number output must be high for that code and this is possible in One
4-input NAND gate, one inverter option only. A decoder is a combinational circuit that converts
binary data to n-coded data upto 2n outputs.
7. What is the indication of a short to ground in the output of a driving gate?
a) Only the output of the defective gate is affected
b) There is a signal loss to all load gates

c) The node may be stuck in either the HIGH or the LOW state
d) The affected node will be stuck in the HIGH state
View Answer
Answer: b
Explanation: Short to ground in the output of a driving gate indicates of a signal loss to all load gates.
This results in information being disrupted and loss of data.
8. For the device shown here, assume the D input is LOW, both S inputs are LOW and the input is
LOW. What is the status of the Y’ outputs?
The diagram is demultiplexer because it takes single input & gives many outputs
a) All are HIGH
b) All are LOW
c) All but Y0 are LOW
d) All but Y0 are HIGH
View Answer
Answer: d
Explanation: In the given diagram, S0 and S1 are selection bits. So,
I/P S0 S1 O/P
D = 0 0 0 Y0
D = 0 0 1 Y1
D = 0 1 0 Y2
D = 0 1 1 Y3
Hence, inputs are S0 and S1 are Low means 0, so output is Y0 and rest all are HIGH.
9. The carry propagation can be expressed as ________
a) Cp = AB
b) Cp = A + B
c) All but Y0 are LOW
d) All but Y0 are HIGH

View Answer
Answer: b
Explanation: This happens in parallel adders (where we try to add numbers in parallel via more than
one adders). A carry propagation occurs when carry from one adder needs to be forwarded to other
adder and that second adder is holding the computation (addition) because carry from first adder
has not come yet. So, there is a slight delay for second adder and this is known as carry propagation.
10. 3 bits full adder contains ________
a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs
View Answer
Answer: d
Explanation: Full Adder is a combinational circuit with 3 input bits and 2 output bits CARRY and SUM.
Three bits full adder requires 23 = 8 combinational circuits.
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1.A ripple counter's speed is limited by the propagation delay of:
A. each flip-flop
B. all flip-flops and gates
C. the flip-flops only with gates
D. only circuit gates
Answer: Option A
2.
To operate correctly, starting a ring counter requires:
A. clearing all the flip-flops
B. presetting one flip-flop and clearing all the others
C. clearing one flip-flop and presetting all the others
D. presetting all the flip-flops

Answer: Option B
3.
What type of register would shift a complete binary number in one bit at a time and shift all the
stored bits out one bit at a time?
A. PIPO
B. SISO
C. SIPO
D. PISO
Answer: Option B
4.
Synchronous counters eliminate the delay problems encountered with asynchronous (ripple)
counters because the:
A. input clock pulses are applied only to the first and last stages
B. input clock pulses are applied only to the last stage
C. input clock pulses are not used to activate any of the counter stages
D. input clock pulses are applied simultaneously to each stage
Answer: Option D
5.
One of the major drawbacks to the use of asynchronous counters is that:
A. low-frequency applications are limited because of internal propagation delays
B.high-frequency applications are limited because of internal propagation delays
C.Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-
frequency counting applications.
D.Asynchronous counters do not have propagation delays, which limits their use in high-frequency
applications.
Answer: Option B
6.
Which type of device may be used to interface a parallel data format with external equipment's
serial format?
A. key matrix
B. UART
C. memory chip
D. serial-in, parallel-out
Answer: Option B
7.
When the output of a tri-state shift register is disabled, the output level is placed in a:
A. float state
B. LOW state
C. high impedance state
D. float state and a high impedance state
Answer: Option D
8.
A comparison between ring and johnson counters indicates that:
A. a ring counter has fewer flip-flops but requires more decoding circuitry
B. a ring counter has an inverted feedback path
C. a johnson counter has more flip-flops but less decoding circuitry
D. a johnson counter has an inverted feedback path
Answer: Option D
9.
A sequence of equally spaced timing pulses may be easily generated by which type of counter
circuit?
A. shift register sequencer
B. clock
C. johnson
D. binary
Answer: Option A
10.
What is meant by parallel-loading the register?
A. Shifting the data in all flip-flops simultaneously
B. Loading data in two of the flip-flops
C. Loading data in all four flip-flops at the same time
D. Momentarily disabling the synchronous SET and RESET inputs
Answer: Option C
11.
What is a shift register that will accept a parallel input and can shift data left or right called?
A. tri-state
B. end around
C. bidirectional universal
D. conversion
Answer: Option C
12.
What happens to the parallel output word in an asynchronous binary down counter whenever a
clock pulse occurs?
A. The output word decreases by 1.
B. The output word decreases by 2.
C. The output word increases by 1.
D. The output word increases by 2.
Answer: Option A
13. Mod-6 and mod-12 counters are most commonly used in:
A. frequency counters
B. multiplexed displays
C. digital clocks
D. power consumption meters
Answer: Option C
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Conductivity of Silicon and MOSFET Basics

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Conductivity of Silicon and MOSFET Basics

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1.

The conductivity of the pure silicon is raised by:

a) Introducing Dopants (impurities)

2. The n-type semiconductor have _______ as majority carriers.

: In n-type semiconductor the majority charge carriers present are electrons.

3. The majority carriers of p-type semiconductor are:

: The majority charge carriers of n-type semiconductors are holes.

4. The n-MOS transistor is made up of:

a) N-type source, n-type drain and p-type bulk

b) N-type source, p-type drain and p-type bulk

c) P-type source, n-type drain and n-type bulk

d) P- type source, p-type drain and n-type bulk

5. The correct representation of n-MOSFET is:

a) Representation of n-MOSFET - option a

b) Representation of n-MOSFET - option b

c) Representation of n-MOSFET - option c

d) None of the mentioned

: This is the correct representation of n-MOSFET : Representation of n-MOSFET - option c

6. The correct representation of p-MOSFET is:

a) Representation of p-MOSFET - option a

b) Representation of p-MOSFET - option b

c) Representation of p-MOSFET - option c

d) Representation of p-MOSFET - option d

: This is the correct representation of p-MOSFET: Representation of p-MOSFET - option b

7. The oxide layer formed in the MOSFET is:

c) Poly Silicon oxide

d) Oxides of Non metals

8. The drain current is varied by:

a) Gate to source voltage

d) None of the mentioned

9. The low voltage on the gate of p-MOSFET forms:

a) Channel of negative carriers

b) Channel is not formed

d) Channel of positive carriers

10. The n-MOSFET is working as accumulation mode when:

a) Gate is applied with positive voltage

c) Gate is applied with negative voltage

d) Gate is connected to source

1. The current through the n-MOS transistor will flow when:

a) Vgs > Vtreshold, Vds=0

b) Vgd < Vtreshold, Vds=0

c) Vgs > Vtreshold, Vds>0

d) Vgd > Vtreshold, Vds<0

2. The p-MOS Transistor is said to be in Saturation mode when:

b) Vgsp < Vdsp –Vtp

c) Vgsp > Vtp

d) Vdsp < Vgsp – Vtp

3. The Fermi potential of the p-type MOSFET is:

4. The Fermi potential(φfp) for the n-type MOSFET is:

5. The principle of the MOSFET operation is:

6. The conduction of current IDS depends on:

i) Gate to source voltage

ii) Drain to source voltage

iii) Bulk to source voltage

iv) Threshold voltage

b) Only i, ii and iii

d) All of the mentioned

: The current depends on Vgs, Vds, Vbs, Vt and dimensions of MOSFET.

7. The impedance at the input of n-MOS transistor circuit is:

a) Lesser than p-MOS transistor

b) Greater than BJT transistor

c) Lesser than JFET transistor

d) None of the mentioned

21. The MOSFET combines the areas of _ & ___