Marmara University

Electrical-Electronics Eng. Dept.

CSE2003 Digital Design

Laboratory Report #4

GROUP 63

MERT TERZİ 150718061

MERT EREN AĞACABAY 150718042

ÖMER FARUK AKYÜREK 150718035

PURPOSE
For this laboratory assignment, you will use Altera Quartus II software and DE-115 FPGA kit
and design an analog
signal comparator that has the Input/output definitions below.

- The analog signal, which is applied to ADC input is changing from 0 to 3V. The ADC is an 8-
bit device, which
has the output pins connected to FPGA.
- Combinational logic will be designed by using three 8-bit comparators that include 4x1
multiplexers.
- The circuit should measure the analog input and the duty cycle of the PWM generated by
FPGA device is
changing according to analog input value. You can see the duty cycle values (for the input
voltages) in the
table below: 0 ≤Vin<0.5 → duty cycle=0%
0.5≤Vin<1.5 → cycle=30%
1.5≤Vin<2.5 → cycle=60%
2.5≤Vin<3.0 → cycle=100%

DESIGN DETAIL
First we designed a 2 bit comparator and then we made an 8 bit comparator using it. We
designed the pwm part and wrote our verilog code.
Verilog Code

module Comp_2_bit(A0,A1,B0,B1,OaLtb,OaEqb,OaGtb);

input A0,A1,B0,B1;

output OaLtb,OaEqb,OaGtb;

wire nA0, nA1, nB0, nB1;

wire wA1nxorB1, wA0nxorB0, wA0nB1nB0, wnB1A1, wnB0A1A0, wB1nA1, wB0nA1nA0,

wB1B0nA0;

not (nA0, A0);

not (nA1, A1);

not (nB0, B0);

not (nB1, B1);

and (wnB1A1, nB1,A1);

and (wnB0A1A0, nB0, A1,A0);

and (wB1nA1, B1, nA1);

and (wB0nA1nA0, B0, nA1, nA0);

and (wB1B0nA0, B1, B0, nA0);

xnor (wA1nxorB1, A1, B1);

xnor (wA0nxorB0, A0, B0);

assign OaLtb= wB1nA1 | wB0nA1nA0 | wB1B0nA0;

assign OaGtb= wA0nB1nB0 | wnB1A1 | wnB0A1A0;

assign OaEqb= wA1nxorB1 & wA0nxorB0;

endmodule

module Comp_8_bit(x1,x2,x3,x4,x5,x6,x7,x8,y1,y2,y3,y4,y5,y6,y7,y8,lesser,equal,greater);

output lesser,equal,greater;

input x1,x2,x3,x4,x5,x6,x7,x8,y1,y2,y3,y4,y5,y6,y7,y8;

wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12;

Comp_2_bit(x1,x2,y1,y2,w1,w2,w3);

Comp_2_bit(x3,x4,y3,y4,w4,w5,w6);

Comp_2_bit(x5,x6,y5,y6,w7,w8,w9);

Comp_2_bit(x7,x8,y7,y8,w10,w11,w12);

assign lesser=w1||(w2&w4)||(w2&w5&w7)||(w2&w5&w8&w10);

assign equal=w2&w5&w8&w11;

assign greater=w3||(w2&w6)||(w2&w5&w9)||(w2&w5&w8&w9);

endmodule

module ledperc(led,clk,per0,per30,per60,per100);

output led;

input per100,per60,per30,per0,clk;

reg [6:0] per;

reg [7:0] cnt;

initial cnt <= 8'b0;

always@(posedge clk) begin

if (cnt<100) cnt <=cnt+1;

else cnt<=0;

if (per100==1) per <=100;

else if (per60==1) per <=60;

else if (per30==1) per <=30;

else if (per0==1) per <=0;

end

assign led=(cnt<per) ? 1:0;

endmodule

module Lab3_pwm(I,clk,pwm_out);

output pwm_out;

input clk;

input [7:0] I;

wire per100,per60,per30,per0;

wire [3:1] S;

wire [3:1] G;

wire [3:1] E;

Comp_8_bit(E[1],S[1],G[1],I,0,0,1,0,1,0,1,1);

Comp_8_bit(E[2],S[2],G[2],I,1,0,0,0,0,0,0,0);

Comp_8_bit(E[3],S[3],G[3],I,1,1,0,1,0,1,0,1);

assign per100=G[3]||E[3];

assign per60=E[2]||(G[2]&S[3]);
assign per30=E[1]||(G[1]&S[2]);

assign per0=S[1];

ledperc(pwm_out,clk,per0,per30,per60,per100);

endmodule