BANDWIDTH EFFICIENCY

Module 5
 BANDWIDTH EFFICIENCY

• Bandwidth efficiency (information density or spectral efficiency) is often

used to compare the performance of one digital modulation
technique to another.

transmission rate (bps)

Bη =
minimum BW (Hz)

Where: Bη = bandwidth efficiency (bits/cycle)

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DIGITAL MODULATION SUMMARY
Modulation Encoding Bandwidth Baud Bandwidth
(Hz) Efficiency
(bps/Hz)
FSK Single bit ≥fb fb ≤1
BPSK Single bit fb fb 1
QPSK Dibit fb/2 fb/2 2
8-PSK Tribit fb/3 fb/3 3
8-QAM Tribit fb/3 fb/3 3
16-PSK Quadbit fb/4 fb/4 4
16-QAM Quadbit fb/4 fb/4 4
Bandwidth Efficiency
• Determine the bandwidth efficiencies for the
following modulation schemes: BPSK,QPSK, 8-
PSK and 16-QAM.

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 CARRIER RECOVERY

• It is the process of extracting a phase-

coherent reference from a receiver signal.
This is sometimes called phase referencing.

• Kinds:
– Squaring Loop
– Costas Loop
– Remodulator

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Carrier Recovery
Squaring Loop

Squaring loop carrier recovery circuit for a BPSK receiver

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Carrier Recovery
Costas Loop (Quadrature Loop)

10
0
 CARRIER RECOVERY

• The filtering reduces spectral width of the

received noise
• The squaring removes the modulation and
generates second harmonic of the carrier
frequency
• Phase-locked loop (PLL) tracks the second
harmonic

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 CARRIER RECOVERY

• PLL Basics (basic elements)

– Phase comparator/detector
– Loop filter
– Voltage-controlled oscillator (VCO)

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 CARRIER RECOVERY

• PLL Operation

Reference: http://www.radio-electronics.com
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 Differential Phase Shift Keying is an
DIFFERENTIAL alternative form of digital modulation
where the binary input information is
PHASE SHIFT contained in the difference between two
successive signaling element rather than
KEYING absolute phase.
DIFFERENTIAL PHASE SHIFT KEYING

DBPSK Modulator Block Diagram

DBPSK MODULATOR TIMING DIAGRAM
DBPSK DEMODULATOR BLOCK DIAGRAM
DBPSK DEMODULATOR TIMING SEQUENCE
 Primary advantage of Differential Binary Phase-Shift
DIFFERENTIAL Keying (DBPSK) is the simplicity of its implementation
since no carrier recovery circuit is needed.
PHASE SHIFT •A disadvantage is that it requires between 1 dB and
KEYING 3 dB more S/N ratio to achieve the same bit error rate
as that of PSK
CLOCK RECOVERY
Clock Recovery Circuit
It is commonly used to recover clocking
information from the receive data. The recovered are
delayed by one half in bit time and then compared
with the original data in an Xor circuit.
Timing Diagram
As long as the receive data contains a
substantial number of transition (sequences), the
recovered clock is maintained. If the receive data
were to undergo an extended period of successive 1s
and 0s, the recovered would be lost. To prevent this
from occurring, the data are scrambled at the
transmit end and descrambled at the receive end.
CLOCK RECOVERY

Figure a shows the clock recovery circuit Figure b shows the timing diagram