SAR REF Input:

The Capacitive DAC (CDAC)

TIPL 4503
TI Precision Labs – ADCs

Created by Luis Chioye

Presented by Cynthia Sosa

1
Agenda
Reference Performance Specifications:
Initial Accuracy, Drift, Long Term Drift, and Noise
Overview of SAR REF Drive Topologies:
Reference standalone VS Buffered Reference
SAR ADCs with Internal Reference Buffer
SAR REF Input Overview: The Capacitive DAC (CDAC)
Build TINA REF Input Model for a SAR:
Discrete Charge Model
TI Device Specific Model
SAR REF Drive Circuit Design:
Reference Bypass Capacitor
Reference Buffer Stability and Compensation

2
Acquisition phase

Sample and Hold Capacitor Settling During Aquisition

FS

Sample and hold Voltage

ADS8330
ADS7042
+5V 3/4FS
Rfilt
R
RSH
SH
Vin±0.5LSB
-+ 100Ω
150Ω
50Ω VSH
+ N-Bit
+ S1 Comp Register 1/2FS
OPA320 C
FILT CSH S2 - VSH
+

800pF
2.6V Vin 40pF
N-Bit
1/4FS
CDAC
Closes at start of
acquisition 4.096V
0
Acquisition Time

3
Conversion Phase

CDAC Output During the Conversioin Cycle

FS

Bit=0
+5V 3/4FS Bit=0 Bit=0
RSH Vin Bit=1
Rfilt
-+ 100Ω 150Ω
Bit=1

VDAC
+ N-Bit
+ S1 Comp Register 1/2FS
OPA320 C CSH -
FILT MSB MSB-1 MSB-2 MSB-3 LSB
+

800pF
2.6V Vin 40pF
N-Bit
1/2 FS 1/4 FS 1/8 FS 1/16 FS 1/32 FS
1/4FS
CDAC

4.096V
0
Time
CDAC
Reference
input

4
SAR ADC Architecture: The Capacitive DAC (1)
Based on TLV- Series
SAR ADCs
REF_IN

Acquisition Phase

+
VREF=4.096V

+2.6V
+

SB
VIN=2.6V Q = -2C · VIN
VIN=2.6V -

2C
+
S1 S2 S3 S4 S5 S5'

C C/2 C/4 C/8 C/16 C/16'

- COMPARATOR
0V SA +

5
SAR ADC Architecture: The Capacitive DAC (2)
Based on TLV- Series
SAR ADCs
REF_IN
Conversion Phase
Hold Mode

+
VREF=4.096V

0V
+

SB
VIN=2.6V VC = -2.6V
-

2C
+
S1 S2 S3 S4 S5 S5'

C C/2 C/4 C/8 C/16 C/16'

- COMPARATOR
V= -2.6V
-2.6V SA +

6
SAR ADC Architecture: The Capacitive DAC (3)
Based on TLV- Series
SAR ADCs
REF_IN: Sees CMSB Load
Conversion Phase
MSB

+
VREF=4.096V

0V
+

SB
VIN=2.6V VC = - VIN + VREF/2
VREF -

C
+

S4 C
S1 S2 S3 S5 S5'

+½
VREF C C/2 C/4 C/8 C/16 C/16'

- COMPARATOR
V= -2.6V + ½ VREF MSB=1
V= -0.552V SA -0.552V +

CODE=1----

7
SAR ADC Architecture: The Capacitive DAC (4)
Based on TLV- Series
SAR ADCs
REF_IN: Sees CMSB-1 Load
Conversion Phase
MSB-1

+
VREF=4.096V

0V
+

SB VC = -VIN + ¾ VREF
VIN=2.6V
VREF -

1/2 C
+

S4 3/2 C
S1 S2 S3 S5 S5'

+½ +¼
VREF C VREF C/2 C/4 C/8 C/16 C/16'

- COMPARATOR
V= -2.6V + ½ VREF + ¼ VREF MSB-1=0
V= +0.472V SA +0.472V +

CODE=10---

8
SAR ADC Architecture: The Capacitive DAC (5)
Based on TLV- Series
SAR ADCs
REF_IN: Sees CMSB-2 Load
Conversion Phase
MSB-2

+
VREF=4.096V

0V
+

SB
VIN=2.6V VC = -VIN + 5/8 VREF
VREF -

3/4 C
+

S4 5/4 C
S1 S2 S3 S5 S5'

+½ +1/8
VREF C C/2 VREF C/4 C/8 C/16 C/16'

- COMPARATOR
V= -2.6V + ½ VREF + 1/8 VREF MSB-2=1
V= -0.040V SA -0.040V +

CODE=101--

9
SAR ADC Architecture: The Capacitive DAC (6)
Based on TLV- Series
SAR ADCs
REF_IN: Sees CMSB-3 Load
Conversion Phase
MSB-3

+
VREF=4.096V

0V
+

SB VC = -VIN + 11/16 VREF

VIN=2.6V
VREF -

10/16 C
+

S4 22/16 C
S1 S2 S3 S5 S5'

+½ +1/8 +1/16
VREF C C/2 VREF C/4 VREF C/8 C/16 C/16'

- COMPARATOR
V= -2.6V + ½ VREF + 1/8 VREF + 1/16 VREF MSB-3=0
V= +0.216V SA +0.216V +

CODE=1010-

10
SAR ADC Architecture: The Capacitive DAC (7)
Based on TLV- Series
SAR ADCs
REF_IN: Sees CLSB Load
Conversion Phase
LSB

+
VREF=4.096V

0V
+

SB VC = -VIN + 21/32 VREF

VIN=2.6V
VREF -

11/16 C
+

S4 21/16 C
S1 S2 S3 S5 S5'

+½ +1/8 +1/32
VREF C C/2 VREF C/4 C/8 VREF C/16 C/16'

- COMPARATOR
V= -2.6V + ½ VREF + 1/8 VREF + 1/32 VREF LSB=0
+ Thomas Kulgelstad:
V= +0.088V SA +0.088V
The operation of the SAR-ADC based on
charge redistribution,
CODE=10100 Analog Applications Journal (slyt176), Texas
Instruments, February 2000.

11
SAR ADC Architecture
• The Reference is sampled several times during each conversion
• High-current transients (~10’s mA range) are present in this REF input where the ADC’s internal
capacitor array is switched and charged as the bit decisions are made.
• Current transient pulses occur only a few nanoseconds away of each other during conversion.

Convert Start Signal

ADS8028
Current Transients (mA)

Initial Current Transient

Bit Transients (12 for 12-Bit Converter)
REFIN Input

Pulses are nanoseconds from each other 12

Thanks for your time!
Please try the quiz.

13
14