Int. J. Electron. Commun.

(AEÜ) 90 (2018) 88–96

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Int. J. Electron. Commun. (AEÜ)

journal homepage: www.elsevier.com/locate/aeue

Regular paper

Low-voltage PVT-insensitive bulk-driven OTA with enhanced DC gain in T

65-nm CMOS process
⁎
Harikrishna Veldandi , Rafi Ahamed Shaik
Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati, Guwahati 781 039, India

A R T I C LE I N FO A B S T R A C T

Keywords: This paper presents a high DC gain bulk-driven operational transconductance amplifier (OTA) for low voltage
Bulk-driven transistor applications. A cross-coupled active load is employed at the bulk-driven input stage to enhance the gain of OTA.
DC gain A cross-forward (CF) gain stage was placed between the input and output stages of the OTA to enhance the
Cross-forward stage output stage transconductance. The CF stage improves the phase margin of OTA and keeps the amplifier stable
OTA
even for large capacitive loads (up to 50 pF) and also improves overall DC gain. The proposed OTA simulated
Low voltage
using UMC 65-nm standard CMOS process, operates at a supply voltage of 0.5 V. Simulation results show that the
Unity gain frequency
OTA provides a gain of 72 dB at very low-frequencies. It has a phase margin of 74° and a unity gain frequency of
680 kHz for a load capacitance of 20 pF. Because of the bulk-driven input stage, the OTA achieved rail-to-rail
input common-mode range. When the OTA simulated with a supply voltage of 0.35 V and load capacitance of
20 pF, the OTA provides a DC gain of 55 dB and a phase margin of 68° at a unity gain frequency of 617 kHz. The
power dissipations were 3.03 μ W and 1.56 μ W for supply voltages of 0.5 V and 0.35 V, respectively. In com-
parison to previous works, the figure of merit of the proposed OTA has more than doubled in all respects.

1. Introduction
In the recent years, the demand for emerging battery-operated
portable and wearable electronics devices such as mobile phones, music
players, and biomedical instruments (hearing aids, implantable cardiac
pacemakers and heart-rate detectors) has been increasing. Most of these
applications use system-on-chip (SoC) that consists of analog, digital,
and intrinsic mixed-signal circuits. In order to extend the battery life in
these systems, their design should be more power efficient. Also, the
system should be able to operate with a low voltage (LV) supply.
Moving towards thin-oxide sub-nanometer CMOS technology entails
the use of low supply voltages to ensure device reliability. However, the
threshold voltage (Vth ) of MOS devices is not scaled down at the same
rate as that of the power supply, in order to limit their leakage currents.
Low-Vth device and low-supply voltage benefit digital circuits in terms
of higher speed, better integration and power efficiency. On the other
hand, short channel effects and other higher-order effects degrade the
analog circuits performance. Because of these effects, it becomes diffi-
cult to achieve the design specification targets such as linearity, gain,
and speed with low power consumption [1]. Also, due to the reduced
voltage headroom, the design of analog and mixed-signal circuits be-
comes highly challenging. To overcome the above problems, a number
of innovative LV design techniques have been developed in recent
years, such as those based on level shifter, bulk-driven (BD), floating
gate (FG), self-cascode, and design in sub-threshold region [1,2].
Most of the analog and mixed signal integrated circuits include
operational transconductance amplifiers (OTA). Often, these OTAs are
the most power hungry blocks applications such as pre-amplifiers, in-
tegrators, switched capacitor circuits, analog filters, and data con-
verters. For these applications, the OTA is required to have high DC
gain, high speed, high slew rate, linearity, and process, voltage and
temperature (PVT) insensitive.
However, the conventional gate-driven techniques are suitable for
the design of high gain and low noise amplifiers. But, these circuits offer
limited common-mode input range under low-voltage condition, due to
threshold voltage limitation in signal path. There are many traditional
design approaches for implementing a low-voltage transconductance
amplifier to increase the input common-mode range. By using a com-
plementary input stage [3–5], or by using dynamic level shifters [6],
the input range can be extended. But complex bias circuits are required
to minimize the dead zone in the input range. By employing floating-
gate MOS devices [1], the input common-mode range can be improved,
but the noise performance degrades. Also, the residual charge on the
floating gate has a widely varying effect on the circuit performance
[7–9].
In such LV applications, the BD-MOSFETs are preferred over their

⁎
Corresponding author.
E-mail address: h.veldandi@iitg.ernet.in (H. Veldandi).

https://doi.org/10.1016/j.aeue.2018.03.033
Received 30 October 2017; Accepted 26 March 2018
1434-8411/ © 2018 Elsevier GmbH. All rights reserved.
H. Veldandi, R.A. Shaik
Vdd
MT1 MT2 MT4 M2A M3A M3B M2B
VBP VBP VCMF
VBP
VOP
V1P V1N
VBN
IBias
ViN ViP
MT3 MT5 M1A VBN M1B
IB1 IB1
Bias Stage Input Stage
Fig. 1. Schematic of the proposed pseudo-differential OTA.
gate-driven counterparts. The former help to achieve rail-to-rail input
operation since these MOSFETs allow a large input signal range without
shifting into the cut-off region [10]. However, the bulk-source trans-
conductance ( gmb ) is smaller than the gate-source transconductance
( gm ) and it is not sufficient to achieve a large DC gain and a gain-
bandwidth product.
Hence, novel techniques are required to overcome the demerits of
BD-MOSFET. In recent years, many LV circuits utilising BD-MOSFETs
such as differential amplifiers [10–30], current mirrors [31], voltage
references [32] and buffers [33–36] have been presented, showing
improved performance under low-voltage operation.
Various solutions have been proposed in the literature to improve
the performance of BD-OTAs for sub-1 V supply, mostly targeting an
improvement in the DC gain. These solutions do have their merits and
demerits. BD folded-cascoded architecture employs an array of self-
cascode transistors to improve the gain [11]. Current recycling has been
used to improve transconductance of BD input stage [12–15]. However,
these approaches are not suitable for sub-1 V design because the cas-
code structure limits the signal swing. The BD flipped voltage follower
has been employed at the input stage to improve the linearity and dy-
namic performance of OTA [16]. In [17], a multi-signal path input stage
is employed to enhance the transconductance of folded-cascode to-
pology.
Some sub-1 V BD architectures based on two-stage topology were
proposed in order to save power and minimize the compensation task
[18–20]. But these circuits provide limited gain and require more
power to achieve higher unity gain bandwidth (UGB). To overcome
this, some researchers proposed the concept of partial positive feedback
to enhance transconductance with a small amount of current
[10,21–24]. In addition, auxiliary blocks such as differential amplifier
[22,25], current-shunt amplifier [26] were also employed to improve
the transconductance. Other reported designs use a three-stage to-
pology to further enhance the gain and bandwidth of OTA [27–29].
These circuits need a complex compensation network such as nested
miller compensation network or damping factor controlling network to
improve the load driving capability. The design in [28], employed local
common mode feedback (LCMFB) with the help of a resistor to improve
the dynamic performance i.e., slew rate. The design in [29] is based on
a self-biased circuit to improve the common-mode and power-supply
rejection of the OTA.
Some of the designs proposed in literature do not meet the low-
voltage condition [12–15]. In a few other cases, the circuit performance
does not remain constant with PVT variations [10,16,21–24]. Some of
the existing topologies, though suitable for low-supply voltage, come at
the cost of additional power and area [28,29]. Hence, there is a need for
new topologies which work with sub-1 V supplies and meet all the
specifications of OTA with a smaller quiescent current and PVT in-
sensitivity. This article presents a solution to a BD-OTA for low supply
voltage, to obtain adequate DC gain without giving up on other per-
formance parameters of the OTA such as UGB, slew rate, and output
swing.
The proposed high gain OTA design is based on a pseudo-
Int. J. Electron. Commun. (AEÜ) 90 (2018) 88–96
Vdd Cross forward stage
M8A M6A M6B M8B MC3 MC4
V1N V1P
V1P V1N
VCMF
IB2 VFN VFP IB2 IB4 VCMF
CC VON
CC IB5
VOP VON VREF
M7A M5A M4A M4B M5B M7B MC1 MC2 MC5
IB3 IB3
Output Stage CMFB
differential topology is able to work with sub-0.5 V supplies. The circuit
is designed in a 65 nm CMOS technology. All the MOSFETs in the
proposed design operate in weak inversion. The gain of the BD input
stage is improved with the help of partial positive feedback technique.
An additional cross-forward (CF) stage assists in increasing the gain of
second stage. It also improves the driving capability of OTA without
any stability issue. The proposed design can drive capacitive loads of up
to 50 pF, with only a minor reduction in phase margin.
This paper is arranged as follows: Section 2 describes the archi-
tecture and operation of the proposed OTA. The analysis of various
performance parameters and frequency compensation is discussed in
Section 3. Simulation results of the proposed OTA are presented in
Section 4 and the performance of proposed work in comparison to the
state-of-the-art is discussed in Section 5. Section 6 gives the important
conclusions drawn from this work.
2. Pseudo-differential bulk-driven OTA
Schematic of the proposed bulk-driven OTA is shown in Fig. 1. All
the transistor pairs are symmetrical, with each transistor having its
counterpart in the opposite branch. They all operate in the weak in-
version region and are biased at mid-of-supply voltage (i.e., VDD /2) for
desired bias current. In order to achieve maximum voltage swing, the
input and output common-mode node voltages are set to VDD /2. The
input stage is designed using a Triple-well CMOS process with access to
the bulk-terminal of nMOS transistor. The bulk terminals of some of the
MOSFETs are biased at common-mode voltage in order to reduce the
threshold voltage (Vth ) of device which makes it easy to operate at low-
voltages. The proposed OTA architecture constitutes input, output, and
cross-forward stages. In addition, a common-mode feedback (CMFB)
circuit is employed for the output stage. It will help in keeping the
output common-mode node voltage to a known reference value (VREF ).
2.1. Input stage
A bulk-driven pseudo-differential pair is employed as the input
stage of OTA and it consists of transistors M1A,B−M3A,B . Differential in-
puts ViN and ViP are applied across the bulk terminal of M1A and M1B . The
input stage loaded with diode connected pMOS transistors M2A−M2B .
Another pair of pMOS transistors, M3A−M3B , is configured in a cross-
coupled mode to cancel gate transconductance and it enhances the gain
of input stage. The bulk terminals of M3A−M3B are also connected in a
cross-coupled manner, which helps in further improvement of gain.
Under differential input signal, the cross-coupled pair acts in partial
positive feedback mode and gives a negative transconductance and the
overall load conductance will be reduced. This results the differential-
mode gain of the first stage to be set at a high value. With a common-
mode input signal, the operation will be vice versa.
The sub-threshold current-voltage (I-V) relations of MOS transistor
operating in the weak inversion region is given by [37]
89
H. Veldandi, R.A. Shaik
W V −V V 2.4. CMFB stage
ID = IS exp ⎛ GS th ⎞ ⎛⎜1−exp ⎛− DS ⎞ ⎞⎟
⎜ ⎟ ⎜ ⎟
L ⎝ nVT ⎠ ⎝ ⎝ VT ⎠ ⎠
where IS is the characteristics current, VT (=kB T / q) is the thermal vol-
tage and n stands for sub-threshold slope factor in weak inversion (in
fact, the slope factor is not a constant parameter but a function of
process parameters and substrate biasing). All the other symbols have
their usual meaning. If drain-source voltage is VDS > 4VT , then the effect
of VDS on drain current is very minimal, therefore the drain current can
be approximated as follows [11]:
W V −V
ID ≈ IS exp ⎛ GS th ⎞
⎜ ⎟
L ⎝ nVT ⎠
The voltage applied to the bulk actually reduces the threshold vol-
tage Vth of the transistor, which increases the inversion level. The ex-
pression of Vth with bulk-biasing is given by
Vth = Vto + γ ( |2ϕF + VSB| − |2ϕF | )
where γ is the body effect coefficient, and ϕF is the Fermi potential. The
expression for the bulk transconductance gmb , is given by [37]
γ generator circuit [38]. The transistors MT 1−MT 5, with the constant
gmb = gm ≈ (n−1) gm
2 |2ϕF + VSB |
γ
where n−1 = . will change according to the PVT variations. With such an arrangement,
2 |2ϕF + VSB |
2.2. Cross forward stage
Cross-forward stage formed with transistors M4A,B−M6A,B , is a part of
the output stage. The differential output of the first stage is attached to
common source transistors M6A and M6B which are loaded with cross-
coupled transistors M4A and M5B . This arrangement offers finite DC gain
for differential-mode signals and enhances transconductance of output
stage and the overall DC gain of OTA. It also helps to improve the
stability of OTA for large capacitive loads. Moreover, the CF stage
subtracts common-mode signals offering a smaller common-mode gain,
resulting in the improvement of common-mode rejection ratio (CMRR)
of OTA.
2.3. Output stage
The output stage consists of two identical common-source transistor
pairs M7A−M8A and M7B−M8B . In order to obtain Class-AB operation at
the output nodes, the differential output of CF stage is connected to M7A
and M7B , transforming it into an active amplifying device. Here, CF
stage acts as a current replication branch and also offers finite voltage
gain. The load driving capability of OTA depends upon the output stage
transconductance. For large capacitive loads, single Miller-capacitance
compensated OTA requires large transconductance at output stage. For
this, a high current is required for output stage to have the required
stability. Instead, the use of CF stage in the proposed design enhances
the output stage transconductance with only a small current in the
output stage. Class-AB functionality at the output stage improves the
dynamic performance parameters of OTA such as slew rate and settling
time (ts ).
V1
+
gm6V1
Vid
gmb1.Vid
R1 C1
-
Fig. 2. Small signal circuit model of the proposed OTA for frequency analysis.
Int. J. Electron. Commun. (AEÜ) 90 (2018) 88–96
(1)
When the input common-mode voltage changes in differential OTA
architectures, the output node voltage will saturate to one of the supply
rails due to the mismatch between transistors. Hence, we employed
CMFB circuit to maintain the output common-mode voltage at re-
ference voltage (VREF ). The CMFB circuit in Fig. 1 is based on one dis-
cussed in [19]. The CMFB circuit, constituting transistors MC1 to MC4 ,
performs the tasks of the common-mode detection and reference com-
parison. If there is any mismatch between output common-mode vol-
tages of OTA, the feedback mechanism adjusts the both output node
voltages to the desired value (i.e., VREF ). The CMFB circuit acts as a
(2)
buffer for differential input, offers finite gain, and improves CMRR of
the OTA with common mode input. The bandwidth of CMFB circuit
should be more than that of OTA in order to avoid compensation for
CMFB circuit.
(3) 2.5. Voltage bias generator
In Fig. 1, the bias voltages VBP and VBN are generated using bias
current source IBias , are arranged in a feedback configuration to gen-
(4) erate bias voltages VBP and VBN . With this arrangement, the bias voltages
the performance of OTA will be less affected with PVT variations.
3. Analysis of the proposed OTA
The OTA performance parameters such as differential gain,
common-mode gain, power-supply gain and input-referred noise (IRN)
are analyzed. The proposed pseudo-differential circuit is a symmetrical
and parameters of transistor MkA is equal to MkB with opposite phase.
The mathematical equations are expressed as function MOS small-
signal parameters, denoting bulk transconductance as gmbk , gate
transconductance as gmk and drain conductance as gdsk for k th transistor
(k = 1, 2, 3, …8).
3.1. Differential mode analysis
In Fig. 1, the bulk-driven transistors M1A and M1B at input stage are
loaded with diode connected transistors M2A and M2B . To improve the
gain, transistors M3A and M3B are cross-coupled which gives a negative
transconductance cancels the effect of diode transistors M2A and M2B
and improves the overall gain of input stage. The gain of OTA also
depends on the channel length of MOS devices.
The differential-mode frequency characteristics can be studied using
its small-signal equivalent model in Fig. 2. The differential gain ( Adm ) of
the circuit is derived by nullifying all frequency dependence compo-
nents in the small-signal model and is given by Eq. (5). The partial
positive feedback configuration cancels the gate transconductance and
offers larger gain. Here, the major part of differential DC gain is con-
tributed by the output stage. The effective output stage transconduc-
tance of OTA is enhanced due to gain of CF stage, which equals to gm6 Rf
and Rf represents the effective output resistance of CF stage (i.e., at
CC
Vf
Vod
gm8V1 gm7Vf
Rf Cf R2 C2
90
H. Veldandi, R.A. Shaik Int. J. Electron. Commun. (AEÜ) 90 (2018) 88–96

node FN/FP). transconductance (gmb) is small compared to gate transconductance

gmb1 (gm) . It is clear from Eq. (9) that the flicker noise component is more
Adm = . dominant in the low-frequency range. The flicker noise can be mini-
(gds1 + gds2 + gm2−gm3 + gds3−gmb3 )
mized by increasing input stage transconductance, either by increasing
(g m8 + gm7 g
gm6 + gmb6
ds6 + gds5 + gm5 + gds 4 − gm 4 ) input stage current or by choosing the large size input transistor for bias
current. There is a trade-off between the noise and biasing current of
(gds7 + gds8 ) (5) input stage. The thermal noise is dominant after noise corner frequency
In Fig. 2, R1,R2 and Rf represent effective resistance of input, output and it will be constant for medium to higher frequencies. In bulk-driven
and cross-forward stages, respectively. C1 and Cf is parasitic capacitance circuits, the thermal noise can be minimized by increasing transcon-
of input and cross-forward stages, respectively, and C2 is load capaci- ductance of the input stage i.e., gmb1.
tance at output stage.
3.4. Frequency compensation
3.2. Common-mode analysis
The small signal equivalent model of circuit Fig. 1 is shown in Fig. 2.
This analysis is performed to understand the effect of common- The model is similar to that of a conventional miller compensation
signal on the output node by calculating the common-mode gain ( Acm ) model [39], except for an additional transconductance (gm7 ) component
(for an idle case, Acm ≈ 0 ). The common mode rejection ratio (CMRR) at the output stage. The transconductance of output stage is enhanced
is another performance parameter of OTA and it is ratio of Adm to Acm . by the common source amplifier formed with devices M4−M6 and loads
The CMRR of amplifier is used to measure the ability of the OTA to arranged in cross-coupled fashion. The intermediate stage between
reject common-mode signals. The Acm is calculated using the equivalent input and output stages creates a cross forward path.
half-circuit of the proposed OTA and the expression for Acm is given by The characteristics in the low to mid-frequency range, where the
gmb1 non-dominant pole frequency 1/ Rf Cf of the cross forward path and the
Acm = · zero frequencies near unity gain frequency can be omitted. It can be
(gds1 + gds2 + gm2 + gm3 + gds3 + gmb3 )
assumed that the dominant pole (pd1 ) and the first non-dominant pole
(g −g
m8
gm6 + gmb6
m7 g + g + g + g
ds6 ds5 m5 ds 4 + gm 4 ) (pnd2 ) are real and widely separate. As compensation capacitor (CC )
increases, pd1 moves to lower frequencies and pnd2 shifts to higher fre-
(g mb8 g
gmc 4
dsc 4 + gdsc5
+ gds7 + gds8 ) (6)
quencies, indicating the pole-splitting phenomenon as seen for a con-
ventional two-stage OTA. The unity gain bandwidth of the proposed
For common mode input signal, the cross coupled transistor con- OTA is given by
figuration provides negative feedback at input and CF stages, resulting gmb1
in a lower resistance. The CF stage reduces the output stage transcon- UGB ≈
2πCC (11)
ductance and this offers low common-mode gain. The CMFB circuit acts
as an amplifier for common-mode input and it reduces the overall The high frequency characteristics are obtained with a sufficiently
common-mode gain of OTA. large CC . Hence, the pd1 is shifted very close to DC and its location is
given in Eq. (12) and pnd2 starts to interact with the pole frequency at
3.3. Noise analysis 1/ Rf Cf . It can be shown that the two non-dominant poles pnd2 and pnd3
are given in Eq. (13).
The noise performance of a multi-stage amplifier is dominated by 1
the gain of its input stage [28] at low and medium frequencies. The Pd1 ≈ −
R1 R2 gmo CC (12)
noise contribution of second stage is negligible compared to input stage.
The first stage of the proposed OTA has a gain >20 dB. The power C2 + gm8 gm6 Cf ⎧ 4gmo Rf Cf C2 ⎫
spectral-density of IRN (Sv (f )) for a bulk-driven transistor in weak in- Pnd2,nd3 ≈ − 1± 1−
2Rf Cf C2 ⎨ (C2 + gm8 Rf Cf )2 ⎬ (13)
version is given by ⎩ ⎭

gm2 The proposed OTA has two finite zeroes placed at high frequencies.
8 KB Tgm KF
Sv (f ) = 2
+ 2 One of them is due feed forward path through compensation capacitor
3 gmb COX WLf gmb (7) (CC ) and the other is because of the pole frequency at 1/ Rf Cf . There are
The total IRN voltage of the proposed OTA is given in Eq. (8), which two zeroes on left-half-plane, placed near the non-dominant poles. This
comprises of both thermal and flicker noise components. Both noise improves the phase margin further and the locations of zeroes z d1,d2 are
components are expressed individually for comparison purpose. The given by
input-referred flicker noise voltage (Vn2,1/ f ) and thermal noise voltage
(CC−gm8 Rf Cf ) ⎧ 4gmo Rf Cf CC ⎫
(Vn2,th) are given in Eqs. (9) and (10), respectively. Zd1,d2 ≈ 1± 1+
Rf Cf CC ⎨ (CC−gm8 Rf Cf )2 ⎬ (14)
⎩ ⎭
Vn2,in = Vn2,th + Vn2,1/ f (8)
In Eqs. (12)–(14), R1 = (gds1 + gds2 + gm2−gm3 + gds3−gmb3)−1,R2=
2 2 2 (gds7 + gds8)−1,Rf = (gds6 + gds5 + gm5 + gds 4−gm4 )−1 and gmo =
Vn2,1/ f =
2 ⎡ Kfn gm1 + Kfp gm2 + Kfp gm3 ⎤ g +g 6
2 ⎢
COX fgmb1 ⎣ W1 L1 W2 L2 W3 L3 ⎥ gm8 + gm7 g + g m+6g mb .
⎦ (9) ds6 ds5 +gm5 −gds 4 m4

8KB T ⎡ gm1 + gm2 + gm3 ⎤ 4. Simulation results

Vn2,th =
3gmb1 ⎢
⎣ gmb1 ⎥
⎦ (10)
where Kfn,Kfp are the flicker noise coefficients for nMOS and pMOS
transistors, respectively, n is the sub-threshold slope factor, f represents
noise corner frequency, W and L are width and length of MOS device,
respectively, KB is the Boltzmann constant, COX is the gate-oxide ca-
pacitance per unit area and T is the temperature.
The IRN will be large for a bulk-driven OTA because its bulk
In order to validate the proposed OTA topology, the circuit was
designed and simulated in a UMC 65-nm CMOS process in Cadence
design environment. The threshold voltage of nMOS (Vthn ) and pMOS
(Vthp ) transistors is 0.38 V and 0.42 V, respectively, for the given CMOS
technology. The design of OTA was targeted for the following specifi-
cations: DC gain >60 dB, unity gain-bandwidth >500 kHz, phase margin
>60°, load capacitance of 20 pF, and supply voltage of 0.5 V. The

91
H. Veldandi, R.A. Shaik Int. J. Electron. Commun. (AEÜ) 90 (2018) 88–96

80

Magnitude (dB)
80
Magnitude (dB)

60
60
40 40

20 20

0 CL= 20pF CL= 40pF CL= 50pF 0

SS TT FF SNFP FNSP

0 0
Phase (deg)

Phase (deg)
−50 −50

−100
−100

−150 1 2 3 4 5 6
1 2 3 4 5 6
10 10 10 10 10 10 10 10 10 10 10 10
Frequency (Hz) Frequency (Hz)

Fig. 3. Simulated open-loop frequency response of the proposed OTA for dif- Fig. 4. Simulated open-loop frequency response of OTA for different corners of
ferent loads. process model.

dimensions of transistors and operating conditions are set to achieve the 10-4

specifications targeted.
The open-loop magnitude and phase characteristics of the proposed
amplifier at different load conditions is shown in Fig. 3 and outcome SS TT FF SNFP FNSP
parameters are summarized in Table 1. The CF stage enhances the
output stage transconductance and keeps the non-dominant pole at
10-5
higher frequencies, the OTA is expected to remain stable for larger
IRN (V/ HZ)

loads. Here, the OTA was able to drive a load capacitance of up to 50 pF

with only a small reduction in unity gain frequency. Also, it gives a
phase margin larger than 55°.
To observe the magnitude and phase characteristics due to process
variation, the corner simulations have been performed with a load ca- 10-6
pacitance of 20 pF and a supply voltage of 0.5 V. The magnitude and
phase responses for different corners are shown in Fig. 4. At typical
corner, the low frequency voltage gain was 72 dB and the phase margin
was 74° at a unity gain frequency of 680 kHz. To observe the effect of 100 101 102 103 104 105 106
various process corners on the noise performance, noise analysis has Frequency (Hz)
been performed and the response is shown in Fig. 5. From the simula- Fig. 5. Simulated open-loop input-referred noise frequency response of the
tion results, it can observed that the noise response is minimally de- proposed OTA for different process corners.
viated from the typical value for different process corners. At power line
frequency (i.e., at 50 Hz), the CMRR and PSRR is approximately equal
to 120 dB and 144 dB, respectively. The observed CMRR and PSRR
values at 50 Hz are good enough to reject the power line interference
for biomedical applications.
To observe the performance in closed-loop condition, the proposed
OTA is configured as voltage buffer with the help of resistive feedback
network [27]. In order to avoid the loading effect, the feedback re-
sistance should be large as compared to the output node resistance (i.e.,
R2 ). The buffer linear output swing range was observed by sweeping the
differential input voltage (Vid ). The DC characteristics of voltage buffer
is shown in Fig. 6 and it also consists of error plot Vout −Vid . It is clear
from Fig. 6 that the proposed design offers rail-to-rail output swing for
rail-to-rail input, where the output voltage is closer to input voltage
with negligible offset value.
To observe the settling behavior of the proposed OTA, a large step of
0.5 V at frequency of 10 kHz input pulse applied to the voltage buffer

Fig. 6. Simulated DC characteristics of the unity-gain amplifier

Table 1
DC gain, UGB, and phase margin with different load conditions.
Parameter Load capacitance CL
and the transient response is shown in Fig. 7. The differential slew-rate,
which corresponds to the time interval for the differential output vol-
20 pF 40 pF 50 pF tage to change from 10% to 90% of the input pulse, has been calculated
to be equal to 0.16 V/μs and the 1% settling time is equal to 10 μ s.
DC gain (dB) 72 74 74
The proposed OTA can be used as tunable transconductor for a wide
UGB (kHz) 680 655 630
Phase margin (deg.) 74 60 55 range of values by varying the gate bias voltage of input transistors M1A
and M1B . Bias voltages VBP and VBN are generated with the help of a

92
H. Veldandi, R.A. Shaik
0.5 SS
0.4 TT
FF
0.3
SNFP
0.2 FNSP
Vout (V)
0.1 Vin
0
−0.1
−0.2
−0.3
−0.4
−0.5
0 0.25 0.5 0.75 1 1.25 1.5 1.75
Time(s)
x 10
Fig. 7. Simulated transient response of the unity-gain amplifier for different
corners.
constant bias current IBias source and diode connected MOS transistors
as shown in Fig. 1. The change in IBias results in a corresponding var-
iation of VBP and VBN , and simulations results are shown in Fig. 8. The
change in VBN results in the variation of input transconductance and VBP
is employed for bulk-biasing of M2A and M2B , which keeps the input
stage resistance R1 always positive. The input node voltages V1P and V1N
will remain unchanged even with a change in bias current because of
cross-coupled connection.
4.1. PVT simulation
In order to verify the robustness and feasibility of the proposed
amplifier, simulation was performed for different PVT conditions. The
AC, DC, and transient analyses have been performed at different corners
of CMOS process such as SS, SF, TT, FS, and FF, for supply-voltages of
0.45 V, 0.5 V, and 0.55 V. The temperature has been varied from
−55 °C to 120 °C. It has been observed that the amplifier remains op-
erative and shows consistent performance under these circumstances.
The parameters of the proposed OTA for different PVT cases are
summarized in Table 2. It is clear from Table 2 that the proposed OTA is
PVT insensitive. Since, in all PVT cases the proposed OTA meets the
desired specifications i.e., DC gain > 65 dB, UGB > 500 kHz, and phase
margin > 60°. The OTA shows better performance in 65% cases, offering
high DC gain > 70 dB, UGB > 600 kHz, and phase margin > 70°.
The input stage and CF stage low-frequency gain mainly depends on
the positive feedback load resistance. During some PVT variations, the
net load resistance may become a negative value and this causes in-
stability. But for all the PVT conditions the proposed OTA provides high
gain and meeting all the desired specification without hlany stability
issue, since we left some space for the PVT variations and fabrication
Fig. 8. Performance parameters of the proposed OTA for different bias current.
Int. J. Electron. Commun. (AEÜ) 90 (2018) 88–96
errors while designing OTA and this results net resistance always a
positive value.
4.2. Monte Carlo simulation
Monte Carlo analysis were performed at room temperature for 1000
samples with 20 pF capacitive load and supply voltage 0.5 V. Which
shows the robustness of circuit against process variation. The small-
2
signal and large-signal performance parameters are observed from
−4
Monte Carlo simulation and results are summarized in Table 3. From
Table 3, it can observe the mean value (μ) of each parameter is closer to
its typical value and standard deviation (σ ) is very small compare to its
mean value. The ratio between σ and μ shows sensitivity OTA for
process variations and it is <5% for the proposed OTA parameters.
5. Comparison
The low voltage OTA performance parameters of prior works are
summarized in Table 4 and compared with that of proposed work. Even
though the supply voltage is reduced to 0.35 V, the proposed OTA ex-
hibits acceptable performance. The simulation parameters with the
supply voltage of 0.5 V and 0.35 V are listed in Table 4.
A common parameter namely figure-of-merit (FOM) is used to
compare the efficiency of different OTA topologies. It is clear that larger
the FOM implies better the performance. FOM is evaluated by con-
sidering the performance parameters of OTA such as DC gain, UGB and
slew rate at given load condition and the total power consumption. The
small-signal capability of OTA is calculated from IFOMS and FOMS .
These are function of UGB, load capacitance, total bias current and
power consumption. Similarly, the large-signal capability of OTA is
evaluated using IFOML and FOML . Where, FOMS / L evaluate the per-
formance in perspective of system level design and IFOMS / L address an
inspection at the transistor level. The FOM with respect to DC gain is
also calculated to estimate the efficiency of OTA and is denoted as
FOMDC. The transistor threshold-voltages of CMOS technology was in-
corporated to reflect the extent of low-voltage operation, and is denoted
as IFOMT.
From Table 4 it is clear that the proposed OTA exhibits better per-
formance compared to reported works [13,16,24,26,28,29]. The pro-
posed design gives a highest FOM for small and large-signal parameters
such as UGB and slew rate under low voltage environment. It is also
clear from Table 4, that the proposed design provides a minimum of
twice small-signal efficiency (FOMS and IFOMS) compared to the works
reported so far. Moreover, the large-signal performance (FOML and
IFOML) of the proposed design is more efficient compared to the designs
with supply voltage of 0.5 V or less [16,24,26,29].
The main objective of this work is to achieve high DC gain and large
driving capability with minimal power consumption. It can seen from
Table 4, the FOMDC of the proposed OTA is twice that of existing OTAs.
As moving towards sub-nanometer CMOS technologies, analog circuit
design becomes challenging and it is difficult to achieve better perfor-
mance with small quiescent current under low-voltage environment.
Here, we computed the IFOMT by incorporating technology parameter
such as threshold voltage and supply voltage employed for circuit de-
sign. The IFOMT of the proposed design is two to three times more than
others design. The FOM’s of the proposed OTA with low-supply voltage
of 0.35 V is 1.5 times more than that of 0.5 V supply. In summary, the
proposed topology exhibits better performance at supply voltage as low
as 0.35 V.
6. Conclusion
In this paper, a high gain pseudo-differential bulk-driven OTA has
been proposed. The proposed OTA is capable of operating under low
supply voltages and hence well suitable for sub-nanometer CMOS
93
H. Veldandi, R.A. Shaik Int. J. Electron. Commun. (AEÜ) 90 (2018) 88–96

Table 2
Simulated performance of the proposed OTA for PVT variations.
Process corner SS TT FF SNFP FNSP

VDD = 0.45-V
Temperature (°C) −55 27 120 −55 27 120 −55 27 120 −55 27 120 −55 27 120
DC gain (dB) 59.5 62.4 60.6 66 67 63.4 71 70.5 62 66.3 67 62.2 65.4 67 64
UGB (kHz) 675 644 508 719 664 517 730 670 518 702 647 507 733 680 526
Phase margin (deg) 69.4 70 71 72.3 72.6 73.2 72 75 75 724 73 73.6 72.6 72.4 74
Slew rate (↑) (V/ms) 72 114 134 106 137 158 124 158 176 101 140 160 105 136 158
Slew rate (↓) (V/ms) 72 114 134 106 137 158 124 158 177 102 141 161 105 136 159
CMRR (dB) @ DC 125 113 105 147 117 108 137 120 107 137 118 108 133 116 107
PSRR (dB) @ DC 104 119 113 117 135 110 139 120 103 115 137 111 114 133 114
ts+ (μ s) 1% 15.4 10.5 9.1 11.3 9 7.9 9.9 8 7.2 11.5 8.8 7.8 11.4 9 8
ts+ (μ s) 0.1% 18.5 13.3 11.5 14.1 11.2 10 12.1 9.8 9 14.2 10.9 9.9 14.3 11.2 10.1
ts− (μ s) 1% 15.4 10.5 9 11.3 9 7.9 9.8 7.9 7.1 11.5 8.7 7.8 11.4 9 7.9
ts− (μ s) 0.1% 18.6 13.3 11.5 14.1 11.2 10 12.1 9.9 9.1 14. 10.8 9.8 14.3 11.3 10.1
0.76 0.72 0.77 0.77 0.72 0.77 0.77 0.72 0.77 0.77 0.72 0.78 0.76 0.72 0.77
IRN at 10 kHz ( ) μV
Hz
Total current (μ A) 3.82 4.07 4.84 4.14 4.8 6.5 4.73 6.45 10.3 4 4.4 5.7 4.3 5.4 7.9

VDD = 0.5-V
Temperature (°C) −55 27 120 −55 27 120 −55 27 120 −55 27 120 −55 27 120
DC gain (dB) 66.3 67 64.5 71 72 68 77.7 76.2 66 72 72 66.2 72 72.4 69
UGB (kHz) 725 668 521 740 680 527 742 681 526 724 662 517 755 696 536
Phase margin (deg) 71.5 71.6 72 74 74 74.3 76.4 76 76 74 74 75 74 73.7 74
Slew rate (↑) (V/ms) 81 134 156 122 159 184 143 182 206 112 163 186 123 158 184
Slew rate (↓) (V/ms) 81.2 134 156 122 159 184 143 182 206 112 163 186 123 158 184
CMRR (dB) @ DC 140 117 109 138 121 112 140 126 111 145 122 111 135 121 112
PSRR (dB) @ DC 117 124 125 126 145 119 142 131 111 125 137 120 124 139 122
ts+ (μ s) 1% 17.2 11.7 10.1 10.6 10 8.7 11.1 8.9 7.9 13.2 9.7 8.6 13 10.1 8.7
ts+ (μ s) 0.1% 19.3 14.7 12.4 16 12.2 10.8 13.6 10.7 9.8 16 11.9 10.6 16.1 12.4 11
ts− (μ s) 1% 17.2 11.7 10.1 10.6 10 8.7 11.1 8.8 7.9 13.2 9.7 8.6 13 10.1 8.7
ts− (μ s) 0.1% 19.5 14.6 12.5 16 12.2 11 13.6 10.7 9.9 16 11.9 10.5 16.1 12.4 11
0.76 0.72 0.77 0.76 0.72 0.77 0.77 0.72 0.77 0.77 0.72 0.78 0.76 0.7 0.77
IRN at 10 kHz ( ) μV
Hz
Total current (μ A) 4.48 4.8 5.65 4.84 5.75 7.6 5.5 7.5 11.9 4.7 5.2 6.6 5.1 6.3 9.2

VDD = 0.55-V
Temperature (°C) −55 27 120 −55 27 120 −55 27 120 −55 27 120 −55 27 120
DC gain (dB) 71 71.4 69 78 78.7 73.4 87.5 88.6 70.1 78 78.2 71 78.3 79.7 75.5
UGB (kHz) 745 682 530 750 690 534 750 690 534 736 673 524 756 706 543
Phase margin (deg) 73.3 73 73.4 75.6 75.2 75 77.6 77.2 77 75.7 75.6 76 75.3 75 75
Slew rate (↑) (V/ms) 88 151 172 135 178 203 160 202 230 121 182 205 139 176 204
Slew rate (↓) (V/ms) 88 151 172 135 178 203 160 202 230 121 182 205 139 176 204
CMRR (dB) @ DC 136 121 113 141 128 118 148 138 115 144 128 116 139 128 119
PSRR (dB) @ DC 124 129 137 134 146 128 151 147 118 133 142 128 133 145 130
ts+ (μ s) 1% 17.5 11 9.6 12.2 9.3 8.3 10.3 10.6 7.6 12.6 9 8.1 12.2 9.3 8.3
+ μ 0.1% 19.5 15.4 14.1 16.5 13 12.5 14 11.6 11.5 16.7 12.6 12.1 16.5 13 13
ts ( s)
ts− (μ s) 1% 17.4 11.1 9.6 12.2 9.4 8.3 10.3 10.7 7.6 12.6 9 8.1 12.2 9.4 8.3
ts− (μ s) 0.1% 19.5 15.4 14.1 16.4 13 12.6 14 116 11.4 16.7 12.6 12.1 16.5 13.1 13.2
0.76 0.72 0.77 0.76 0.72 0.77 0.77 0.72 0.77 0.77 0.72 0.77 0.76 0.71 0.76
IRN at 10 kHz ( ) μV
Hz
Total current (μ A) 3.16 5.5 6.5 5.56 6.4 8.7 6.3 8.6 13.6 5.4 5.96 7.6 5.8 7.2 10.5

Table 3
technologies. A partial positive feedback technique is employed to
Monte Carlo simulation results. improve the gain of input stage. The cross forward stage at the output
stage improves the driving capability and over all DC gain of OTA. The
Parameter μa σb σ /μ Parameter μa σb σ /μ
proposed OTA is designed and simulated in a UMC 65-nm CMOS
DC gain (dB) 72.2 1.68 2.3% Slew rate (↑) 159.3 7.5 4.7% technology for load capacitance of 20 pF. Simulations were carried out
(V/ms) with different PVT conditions to verify the performance variation and
UGB (kHz) 678.6 15.1 2.2% Slew rate (↓ (V/ 159.3 7.5 4.7% to show robustness of OTA. For supply voltage of 0.35 and 0.5 V, the
ms) proposed OTA offers DC gain of 52 dB and 72 dB, phase margin was 69°
Phase margin 74 0.6 0.8% ts+ (μ s) 1% 10.01 0.435 4.3%
and 74° at the unity gain frequency of 570 kHz and 680 kHz, respec-
(deg.)
CMRR (dB) @ 122 1.8 1.5% ts+ (μ s) 0.1% 12.25 0.6 4.9% tively. The total power consumption was approximately 1.56 μ W and
DC approximately 3.03 μ W for the supply voltage of 0.35 V and 0.5 V, re-
CMRR (dB) @ 141.6 1.86 1.3% ts− (μ s) 1% 10 0.432 4.3% spectively. It was found that the proposed OTA can drive up to load
DC
capacitance of 50 pF without any stability issue and offering the unity
IRN at 10 kHz 0.72 0.003 0.4% ts− (μ s) 0.1% 12.25 0.6 4.9%
gain frequency of 617 kHz and phase margin 55°. In conclusion, the
( )
μV
Hz proposed OTA provides high DC gain and shows better FOM as com-
Total current 5.62 0.234 4.1% ts− (μ s) 0.1% 12.25 0.6 4.9% pared to existing OTAs.
(μ A)

a
Mean value.
b
Standard deviation.
94
H. Veldandi, R.A. Shaik Int. J. Electron. Commun. (AEÜ) 90 (2018) 88–96

Table 4
Comparison of the proposed OTA performance with reported low-voltage OTAs.
Parameter This work [13] [16] [24] [26] [28] [29]

Power supply 0.5 0.35 1.2 ±0.25 0.4 0.5 0.7 0.5 0.35
Single (S)/Differential (D) D D D D S S S
CMOS Technology (nm) 65 180 180 50 180 180 65
DC gain (dB) 72 55 65.5 112 60 67.8 57.5 46 43
UGB (MHz) 0.68 0.6 147 0.07 2.2 0.00326 3 38 3.6
Phase margin (deg) 74 68 81 53 56 69 60 76 56
Slew rate (↑) (V/μ s) 0.159 0.19 69.3 0.057 0.86 0.00084 1.8 43 5.6
Slew rate (↓) (V/μ s) 0.159 0.19 69.3 NA NA 0.00059 3.8 NA NA
IRN (μV/ Hz ) @ 10 kHz 0.72 0.72 5.9@ 1 Hz 0.7 0.12 0.56@ 1 kHz 0.1@ 1 MHz 0.938 0.926
CMRR (dB) @ DC 121 106 NA 133 80@ 5 kHz NA 19 35 46
PSRR (dB) @ DC 145 88 NA 119 NA NA 52.1 37 35
1% ts (+) (μ s) 10 7.5 0.02 NA NA 210 1.3 NA NA
1% ts (−) (μ s) 10 7.5 0.02 NA NA 301 1 NA NA
Load capacitance (pF) 20 5 15 20 15 20 3
Total current (μ A) 5.75∗∗∗ 4.15∗∗∗ 300 1.2∗∗∗ 60 0.052 36.3 364 48.6
Power (μ W) 3.03∗∗ 1.56∗∗ 360 0.724∗∗ 24 0.026 25.41 182 17
FOMDC 323,168 423,076 133,685 162,400 109,980 122,040 135,757 28,796 27,030
FOMS 4488 7692 2041 1450 1833 1880 2361 626 628.6
IFOMS 2365 2891 2450 875 733 940 1653 313 220
FOML 1049 2435 962 1179 716 484 1079 709 987
IFOML 553 915 1155 712 286 242 1542 354 345
IFOMT 3784 6608 2041 1750 872 857 1889 376 381

Note: Current consumption of bias stage is 0.3 μ A.

∗∗
Total power of OTA (including biasing stage power).
∗∗∗
Total current consumption of OTA (excluding bias stage).
DC gain × UGB × CL dB × MHz × pF CL MHz × pF CL MHz × pF
FOMDC = ⎡ ⎤; IFOMS = UGB × Total current ⎡
; FOMS = UGB × Power .
Power ⎣ mW ⎦ ⎣ mA ⎤ ⎦ ⎡
⎣ mW ⎤ ⎦
Vthn + |Vthp | UGB × CL MHz × pF CL V pF CL V pF
IFOMT = Total current ⎡
; IFOML = Slew rate × Total current ⎡ μs × mA ⎤; FOML = Slew rate × Power ⎡ μs × ⎤.
VDD ⎣ mA ⎤ ⎦ ⎣ ⎦ ⎣ mW ⎦

Acknowledgment 2014;68(1):64–72. http://dx.doi.org/10.1016/j.aeue.2013.08.019.

The authors would like to thank Department of Electronics and
Information Technology (DeitY), Government of India, for providing
the software resources under the Special Manpower Development
Program (Phase III and C2SD). The authors would also like to thank Dr.
Arun Tej M. for his useful inputs to improve this article. The authors
would like to express sincere thanks to reviewers for their valuable
comment.
Appendix A. Supplementary material
Supplementary data associated with this article can be found, in the
online version, at http://dx.doi.org/10.1016/j.aeue.2018.03.033.
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