EC101 BECE – Question Bank (more questions will be added)

Q.
No.
Module 1
1. Write down the Einstein equation that establishes relationship among diffusion constant, mobility and
voltage-equivalent of temperature.
2. Why does diffusion current occur in semiconductor?
3. Explain how space charge region is formed in a PN junction. Substantiate your answer with suitable
diagram.
4. Write down the expressions of electron and hole current density in a PN junction having both carrier
gradient and electric field across it?
5. In general, how many maximum components of conduction current can you have in a PN junction? (a) 1,
(b) 2, (c) 3, (d) 4. What are they? Explain each of them.
6. Define conductivity of a semiconducting material in terms of electronic charge, carrier concentration and
carrier mobility.
7. A semiconductor with cross-sectional area of A and length of L contains N electrons (n denotes electron
concentration). Define its charge density. (a) N/A (b) N/LA (c) n/LA (d) nq.
8. 𝑞𝑛μn represents (a) resistivity, (b) permittivity, (c) conductivity, (d) none of them.
9. Derive the Boltzmann Equation of kinetic gas theory.
10. Write down the Boltzmann Equation of kinetic gas theory with hole and explain each term used in it.
11. Write down the Boltzmann equation of kinetic gas theory with electron and explain each term used in it.
12. Derive the expression of built-in potential of PN junction.
13. Potential difference built at the space charge region of a PN junction is known as (a) built-in potential (b)
contact difference of potential (c) barrier potential (d) all of them.
14. Write down the expressions of built-in potential (Vbi) and explain each term used in it.
15. The intrinsic carrier concentration (ni) in germanium at room temperature is 2.5×1019/m3. If the doping
concentration of both type materials of PN junction diode are the same and equals 1021/m3 (i.e., NA = ND
=1021/m3), obtain the values of built-in potential of germanium diode. (a) 0.026 V. (b) 0.191 V. (c) 0.191
mV. (d) 26 mV.
16. The intrinsic carrier concentration ni in silicon at room temperature is 1.5×1016/m3. If the doping
concentration of both type materials of PN junction diode are the same and equals 1021/m3 (i.e., NA = ND
=1021/m3), obtain the values of built-in voltage of silicon diode. (a) 0.026 V. (b) 0.191 V. (c) 0.5745 V.
(d) 26 mV.
17. Define electric flux density, D. Why is the derivative of flux density, D, not constant in depletion region
of PN junction?
18. In the depletion layer of a PN junction, derivative of flux density, D or change in D along x is directly
proportional to (a) density of charge centre expressed in C/m3, (b) ρcharge (c) nq (d) all of them.
19. Derive 1-Dimensional form of Poisson equation.
20. Why are n-type and p-type regions electroneutral?
21. Write down the expressions of depletion layer width (Wp) of a PN junction for ND >> NA and explain each
term used in it.
22. Write down the expressions of depletion layer width (Wn) of a PN junction for NA >> ND and explain each
term used in it.
23. Derive the depletion-layer capacitance of a PN junction.
24. Write down the expressions of PN junction capacitance at zero bias.
25. The capacitance of an abrupt PN junction at zero bias is 0.4 fF. Estimate the junction capacitance (C d) if
the junction is reversed biased with −1 V. Assume that the built-in potential of the junction is 0.7 V.
26. Write the generalized expression of a PN junction capacitance and explain it for all possible biasing
conditions.
27. Draw the plot of junction capacitance with respect to bias voltage for grading coefficient m = 0.5 and
0.33.
28. A (varactor) diode with a linearly graded doping profile has a junction capacitance of 50 pF when no bias
 is applied to the diode. Determine the junction capacitance for the silicon diode when the reverse bias
applied to the diode is of 8 V.
29. A (varactor) diode with a linearly graded doping profile has a junction capacitance of 18 pF when the
reverse bias applied to the diode is 4 V. Determine the junction capacitance if the reverse bias applied to
the silicon diode is increased to 8 V.
30. A radio receiver tunned circuit uses varactor diodes, whose capacitance can be varied from 4 pF to 40 pF,
and an inductance of 12.5 mH. Determine the tuning range of the circuit.
31. A mobile carrier-free region exists near the PN junction, which is called (a) depletion region, (b) space-
charge region, (c) transition region (d) all of them.
32. Why does diffusion current occur in semiconductor?
33. Explain how space charge region is formed in a PN junction. Substantiate your answer with suitable
diagram.
34. Explain the mechanisms behind the formation of space charge region.
35. Is it possible to measure contact difference of potential (V0)? If yes, explain how to measure. If not,
explain why?
36. For the series diode (with γ = 0. 7V) configuration of Fig. shown below, determine VD, VR, and ID.

37. For the series diode (with γ = 0. 7V) configuration of Fig. shown below, determine VD. (a) 0.7 V. (b) 0.3
V. (c) 8 V. (d) 7.3 V.

38. For the series diode (with γ = 0. 7V) configuration of Fig. shown below, determine VR. (a) 7.3 V. (b) 0.3
V. (c) 8 V. (d) 7.3 V.

39. For the series diode (with γ = 0. 7V) configuration of Fig. shown below, determine ID. (a) 3.32 mA. (b)
0.3 mA. (c) 3.32 μA. (d) 7.3 mA.
40. By forward biasing a PN junction can we reduce the barrier to zero? If no, explain why?
41. The ideality factor, η in a diode current equation varies depending on the material and temperature
between (a) 1 and 2, (b) 2 and 3, (c) 3 and 4, (d) none these.
42. Show forward and reverse bias connection of a PN diode. Draw the volt-ampere characteristic of an ideal
p-n diode.
43. Draw the volt-ampere characteristic for a germanium diode with γ = 0.1 V to show the order of magnitude
of currents (expanded scale for reverse current).
44. For the series diode (with γ = 0. 7V) configuration of Fig. shown below, determine VD, VR, and ID.

45. For the series diode (with γ = 0. 7V) configuration of Fig. shown below, determine VD. (a) 0.3 V. (b) 8 V.
(c) 8 V. (d) 7.3 V.

46. For the series diode (with γ = 0. 7V) configuration of Fig. shown below, determine VR. (a) 0 V. (b) 0.3 V.
(c) 8 V. (d) 7.3 V.

47. For the series diode (with γ = 0. 7V) configuration of Fig. shown below, determine ID. (a) 0.3 mA (b) 0
mA. (c) 3.32 μA. (d) 7.3 mA.
48. Consider a germanium p-n junction at 300°K with doping concentration NA = 1.5 × 1018 cm−3 and ND = 2
× 1015 cm−3 in the p and n sides of the junction, respectively. Determine the contact potential across the
junction. Assume that intrinsic carrier concentration of germanium ni = 2.5 ×1013 cm−3 at 300° K.
49. The output voltage through the following circuit is (a) 20 V. (b) 10 V. (c) 9.5 V (d) 5 V.

50. Draw the volt-ampere characteristic of a germanium diode (1N270) with γ = 0.2 V and silicon diode
(1N3605) with γ = 0.6 V at 25℃.
51. The forward voltage beyond which current of a PN junction diode rises very rapidly is called (a) cutin
voltage, (b) offset voltage, (c) break-point, or threshold, voltage (d) all of them.
52. Write down the general equation of diode current. Explain each symbol used in it.
53. A germanium diode has a reverse saturation current of 10−8 A. Calculate the PN junction diode current for
a forward bias of 0.4 V at room temperature. (a) 102.6 mA. (b) 48 mA. (c) 48 μA. (d) 102.6 μA.
54. A germanium diode has a reverse saturation current of 10−6 A (i.e., 1 μA). Calculate the PN junction diode
current for a forward bias of 0.3 V at room temperature. (a) 102.6 mA. (b) 102.6 μA. (c) 102.6 nA. (d) 48
μA.
55. A silicon diode has a reverse saturation current of 10−8 A (i.e., 10 nA). Calculate the PN junction diode
current for a forward bias of 0.8 V at room temperature. (a) 102.6 mA. (b) 48 mA. (c) 48 μA. (d) 102.6
μA.
56. The volt-ampere relationship of diode contains the temperature implicitly in the two symbols. What are
those? Explain why diode current depends on temperature.
57. The theoretical variation of reverse saturation current (I0) with T for silicon is (a) 8 percent/℃ (b) 11
percent/℃ (c) 5 percent/℃ (d) 7 percent/℃.
58. The theoretical variation of reverse saturation current (I0) with T for germanium is (a) 8 percent/℃ (b) 11
percent/℃ (c) 5 percent/℃ (d) 7 percent/℃.
59. The reverse saturation current doubles when the junction temperature increases by (a) 1℃. (b) 2℃. (c) 5℃. (d)
10℃.
60. Define dynamic conductance and resistance. Write down and explain their expressions. At room
temperature and for η = 1, compute the dynamic resistance of a diode for a forward current of 26 mA.
61. The current flowing through a p-n junction Si-diode is 60 mA for a forward bias of 0.9 volt at room
temperature 300K. The static and dynamic resistance of the diode are (a) 15 ohm and 0.43 ohm. (b) 30
ohm and 0.43 ohm. (c) 15 ohm and 0.87 ohm. (d) 30 ohm and 0.87 ohm.
62. Find dynamic resistance of a germanium PN junction diode at a forward current of 2 mA. Assume VT =
 kT/q = 25 mV.
63. Find dynamic resistance of a germanium PN junction diode at room temperature (300K) for a forward
current of 2 mA. (a) 30 Ω. (b) 15 Ω. (c) 13 Ω. (d) 14 Ω.
64. Find dynamic resistance of a germanium PN junction diode at 400K for a forward current of 2 mA. (a) 30
Ω. (b) 45 Ω. (c) 17.5 Ω. (d) 15 Ω.
65. Determine ac resistance for a germanium semiconductor diode having a forward bias of 200 mV and
reverse saturation current of 1 μA at room temperature.
66. Draw the piecewise linear characteristic of a semiconductor diode and explain it.
67. What is the value of dynamic resistance (r or Rf), for current swing from cutoff to 10 mA of a germanium
diode with Vγ = 0.2 V? (a) 5 Ω (b) 10 Ω (c) 15Ω (d) 20 Ω.
68. What is the value of dynamic resistance (r or Rf), for current swing from cutoff to 10 mA of a silicon
diode with Vγ = 0.6 V? (a) 5 Ω (b) 10 Ω (c) 15 Ω (d) 20 Ω.
69. Determine the diode voltage, diode current and voltage across 10 Ω resistor in the series diode
configuration.
70. When a P-N junction is reverse biased, the junction capacitance is termed as (a) space-charge capacitance
(b) transition capacitance, (c) depletion-region capacitance or barrier capacitance (d) all of them.
71. When a P-N junction is forward biased, the junction capacitance is termed as (a) space-charge capacitance
(b) transition capacitance, (c) depletion-region capacitance or barrier capacitance (d) diffusion or storage
capacitance (CD).
72. The P-N junction capacitance is called diffusion or storage capacitance (CD) if the junction is (a) forward
biased. (b) reversed biased. (c) unbiased. (d) none of these.
73. The P-N junction capacitance is called transition capacitance (CT) if the junction is (a) forward biased. (b)
reversed biased. (c) unbiased. (d) none of these.
74. Show that for a forward bias greater than a few tenths of a volt the diffusion capacitance (CD) of a
germanium diode is given as a product of mean lifetime and dynamic conductance.
75. Show that for a forward bias greater than a few tenths of a volt the diffusion capacitance (CD) of a
germanium diode is given as a ratio of mean lifetime to dynamic resistance.
76. Draw the V-I characteristic of a Zener diode. Draw the schematic of the circuit in which such a diode is
used to regulate the voltage across load resistance RL against changes due to variations in load current and
supply voltage. Briefly explain its operation to do so.
77. When the current through a Zener diode increases by a factor of 2, the voltage across its terminals (a) Is
halved. (b) Is doubled. (c) Is practically unchanged. (d) None of these.
78. How many types of breakdowns are there.
79. Explain avalanche breakdown mechanism with suitable diagram.
80. Explain Zener breakdown mechanism with suitable diagram.
81. Zener breakdown takes place in diodes (a) at low reverse voltage when both the N-type and P-type
regions are heavily doped, (b) at high reverse voltage when both the N-type and P-type regions are
heavily doped, (c) at low reverse voltage when both the N-type and P-type regions are lightly doped, (d)
none of these.
82. A diode is connected in series with a load resistance of 160 Ω across a DC supply voltage of 10 V. Draw a
DC load line.
83. Draw the basic circuit diagram of half-wave rectifier. Draw the input (transformer sinusoidal secondary
voltage vi and diode and load current i. Briefly explain its operation.
84. Derive the expression of average current of half-wave rectifier.
85. Derive the expression of average current of half-wave rectifier in terms of peak value of the secondary
voltage and load resistance.
86. Derive the expression of average voltage of half-wave rectifier in terms of peak value of the secondary
voltage.
87. Derive the expression of rms current of half-wave rectifier in terms of peak value of the secondary
voltage, load resistance and forward diode resistance.
88. Derive the expression of rms value of output voltage of half-wave rectifier in terms of peak value of the
secondary voltage.
89. Derive the expression of Form Factor and Peak Factor of half-wave rectifier and write down their
numerical values.
90. The output frequency is the same as input frequency for a half-wave rectifier (True/False).
91. Define Rectification Efficiency. Derive the expression of Rectification Efficiency of half-wave rectifier in
terms of forward diode resistance (or static resistance) RF and load resistance RL.
92. Prove that the maximum possible rectification efficiency for a half-wave rectifier is 40.6% if forward
diode resistance (or static resistance) RF is neglected.
93. What is the efficiency of half-wave rectifier if RL ≫ Rf (a) 12%. (b) 22%. (c) 40.6%. (d) 81.2%.
94. Define Form Factor for half-wave rectifier. Define Ripple Factor. Derive the expression of Ripple Factor
of half-wave rectifier in terms of Form Factor Kf.
95. Define Transformer Utilization Factor (TUF). Derive the expression of Transformer Utilization Factor
(TUF) of half-wave rectifier in terms of forward diode resistance (or static resistance) RF and load
resistance RL.
96. Define Regulation. Derive the expression of Percentage Regulation. What should be value of Percentage
Regulation for an ideal power supply.
97. Draw the circuit diagram of centre-tap full-wave rectifier. Draw the waveforms of individual diode
currents (i1 & i2) and load current (i). Briefly explain its operation.
98. Draw the circuit diagram of centre-tap full-wave rectifier. Draw the input and output voltage/current
waveforms. Briefly explain its operation.
99. Define Peak Inverse Voltage (PIV). What the magnitude of the peak inverse voltage for the half-wave
rectifier and full-wave rectifier. Explain with respect to the half-wave and full-wave rectifier circuit.
100. Draw the circuit diagram of full-wave bridge rectifier. Briefly explain its operation. Advantage of full-
wave bridge rectifier over centre-tab full-wave rectifier.
101. Draw the circuit diagram of full-wave bridge rectifier. Draw input voltage waveform and output
voltage/current waveforms. Briefly explain its operation.
102. Derive the expression of Peak Current (Imax) of full-wave rectifier in terms of forward diode resistance (or
static resistance) RF and load resistance RL.
103. Derive the expression of average current (Idc) (or Iavg) of full-wave rectifier.
104. Assume Input (Vin) = Vmsinωt. In a full wave diode rectifier with R load, the average value of load
current is given by (a) Vm/R. (b) 2Vm/R. (c) Vm/πR. (d) 2Vm/πR.
105. Derive the expression of average voltage of full-wave rectifier in terms of Imax and RL.
106. Derive the expression of rms current of full-wave rectifier in terms of peak value of the secondary current
Imax.
107. Derive the expression of rms value of output voltage of full-wave rectifier in terms of peak value of the
secondary current Imax and RL.
108. Derive the expression of Form Factor and Peak Factor of full-wave rectifier and write down their
numerical values.
109. The output frequency is the same as input frequency for a full-wave rectifier (True/False).
110. For an input signal of 50 Hz, 230V is applied to a full-wave rectifier, calculate the output frequency of the
rectifier. (a) 50 Hz. (b) 100 Hz. (c) 25 Hz. (d) 50 rad/sec.
111. For a 50 Hz ac input, the ripple frequency at the output that a full-wave rectifier produces is equal to (a)
25Hz. (b) 50Hz. (c)100Hz. (d)200Hz.
112. Define Rectification Efficiency. Derive the expression of Rectification Efficiency of centre-tap wave
rectifier and full-wave bridge rectifier in terms of forward diode resistance (or static resistance) RF and
load resistance RL.
113. Define Form Factor for full-wave rectifier. Define Ripple Factor. Derive the expression of Ripple Factor
of full-wave rectifier in terms of Form Factor Kf and write down the numerical values of Form Factor and
Ripple Factor.
114. Define Transformer Utilization Factor (TUF) for centre-tap transformer. Derive the expression of
Transformer Utilization Factor (TUF) of primary winding of centre-tap full-wave rectifier in terms of
forward diode resistance (or static resistance) RF and load resistance RL and write down the numerical
value of TUF of primary winding with RL >> RF.
115. Write down the expression of Transformer Utilization Factor (TUF) of full secondary winding of centre-
tap full-wave rectifier and average TUF and write down the numerical value of TUF of full secondary
winding and average TUF.
116. Merits and demerits of Full -Wave (FW) Rectifier and Half-Wave Rectifier.
117. Sketch the diode current i and output voltage vo, in a half-wave capacitor-filtered rectifier. Define Cutout
point, Cutin point and ripple voltage (Vr) of a half-wave capacitor-filtered rectifier. Show them on the
sketch.
118. Write down the expression of the average or dc value of output voltage, Vdc (or Vavg) of a half-wave
capacitor-filtered rectifier in terms maximum load voltage (Vlmax) and ripple voltage (Vr). Prove that the
ripple voltage (Vr) of a half-wave capacitor-filtered rectifier is directly proportional to load current Idc or
Iavg.
119. Determine the ripple voltage (Vr) of a half-wave capacitor-filtered rectifier for C= 1 μF, frequency of the
input voltage obtained from secondary winding of transformer f = 1 MHz and average current (Iavg) or dc
load current (Idc) = 2 mA. (a) 2 mV. (b) 4 mV. (c) 6 mV. (d) 8 mV.
120. Determine the ripple voltage (Vr) of a half-wave capacitor-filtered rectifier for C= 2 μF, frequency of the
input voltage obtained from secondary winding of transformer f = 1 MHz and average current (Iavg) or dc
load current (Idc) = 2 mA. (a) 1 mV. (b) 4 mV. (c) 6 mV. (d) 8 mV.
121. Derive the expression of ripple factor (𝛾) of a half-wave capacitor-filtered rectifier.
122. Sketch the diode current i and output voltage vo, in a full-wave capacitor-filtered rectifier. Define Cutout
point, Cutin point and ripple voltage (Vr) of a full-wave capacitor-filtered rectifier. Show them on the
sketch.
123. Write down the expression of the average or dc value of output voltage, Vdc (or Vavg) of a full-wave
capacitor-filtered rectifier in terms maximum load voltage (Vlmax) and ripple voltage (Vr). Prove that the
ripple voltage (Vr) of a full-wave capacitor-filtered rectifier is directly proportional to load current Idc or
Iavg.
124. Derive the expression of ripple factor (𝛾) of a full-wave capacitor-filtered rectifier.
125. A full-wave rectifier produces an rms voltage of 10 V from a 50 Hz line source and feeds a resistive load
of 1100 Ω. If the filter uses a capacitance of C = 50μ, find dc voltage, voltage regulation and ripple output
voltage.
Module 2
126. Suppose an electron is somehow “injected” from outside into the right side of the depletion region of a
reversed biased pn junction. What happens to a minority carrier? Explain.

127. How an NPN BJT is biased in forward active mode? Give an example.
128. Explain operation of NPN BJT.
129. Explain the Basic Transistor Action in a NPN BJT.
130. Which statement about a BJT is valid. (a) Emitter doping level is smaller than that of base (b) Base
doping level is greater than that of connector (c) Collector doping level is greater that of Emitter (d) None
of the above.
131. Do the input circuit [i.e., base-emitter junction (JE)], and output circuit [i.e., base-collector junction (JC)]
offer the same level (value) of resistance? If not, why?
132. Why are NPN and PNP devices called transistors?
133. Why are NPN and PNP transistors called bipolar junction transistors (BJT)?
134. Can two discrete diodes connected back-to-back work as a transistor?
135. Why is NPN BJT preferred to PNP BJT?
136. Draw a structure of a PNP transistor and write down its terminal currents and internal currents with
appropriate direction when it is properly biased. Explain the reason for the flow of such currents.
137. Define large-signal current gain 𝛼 of a common base transistor. Write down the complete expression of IC
for any VC and IE.
138. Bias a PNP BJT in CB configuration (draw your biasing scheme and briefly explain it) and give a
physical explanation of why the transistor acts as an amplifier.
139. Define the small-signal short-circuit current transfer ratio, or gain, or current amplification factor, i.e.,
𝛼 ′ (= −𝛼) of a BJT.
140. Established relationship between alpha factor (α) and beta (β) of a BJT.
141. Define DC Current gain αdc and small signal current gain αac.
142. For a transistor if IE = 1 mA and α = 0.98, determine the value of IB.
143. In a CB configuration of a PNP transistor the current amplification factor α = 0.988. Determine the value
of base current IB if emitter current IE = 1.2 mA. Neglect collector leakage current.
144. For a given transistor αdc = 0.98. Calculate βdc and IB.
145. For a PNP BJT the base current and collector current are respectively 45 μA and 5.45 mA. Determine (1)
values of transistor α, β and IE; (ii) Base current required to make collector current of 10 mA.
146. Explain the Input Characteristics of CB Configuration with suitable curve.
147. Explain the Output Characteristics of CB Configuration with suitable curve.
148. Draw the Output Characteristics of CB Configuration of PNP BJT with suitable curve and indicate the
Active Region, Saturation Region and Cutoff Region. Briefly explain them.
149. A transistor is connected in CB configuration. When the emitter voltage is changed by 200 mV, the
emitter current changes by 5 mA. During this variation, the collector-to-base voltage is kept fixed.
Calculate the dynamic input resistance of transistor.
150. In a grounded base configuration the voltage drop across load resistance of 4 kΩ is 3 V. Determine base
current. α = 0.96.
151. The current gain of an NPN transistor α = 0.98. It is connected in CB configuration and gives reverse
saturation current ICO = 10 μA. Find the base and collector currents for an emitter current of 2 mA.
152. In a CB configuration the emitter current is 1.6 mA. The collector current with emitter circuit open is 10
μA. Determine the total collector current assuming α = 0.98.
153. The reverse saturation current of an NPN transistor in a CB circuit is 12.5 μA. For current of 2 mA,
collector current is 1.97 mA. Determine the current gain and base current.
154. What is base narrowing or base-width modulation or the Early effect? Substantiate your answer with
suitable curve/diagram.
155. Bias a PNP BJT in CE configuration with appropriate bias voltages and load resistance R L. Draw your
biasing scheme and briefly explain it.
156. Bias a NPN BJT in CE configuration with appropriate bias voltages and load resistance RL. Draw your
biasing scheme and briefly explain it.
157. Explain the Input Characteristics of CE Configuration of PNP BJT with suitable curve.
158. Explain the Input Characteristics of CE Configuration of NPN BJT with suitable curve
159. Define dynamic input resistance (rin) of a p-n-p germanium transistor connected in CE configuration.
160. Explain the Output Characteristics of CE Configuration with suitable curve.
161. Draw the Output Characteristics of CE Configuration of NPN BJT with suitable curve and indicate the
Active Region, Saturation Region, and Cutoff Region. Briefly explain them.
162. A change of 250 mV in base-emitter voltage causes a change of 1 mA in the base current. Determine the
dynamic input resistance.
163. Increase in collector-emitter voltage from 5 V to 10 V causes an increase in collector current from 5 mA
to 5.8 mA. current. Determine the dynamic output resistance.
164. In a CE configuration, the collector supply voltage is 10 V. When a resistor RC = 1 kΩ is connected in the
collector circuit, the voltage drop across it is 0.5 V. For α = 0.98, determine the collector emitter voltage
and the base current.
165. IE = 5 mA, IC = 4.95 mA, ICEO = 200 μA. Calculate βdc and leakage current ICBO.
166. In an NPN transistor, α = 0.995, IE = 10 mA and ICO = 0.5 μA. Determine the values of IC, IB, β and ICO.
167. Find the transistor currents in the circuit of Fig. 5-12a. A silicon transistor with β = 100 and ICO = 20 nA =
2×10−5 mA is under consideration. (b) Repeat part a if a 2-K emitter resistor is added to the circuit, as in
Fig. 5-12b.
168. If hFE = 100 of the BJT shown in the circuit (as indicated in Fig. 5-18), determine whether or not the
silicon transistor is in saturation and find IB and IC. (b) Repeat with the 2K emitter resistance added.

Fig. 5-18
169. Bias a PNP BJT in CC configuration with appropriate bias voltages and load resistance R L. Draw your
biasing scheme and briefly explain it.
170. Bias a NPN BJT in CC configuration with appropriate bias voltages and load resistance R L. Draw your
biasing scheme and briefly explain it.
171. How do you establish the operating point of a common-emitter circuit? If the operating point is not
established properly what will happen?
172. What factors decide the selection of an operating point or Q point?
173. Consider the fixed bias circuit shown in Fig. 8.1 where an n-p-n silicon transistor with β = 90 is used with
VCC = 15 V, RC = 2 K and Rb = 1 M. Assume VBE = 0.6 V. (a) Find the quiescent point (or Q-point) of the
circuit, and (b) Obtain the equation for the ac load line for RL = 1 K.
174. In CE configuration (Fig.8.32) collector supply voltage VCC = 10 V, load resistance RC is 8 kΩ. Draw dc
load line. Determine the operating point Q for zero signal if base current is 15 μA and β is 40.
175. Despite the tremendous strides that have been made in the technology of the manufacture of
semiconductor devices, transistors of a particular type still come out of production with a widespread in
the values of some parameters such as β. If the transistor of the fixed-bias circuit shown below is replaced
with the same type what will happen to the operating point or Q point. Draw the load line and Q points to
explain the same.

176. Explain bias instability of BJT used in fixed-bias circuit shown below for the variation in temperature.

177. Define the Stability Factor S. What are the two techniques used to maintain the operating point stable?
178. Derive the expression of stability factor of the BJT used in the fixed-bias circuit shown below and
comments on it.

179. Derive the expression of stability factor of the BJT used in the collector feedback-bias circuit shown
below and comment on it.
180. The transistor in Fig. shown below is a silicon-type 2N708 with β = 50, VCC = 10 V, and RC = 250 Ω. It is
desired that the quiescent point be approximately at the middle of the load line. Find Rb and calculate S.

181. (a) Schematize a self-biasing or emitter bias circuit. (b) Also schematize the simplified version of the
circuit after simplifying the base circuit using Thevenin’s theorem. (c) Self-Bias or Emitter Bias circuit is
used to establish a stable operating point. Justify/validate the statement. Convince with the physical
reason that a Self-Bias or Emitter Bias circuit can establish a stable operating point. Write physical reason
for an improvement in stability with a Self-Bias or Emitter Bias circuit.
182. Justify/validate the statement that “Self-Bias or Emitter Bias circuit is used to establish a stable operating
point”. Convince with the physical reason that a Self-Bias or Emitter Bias circuit can establish a stable
operating point.
183. Write physical reason for an improvement in stability with a Self-Bias or Emitter Bias circuit.
184. Write detailed analysis of the Self-bias or Emitter bias circuit.
185. What are the three sources of instability of IC? (a) ICO, (b) β, (c) VBE, (d) All of them.
186. What are the three sources of instability of collector current IC?
187. Tabulate the values of silicon transistor parameters such as ICO, β and VBE at −65℃, 25℃ and 175℃.
188. Tabulate the values of germanium transistor parameters such as ICO, β and VBE at −65℃, 25℃ and 175℃.
189. The value of silicon transistor parameters such as ICO at room temperature (i.e., 25℃) is (a) 0.1 nA, (b) 1
nA, (c) 0.1 μA, (d)1 μA.
190. The value of germanium transistor parameters such as ICO at room temperature (i.e., 25℃) is (a) 0.1 nA,
(b) 1 nA, (c) 0.1 μA, (d)1 μA.
191. Define stability factor S, which is related to the reverse saturation current and derive expression of the
same.
192. Define stability factor 𝑆 ′ , which is related to the base emitter voltage VBE and derive expression of the
same.
193. A silicon transistor whose common-emitter output characteristics are shown in Fig. 9-6b is used in the
 circuit of Fig. 9-5a, with VCC = 22.5 V, Rc = 5.6 K, Re = 1 K, R2 = 10 K, and R1 = 90 K. For this transistor,
β = 55. Find the Q point (a) graphically (b) from the known value of β (c) Calculate S.

Fig. 9-6

Fig. 9-5
194. What are the advantageous characteristics FET over the conventional transistors?
195. Draw the basic structure of an n-channel junction field-effect transistor (JFET). Mark its terminals and
briefly explain its operation.
196. Explain how JFET channel and channel current is affected by the reverse gate bias.
197. Draw the common-source circuit with an n-channel JFET.
198. Draw the current-voltage (I-V) output characteristics of common-source circuit with an n-channel JFET
and briefly explain.
199. Schematize a practical n-type JFET structure and briefly explain it.
200. Define Pinch-off Voltage of an n-type JFET and derive its expression.
201. Derive the expression of channel width of an n-type JFET.
202. For an n-channel silicon FET with a = 3×10−4 cm and ND = 1015 electrons/cm3, find (a) the pinch-off
voltage and (b) the channel half-width for VGS = ½ VP and ID = 0.
203. Derive the Volt-Ampere (V-I) Characteristic of an n-type JFET
204. Derive the expression of ON Resistance rd,ON from the Volt-Ampere (V-I) Characteristic of an n-type
JFET.
205. Write down the current expression of an n-type JFET for the gradual channel pinch-off condition and
explain the same.
206. Explain the pinch-off region of an n-type JFET and schematize the channel structure after pinch-off.
207. Write down the expression of saturation drain current of an n-type JFET.
208. Explain the cutoff region of an n-type JFET.
209. Draw the basic structure of a p-channel enhancement MOSFET. Mark all the regions and terminals of the
same.
210. Describe the principle of operation of a p-channel enhancement MOSFET.
211. Schematize the drain characteristics (ID-VDS) of an p-channel enhancement MOSFET.
212. Draw the transfer curve (i.e., ID-VGS) (for VDS = 10 V) of a p-channel enhancement-type MOSFET.
213. What are the three methods used to lower the magnitude of VT of MOSFET.
214. Draw the basic structure of a n-channel depletion-type MOSFET. Mark all the regions and terminals of
the same.
215. Schematize the drain characteristics (ID-VDS) of an n-channel MOSFET and show enhancement and
depletion modes.
216. Draw the transfer curve (i.e., ID-VGS) (for VDS = 10 V) of a n-channel MOSFET and show enhancement
and depletion modes.
217. The most important or key feature of a MOSFET is its (a) channel length, (b) drain diffusion area, (c)
source diffusion area, (d) junction depth.
218. Write down the nMOS current model in linear region.
219. Write down the nMOS current model in saturation region.
220. Write down the nMOS current model in saturation region taking channel-length modulation into account.
221. The condition of an n-MOSFET in saturation region is (a) VDS < VGS – Vt. (b) VDS < Vt. (c) VDS ≥ VGS –
Vt. (d) None of these.
222. Find the region of operation of the p-MOSFET.

223. Find the region of operation of the n-MOSFET.

224. The source voltage, threshold voltage and gain factor are given. What is the highest voltage that can be
applied to the drain while the device operates in saturation? Neglecting the channel length modulation
effect (i.e., λ = 0), find the drain current of Fig. (a) for VD = −0.4 V and drain current of Fig. (b) for VD =
−5V.

225. The nMOSFET shown in the figure operates in (a) cut off region, (b) triode region, (c) moderate inversion
region, and (d) saturation region.
226. Write down the expression of threshold voltage of a MOSFET and briefly explain each symbol used in it.
227. Draw the output characteristic curves of the n-MOSFET and briefly explain it.
228. Draw the transconductance characteristic of an nMOSFET as a function of the source-bulk voltage, VSB.
229. What are channel length modulation and Early voltage?
230. Draw the simplest low-frequency small-signal model of an n-MOSFET.
231. Draw the low-frequency small-signal model of an n-MOSFET taking channel length modulation effect
into account.
232. Draw the low-frequency small-signal model of an n-MOSFET taking channel length modulation and body
effect into account.
233. Transconductance (gm) of a MOSFET is given by (a) 2IDS/VOV, (b) 2IDS/(VDS-Vt), (c) IDS/2(VGS-Vt), (d)
2IDS/(VBS-Vt).
Module 3
234. What is a Differential Amplifier?
235. Define differential-mode input voltage, common-mode Input voltage, differential-mode voltage gain and
common-mode voltage gain.
236. Common mode rejection ratio is defined as (a) AVD/AVC, (b) AVC/AVD, (c) ISS/CL, (d) none of these.
237. Define Input common-mode range (ICMR), Output offset voltage (VOS(out)), Input offset voltage
(VOS(in) = VOS).
238. An operational-transconductance amplifier (OTA) has (a) high input impedance, (b) high output
impedance, (c) low output impedance, (d) a and b.
239. A voltage op amp is a (a) buffered op amp, (b) unbuffered op amp, (c) three stage op amp, (d) a and c.
240. Show block diagram a general two-stage op amp followed by buffer stage and briefly explain the function
of each block.
241. Write down the characteristics of an ideal Op Amp.
242. In a two-stage op amp, (a) 1st stage performs voltage to current conversion and then current to voltage
nd
conversion, (b) 2 stage performs voltage to current conversion and then current to voltage conversion,
(c) a and b, (d) all of the above.
243. Draw schematic of a two-stage op amp dividing into voltage-to-current and current-to-voltage stages and
briefly explain the function of each stage.
244. 2nd stage of a two-stage op amp is (a) common-source amplifier loaded by a current-sink load, (b) a
current-sink inverter, (c) a voltage to current and current to voltage converter, (d) all of the above.
245. Draw circuit diagram of 2nd stage of a two-stage op amp. Explain its function.
246. Define (i) common-mode rejection ratio (CMRR) and (ii) slew rate.
247. Unit of slew rate is (a) V/µs, (b) mV/µs, (c) µV/µs, (d) all of the above.
248. Draw circuit diagram of 1st stage of a two-stage op amp. Explain its function.
249. Draw the ckt diagram of a two-stage op amp and write down the expressions of its slew rate, first-stage
gain, second-stage gain, and gain-bandwidth product (GBP).
250. Write down design guidelines for 2-stage op amp.
251. (a) Consider the situation referred to above where the first set of signals is v1 = +50 μV and v2 = −50 μV
and the second set is v1 = 1,050 μV and v2 = 950 μV. If the common-mode rejection ratio is 100, calculate
the percentage difference in output voltage obtained for the two sets of input signals. (b) Repeat Part (a) if
ρ= 10,000.
252. Draw circuit diagram of an emitter-coupled difference amplifier. Write down the expression of common
mode gain and differential mode gain.
253. If emitter resistance, Re of an emitter-coupled Diff Amp is increased, its CMRR (a) decreases, (b)
increases, (c) remains same, (d) none of these.
254. Draw the transistor-level circuit diagram of differential amplifier with constant-current stage in the emitter
circuit. Briefly explain it.
255. The transconductance gmd of the DIFF AMP with respect to the differential input voltage, when evaluated
at VB1−VB2 is given by (a) IO/4VT, (b) IO/2VT, (c) IO/VT, (d) none of these.
256. It is possible to increase the region of linearity by inserting two equal resistors Re in series with the
emitter leads of Q1 and Q2 DIFF AMP but at the cost of (a) lower gmd (b) lower Ad, (c) both (a) and (b),
(d) none of these.
257. Integrated OP AMP Motorola MC1530 consists of various stages. What are those?
258. Input resistance of integrated OP AMP Motorola MC1530 could be increased by replacing Q1 and Q2 of
first differential stage with (a) Darlington pairs, (b) matched FETs, (c) supergain transistors, (d) all of
these.
259. Show the pin configuration of the IC 741 operational amplifier.
260. Draw the measurement setup of output offset voltage VO.
261. Draw the measurement setup of input offset voltage ViO
262. Draw the noninverting amplifier circuit with operational amplifier and estimate its gain.
263. What do you understand by virtual ground. Draw the inverting amplifier circuit with operational amplifier
and derive its gain.
264. Write down the characteristics of an Ideal Operational Amplifier. Write the important features of an ideal
op-amp.
265. Draw the op-amp based adder circuit, or summing amplifier circuit and deduce the expression of its
output voltage (vO).
266. Draw the circuit diagram of differential amplifier using one OP AMP and briefly explain it.
267. The output voltage, VO of an OP AMP based differentiator is given by (a) −R/Cdv/dt, (b) −RCdv/dt, (c)
−C/Rdv/dt, (d) none of these.
268. Show that an OP AMP can be used as an Analog Differentiator.
269. The output voltage, VO of an OP AMP based integrator is given by (a) −1/RC∫vdt, (b) −R/C∫vdt, (c)
−C/R∫vdt, (d) none of these.
270. Show that an OP AMP can be used as an Analog Integrator.
271. Which characteristic of an amplifier needs to be improved for transferring maximum output of an
antenna/transducer?
272. What is the basis of classifying the amplifiers as voltage, current, transconductance, or transresistance
amplifiers? Briefly explain.
273. Classify amplifiers into categories based on the magnitudes of the input and output impedances of an
amplifier relative to the source and load impedances.
274. State the basis of classifying the amplifiers as voltage, current, transconductance, or transresistance
amplifiers. Briefly explain.
275. Explain the characteristics of voltage amplifier with the help of Thevenin's equivalent circuit.
276. Explain the characteristics of current amplifier with the help of Norton's equivalent circuit.
277. The input resistance Ri of an ideal (a) voltage amplifier is ∞, (b) current amplifier is ∞, (c)
transconductance amplifier is 0, (d) transresistance amplifier is ∞.
278. The output resistance RO of an ideal (a) voltage amplifier is ∞, (b) current amplifier is ∞, (c)
transconductance amplifier is 0, (d) transresistance amplifier is ∞.
279. Explain the characteristics of Transconductance Amplifier with the help of Thevenin's equivalent in its
input circuit and a Norton's equivalent in its output circuit.
280. Explain the characteristics of Transresistance Amplifier with the help of Norton's/Thevenin's equivalent
 circuit for input and output ports respectively.
281. Draw block diagram of single-loop feedback connection around a basic amplifier. Briefly explain purpose
of each block.
282. What are advantages of negative feedback? What is the cost of advantages of negative feedback?
283. The reverse transmission factor β for a (a) voltage series feedback amplifier is Vf/IO , (b) current series
feedback amplifier is Vf/VO , (c) current shunt feedback amplifier is If/IO , (d) none of these.
284. The reverse transmission factor β for a (a) voltage series feedback amplifier is Vf/IO , (b) current series
feedback amplifier is Vf/VO , (c) voltage shunt feedback amplifier is If/VO , (d) none of these.
285. The reverse transmission factor β for a (a) current series feedback amplifier is Vf/IO , (b) current shunt
feedback amplifier is If/VO , (c) voltage shunt feedback amplifier is Vf/VO , (d) none of these.
286. Derive the expression of transfer gain with feedback and comment on the same.
287. Define loop gain or return ratio of a single-loop feedback amplifier.
288. Define return difference of single-loop feedback amplifier
289. Since negative feedback reduces the transfer gain, why is it used?
290. Define sensitivity of the transfer gain of a single-loop feedback amplifier.
291. Define desensitivity of a single-loop feedback amplifier and comment on the percentage variation gain
with and without feedback.
292. Show the schematic representation of a single-loop feedback amplifier.
293. Define desensitivity of a single-loop feedback amplifier and comment on the percentage variation gain
with and without feedback.
294. Explain how stability can be achieved with feedback network.
295. State the principle/conditions of unsustainability of oscillation of a oscillator.
296. State the Barkhausen criterion for sustained oscillations.
297. Any electronic circuit to operate as an oscillator, it must have the following characteristics: (a) Some form
of Amplification, (b) Positive Feedback (regeneration), (c) A Frequency determine feedback network, (d)
All of these.
298. Draw the circuit diagram of FET-based phase-shift oscillator.
299. Draw the small-signal equivalent circuit of FET-based phase-shift oscillator and briefly explain it.
300. Draw the circuit diagram of BJT-based phase-shift oscillator and briefly explain it.
301. Draw the small-signal equivalent circuit of BJT-based phase-shift oscillator and briefly explain it.
302. Draw the circuit of BJT-based Colpitts oscillator and briefly explain it.
303. Draw the circuit of FET-based Hartley oscillator and briefly explain it.
304. Draw the circuit of BJT-based Hartley oscillator and briefly explain it.
305. Draw the circuit of BJT-based Hartley oscillator and briefly explain it.
Module 4
306. State De Morgan’s 1st theorem and 2nd theorem. Symbolize both the theorems.
307. State duality theorem and give example of duality theorem.
308. State Absorption Theorem, Elimination Theorem and Concensus Theorem and prove them.
309. Verify DeMorgan’s Theorem with Truth Tables.
310. Illustrate/sketch the symbolic representation of different Digital Logic Gates such as AND, OR, NOT,
NAND, NOR, EX-OR and EX-NOR.
311. Show/prepare Boolean algebraic function of different Digital Logic Gates such as AND, OR, NOT,
NAND, NOR, EX-OR and EX-NOR.
312. Show/prepare Truth Table of different Digital Logic Gates such as AND, OR, NOT, NAND, NOR, EX-
OR and EX-NOR.
313. Why are NAND and NOR gates called universal gates?
314. Realize basic logic gates such as INVERTER, OR gate and AND gate using universal gate such as NAND
gate.
315. Show alternative symbolic representation of NAND and NOT Gates
316. Realize basic logic gates such as Inverter, OR gate and AND gate using universal gate such as NOR gate.
317. Show alternative symbolic representation of NOR gate.
318. Realize Exclusive-OR gate with minimum number of NAND Gates.
319. Simplification of the Boolean function F(A, B, C) = A(A' + C) (A'B + C) (A'BC + C’) results in (a)
AC(B+C), (b) BC(A+C), (c) 0, (b) 1.
320. Simplification of the Boolean function F(A, B, C) = (A+ B) (A'(B' + C'))' + A'(B + C) results in (a)
A+BC+ A’(B+C), (b) A+B+C+ BC, (c) A+B+C(1+B), (d ) A+B+C.
321. What do you understand by fundamental products or minterms.
322. Show example of canonical sum form of a truth table.
323. Translate a truth table into the Karnaugh map, look for octets, quads and pairs and obtain the simplified
Boolean equation.
324. Show the advantage of Overlapping Group in Karnaugh Map Simplification with an example.
325. Show the advantage of Rolling the Map in Karnaugh Map Simplification with an example.
326. What is the Redundant Group in a Karnaugh map and why is it eliminated? Substantiate your answer with
a suitable example of Karnaugh map.
327. Show the advantage of DON'T-CARE CONDITIONS in Karnaugh Map Simplification with an example.
328. Draw the simplest logic circuit for following logic equation where d represents don't-care condition for following
locations. F(A, B, C, D) = Σm(7) + d(10, 11, 12, 13, 14, 15).
329. Obtain sum-of-product equation for Table given below. (a) Y = AD +A𝐷′ . (b) Y = BCD. (c) Y = AB𝐷′ . (a) Y =
AB𝐶′ .

330. Define fundamental sum or maxterm. Substantiate your answer with an example of Truth Table.
331. What do you understand by canonical product form. Substantiate your answer with an example of Truth Table.
332. A product-of-sums expression leads to what kind of logic circuit? (a) OR-AND or NOR-NOR circuit. (b)
AND-AND circuit. (c) NAND-NAND circuit.
333. Draw a logic circuit by drawing an OR-AND network based on the product-of-sums equation Y = F(A, B,
C) =πM(0, 3, 6).
334. Draw a logic circuit by drawing a NOR-NOR network based on the product-of-sums equation Y = F(A,
B, C) =πM(0, 3, 6).
335. Explain how product-of-sum (POS) representation can be obtained from the sum-of-product (SOP)
representation. Substantiate your answer with a suitable Truth Table.
336. Explain how representation sum-of-product (SOP) can be obtained from the product-of-sum (POS)
representation. Substantiate your answer with a suitable Truth Table.
337. Explain how canonical product form can be obtained from the canonical sum form. Substantiate your
answer with a suitable Truth Table.
338. Explain how canonical sum form can be obtained from the canonical product form. Substantiate your
answer with a suitable Truth Table.
339. Y = F(A, B, C) = Σm(3, 5, 6, 7) can be representad as (a) Y = F(A, B, C) = ΠM(1, 2, 4). (b) Y = F(A, B,
C) = ΠM(0, 1, 2, 4). (c) Y = F(A, B, C) = Σm(0, 1, 2, 4). (d) None of these.
340. Draw a logic circuit by drawing an AND-OR network based on the sum-of-product equation Y = F(A, B,
C) = Σm(3, 5, 6, 7).
341. Draw a logic circuit by drawing a NAND-NAND network based on the sum-of-product equation Y = F(A,
B, C) = Σm(3, 5, 6, 7).
342. Obtain product-of-sums equation for Table given below. (a) Y = (A+D) (A+C) (A+𝐷′ ). (b) Y = (A+B)
(A+C) (A+𝐷′ ). (c) Y = (A+B) (A+D) (A+𝐷′ ). (a) Y = (A+B) (A+C) (A+𝐶 ′ ).

343. Draw the simplest logic circuit by drawing an OR-AND network based on the Truth Table given below.

344. Obtain product-of-sums equation for Table given below. (a) Y = (A+D) (A+𝐷′ ). (b) Y = C(B+D). (c) Y =
(A+B) (A+𝐷′ ). (a) Y = (A+B) (A+𝐶 ′ ).

345. Prove the universality of NAND Gate.

346. Prove the universality of NOR Gate.
347. Exclusive-OR (XOR) gate can be used as a (a) controlled inverter. (a) controlled OR gate. (b) controlled
AND gate. (c) controlled NAND gate. (d) controlled inverter.
348. Draw a simplified logic diagram based on the given Truth Table.
349. Prepare a Truth Table of Half Adder and draw its simplified Logic Diagram and briefly explain it.
350. Prepare a Truth Table of Full Adder and draw its simplified Logic Diagram and briefly explain it.
351. Draw Logic Diagram of 4-Bit Ripple Carry Adder and briefly explain it.
352. Prepare a Truth Table of Half Subtractor and draw its simplified Logic Diagram and briefly explain it.
353. Prepare a Truth Table of Full Subtractor and draw its simplified Logic Diagram and briefly explain it.
354. Realize a half adder using Not-AND-OR gates. Realize a half adder using AND-XOR gates. Which one is
preferred?
355. Design XOR gate with minimum number NOR gates is shown below. Design a half adder with minimum
number of NOR gates.
356. Draw Logic Diagram of 4-Bit Ripple Carry Adder/subtractor and briefly explain it.
357. A 3-stage ripple carry adder is composed of two 1-bit full adders and one-half adder (for its 1st stage). Its
 sum output bits are S0, S1, S2 and final carry output bit is CO. Find out the propagation delay of the S2
and CO, if each gate, be it an OR gate, AND gate or XOR gate has a propagation delay of 10 ns.
358. A 4-stage ripple carry adder is composed of two 1-bit full adders and one half adder (for its 1st stage). Its
sum output bits are S0, S1, S2, S3 and final carry output bit is CO. Find out the propagation delay of the
S3 and CO, if each gate, be it an OR gate, AND gate or XOR gate has a propagation delay of 10 ns.
359. A 3-stage ripple carry adder is composed of two 1-bit full adders and one half adder (for its 1st stage).
Find out the propagation delay of the final CO (carry out), if each gate , be it a OR gate or AND, has a
propagation delay of 10 ns.
360. A 4-stage ripple carry adder is composed of three 1-bit full adders and one half adder (for its 1st stage).
Find out the propagation delay of the final CO (carry out), if each gate , be it a OR gate or AND, has a
propagation delay of 10 ns.
361. The Boolean function F in the following fig. equals to (a) 𝐹 = 𝑋̅𝑌𝑍 + 𝑋̅𝑌𝑍̅ + 𝑋𝑍 (b) 𝐹 = 𝑌𝑍 + 𝑌𝑍̅ +
𝑋𝑍 (c) 𝐹 = 𝑋𝑌̅𝑍 + 𝑋̅𝑌𝑍̅ + 𝑋𝑍 (d) = 𝑋𝑌̅𝑍 + 𝑋𝑌𝑍̅ + 𝑋𝑍.

362. The Boolean function F in the following fig. equals to (a) 𝐹 = 𝑋̅𝑌 + 𝑋𝑌̅ (b) 𝐹 = 𝑋𝑌 + 𝑋𝑌̅ (c) 𝐹 = 𝑋𝑌
(d) = 𝑋̅𝑌̅ + 𝑋𝑌.

363. The Boolean function F in the following fig. equals to (a) 𝐹 = 𝑋̅𝑌 + 𝑋𝑌̅(b) 𝐹 = 𝑋𝑌 + 𝑋𝑌̅ (c) 𝐹 = 𝑋𝑌
(d) = 𝑋̅𝑌̅ + 𝑋𝑌.

364. The Boolean function F in the following fig. equals to (a) 𝐹 = 𝑋̅𝑌 + 𝑋𝑌̅ (b) 𝐹 = 𝑋𝑌 + 𝑋𝑌̅ (c) 𝐹 = 𝑋𝑌
(d) = 𝑋̅𝑌̅ + 𝑋𝑌.
365. The minimum number of 2-input NAND gates required to realize a Half Adder circuit is (a)4 (b) 5 (c) 6
(d) 7.
366. The minimum number of 2-input NAND gates required to realize an Exclusive-NOR gate is (a)4 (b) 5 (c)
6 (d) 7.
367. The minimum number of 2-input NOR gates required to realize an Exclusive-OR gate is (a)4 (b) 5 (c) 6
(d) 7.
368. The number of MOSFETs required to implement 2-input Exclusive-OR gate using static CMOS logic
family is (a)10 (b) 12 (c) 14 (d) 16.
369. The number of MOSFETs required to implement 2-input Exclusive-NOR gate using static CMOS logic
family is (a)10 (b) 12 (c) 14 (d) 16.
370. The number of MOSFETs required to implement half adder using static CMOS logic family is (a)16 (b)
18 (c) 20 (d) 22.
Module 5
371. Determine the wavelength of voice signal of 1 kHz frequency, broadcast radio frequency of 100 MHz,
and cellular phone frequency of 900 MHz.
372. Define Electromagnetic Wave.
373. Divide the Electromagnetic radio-frequency (RF) spectrum into several narrower frequency bands such as
LF, MF, HF, etc.
374. Summarize various RF spectrum bands in tabular form and give typical applications for each band.
375. What are the advantages of using radio waves as means of transmitting wireless signals?
376. What is the purpose of any electronic communication system?
377. What is an electromagnetic signal?
378. What is an analog signal?
379. What is a digital signal?
380. What is time-domain representation of the signal.
381. Illustrate the analog signal waveforms of the type s(t) = Vm sin (2π f t + θ) under the following conditions:
(a) Vm = 10 V, f = 1 Hz, θ = 0 radians
(b) Vm = 5 V, f = 1 Hz, θ = 0 radians
(c) Vm = 10 V, f = 2 Hz, θ = 0 radians
(d) Vm = 10 V, f = 1 Hz, θ = π/4 radians
Comment on the results obtained.
382. What is the electromagnetic signal composed of?
383. What is the basic difference between a spectrum analyzer and an oscilloscope?
384. What is the difference between spectrum and bandwidth? Briefly explain with an example.
385. An amplifier senses a sinusoidal signal and delivers a power of 0 dBm to a load resistance of 50 Ω.
Determine the peak-to-peak voltage swing across the load.
386. What are the advantages of representing power levels in dB?
387. Illustrate a simplified block diagram of an electronic communication system and briefly explain each
block.
388. What are major design parameters of an electronic communication system?
389. Briefly explain the merits and demerits of analog and digital communication.
390. A device that produces digital bit stream from analog information data is known as (a) codec (coder-
decoder), (b) digital transceiver, (c) modulator, (d) demodulator.
391. What is digital transmission. Illustrate a simple model of digital transmission and briefly explain it.
392. Draw the block diagram of typical digital communication system.
393. Explain the advantages of digital transmission techniques.
394. What are fundamental two-point data communication equipments for two-way communications?
395. Briefly explain each of the fundamental two-point data communication equipment/circuits used for two-
way communications.
396. What are the three distinct modes of transmission for any communications link. Briefly explain with an
example.
397. What is half-duplex mode of communication? Briefly explain with an example.
398. What is full-duplex mode of communication? Briefly explain with an example.
399. What is Modulation. Define analog modulation.
400. Why should the carrier signal be of higher frequency?
401. Can we radiate the baseband information bearing signal directly on to the wireless channel? If not, why?
402. With the help of suitable example data, show that the process of modulation allows the practical length of
antennas to be used for wireless signal transmission.
403. Justify that the process of modulation leads to simplification of design and processing of signals in
electronic communication systems.
404. How can analog modulation be distinguished from Digital modulation?
405. What do you understand by Frequency Division Multiplexing (FDM)?
406. Consider three voice signals, each having frequency range of 300 Hz–3400 Hz, are required to be
frequency-division multiplexed using 12 kHz, 16 kHz, and 20 kHz analog carrier signals. Illustrate the
resultant spectrum at the output of FDM with the help of appropriate functional block diagram.
407. Consider three voice signals, each having frequency range of 300 Hz–3400 Hz, are frequency-division
multiplexed using 20 kHz, 24 kHz, and 28 kHz analog carrier signals. Find the minimum channel
bandwidth of resultant FDM signal, assuming 1 kHz as guard band between the channels to avoid
interference.
408. There may be three distinct possibilities for the process of analog modulation. What are those. Briefly
explain each of them.
409. Explain the principles of amplitude modulation with a suitable diagram.
410. A carrier signal vc(t) = 5 sin [(2π × 106)t] is amplitude modulated by a modulating sinusoidal signal vm(t)
= sin [(4π × 103)t]. Determine the amplitude and frequency of the carrier signal and the modulating signal.
Also write the expression for the resulting AM signal.
411. A carrier signal with an RMS voltage of 2 V and a frequency of 30 MHz is amplitude modulated by a
modulating sinusoidal signal with a frequency of 500 Hz and maximum amplitude of 1.4 V. Write the
expression for the resulting AM signal.
412. A carrier signal vC(t) = 2.8 sin (2π × 30 × 106t) is amplitude modulated by a modulating sinusoidal signal
vm(t) = 1.4 sin (2π × 500t). Calculate amplitude modulation index, ma and percent modulation, Ma.
413. Expression of amplitude-modulated (AM) signal in terms of modulation index.
414. Let vm(t) = sin (2π × 2000t) be the information signal and vC(t) = 5 sin (2π × 106t) be the carrier signal.
Write the expression for AM wave in terms of modulation index.
415. An angle-modulated signal is given as xC(t) = 100 cos [400πt + π/4]. Determine the instantaneous
frequency.