COMPUTER SYSTEM ORGANISATION & ARCHITECTURE

YEAR – 2016

1. A. Choose the correct answer from the given alternatives:

i) Which of the following statement is true about cache memory?- (a) It is used to increase the
memory size, (b) It is used to decrease the memory size, (c) t decreases the overall
performance of the CPU, (d) It minimizes the speed gap between CPU and main memory.
Ans. = (d) It minimizes the speed gap between CPU and main memory.
ii) ii) MAR stands for - (a) Memory Access Register, (b) Memory Address Register, c) Memory
Access Reference, (d) Memory Address Reference.
Ans.= (b) Memory Address Register
iii) Exponent in floating point number can be represented by - (a) Sign-magnitude form, (b) 1's
complemented form, (c) 2's complemented form, (d) biased form.
Ans.= (d) biased form
iv) If negative numbers are stored in 2's complemented form, the range of numbers that can be
stored in 16 bits is - (a) -128 to +128, (b) -128 to +127, (c) -127 to +127, (d) -32768 to
+32767.
Ans.= (d) -32768 to +32767.
v) Which one is fastest?- (a) Cache memory, (b) CPU Registers, (c) RAM, (d) Hard disk drive.
Ans.= (b) CPU Registers
vi) Cache memory uses - (a) SRAM, (6) DRAM, (c) EEPROM, (d) EPROM.
Ans.= (a) SRAM
2. a) Describe Booth`s algorithm with suitable block diagram and flowchart.
Ans= Booth`s algorithm diagram :
START

A=0;Q[-1]=0
Q=Multiplier
M=Multiplicand
N=Size

NO
Q[0]=0 NO Q[0]=1
Q[-1]=1 Q[-1]=0

YES YES
A=A+M A=A-M

Arithmetic Right shift(AQ)

Size=Size-1

NO Size=0?

YES
Product (AQ)

END
b) Show the steps of multiplication performed by using Booth's algorithm of 7×-5.
Ans.= Let M = 7 (7)10 = (0111)2
Q= -5 (+5)10=(0101)2 (-5)2=(1011)2
n=4

Initial M A Q Size r.w

Configuration
0111 0000 1011 4
0111 0000 1011 0 -
Q[-1]

0111 1001 1011 4 A=A-M

Step 1: A=A+(-M)
Q[0]=1,Q[-1]=0 A=0000
i.e. A=A-M M=1001
1011

0111 1100 1101 4-1=3

ARS(AQ)
SIZE= SIZE-1

Step 2: 0111 1110 0110 3-1=2

Q[0]=1Q[-1]=1
ARS(AQ)
SIZE=SIZE-1

Step 3: 0111 0101 0110 - A=A+M

Q[0]=1,Q[-1]=1 1110
i.e. A=A+M 0111
0101

ARS(AQ) 0111 0010 1011 2-1=1

SIZE= SIZE-1

Step4: 0111 1011 1011 -

Q[0]=1,Q[-1]=0
i.e. A=A-M

ARS(AQ) 0111 1101 1101 1-1=0

SIZE= SIZE-1
Final product result of (7×-5) =(-35)which get in A and Q register after taking 2`s compliment
2`s compliment of (11011101)
=-(00100011)=-35
6. What do you mean by pipeline hazards/conflicts? Discuss the different type of hazards being
observed and also explain the possible solutions.
Ans. = Pipeline Hazards/conflicts:- Pipeline hazards are situation that prevent the next instruction in
the instruction stream from executing during it`s designated
clock cycled. The instruction is set to be stalled, all instruction letter in the pipeline then the stalled
instruction are also stalled. Instruction earlier than the stalled one continue. No new instructions are
fetched during the stall.
The type of hazards are – i) Control Hazard
ii) Structural Hazard
iii) Data Hazard
 Control hazard :- Control Hazard arrives from the pipelining of branches and other instructions
 that changes the contain of programme counters(PC) register. A tipical computer
programme consist of 4 type of instruction they are arithmetic/ load type :60% ,store type:
15%,branch type : 5% , conditional branch type: 20%.
The arithmetic/load type and store instruction do not altern the sequential execution
order of the programme. This implies that pipeline floor is linear type. However, the branch
instruction may after the programme counter’s contain in order to jump to a programme
location other than the next instruction.

0 1 2 3 4 5 6 7 8 9 10 11 12 Clock period

I1
I2

I3

Overlapped execution of instructions without branching

0 1 2 3 4 5 6 7 8 9 10 11 12 Clock period

I1
I2

I3
I4
I5
I6

Penalty:- 4Cycle
Instruction I3 is as a branch instruction fig effect of branching on the performance of an instruction pipeline.

 Solution of control hazard :- an important technique prefetching states that instruction word ahead of
the one currently being decoded in the instruction decoding states (ID) state request them. In the figure
bellow fig1 illustrate the prefetching technique. The memory here is assumed to be in multiple modules,
all modules can be accessed concurrently. There are 2 prefetching of instruction use. a) Sequential
prefetching, b) Target prefetch buffers.

Sequential instruction Memory System Instruction from branched

indicated by PC location

Sequential prefetch Target prefetch

buffer buffer

Decoder

Execution Pipeline
2
 Structural Hazard :- This hazard occur when a certain resource is requested by more than 1
instruction at the same time.
 Solution of Structural Hazard:- Certain resources are duplicated in order to avoid structural hazard.
Functional Unit (ALU)etc. can be pipeline them selves in order to
support several instruction at a time. A classical way to avoid hazard and memory access is by
providing separate data and instruction.
 Data Hazard:- Inter instruction dependences may arrives to prevent the sequential data flow in the
pipeline, when success instruction overlap there fetch, decode and execution
through a pipeline processor. This situation due to inter-instruction decencies is called data hazard.
 Solution of Data Hazard :- The system must resolve the interlock situations when a hazard is detected
consider the sequence of instruction (I,I+1 ……….J,J+1)in which a hazard has
been detected between the current instruction J and the previous instruction I. This hazards situation
can be resolve in one of the two following ways-
i) One simple solution is to stall the pipeline and ignore to execution of
instruction J,J+1 ……. , drawn the pipeline until the instruction I has passed
the point of resource conflict.
ii) A more advance approach is to ignore only instruction J and continue the
flow the instruction J+1,J+2 …… drawn the pipeline. However, the potential
hazard due to the suspension of J must be continues tested as instruction of
H+1,J+2 …….. execute prior to J. the multi level hazards definition may be
encountered, which requires much more complex control polices to resolve
such multi level of hazards.