GM62093A

GM62093A
12 × 8 CROSSPOINT SWITCH
WITH CONTROL MEMORY

Description Pin Configuration

The GM62093A contains a 12 × 8 array of (Top View)
crosspoint together with a 7 to 96 Line decoder
and latch circuits. The GM62093A employs
LG’s advanced high voltage CMOS process Y3 1 40 VDD
technology. It provides extra low operating AY2 2 39 Y2

current and low power dissipation. RESET 3 38 DATA

Anyone of the 96 switchs can be addressed by AX3 4 37 Y1

AX0 5 36 NC
selecting the ap-propriate 7 input bits. The
NC 6 35 Y0
selected turned on or off by applying a logical
NC 7 34 NC
one or zero to the data in and the strobe input X6 33 X0
8
at logical one. A reset signal can be used to X7 32 X1
9
turn off all the switches together when is 10 31
X8 X2
switched at logical one. The GM62093A is X9 11 30 X3
avail-able in a 40 lead dual in-line plastic and 12 29
X10 X4
ceramic package. 13 28
X11 X5
NC 14 27 NC

Feature Y7 15 26 NC

• CMOS 12 × 8 Cross Point Switch with NC 16 25 AY1

Y6 17 24 AY0
Control Memory 23
STROBE 18 AX2
• Low On Resistance 22 AX1
Y5 19
• Internal Control Latches
• ∆Ron 15 Ω Max VSS 20 21 Y4

• Less Than 1% Total Distortion at 0 dbm

• Extra Low Operating Current Application
• Extra Low Cross-Talk Between Any Two • PBX Systems
Switches • Mobile Radio
• Standard CMOS Noise Immunity • Test Eqiepment Instrumentation
• TTL Compatible Input • Analog/ Digital Multiplexer

Block Diagram X0
DATA RESET
STROBE
1 8 0 7

ADDRESS
AX0
Xi iInput (I=0~11)
7 TO 96 DECODER

AX1
LATCHES

AX2

AX3

AY0

AY1

AY2

96 8 88 95 X11

Y0 Yi Input (i=0~7) Y7

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 GM62093A

Absolute Maximum Rating

SYMBOL PARAMETER MIN MAX UNIT
VDD DC Supply Voltage -0.5 18 V
VIN Input Voltage Range -0.5 V+0.5 V
IIN DC Input current ±10 mA
P(P-DIP) Power Dissipation 0.6 W
(C-DIP) 1
TOPR Operation Temperature Range 0 70 °C
TSTG Storage Temperature Range -65 150 °C

Recommended Operating Range

SYMBOL PARAMETER MIN MAX UNIT
VDD DC Supply 8 16 V
VIN Input Voltage Range 0 VDD V
TOPR Operation Temperature Range 0 70 °C

Static Electrical Characteristics: ( TA = 0°C to 70°C , VCC = 14V )

SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
CROSS POINT
I DD Quiescent Supply All Digital Input at Vss or VDD 100 µA
Current All Digital Input at 2.4 V 7 15 mA
Ron On Resistance VDD = 3.5V and I(thru S/W)=10mA 65 Ω
Ron Ron Difference Between 15 Ω
Any Two Switchs
Asc Analog Signal Capability VDD = 14V All Switchs On 13.96 14.0 V
Vis = 14V and
I(thru S/W)= −100µA
I LOFF Off Leakage All Switch off V=V=0 to V ±500 nA
CONTROLS
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.4 V
I LEAK Input Leakage VIN = 0 to VDD ±500 nA

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 GM62093A

Dynamic Electrical Characteristics : ( TA = 25°C , CL = 50pF , VDD = 14V )

SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
CROSS POINT
Propagation Delay Time R L = 1kΩ, VDC = 5V
tP 30 NS
VIS = 2VPP
Frequency Response R L = 1kΩ, VDC = 5V
f RES 40 MHz
[20log(VOUT/VIN)=-3dB] VIS = 2VPP , C L = 3p F
Sine Wave Response(Distortion) R L = 1kΩ, VDC = 5V , VIS = 2VPP , f = 1MHz 1 %
Feedthrough (All S/W’s Off) R L = 1kΩ, VDC = 5V VIS = 2VPP , f = 10KHz -80 dB
Crosstalk Between Any
R S = 50Ω, R L = 1kΩ , VIS = 2VPP , f = 1KHz -110 -95 dB
Two Channels
CX Capacitance (XN to Ground) Switch Off 20 pF
CY Capacitance (YN to Ground) Switch Off 30 pF
C DI Digital Input Capacitance 5 pF
CONTROL
t DS Strobe to Switch Delay R L = 1kΩ, t r = t f = 20nS 160 nS
t DD Data to Switch Delay R L = 1kΩ, t r = t f = 20nS 180 nS
t DA Address to Switch Delay R L = 1kΩ, t r = t f = 20nS 200 nS
t DR Reset to Switch Delay R L = 1kΩ, t r = t f = 20nS 200 nS
t SD Data Setup Time
R L = 1kΩ, t r = t f = 20nS 30 nS
t SA Address Setup Time
t HD Data Hold Time
R L = 1kΩ, t r = t f = 20nS 30 nS
t HA Address Hold Time
t SW Minimum Strobe Pulse Width
R L = 1kΩ, t r = t f = 20nS 200 nS
t RW Minimum Reset Pulse Width

Functional Description
DATA pin may be held high to turn the switch
The GM62093A contains a 12 × 8 array of on, or low to turn it off.
analog switches, each with a latch to maintain Finally a positive pulse to the STROBE pin
its on(closed)or off(opened) state. initiates the ac-tion determined by the
Seven ADDRESS lines(AX0~AX3, ADDRESS and DATA pins. All 96 switches
AY0~AY2) are provided to address any one of can be turned off by forcing the RESET pin
the 96 switches. high.
After any one of the switches is selected, the

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 GM62093A

Timing Diagram
t SW

STROBE t DS
t SA t HA

ADDRESS
t DA
t HD
t SD
DATA
t DD t RW

RESET
t DR
ANALOG
OUTPUT

Truth Table
Address
Connections
AX0 AX1 AX2 AX3 AY0 AY1 AY2
0 0 0 0 0 0 0 X0-Y0
1 0 0 0 0 0 0 X1-Y0
0 1 0 0 0 0 0 X2-Y0
1 1 0 0 0 0 0 X3-Y0
0 0 1 0 0 0 0 X4-Y0
1 0 1 0 0 0 0 X5-Y0
0 0 0 1 0 0 0 X6-Y0
1 0 0 1 0 0 0 X7-Y0
0 1 0 1 0 0 0 X8-Y0
1 1 0 1 0 0 0 X9-Y0
0 0 1 1 0 0 0 X10-Y0
1 0 1 1 0 0 0 X11-Y0
0 0 0 0 1 0 0 X0-Y1
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
1 0 1 1 1 0 0 X11-Y1
0 0 0 0 0 1 0 X0-Y2
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
1 0 1 1 0 1 0 X11-Y2
0 0 0 0 1 1 0 X0-Y3
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
1 0 1 1 1 1 0 X11-Y3
0 0 0 0 0 0 1 X0-Y4
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
1 0 1 1 0 0 1 X11-Y4
0 0 0 0 1 0 1 X0-Y5
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
1 0 1 1 1 0 1 X11-Y5
0 0 0 0 0 1 1 X0-Y6
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
1 0 1 1 0 1 1 X11-Y6
0 0 0 0 1 1 1 X0-Y7
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
1 0 1 1 1 1 1 X11-Y7
A X =0110, 1110, 0111 and 1111 and not allowed

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 GM62093A

Test circuit and Characteristics.

l CROSSTALK vs. FREQUENCY

dB
Fig.1-Crosstalk
-80

l TEST CIRCUIT
-90
VIN
S/W ON S/W ON
VOUT
-100

50Ω 1KΩ 1KΩ 1KΩ

-110

5V 5V 5V 5V -120

-130

VDD = 14 V
10 10 2 103
VIN =2Vp-p
f(KHz)

l RESULT
VOUT
Fig.2 –analog signal capability(Vin vs. Vout) (V)

VDD = 16

l TEST CIRCUIT 16

VDD
VDD = 12

12

VIN VOUT VDD = 8

S/W
ON 8

VDD = 4

4
VIN = 0 ~ 20 V
VCONTROL = 5 V

0 4 8 12 16 (V) VIN

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 GM62093A

l RESULT
Fig.3-Ron measurement R ON

Ω
l TEST CIRCUIT
VDD
60

10mA 50
S.W
ON

40

3.5V

30
+Ä V

˜ V ˜ V
R ON = =
I ON 10mA 20
6 8 10 12 14 16 VDD
VCONTROL = 5V
VDD = 6 ~ 18 V

l BANDWIDTH
Fig.4-Frequency response. (-3dB point: ABOUT 45MHz)

l TEST CIRCUIT dB

-2

S/W VOUT -4
VIN
ON
-6

15KΩ
-8
VDD = 14 V
VIN=2Vp-p
-10

1 10 10 2
f(MHz)