'.

l ': 1

Chapter 4: Standard Single.Purpose Processors: Peripherals

· should set the following data to shift to the left, have a data length of 8-bits and a font
of 5 x 10 dots, and be displayed on one line.
4.9 Given a 120-step stepper motor with its own controller, write a C function Rotate (int
degrees), which, given the desired rotatlon amount in degrees (between O and 360),
pulses a microcontroller's output port the correct number of times to achieve the CHAPTER 5: Memory
desired rotation.
4.10 Modify only the main function in Figure 4 .12 to cause a 240-step stepper motor to
rotate forward 60 degrees followed by a backward rotation of 33 degrees. This stepper
motor uses the same input sequence.as the example for each step. In other words, do not
change the lookup table.
4.11 Extend the ratio and resolution equations of analog-to-digital conversion to any voltage
5.1 Introduction
range between Vmin to Vmaz rather than Oto _Vma.·
4.12 Given an analog output signal whose voltage should range from Oto 10 V, and an 8-bit 5.2 Memory Write Ability and Storage Permanence
digital encoding, provide the encodings for the following desired voltages: (a) 0 V, (b) 5.3 Common Memory Types
1 V, (c) 5.33 V, (d) IO V, (e) What is the resolution of our conversion? 5. 4 Composing Memory
4.13 Given an analog input signal whose voltage ranges from O to 5 V, and an 8-bit digital 5. 5 __Memory Hierarchy and Cache
encoding, calculate the correct encoding for ·3.5 V, and then trace the ~ - Advanced RAM
successive-approximation approach (i.e ., list all the guessed encodings in the correct 5.7 Summary
order) to find the correct encoding.
ii 5.8 References and Further Reading
4.14 Given an analog input signal whose voltage ranges from - 5 to 5 V, and a 8-bit digital
encoding, calculate the correct encoding 1.2 V, and then trace the successive- 5. 9 Exercises
1: .
approximation approach to find the correct encoding. .
Ji 4.15 Compute the memory needed in bytes to store a 4-bit digital encoding of a 3-second f
I analog audio signal sampled every 10 milliseconds. f

I
5.1 Introduction
Any embedded system's functionality consists of three aspects: processi~g, storage, and
communication. Processing is the transformation of data, stm:age is the retention of data for
later use, and communication is the transfer of data. Each of these · aspects must be

I implemented. We use processors to implement processing, memory to implement storage, and

buses to implement communication. The earlier chapters described common processor types:
custom single-purpose processors, general-purpose processors, and standard single-purpose

I processors. This chapter describes memory. ·

Let's start by describing some basic r11emory concepts. A memory stores Jaige numbers.
of bits. These bits can be viewed as m words of n bits each, for a total of m • n bits, as
illustrated in Figure 5.l(a). We refer to a memory as an m x n ("m-by-n ") memory. Figure
5. l(b) shows an external view of a memory. Log:z(m) address input sigI!als are required to
identify a particular word. Stated another way, if a memory has k address inputs, it can have
up to 2k words. n data signals are required to output (and possibly input) a selected word. For
example, a 4,096-by-8 memory can store 32,768 bits, and requires 12 adctfuss signals and

I eight input/output data signals. To read a memory means to retrieve the word of a particular
address, while to write a memory means to store a word in a particular address. A memory
access refers to either a read or write. A memory that can be both read and written ~ ~ .

Embedded System Design Embedded Sr-;tem Design

•. 109
108

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· · ·' - .. -···-·-·· -- ·------··---------- -- ····-·· ··- ----·---,·- -· ----------- __________
- ··- ·-- ---'--···" ._....
- - - - - --- --- · ~ ---·--- i
Chapter S: Memory
5.2: Memory Write Ability and Storage Permanence

rn x n memory
r/w
enable 2• x n read and
write memory Mask-programmed ROM Ideal ,gemo,y

1~ "-----v----1
Ao
Life of
product
•
OTP ROM
•
11 bits per word
On-I Qo Tens of EPROM !EE~ROM FLASH

(a) (b)
• • •
NVRAM
Figure 5 l : t..t..iory: (a) words and bils per word.7ry block diagram.
.. •
···-··-·····-···········--···-·---- ·--·--·- ··-·-···----·-·-···--·- - ···-·····-··---··-··- - -··-··

In-system
additional control input. labeled r 1w in Figure 5. l(b). to indicate which access to perform_ SRAM/DRAM
i programmable
Most memo!}· types have an enable control input. which when ~cassertcd. causes the memory
to ignore tJ1e address. such that data is neitJ1cr written to or read from the memory. Some types
Near
zero r Write
ability
•
of memo11·. known as multiport memory. support multiple accesses to different locations During External External fa.1emal
simultaneously. Such a memory has multiple sets of control lines. address lines. and data fabrication programmer, programmer ogrammer programmer In-system, fast
lines. where one set of address and corresponding data and control lines is known as a port. only one time only OR in-system, OR in-system., writes,
Memory has evolved ve_T)' rapidly over the past few decades. The main advancement has 1,000s block-oriented wilimited
been tJie ttend of memol}·-chip bit-capacity doubling every 18 months, following Moore's of cycles writes, 1,000s cycles
of cycles
Law. The importance ofthisl(end in enabling today"s sophisticated embedded systems should
not be underestimated. No matter how fast and complex processors become. t_hose processors
Figure 5.2: Write ability and storage pennanence of memories, showing relative degrees along each axis (nol lo
still need memories to store programs and to store data to operate on. For _example, a digital scale).
camera is possible not only bccaule of fast A2D and compression processors but also because
of memories capable of storing sufficient quantities of bits to represent quality pictures.
Further advancements to memory have blurred tJ1e distinction between the two traditional
memo!}' categories of ROM and RAM. providing designers with the benefit of more choic,f
Traditionallv. tlie term ROAi has referred to a mcmorv that a processor can only read. and 5.2~;;;;rite Ability and ~ e n c e
which hold; its stored 'bits even without a power sou.rec. The term RAM has referred to a
memory that a processor can both read and write but loses its stored bits if power is removed._ Write Ability
However. processors can not only read. but also wrile to advanced ROMs. like EEPROM and We use the term write ability to refer to the manner and speed that a particular memory can be
Flash. although such writing may be slow compared to writing RAMs. Furthermore. advanced written. Al_l types of memoi:y can be read from bfa processor, since otherwise their stored
RAMs, like NVRAMs. can hold their bits even when power is removed. bits would sen ·e littJe purpose in an embedded system. Likewise, all types of memory can be
Thus, in this chapter, we depart from the ttaditional ROM/RAM distinction. and instead written. since otherwise we w9_uld have no way to store bits in such a memory. However, the
distinguish among memories using two characteristics. namely write ability and storage manner and spc_i_:d ofsuch writing vari~l'_greatly among memory types.
permanence. We then introduce forms of memories commonly found in embedded systems. Afthe-Y1igh encf.of the rai'C ' ·- . we have tYJ>CS of memory that_ a processor
We describe techniques for the common task of composing memories to build bigger can write to simply and quickly by setti· uch a memory's address lines, datJ, input-bits, and
memories. We describe the use of memory hiernrchy to improve memory access speed. control lines lippropriately .o_F.ard e middle of the ran e,
we have types of memory that are··
slower to write by a processor ~~~ e . er~!!._ ofth; range; we liavel)yes
of memory .
that can on! be' writte b a s u:ce ot~uipmenf called a "progranurre_y. 11lis
de~ice=must apply cia1 voltage
--,,.-C--:;:= =-=--- - - - ---·-···
levels
Jo wn-'re:.c.To·-llie memory, also knO\m as

110 Embedded System Design

Embedded System Design 111

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!.
l .I
Chapter 5: Memory
"programming" or "burning" the memory. Do not confuse this use of the term programmer
with the use referring to someone who writes software. At the low end of the r_ange of write·
ability, we have types of memory that can only have their bits stored when the' memory chip
itself is being fabricated. · enable
Storage Permanence
Storage permanence refers to the ability of memory to hold its stored bits after those bits ·have
been written. At the low end of the range of storage permanence is lTlelJIOry t_~ t begins to lose
. b. s almost immediately after those bits are written, an"inlierefoie must be ·continually
hed. Next is mem._q_ry_that wiH ho~d its bits as long as power is applied tq the me?1o~. .
comes memory that can hold 1ts bits for days, months, or even years after the memory s
po :er source has been turned off. At the high-end of the range is memory that ~sentially '· •
er lose its bits- as long as the memory chip is not damaged, of course.v .
The terms nonvolatile and volatile are commonly used to divide mernocy_ty~two
e
gories along the stora permanence axis, as ·shown in Figure 5.2. Nonvolatile memory
can hold its bits even . e~ power is no longer supplied. Com:ersely, volatile ~ i:equires
continual power. to tam its data. ·--~ ·.
Likewise, e term in-system programmable is used to divide\ memories into two
the write ability axis. In-system prograrnmabl emoryJ;lUl-be-written to by
-· p _ ·ng in the embedded system thal,:f'JReS..-1J1e memory. Conversely, a memory
-system prog ble must be en by some external means, rather than
al o ration the embedded o=-- <
As described in Chapter 1, design metrics often compete with one another. Memory write :
ability and storage penYlanence are two such metrics. Ideally, we want a memory· with the
highest write ability a4,d the highest storage permanence, as illustrated by the ideal memory
point in Figure 5.2. Unfortllllately, write ability and storage permanence tend to be inversely
proportional to one another. Furthermore, highly writable membry typically requires more
area and/or power than less-writable memory.
5.3~mmon Memory.Types
Introduction to "Reaq-Only" Memory - ROM
ROM, or read-only memory, is a nonvolatile memory that can be read frnm, but not written
to, by a processor in an embedded system. Of course, there must be a mechanism for setting
the bits in the . memory, but we call this progranuning, not writing. For traditional types of ·
ROM, such programming is <kine off-line, when the memory is not actively serving as a
memory in an embedded system. We program such a ROM before inserting it into the
embedded system. Figure 5.3(a) provides an external block diagram of a ROM · order of increasing write ability. In tenns of write ability, the latter two have such a high
Embedded System.Design.
112
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. ·-- ------~· . ---- ··-· .
5.3: Common Memory Types
8 x 4 ROM
r~~"l-..e..::r-<"'::::r...._~-=- word 0
zk x nROM 3 x 8 r---.::r--==t---.::t-e..r- word I
decoder word 2
t-4<:::t-""d--4's::t-e<;j,---E-, word line
data line
Qo
programmable
wired-OR
connection
(a)
Figure 5.3: ROM: (a) external block diagram, (b) internal view of an 8 x 4 ROM.
We can use ROM for various purposes. One use is to store a software program for a'
general-purpose processor. We may write each program instruction to one ROM word. For
some processors, we write each instruction to several ROM words. For other processors, we
may pack several instructions into a single ROM word. A related use is to store constant data,
like large lookup tables of strings or numbers.
A second common use is to store constant data needed by a system. A third, less
common, use is to implement a combinational circuit We can implement any combinational
function of k variables by using a 2k x l ROM, and we can implement n functions of the same
k variables using a 2k ~ n ROM. We simply program the ROM to implement the truth table
for the functions, as shown in Figure 5.4.
Figure 5.3(b) provides a symbolic view of the internal d.;sign of an 8 x 4 ROM. To the
right .o f the 3 x 8 decoder in the figure is a grid of lines, with word lines running horizontally
and data lines vertically; lines that cross without a circle in the figure are not connected. Thus,
word lines only connect to data lines via the programmable connection lines shown. The
figure shows all connection lines in place except for two connections in word 2. To see how
this device acts as a read-only memory, consider an input address of 010. The decoder will
thus set word 2 's line to I. Because the lines connecting this word line with data lines 2 and 0
do not exist, the ROM output will read 1010. Note that if the ROM enable input were 0, then
no word would be read, since all decoder outputs would be 0. Also note that each data line is
shown as a wired-OR, meaning that the wire itself acts to logically OR all the connections to
it.
How do we program the programmable connections? The answer depends on the type of
ROM being used. Common types include mask-programmed ROM, one-time progranunable
ROM, erasable programmable ROM, electrically erasable programmable ROM, and Flash, in
Embedded System Design · 113
 ·i
tJ
~!
Chaplet" 5: Memory
~ --· 5,3: Conwnon Memory Types _ ~l.
connectio
. n can never be reestablished. For this reason, basic PROM is often re£erred
Truth table (ROM contents) toas
one-ume-programmable ROM, or OTP ROM. -
Inputs (address) Outputs
OTP ROMs have the lowest write ability of all PROMs, as illustrated in figure
a b C V z 5.2, since
wordO they~ only be written once, and they require a progranuner device. However
0 0 0 1-00 ....... 0(".: ....~ very high storage permanence, since their stored bits.won't change unless someone
, they have
0 0 I word I recorutects
0 I 0 o···-··T···' 0 the device to a programm er and blows more fuses. Because of their high storage
permanence,
0 I I I 0 I 0 OTP ROMs are commonl y used in final products, versus other PROMs,
enable which are more
I 0 0 I 0 I 0 susceptible to having their contents inadvertently modified from-radiation, malicious
I 0 I I I ness or
I I jUSt the mere passage Of many years:·· "-- -- I
I I 0 I I C
I I ,

I I I b-__;_ ~-a---- i---1 OTP ROMs are also cheaper per chip"thani>~er PROMs, often costing under
I I I I word? a dollar
each. This also makes them more attractive in final products versus other types
of PROM, and
y z also versus mask-pro grammed ROM when time-to-rruuket constraints or unit costs
make them
a ~tter choice. Because the chips are so cheap, some designers even use OTP
ROMs during
design development. Those designers simply throw away the used chips as they
(a) (b) program new
ones. ·
Figure 5.4: Implementi ng combinational functions with a ROM: (a) truth tab!~,
(b) ROM contents . EPROM ·- Erasab le Programmable ROM , Erase at chip level
degree of write ability that calling them read-only memory is not really accurate. Another type of PROM is an erasabie PROM, or EPROM. This device uses a
In terms of MOS transistor
storage permanence, all ROMs have high storage permanence, and in fact, all as its programmable compone nt. The transistor has a "floating gate," shown
are nonvolatile. in Figure 5.5(a),
We now describe each ROM type briefly. meaning the transistor 's gate is not connected and is instead surrounded by
insulator. An
EPROM programm er injects electrons into the floating gate, using higher than
normal voltage
(usuaHy-12 V to 25 V) that causes electrons to tunnel through the insulator into
Mask-P rogram med ROM the gate, as in
Figure 5.5(b). When that high voltage is removed, the electrons cannot escape,
In a mask-pro grammed ROM, the corutection is programmed when the and hence the
chip is being . gate has been charged and programming has occurred. Reading an EPROM
fabricated by creating an appropriate set of masks. Mask-programmed ROM is much faster
obviously has than writing, since reading doesn't require programming. To erase the progra111,
extremely low write ability, as illustrated in Figure 5.2, ·but has the the electrons
highest storage must be excited enough to escape from the gate. Ultraviolet (UY) light is u6ed
permanence of any memory type, since the stored bits will never change unless to fulfill this
the chip is role of erasing, as shown in Figure 5.5(c). The device must be placed under a
damaged. Such ROM types are typically only used after a final design has been UV eraser for a
determined, period of time, typically ranging from 5 to 30 minutes, after which the
and only in high-volume systems, for which the NRE costs can be amortize device can be
d to result in a programmed again. For the UV light to reach the chip, EPROMs come with
a small quartz
lower unit cost than other ROM types.• window in the package through which the chip can be seen, as shown in Figure

l
5.5(d). For
this reason, EPROM is often referred to as a windowed ROM device. EPROMs
can typically
OTP ROM _ One-Time Programmable ROM be erased and reprogrammed thousands of times; and standard EPROMs are guarantee
d to
Many systems use som form of user-programmable ROM devi~e, meaning hold their programs for at least IO years. ·
the ROM can be
programmed by esigner in the lab, long after the chip has been manufactured. Compared with OTP ROM OMs have improved write ability, as illustrate d in Figure
User-progra le ROMs are generally referred to as programm able ROMs, or PROMs. 5.2, since they can be e and reprogrammed thousands of times. However, they have
These devi s are better suited to prototyping and to low-volume applicatio reduced storage pe ence, since they _are guaranteed to hold a program only for about I 0
ns than are
mask-pr ed ROM. The most basic PROM uses a fuse for each programmable years, and the· stored _bits are susceptible to undesired changes · if the
chip is used in
conn ion. To program a PROM device, the user provides a file that indicates en-vironme with much electrical 11oise or radiation. Thus, use of EPROMs in productio
the desired n
R contents. A piece of equipment called a ROM programmer then configure parts i united. If used in production, EPROMs should have their windows
s each covered by a
rograrnmable connection according to the file. Note that here the programm stic r _to reduce _the likelihood of undesired changes of the memory.
er is a piece of
equipmeat, not a person who writes software. The ROM programmer blows \
fuses by .passing
a large current wherever a connection should not exist. However, once a fuse
is blown, the

114 E1$edded System Design · Embedded System Design

115

__ ___ ._............___,.~ ·~ ·-·- - -. - - ----· - --------··-·· ··-·-· ·· www.compsciz.blogspot.in ·-·--·--···-- ~----- . ·- -~-- ... - ,. ---- ·--- - -·- ... - - - -~--
 I

5.3: Common Memory Types

Chapter 5: Memory

EPROMs can only be erased in their entirety. EEPROMs are typically more expensive than
. EPROMs:, but far more convenient to use. EEPROMs are often -called E2 s, pronounced "E-
squareds..
Because EEPROMs can be erased and programmed electronically, we can build the
circuit providing the higher-than-nonnal voltage levels for such electronic erasing and
programming right into the embedded system in which the EEPROM is being used ..Thus, we
can treat this as a memory that can be both read and written - a write to a particular word
would consist of erasing that word followed by progranuning that word. Thus, an EEPROM is
in-system progranunable. We can use it to store data that an embedded system should save
after power is shut off. For example, EEPROM is typically used in telephones that can store
(a) Initially, the negative charges form a ~hannel commonly dialed phone numbers in memory for speed-dialing. If you unplug the phone, thus
between the source and drain of the tranststor
shutting off power, and then plug it back in, the numbers will still be in memory. EEPROMs
storing a logic l at that cell's location.
can typically hold data for IO years and can be erased and programmed tens of thousands of
times before losing their ability to store data.
+15V
In-system programming of EEPROMs has become so common that many EEPROMs
(b) By applying a larg~ positive vol~e come with a built-in memory controller. A memory controller hides internal memory-access
at the gate of the transistor, the negab.ve details from the memory user, and provides a simple memory interface to the user. In this
charges move out of the c~el area ·case, the memory controller would contain the circuiUy and single-purpose processor
and get trap~ in the floa~ gate: necessary for erasing the word at the user-specified address, and then programming the
storing a logic O at that cell s location.
user-specified data"irito that word.

(c) By shining UV rays on th~ surface

5-30min
I While read accesses may require only tens of nanoseconds, writes may require .tens.of
microseconds or more, because of the necessary erasing and programming. Thus, EEPROMs
with built-in memory controllers will typically latch the address and data, so that the writing
of the floating-gate, the negative processor can move on to other tasks. Furthermore, such an EEPROM would have an extra
charges move down into the channel
restoring the logic l at the cell's
"busy" pin to. indicate to the processor that the EEPROM is busy writing, mearting that a I
processor wanting to write to the EEPROM must check the value of this ousy pin before
location.
attempting to write. Some EEPROMs support read accesses even while the memory is busy .\
writing.
A common use of EEPROM is to serve as the program memory for a microprocessor. In \
(d) An EPROM package ~th a this case, we may want to ensure that the memory cannot be in-system programmed. Thus,
quartz window through which UV \
EEPROM typically comes with a pin that can be used to disable programming.
light can pass.
EEPROMs are more writable than EPROMs, . as illustrated in Figure . 5.2, since
\
EEPROMs can be program m-system, and they are easier to erase. EEPROM is where the
Figure 5.5: EPROM internals. distinction between and RAM begins to blur, since EEPROMs are in-system
programmable us writable directly by a processor. Thus, the term "read-only-memory" .•\
for EEPRO · really a misnomer, since the processor can in fact write to an EEPROM. Such
EEPROM - Electrically Erasable Programmable ROM
Electrically erasable PROM, or EEPROM, develo~ed in th~ earl\ 1;sOS, "'.35g
eliminate the time-consuming and sometimes impossible requrremen o expos~
·
. .
th R:OM An EEPROM is not only programmed electrorucally, but 1t 1s
:t::~
. writes ar ow compared to reads and are limited in number, but nevertheless, EEPROMs can
and · commonly written by a processor during normal system operation.

Flash Memory
to UV hght to erase e · · h lectr ·c s
al~ erased eiectronically, typically by using higher than no~ voltag~.eduf~r ;PRO':. Flash memory is an extension of EEPROM that was developed in the late 1980s. While also
erasing typically only requires seconds, rather than the many mmutes reqwr h eas using the floating-gate principle of EEPROM, flash memory is designed such that large
Furthermo ' re, EEPROMs ::an have individual words erased and reprogrammed, w __ er _ blocks, of memory can be erased all at once, rather than just one word at a time as in

ii
116
Embedded System pesign ' Embedded System Design 117 n
T'
www.compsciz.blogspot.in ___j
·- .. -----'----·- · ........ . _.___
_ .
-- --··- --·--'·---·~ . ----~ -
-·
 Chapter 6: Memory
5.3: COIJWnori Mern T •--·
ory ypes

traditional EEPROM. A block is typi~ally several thousand bytes large. This fast erase ability
can vastly improve the performance of embedded systems where large data items must be
l stored in nonvolatile memory, systems like digital cameras, TV set-top boxes, cell phones,
and medical monitoring equipment. It ·can also speed manufacturing throughput, since
programming the complete contents of flash may be faster than programming a similar-sized
EEPROM.

I
Like EEPROM, each block in a flash memory can typically be erased and reprogrammed
II tens of thousands of times before the .block loses its ability to store data, and can store its data
for 10 years or more.
A drawback of flash memory is that writing to a single word in flash may be slower than
w
i writing to a single word in EEPROM, since an entire block will need to be read, the word (a)
within it updated. and than the block written back. · (bl
Figure 5.7: Memory cell internals: (a) SRAM. (b) DRAM.

Introduction to Read-Write Memory - RAM

the media, one would have to sequence throu h a n be .
We now tum our'attention to a type of memory referred to as RAM. RAM, or random-access tape -would have to be rewound or fast-forw~rded u~ r of other !oca!lons. For example. a
memory. is a memory. that can be both read and written easily. Writing to a RAM is about as memory location could be accessed in the same . n contrast, . with RAM. any ··random ..
fast as reading from a RAM. in contrast to in-system programmable ROMs where writes take r~g~dl~s _of the previously accessed location. Thiamount of_ llme as any other location..
much longer than reads. Furthermore, RAM is typically volatile. Unlike forms of ROM, RAM d1stmgu1shi11g feature of this memo typ th . s ~dom access feature was the kev .
never contains data when inserted in an embedded system. Instead, the system writes data to stuck even today. ry e at e llme of Its mtroduction. and the name ha·s
and then reads data from the RAM during its execution. Figure 5. l(b) provides a block
. A RA!vf's_ internal structure is somewhat more com le than •
diagram of a RAM. Figure 5.6, which illustrates a 4 >< 4 RAM M . P x a ROM s. as shown in
A common question is. where does the term random-access come from in the name not just four as in the figure) Each d . ( . ote. RAMs typically have thousands of words
random-access memory? RAM should really be called read-write memory, to contrast it from bit. In the figure each inp~t data ;or consists of a number of memory cells. each storing
, me connects to every cell in its col L.k
i
read-only memory. However, when RAM was first introduced, it was in stark contrast to the output d~ta line connects to every cell in its colu ., umn. I eni sc. each
then-common sequentially accessed memory media, like magnetic tapes or drums. These ORed wuh the output data line from bo E hmn, with the output of a memory cell being
media required that the particular)ocation to be accessed be_positioned under an access device t · . · a ve. ac word enable line fr th .<f
o every cell m its row. The read/write input (rd/wr) . om e ecoder connects
(e.g., a head). To access another location not immediately adjacent to the current location on The memory cell must possess logic such that it t is :s~med to be connected to eve~ cell .

iii i
.
wnte and the row is enabled and
~~~e;:g~!~~;~ : ;~; : : ~s~~t:~
than dynamic RAM Furth--- - - ---",- -
. .
: :~~tlu~.
h th . s ores e mput data bl! when rd 117 indicates
~i! \\~h~~-~~'.»·r .i~ilicates re,d and
. - '.1°1 c. ~ta~ic RAM.1s fast.er but larocr.
1
errnore, stallc RAM is easily im 1 -· - d ·-- .-- . . . " •
processors, whereas.dynamic RAM is usually i·m I d p emente on._~_same :r ,1 ,
i{
enable 2 x4 ._ p emente on..asep_<ll]!t_e 1c;,, .
'I l SRAM - Static RAM ;;;:::;
I
Ao Static RAM or SRAM
Ij A, ·. ' , uses a memory cell shown in Figure 5 7( ) - .
to sto_~~a: -~it E~-=bjJ .thus requires abou; six . - ·.- -a , cons~stm~ of a It "i°'f-
I because !~Will hold its data: as fon ~ as ~w · -~3:fl~l/i!o~s. This RAM type )S S1,!!$L::;::J ,,
RAM is typ· u· - . .·· - ~,c~ --. p ens supphed, m contrast to dvnanuc RAi\r -:. ·,'
rd/wr . , 1ca, y used for h1gh-peifo ce part f --······ - . ,,, "
r . . . . . - -- . . . so a system (e.g., cache).
=--- .y : • ,..:: ~':'.!
fJ
-, ·~ : .-, .-. . !' / ."','·
Figure 5.6: RAM internals.
.' ,~
y- ~': ·':{:, '. G >.

118 Embedded System Design e:m:be:d:d:~d:;:S:ys:te:m:::Des:'.=:ig:::n-----------.....:__________ _ _.: :· ,. ._l

~~(-~!~~~-

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 {f.S~,('/A
_.: .. . .
Chapter 5: Memory
5.3: Common Memory Types

DRAM - Dynamic RAM

Dynamic RAM, or DRAM, uses a memory cell, shown in Figure 5.7(b), consisting of a MOS 11-13, 15-19...... data<7 ... 0>
11-13, 15-19 - data<7 ...0>
transistor and capacitor to store a bit. Each bit thus requires only one transistor, resulting in
2,23,21,24, addr<l5 ..O>
more compact memory than SRAM. However, the charge stored· in the capacitor leaks 25, 3-10 27,26,2,23,21 , - addr< IS ..0>
gradually, leading to discharge and eventual~to loss of data- TQ..prev~Hoss of_data;_each 22
24,25, 3-10
/OE
cell must regularly have its charge "refreshed.:)A typical DRAM cell's minimum refreslpate 22 - - /OE
is once every 15.625 microseconds. B~use~f the way D ~ aredesigned, reading a 27 . !WE
DRAM word refreshes ~t word's cells.~ ~~cular, ~~ng.a,.ilRAM-W?~g{(!_SuJ.ts...m_the 2 0 - - /CS

tend to be ~lower .to ~cc;ess t h a n ~ ~ 7 . ,· · ·:, '·

word's data being stored ma buffer and then bemg wntten back tQJhe_words_c:_¢lls. Q,M_Ms 20

26
/CS I

CS2 HM6264
27C256
PSRAM - Pseudo-Static RAM ~ (a)
Many RAM variations exist. Pseudo-static RAMs, or PSRA.i\.fs, are DJlAMs with a memory
refresh co Iler built-in. Thus, since the RAM user need not wom--about refres!!mg, the Device Access Standby Active Pwr. Vee Voltage
devic pears to ~have much like ·an ~..Ho'wever, ~ -confrast ~~. a HM6264
Time (ns)
85-100
Pm. (mW)
.01
(mW) (V)
may be busy reftes~ing itself when accessed, which could slow access time and add 27C256
15 s
90 .5 IOO s
some system complexity: Nevertheless, PS popular low-cost high~ensfiy memory
alternative to SRAM in many embedded systems. " (b)
lrr-P c_.,,~'(
.~'>VJ
_1,
Read oikration
NVRAM - Nonvolatile RAM Write operation wlj
\/Nonvolatile RAM, or NVRAM, is a special RAM variation that is able to hold its data even f data
;.
aftffextemal power is removed. There are two common types t,NVRAM. -,r======!~
"I
-1 ~
data
One type, often called battery-backed RAM, contains'a ·static RAM along with it own
permanently connected battery. When external po e(is removed or drops below a certain
threshold, ·the -irijmal battery maintains power J.!(!Jle--SRAM, a n ~ o r y continues
addr
OE
~ -~
.______Jr--
addr
WE
-1_~_-_-_-_.::,:::_::----l~
to store..i~itsr Com ared ~itll._Qth~r-~~Illl ' f'iionvolatil~ memo~ battery-baci~ -~ > is /CSI /CS ! - - - ~...__ _ __ _1

far moi?"wri~We as illustrated in Fi · , : r-Since no-special prograifiliiinjfis necessary, CS2 CS2---..s------,

wfifci°tai:ectone m nanoseconds,
/; -- - ---·- . unlike
just like reads. Furthermore, ROM•ba~ [omis of
---·=,.-~.,.-....
~~o;:~,~~~~~R~~~~-s~~~~~~-~~~
j (c)
,.
1. :~ven~-~le
~: N- ·· having attenes lliaCtarr-fast for 10 years. ·However,'!iNRAMs are more Figure 5.8: IIM6264 and 27C256 RAM,'ROM devices: (a) block diagram (b) ·I ..
• c.:
.. . · · ·
1arai.:h!nsllc.:s. (c) hmm!; diagrams.
.
F'
sceptible to having bits changed inadvertently due to noise than are EEPROM or flash.
t A second type of NVRAM contains a static 'RAM as ell as an EEPROM or flash having Subsequent digits ~ive the memory capacit)· in kilobits. Both these devices arc a\·ailable in 4
the same capacity as the static RA1f1 T · . its co · RAM contents 8: 1_6 : 32, an~ 64 kllobytes. so the part numbers 62 or 27 would be followed bv the number of
into the EEPROM just before power is turned e data, k1lob1ts.. which
. . may be 32. , 64, 128 · ·· some of the
. , 2:,-6. or .,c 12. F.1gure 5.8(b) summanzcs
and then reloads that.data from EEPRO/ .·.. . , charactenst1cs of these devices. ·
Memory access:to and from these devices is performed through an 8-bi; parallel protocol.
Example: HM6264 and 27C256 RAM/ ~,:Devices / . ·. Placmg a memory addr_ess on th_e address-bus and asserting the read signal output enable (0/:)
_·· pacity memory devices, shown in ·1
In this example, we introduce a pair of low-c t low-:ca performs a read ~perauon. Placmg-some data and a memoiy address on the data and address
Figure 5.8(a), commonly used in 8-bit microc trailer-based embedded systems. The first two busses _a n~ assert_mg. the write signal write enable ( II F ) performs a write operation. n,c read
numeric digits irt these devices indicate ether the device is RAM (62) or ROM (27). . and wnte tlmmg 1s giv~n m Figure 5.&(c). ·

120 Embedded System Design Embedded System Design-

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Chapter 6: Memory
5.4: Composing Memory

byte 1/0. The interested reader should refer to the manufacturer's datasheets for complete
timing information. The read operation can be initiated with either the address status
processor (ADSP) input or the address status controller (ADSC) input. Here, we have asserted
data<31.. .0> Device Access Standby Active Pwr. Vee Voltage both. Subsequent burst addresses can be generated internally and are controlled by the address
Time (ns) Pwr. (mW) (mW) (V)
adyance (ADV) input. In other words, as long as ADV is asserted, the device will keep
addr<IS ... O> TC55V23 JO na 1200 3.3 incrementing its address register and output the corresponding data on the next clock cycle.
25FF-100
addr<IO ...O>
(b)
/CS! 5.4 Composing Memory
/CS2 ~ embedded system designer is often f;:i~ with the situation o_f needing a particular-sized
A single read operation
memory (ROM _o r RAM), but ha~mg readily available memones _o f a .different siz~or
example, the designer may need a_2 x 8 ROM, but may have 4k x 16 ROMs readily ava1lable.
/WE
CLK a
Alternatively, the designer may need 4k x 16 ROM, but may have zk x 8 ROMs available for
use. (le.('cft..dL ~~ ~ -
/ADSP The case where the available memory is larger than.needed_js-easy"to deal with. We
/OE
/ADSC simply use the needed l~we.r words. inJ!!Dnenro~ignoring-aj!heedciHtigher words aii.cf-
MODE their high-order addtess -~ iand t s ; use the lowe_r ]a~ mput/outputhnes, thus ignoring
/ADV unneeded hd1gher dala Ii~ Of rse, W! Wuld_~f~}~e ~igh~j line~ ~~ignor! . the lower
/ADSP 1mes mstea . . • _;rr - ·
addr<l5 ... 0> The case where the available memory is smaller than needed requires more design effort.
/ADSC /WE In this case. we must ·comµpse several smaller· niemories io behave as the larger· memory we
/ADV /OE need. Suppose the available memories have. the correct number of words, but each word is not
\_yi_~_e cnpµ_gh. In this case, we. can simpli conoei::t The available memories side-by-side. For
CLK /CS I and /CS2 exampT., igure 5. IO(a) illµstrates the situation Qf_fil!_eding_a..B.OM ,three-times wider that
ava· e. We connect-thr¢eROf,XS"side-by-side, sharing the same address and
TC55V2325F CS3 - n th d concatenating the data lines to form the desired word ,vidth.
F-100
_ uppose mstea at the available memones _ave wor w1 t , ut not enough
data<31 ...O>
~d,:;. In this case, we can connect the availa~le memories' top ·lo botfom. For-exan1ple,
Figure 5.1 O(b) illustrates the situation of needing a ROM with twice as many words, and
(a) (c)' hence needing one extra address line, than that availabk We connect the ROMs top to
bottom. ORing the corresponding data lines of each. We use the extra ltigh-order address line
to select the higher or lower ROM using a I " 2 decoder, and the remaining address lines to
Figure 5.9: TC55V2325FF-IOO RAM devices: (a) block diagram, (bi characteristics, (c) timing diagrams.
offset into the selected ROM. Since only one ROM will ever be enabled at a time, the ORing
of the data lines never actually involves more than one nonzero data line.
If we instead needed four times as many words, and hence two extra address lines, we
Example: TC55V2325FF-100 Memory Device would instead use four ROM 2 x 4 decoder having the two high-order address line as
In this example, we introduce a 2-megabit synchronous pipelined burst SRAM mem~ry input »'.9!:!ld select one e four ROMs to access.
device, shown ill Figure 5.9(a), designed to be interfaced with 32-bit process?rs. This device, Suppose the -ailable memories ve a smaller word width..as well as fewer wor s t ian
made by Toahiba Inc., is organized as. 64K x 32 bits. Figure 5.9(b) sununanzes some of the necessarv. then combine the above two techpiques, fir cieaiing the number of columns.
characteristics of this device. of mem es necessary to achieve· the needed word wi and then creating thenumber of
In Figure 5.9(c), we present the timing diagram for a single read operation. Write rows o memories necessary, along with a deco s. ·
operation is similar. This device is capable of fast sequential reads· and writes as well as single The a p p r ~ t e c i in Figur

Embedded System Design · ~inbe"dded System Design 123

122
\

·-···--- ----~~ ,.~ ·

-· . ·---- --~~·------
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., -··· ., :. ·. .
 -----------------~---------------_.:_-
Chapter S: Memory 5.5 : Memory Hierarchy and Cache

(a)
2m x 3n ROM /

enable .... 2m x n ROM __ ___ 2m__ >$_n,__ ROM _____ 2m x n ROM

Ao

Oln-1 Q2n-l On-I Qo

,, (b) (c)
i i

2rn•I x n ROM
A
2'" xn ROM
Disk
Ao
Am-I
Arn Jx2 Tape
decoder
-.. ..........-- ................... _________________________________ ______________________
: .............................. , .. , , , , .....--------·-···-··············
,,,,

outputs
Figure 5.11 : An example memory hierarchy.

enable - + - - - - '

5.5 Memory Hierarchy and-Cache

Qn-1 Qo
Figure 5.10: Composing smaller memory J)"r1s into larger memory.
Note that, when composing memories to increase the number of words, we don'!
necessarily have to use the highest-order address lines to select the appropriate memory, ·
although these are ·the most logical choice. Sometimes, especially when we are composing
just two memories, we use the lowest order bit to select among memories - thus, one
memory represents "odd" addresses, and-the other represents "e11:en"-addresses.
When we design a memory tci store an embedded system's program and data, we are often
faced with a dilenuna: We want an inexpensive and fast memory, but inexpensive memory
tends to be slow, whereas fast memory tends to be ~nsive. The solution to th.is problem is
~o create a me~~!)'..!):_i~rarctiy, as illUSlrated in Figure 5.11. '!le use an inexpensive but slow
main memory to store all of the program and datr."We_use a small .amoul!~~f fast but
expensive cache memory to store)::opies of likely accessed parts of main memory. Using
cache is analogous to posting on a wall near a telephone a short list of important p~one
n · · 1
me ude even larger and less expensive forms of memory, .sue as
·tape; for some of their storage needs. However, we do not consider these further as they are
not especially common in embedded systems. Also, although the figure shows only one
cache, we can include any number of levels of cache, those closer to the processor being
smaller and faster than those closer to main memory. A two-level cache scheme is -common.
C~clie is usually designed using static RAM rather than dynamic RAM, which is one
reason that <:ache is more expensive but faster than main memory. Because cache usually
appears on the same chip as a processor, where space is very limited, cache size is typically

124 Em~dded System Oesig~ Embedded System Design 125

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 Chapter 5: Memory

rr=====,.===;~=v===,.q
only a fraction of the size of main memory. Cache access time may be as low as just one Tag
clock cycle, whereas main memory access time is typically several cycles. ·
~ache -99erat,;s as follows. When we want the processor to access (read or write) a V
main mt.iiory address, we first check for a copy of that location in cache. If the copy is ln the ·
cache, called a cache hit, then we can access it quickly. If the copy is not there, called a cache.
(a)
miss, t.!1-_~n we must first read the. addre~s and perhaps some of its neighbo~o .!!.1e. cad~,,
This description of cache operation leads to several cache design choices: cacne m a ~
cache rep\acement policy1 and cac!_ie write techniques. The_se ..design . choic~~ave
significant impact on system cost, pe ormance, as well as power, and thus should be
evaluated carefully for a given appr 10 ' ·

e Mapping Techniques
'Cache mapping is the method for assigning main memory addresses to the far fewer number
of available cache addresses, and for determining whether a particular main memory address's
contents are in the cache. Cache mapping can be accomplished using one of three basic
techniques (see Figure 5.12):
(b)
I. In direct mapping, illustrated in Figure 5.12(a), rhe ·main memory address is divided
into two fields, the index and the tag. The index represents the cache address, and
thus the .number 'or index bits is determined by the cache size (i.e., index size =
log2(cach size)}»)No~~ that many different ·main memory addresses will map to thJ
e che a<f~ss. Wh91 we store .the -contents of a main memory address in the
a
e, we·'a!s~ store the ! ~ o determine if desired main memory address' is' in the
.. he, we g~ to the cat~ddress indicated by the ~~x, an~ c?mp~~-~g:!!!e~
~1~h the desired tag. If the ta_gs~match, then.we-,c~eck-the vahd _bi~ ~lid-.bzt :fag
indicates >Nhether the .data'st6red ih ~t:eache slot nas pr~viously ~~n'toaded _into
the cache fi'.om the main n_ie~ol)1JWe tfSe:f' · ojJ}et po~on of tnl!."I_ l@'.n~l?,' ~<l~ess t~ V
grab a articular word within tire cacne-1 · .cache line, also known a~ ·caehe
bl~_ . . the number of (inseparable) ~d· . nt 'memory a,d dres~es loaded from or
ed into main memory at a time. A.typical block size is four or eight addresses. (c)
<:1' ly .associative mapping, illustrated in Figure, 5.12(b), each cache address .·
'1:l;,, ms !J.Ot only the contents of a niainmemory address, but also the complete main
di a
address. To determine if desired main memory address is in the cache, we .

I1 ired address.
..
si I eously (assodaiively) compare-all-the
··
\ .
_ ·
addresses
·, .
' , ·
stored
. in the. cache with the
.J . •·
' "

'' i
1.·1
,: I
In set-associative mapping, illustrated in Figure 5.12(c), a compromise- is reached
,1,I betwee /direct and fully associative mapping. As in direct mapping, aJ\. ~ a P L
u ea m · memory address to a cache address, b ~ s contains
1
e ontent and tags of two~ o f y ~ < : _ l y,,a ~et oi e~!lfy~ ·
etenni~e i~ a .desired ~ memory addre~ is · . 'ffie ·cac~ i:9e_. B': _ l ! ~__cac~e' Figure 5. I 2: Cache mappjng techniques: (a) direct-mapped, (b) rur' y associative, (c) two-way set associative.
address md_1¢ated by the mdex, and we then s1 taneousl ~ssoqaUvruY) compare
.Direct-mapped caches are easy to implement, but may result in numerous misses if two
allthe tags at that location (i.e., of that set) · · the d · .. . . : A cache a set of wth or .more words with the same index are accessed frequently, since each will bump the other
size 1:f Js called an. N-way set-associati cao/', jp y!., ~ - w a y set ?'1t ofth~ ~he. F~ly associative~ches on the other hand are rasi:but the a'imparison logic
assoc_ 1at1ve caches are c o ~: ..f .J./ 1 · • .• . . ts expensive to implement Set-associative caches can reduce · misses compared to

' ' '

126 Em~_d ded System Design

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Chapter 5: Memory

6:fi: Memory Hier.1rchy and Cache

direct-mapped caches, without requiring nearly as much comparison logic as fully associative .·
caches.
Caches are usually designed to treat collections of a small number of adjacent main. ·
memory addresses as one indivisible block, also known as a line, typically consisting of about
eight addresses. ·

I Kb 2 Kb 4 Kb 8 Kb 16 Kb 32. Kb 64 Kb

Cache Write Tyfmiqu~ · · Figure 5.13: Sample cache performance trade-offs.

. . - :/M~ ..•
Whe e write to/a cache, we must 1'1 some point update the main memory. Such update is
:· i
y an issue .· rdata cache, since instruction cache is read--0nly. There are two common cache design are the total size of the cache, its degree of associativity and the data block ·
k 1· . tha . , Size,
a. .a., me size,. t 1s read or written during each cache access by the microprocessor. _
update tee . ques, write-throughand write-back.
In ·write-through techniq'iie, whenever we writf\_ to the cache, we also write to main The total. size.of the cache is measured as the total number of data bytes that the cache I
me ,· requiring the processor to wait until pie write to main memory completes. Although . can hold. Nouce that a ~che sto~es other information, such as the tags and valid bits, which I
· to implement, this t hr.ique may result in several unnecessary writes to main memory. .· do not contnbute to the size of the cache. So, a 32 Kbyte·cache has room for 32,678 bytes of
or example, suppose ograrn writes to a block in the cache, then reads it, and then writes .. da~, plus add1uonal storage ~or ~ag and house k~ping bits. By making a cache larger,. one
it again, with the b staying in the cache during all tlu·ee accesses. There would have been , achieves lower ~1ss rates, which 1s one of the design goals. However, accessing words within
no need to u · ihe main memory after the first write, since the second write overwrites this a .large cache wlll be slower than accessing words in a smaller cache. To clarify this, we will
first write give an example. ~irst let us assume that we are designing a small 2 Kbyte cache for our
Th write-back technique reduces the..number of writeio main memory ~ n g , a processor. With this cache, we have measured the miss rate to be 15%, meaning 15 out of
~ main.me~ory o~y when th~ b~Q~kis bei.ng replac~d -'=~-~~r19.rtl:?':.,i ~~ -,.1ock
was every I00_accesses to the cache result in a miss on the average. The cost of going to main
wntten to dunng its stay m the cache. fins tecJ!nique reqw s tfiat we a~ g1_!~_ll.l! S:xtra bll, memory (1.e., the cost of memory access when there is a miss) is 20 cycles. The·cost of going
called a dirty bit; w"ith each block.(We ~rthis bil wheu . - / 'ITI~ to tfil!~t~ ~'4~he, . only to the cache (1.e., the cost of memory.access when there is a h i t ~ cycles. Hence, on
ai:idy;e then C~t::Ck it when replac~biock to det inc if we sli.o~!~r ~~~k to . Qte average,. the cost of a memory access 1s (0.85 * 2) + (O.J5~~-4? cycles. Now let us
main memory. · douMe the size of the cache, and assume this inlproV:t::S our hit rate to 93 .5%, at the expense of
slowmg the cache down by an extra clock cycle: Now, the average cost of a memory access
Cache Impact on·System Perfo · becomes <_?.935 * 3) + (0.065 * 20) = 4. W5_cycles. This second cache will perform better
The design and configuration of caches n have a large impact on performance and power than .our urst one. Now, w~ double ~ ze
of our cache one more time, resulting in an
consumption of a system. So far, we looked at cache mapping, associativity, write back, and add1uonal clock cycle per hit achieving 94.435% inlprovemenl in terms of hit rate. The
replacement policies. From a performance point ofvie.w, the ·most important parameters in average cost of me access, thus, becomes (0.94435 * 4) + (0.05565 * 20) = 4.8904
cycles. This larg cache will perform worse than our first two designs.

128
Embedded System Design , p - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - -
• Embedded System Design
129
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...........·,.. .. ....... . .. .,_. - - - - - = i i !!l!ii!
Chapter S: Memory
S.6: Advanced RAM

Note that the problem of making a cache larger is additional access time penalty, which
quickly offsets the benefits of improved hit rates. Designers often use other methods to data
improve cache hit rate without increasing the cache size. For example, they make a cache set
associative or increase the line size. These methods too incur additional logic and add to the
access time latency. Increasing the line size can, additionally, improve main memory access
time. at the expense of more complex multiplexing of data and thus increased access latency. Sense
Figure 5.13 summarizes the effects of cache size and associativity in terms of average miss Amplifiers
rate for a number of commonly used programs under the Unix environment, such as gee.
The behavior of caches is very dependent on the type of applications that run on the
processor. Fortunately, for an embedded system, the set of applications are well defined and
known at design time. so the designer has the ability to measure the performance of some
candidate cache designs and choose one that best meets the performance, cost, and power ~:, :,
constraints. One way to perform such analysis is as follows. We instrument the executable m m
'::i ..;
with additional code such that, when executed, it outputs a trace of memory references. Then, 0 "O
"O
s -<
we feed these traces through a cache simulator, which outputs cache statistics at the end of its
execution. We can perform all this analysis on our development computer.
address
"'
Cl
&
~
._
ras

5.6
Figure 5.14: Basic DRAM architecture.
icr DRAM as a type of st~~ag_e~ice that uses a single ·
transistor/ citor pair to store a bit. Because of such architecture and the resulting high
capac nd low cost. DRAMs are commonly used as the main memory in yrocessor bas~d J
e ded systems. In order for DRAMs to keep pace with processor speeds, many variations ·
on the basic DRAM interface has been proposed. In this section, we d~rtbe the stn"icture of a

~·::
~ s i c DRAM
. .
.
------------- --~
basic DRAM as well as some of the mo~ recent and advanced DRAM desj2_ns_.... .

.
, .

l
;.
The basic DRAM architecture is depicted iil Figure 5.14. The addressing mechanism for a :
memory read· works as follow/Th; address bus is multiplexed between row and column.·
components. Using the row adMs°" select (ras) signal; the row component of the address is ·
latched into tlte row address buffer. Likewise, using the column address select (cas) signal, ·
the col component of the address is latched into the column address ~offer. (Note that in ·.
days, the number of 1/0 pins were limited, hence manufacturers of DRAMs adopted ·
s multiplexed scheme to reduce e overall 1/0 requirements. In fact, some DRAM devices
used the same 1/0 pins form · exed data as well as multiplexed address signals.) As soon ~e fas! page mode DRAM design is an improvement on the basic DRAM architecture. In
as the row address co nent is latched into the row address buffer, the row decoder · this design, each ro_w of the memory bH-array is viewed as a page. A page contains·multiple
~~:::::...;;:.~~~~-~--~:. .s. The length of this bit-row depends on the word size and words. Each ~rd 1s addr~ssed by a different column address, The sense amplifier in FPM
ce. ce the column address buffer is latched, the column decoder enables DRAM amphfies the entire page once its address is strobed into the row address latch.
the particul ord (referred the address) in order for it to propagate to the sense amplifier Thereafter, ea~h _wor~ of that page is read (or written) by strobing the corresponding column
(Die se amplifier's las ·s to detect the voltage level of the bits (transi$tor/capacitor pairs) addre~s. The t1mmg diagram for FPM DRAM is depicted in Figure 5.15. Here, after selecting
corr nding to the erenced word and amplify them to a high enough level for latching a particular page (row), three data words within that page are read consecutively. The page
int the output b ce the data is in the output buffers, it can be read by asserting tm

130 Embedded System Design Embedded System Design

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Chapter 5: Memory 5.6: Advanced RAM ·1

ras
_J (f~~ i
cas ______,..n. . __~n.__ ____.n. . .___ ras l
address
cas L
row
address

,_
data
data
data

Figure 5.15: FPM DRAM timing.

Figure 5.16: EDO DRAM timing.
\,\,,1\o.
The enhanced synchronous DRAM. or ESDRAi'v1. is an improvement to the SDRAM
design. ~ j_m_proyerne.fil::!~ ~ qg()us) £ 2,l!i!L!WI.Q.\UQ~t!le ~M QR.AM by .the ED In
-~.hart, ca.(jJ.i;:f.{6iillersTn~ ~- 6¢en .ad.ded .to.Jhe..s_cl!fil;_ amplifiers o enable overlapping of e
column addressing. ·s enables faster clocking-and low atency in reading 1ting
data. ,, J .,,a,.'Y,d) _ .o ci,.~V-:3) . _,11.{_
u':'.:'. ().Ji"- 3/ . Sq(\.J-Jt.a-1 ~- ~ rJ5'lP
R _(RDRAM) 0 ~w,.i'l ~~~
Rambus is really more of a bus interface arch.itectuie than DRAM architecture, Rambus uses
multiplexed address/data lines · to connect the me_mory .controller (or processor) to the
RD~ device. The specification for tl1is interface states that the clock runs at 300 MHz. In
addition, data is latched on both rising and falling edge of the clock. Using such a bus.
theoretically, a transfer rate of 600 million cycles is possible. In addition. each 64-Mbit
RDRAM is bro~ into· four banks (pmts) each with its own row decoders. So. at any given
time, four pages remain open_ The RDRAM protocol is packet driven. where address packets
ar.e followed by data packets. The smallest transaction requires a minimum of four cycles.
Because of its mu!_tiple open page s.::hcmcs. and fast bus 1/0. RD RAM. when utilized properly.
is capable of very high throughput.

DRAM lntegra~on Problem \,\,fl\..0 •

So far, we have discussed static and dynainic types of RAMs and brought up the benefits and
disadvantages of each type. In th.is section. we describe the problem of integrating memory
and conventional logic (gates) on the same IC. While most static types of RAMs can easily be
integrated with other logic on a single chip (e.g., .JCs containing· a cache and a·
microprocessor), it is very difficult to integrate DRAMs and conventional logic The iiifficuhy
l (}-l. arises from tlie different chip making process that is involved when making DRAMs as
opposed to c~nventional logic. When designing · conventional logic ICs. the goal of the
designers is to minirnize,the parasitic capacitance in order to reduce signal propagation delays
and power consumption. In contrast, wh~n designing DRAMs, the goal of the designers is to

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132 Embedded System Design 133
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Chapter 5: Memory
5.8: References and Further R. · d.
ea mg

copies of frequently accessed instructions/data in small fast memori s c h ·

clock l
fast memory between a processor and main. memory. Several cachee desi3c is a small and
mfluence the speed and cost of cache, including mapping techniques re:ce~~:~s ~~tly
ras and wnte techniques. Several advanced DRAMs provide high speed' po 1c1.es,
FPM RAM EDO RAM - . ,memory access hke
cas . , , and SDRAM. lntegrating DRAM with on-chi · ·rocessor '
diflkult due 1.0 different re processes. Thus, choice of memory types and ~!ign of a ~~n be
archt1ecture is an important part of embedded .system desi and . . mory
performance. power, size, and cost. gn, can greatly impact

./~ !5i¥1~~ta~·H data 5.8 References and Further Reading ·

• http://www.instantweb.com/- foldoc/contcnts html The Free o 1· !) · ·
Figure 5. I 7: SDRAM timing. C I p ·d · ' n me 1cllonary of
. ompu mg. rov1 es definitions of a variety of computer-related terms · I di
numerous ROM and RAM variations. ' me u ng
create capacitor cells in order to retain stored infonnation. lllis difference in design goal leads
• David Patt~rson and John He~essy, Computer Organization and Design. San Francisco
to a design process that is considerably different between DRAM and conventional logic.
CA. Morgan Kaufmann Publishers, lnc. lncludes discussion of memorv hierarchy and'
However, integrated processes are beginning to appear. cache. ·J

Memory Management Unit (MMU)

We conclude this section by briefly discussing the duties of a MMU. A gystem that contains
DRAM requires some processor that handles tasks such as refresh, DRAM bus interface and
arbitration and sharing of a memory among multipls: processors. In addition, the MMU
translates logical memory addresses, issued by attached processors, to physical memory
addresses thai make sense to the particular DRAM architecture in use. Modem CPUs often
come with a .MMU built as part of the processor's core. Otherwise, single-purpose processors
can be designed or purchased to handle such memory management tasks.
5.7 Summary
Memory stores data for use by processors. We have categorized memory using two
characteristics, namely, write ability and storage permanence. ROM typically is only read by
an embedded system. It can be programmed during fabrication (mask-programmed) or by the
user (programmable ROM, or PROM). PROM may be erasable using UV light (EPROM), or
electronically erasable (EEPROM) word by word, or in large blocks (Flash). RAM, on the
other hand, is memory that can be read or written by an embedded gystem. Static RAM uses a
flip-flop to store each bit, while dynamic RAM uses a transistor and capacitor, resulting in
fewer. transistors but the need to refresh the charge on the capacitor and slower performance.
Psuedo-static RAM is a dynamic RAM with a built-in refresh controller. Nonvolatile RAM
keeps its data even after power is shut off. Designers must not only choose the appropriate
type of memories for a given gystem, but must often compose smaller memory parts into
larger memory. Using a memory hierarchy can improve system performance by keeping
5.9 Exercises
5. I Briefly define each of the following: mask-programmed ROM. PROM EPROM
EEPROM, flash EEPROM, RAM. SRAM, DRAM, PSRAM, and NVRAM. ' '
5.2 Define the.two ma.m characteristics ofme~ories as discussed in this chapter. From the
types of. memory mentioned m Excerc1se 5.1, list the worst choice for each
charactensllc. Explain. . ·
~ ketch the internal design of a 4 x 3 ROM. ·
,JA"' _,Sketch the mtemal design ofa 4 x 3 RAfvf.
,, }-~ om.pose 1Kx 8 ROMs into a IK x 32 ROM (Note: IK actually means 1,024 words).
~om pose I K x 8 ROMs mto an 8K x g ROM.
om pose I K x 8 RO Ms into a 2K x 16 ROM.
5.8 Show how to use a IK x 8 ROM to implement a 512 z 6 ROM
5 .9 Given the following three cache designs, find the one with. the best performance bv
~alcula~~g the average co!t of.access. Show all calculations. (a) 4 Kbj1e. 8-way sct-
as.soc1all\·c cache with a 6 1/o miss rate; cache hit costs one cycle. cache miss costs 12
cycles. (b) 8 Kbytc,. 4-.way set-associative cache with a 4% miss rate: cache hit costs
~~·(.) cycles, cache nµss costs 12 cycles. (c) 16 Kb.ytc. 2-way set-associat1ve cache with a
-1/o miss rate, ·cache hit costs tlrrce cycles. cache miss costs 12 cvcles.
S. IO Given a 2-lcvcl cache design where the hit rates arc 88% for th~ smaller cache and 97%
for the. .larger cache, the access costs for a miss arc 12 cycles and 20 ovcles.
rcspccll\cl:,, , and the access cost for a hit is one cycle. calculate the average c~st of
access.

134 Embedded System Design Embeild~di System Design

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