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A Novel Reclosing Scheme for Mitigation of
Distributed Generation Effects on Overcurrent
Protection
Keaton A. Wheeler, Student Member, IEEE, Mohamed Elsamahy, Member, IEEE
and Sherif O. Faried, Senior Member, IEEE
 generation (DG) sources has attracted growing attention,
Abstract— This paper proposes a novel scheme to mitigate
distributed generation (DG) effects on existing fuse-recloser
protection infrastructure in radial distribution networks. The
proposed scheme employs a control unit, variable load bank and
dedicated recloser at the point of common coupling (PCC). It
detects the increase in the DG terminal current producing a
tipping signal when it exceeds a preset value. The proposed
scheme also receives a fault detection signal from the head-end
recloser via a fast communication channel. Upon verifying both
signals, the scheme disconnects the DG unit from the system.
Simultaneously, it connects a transfer impedance at the PCC to
operate the DG unit at its pre-fault load sharing condition. This
allows the DG unit to continue supply to the transfer impedance
at the pre-fault load sharing condition, i.e. maintain operation at
the pre-fault level with no need for immediate shut down.
Furthermore, it also allows the DG to maintain its speed and
frequency at the pre-fault levels which in turns allows faster
reconnection of the DG unit to the system after successful
reclosing. For the case of unsuccessful reclosing or the case where
the fault is not cleared within the set utility time set frame, the
proposed scheme shuts the DG source down. The transfer
impedance is selected from a variable load-bank and is a function
of the pre-fault load sharing condition; therefore, a sensitivity
survey was performed during the investigations of this paper to
cover all possible system operating conditions and its
corresponding transfer impedances. In the context of this paper,
multiple in-depth time domain simulations are conducted to
ascertain the efficiency of the proposed scheme in mitigating the
impact of DG sources on existing overcurrent protection
infrastructure. Time domain simulations have been conducted
using a typical distribution network in the EMTP-RV software
environment for validation purposes.
Index Terms— Distributed Generation,
Protection.
I. INTRODUCTION
D UE to increasing consumer energy demand, electrical
utilities are seeking viable solutions to increase
generating capacity without yielding increased strain on
system infrastructure. Emerging solutions capable of
achieving this include distributed energy resources (DERs)
that supply power to the load demand on a local level thus
removing the requirement for increased grid generation
capacity [1]. Conceptually, inclusion of DERs/distributed
K.A. Wheeler, M. Elsamahy and S.O. Faried are with the University of
Saskatchewan, Saskatoon, Canada (e-mail: keaton.wheeler@usask.ca,
mohamed.elsamahy@usask.ca, sherif.faried@usask.ca).
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especially in the context of smart grid operation, since
individual loads are able to install DG sources locally. Solar
photovoltaic (PV), wind and biogas have the capability of
generating grid quality power. This practice has its own
challenges in that the inclusion of DG sources may affect
traditional grid operational characteristics, compromising
existing equipment functionality and reliability [2]-[4]. The
extent of influence is determined through DG size, location,
type and interconnection methods [5] - [8]. IEEE Std. 1547
[5], was the initial prototype facilitating disconnection of all
DG units from the system following fault detection: to prevent
its short circuit current contribution during such an event.
Many utilities follow the settings of IEEE Std. 1547 as shown
in [6]. Reference [7] demonstrates that inverter based DG has
little effect on existing protection coordination when
compared to synchronous machine (SM-based) DG sources,
therefore, this paper uses SM-based sources (biogas turbines).
A method for determination of DG penetration levels that
yield loss of coordination in fuse recloser protection systems is
given in references [7] and [8], with the latter proposing
limiting the DG penetration levels on a unique feeder to the
level found in the algorithm. This prevents a need for
protection system re-coordination, but lacks long term
feasibility: the feeder can sustain limited DG penetration
levels. The former [7], proposes an alternative solution which
is to redesign the protective schemes, but significant financial
and engineering effort is required. Reference [9] presents an
off-line analysis method whereby individual relays are
programmed with every possible state that the network will
Fuse-Recloser encounter to allow for adoption of a suitable tripping
characteristic. This requires configuration to ensure that every
possible state is programmed. Should the system encounter a
non-programmed state, the relay will operate incorrectly or
will not operate at all. Reference [10] reviews various options
for DG/microgrid protection. Voltage based methods monitor
the voltage of the DG sources and convert the measurements
into the d-q reference frame. Communication links are utilized
between relays for discrimination between grid and
DG/microgrid fault types; comparing voltage measurements in
each relay with average values [11]. Key issues associated
with voltage based methods include: low percentage voltage
drop differences among relays can lead to protection
operational failure as a result of voltage gradient reduction;
calculation complexity is increased when converting using the
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Park’s transformation; and issues associated with high 2. Protection Coordination

impedance fault detection. Typically, in a radial distribution network the recloser will
A differential protection scheme based on relays with operate quickly in an attempt to allow for temporary faults to
communicative overlays is presented in reference [12] and self-clear. Following recloser operation, if the fault is still
gives consideration to high impedance faults in radial and present, the fuse melts (a ‘fuse saving scheme’) [16]. In order
meshed networks, however if communicative infrastructure to implement a fuse saving scheme, maximum and minimum
for differential protection methods in the DG context fails, the fault currents for the protected feeder must be known. This
operational grid is unprotected. Additionally, synchronized allows coordination between the recloser and fuse such that
measurements are required by the relays, and imbalance in the recloser will operate before the fuse attempts to clear the
system phases can yield mis-operation of protective schemes. fault. The fast characteristic curve of the recloser is placed
Another viable protection infrastructure option following DG below the fuse’s minimum melting time (MMT), while the
integration is to install a current-limiting device that is self- slow characteristic is placed above the total clearing time
triggering, rapidly activated within milliseconds, and failsafe. (TCT) curve. This ensures that for a temporary fault the
Fault Current Limiters (FCLs) are series devices with low recloser will operate allowing for self-clearing without fuse
impedance (considered zero) during steady state operation but operation. The relay will operate if both the recloser and the
change to a high impedance value, limiting short circuit fuse fail to clear the fault. An increase in DG penetration
current following a fault [13]. In conclusion most of the levels can result in downstream protective devices
utilities and research work that has been done to mitigate the experiencing fault levels greater than those that are upstream.
impact of the DG resources on the coordination of overcurrent This can result in alterations in their behavior under short
protection infrastructure follow two main directions: The first circuit conditions, including loss of coordination and incorrect
is to disconnect the DG source(s) from the system and shut performance of fuse saving schemes. It is worth highlighting,
it/them down, then reconnect the DG source(s) after the fault that for the system used in the investigations of this paper the
is cleared. The second is to restrict the DG penetration level to fuse-recloser coordination is maintained by limiting both the
the limit that will not disturb the coordination. This highlights connection points and DG penetration capacity to the system;
the novelty of the contributions of this paper which are however, this is explained in Section IV.
emphasized in the following points:
1. This paper proposes, through in-depth time-domain
simulation studies, a novel reclosing scheme to mitigate the
∞ Utility RE1 & RE2 = Head-end Recloser
F = Fuse
effects of DG sources on overcurrent protection infrastructure L = Load
without alteration of the existing settings. 138/25 kV
P = Pigeon conductor
2. The proposed scheme disconnects the DG source and keeps R = Raven conductor
it operational at its pre-fault load sharing level with no need
Relay T = Tulip conductor
for immediate shut down. This allows the DG to maintain its
pre-fault speed and frequency, hence, it guarantees a faster 2 Ω reactor F5 L5
reconnection of the DG unit to the system after successful
reclosing. In other words, it results in an increase in the DG T 1 km
2.5 km
reliability and reduction of the cost of shutting-down/restarting RE2 2 km 1 km
procedures [14], [15]. Furthermore, for the case of
RE1 Feeder 2 F4
unsuccessful reclosing or the case where the fault is not 0.5 km
Feeder 1 F1
cleared within the utility time set frame, the proposed scheme 4 km 0.5 km
shuts the DG source down.
F6
3. The proposed scheme removes any limitation on the DG L1 F2
penetration levels that can be connected to distribution system. 2 km 1 km L4
L6
II. FUSE-RECLOSER PROTECTION IN RADIAL NETWORKS 4 km
1. System Under Study F3
L2
The system used in the investigations conducted in this L3
paper, shown in Fig. 1, is a modification of an actual network Fig. 1. Single line diagram of the typical system under study.
currently in use in the province of Saskatchewan, Canada. It
contains a substation which serves two feeders which are III. THE PROPOSED RECLOSING SCHEME
tapped-off at the same point of connection. The system loads
are characterized as: constant impedance loads (L1, L2 and L4), The proposed scheme (RD), shown in Fig. 2, is applied at
constant power loads (L3), and composite loads (L5 and L6). the point of common coupling (PCC) between the DG and the
All the loads are fuse-protected (F1 to F6). In addition to the utility network. The structure of RD consists of the following:
utility relay provided in the substation, each of the two feeders 1- The communication & control unit (CCU):
is protected by its own head-end recloser (namely, RE1 & - The CCU contains both the receiver/transmitter (R/T) unit
RE2). This results in six coordination paths each with a relay- and the control component of the DG recloser (DG-RC). The
recloser-fuse scheme. Dynamic simulation studies are main function of the R/T unit is to allow RD to receive a fault
conducted using the EMTP-RV software. detection signal from the head-end recloser (RE1 & RE2). The
function of the DG-RC unit is to detect the rise in the DG

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terminal current during the fault, i.e. it produces a trip signal if
the DG terminal current exceeds its pickup value. Based on
the previously mentioned two detection signals, the CCU
transmits a control signal to the fast circuit breaker CCB1
(normally closed) to disconnect the DG from the system.
- Simultaneously, the CCU transmits another two control
signals; the first is to a load-bank (ZRE ) to select the value of
the transfer impedance and the second to close CCB2
(normally open) which connects the selected transfer
impedance ZRE at the PCC.
- It is worth highlighting that for the communication between
the head-end recloser and the proposed scheme, the authors
recommend the application of Ethernet Fiber Links technology
with a delay time in the order of a few milliseconds [17]. This
technology suits the in-field application of the proposed
scheme however other communications schemes could be
adequate. During the time-domain simulations conducted in
this paper, the structure of the proposed communication
technique is accounted for by a delay time of 5 milliseconds.
- It also worth mentioning, that CCB1 and CCB2 are thyristor-
based circuit breakers (TBCB) which have fast clearing time
(in the order of microseconds) [18]. A 10 microsecond delay is
incorporated during the investigations of this paper to allow
for the clearing time in the circuit breaker.
Interconnecting Head–end pickup
Utility
Transformer PCC control
Network
CCB1
DG CCU ∞ ranges given in this table are only for three load sharing
Collector Feeder
CCB2
ZRE
RD ZRE selecting signal
Shutdown signal
in case of unsuccessful
reclosing
Fig. 2. DG source interconnection setup with an RD recloser.
2- Controlled transfer impedance ZRE:
- The selected value of the transfer impedance from the load
bank (ZRE), to be connected at the PCC, is evaluated according
to (1). The prime function of this transfer impedance is to
maintain the DG operation at the same pre-fault conditions
(current, frequency and terminal voltage) after the
disconnection from the system such that the DG source can
easily be reconnected to the system following fault clearing.
(1)
( )
Where: Vph is the phase voltage of the system. DGpre-fault output is
the summation of the power supplied by the DG to the
distribution system (Ssys) and to any local load connected at
the low voltage side of the DG interconnection transformer
(Slocal). As can be seen from (1), there is a relationship
between the DG current contribution during the fault and ZRE.
This relationship is used to select the value of the transfer
impedance ZRE. In this regard, during the investigations of this
paper a sensitivity study was performed to decide the possible
DG load sharing conditions and their corresponding DG
current contribution during the fault (the corresponding pickup
values in the CCU). The sensitivity analysis resulted in three
possible load sharing conditions, namely LS1, LS2 and LS3.
This results in three different transfer impedance values ZRE1,
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ZRE2 and ZRE3. The CCU selects the transfer impedance value
based on pre-fault measurements of real and reactive power
delivered by the DG unit in conjunction with the
corresponding current and voltage. From these measurements
the CCU calculates ZRE (RRE + jXRE) using well known power
equations [16]. These calculated values are stored temporarily
in memory and are only transmitted to the load bank after a
0.5 second delay which matches them with an available RRE
and XRE in the load bank. The purpose of the delay is to
account for the fact that a steady state short circuit is
considered to be present 30 cycles (0.5 seconds in a 60 Hz
system) after fault inception [19]. Considering that RD
operates within the first few cycles of fault inception, the
values of RRE and XRE that are transmitted to the load bank are
from a steady state operating condition. By selecting the
values based on the steady state load sharing condition, factors
that affect short circuit levels such as fault location, system
topology and fault impedance existence do not influence the
RRE and XRE selection procedure. The pickup settings of the
DG-RC are related to the rating of the DG unit. The sensitivity
studies conducted showed that during the three load sharing
conditions the corresponding DG current outputs do not
exceed 3 and 2 times the rated current of the DG unit (IDG-
rated) following reconnection for phase and ground faults
respectively. The load sharing conditions, pickup current
settings and the ZRE values with their corresponding ranges are
given in Table IV in the Appendix. It should be noted that the
conditions. If more load sharing conditions are present,
additional ranges would be required.
3- Sequence of operation:
- In the case of fault occurrence, the head end recloser detects
it and transmits this information via a communication channel
(5 milliseconds time delay) to the CCU. Meanwhile, the DG-
RC unit measures the current from the DG source.
- If the head end recloser trip signal is provided and the DG
current output exceeds the pickup setting of DG-RC (3×IDG-
rated or 2×IDG-rated for phase and ground faults respectively)
then it produces a trip signal to disconnect the DG from the
system.
- As RD trips the DG unit from the system, it sends a control
signal to connect the selected value of the load bank to the
PCC. This selected impedance acts to maintain the speed and
frequency of the DG source such that it easily reconnects to
the network following the fault clearance.
- After the fault is cleared, the head-end recloser (RE1 or
RE2) sends a clear-signal to the CCU. Upon receiving this
signal, the DG recloser control (DG-RC located in the CCU)
waits until the minimum reclose time (0.5 seconds) is elapsed.
During this minimum wait time, the CCU receives a synch-
signal from the synchronizer indicating that the DG source is
synchronized with the system. If the minimum reclose time is
exceeded and the synch-signal has not been received, the CCU
will wait for it.
- Once the minimum wait time is exceeded and the CCU has
received the synch-signal then RD disconnects ZRE and
attempts to reconnect the DG source into the system.
- If the DG source attempts to reclose and fails at least twice
or the fault is not cleared within a time set by the utility, then
the proposed scheme (RD) shuts the DG source down.
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IV. APPLICATION OF THE PROPOSED SCHEME TO MITIGATE faults under varying DG ratings. Short circuit levels presented
THE DG INFLUENCES ON OVERCURRENT PROTECTION in both figures are experienced at F1.
This section presents the effectiveness of using the - Figs. 6 and 7 show the variation of the DG contribution to
proposed scheme (RD) through four comparative studies. The the short circuit levels during both types of faults, for different
four comparative studies are divided into four parts as follows: configurations of the DG interconnecting transformer, namely
Part (1) shows a study that includes the application of a Yg/Yg and Yg/D. During the cases presented in both figures,
conventional method to maintain the protection coordination. a selected DG capacity of 8 MVA (outside the safe penetration
This conventional method is based on restricting the DG limit) is used.
penetration points and penetration levels to the limit that will 7500
6567
not disturb such a coordination. Part (2) shows in-depth time- 6000 5728

Current (A)
4141 4295 4132 1.6 MVA
domain simulation studies which highlight the effectiveness of 4500
8 MVA
the proposed scheme to manage DG penetration levels beyond 3000
the DG limits introduced by the conventional method, in Part 16 MVA
1500
(1), during different fault types. Part (3) compares the 0
effectiveness of the proposed scheme in Part (2) over one of No DG DG No RD DG with RD
the schemes that are presented in the current literature, namely Fig. 5. Short circuit levels experienced by F1 for a LL-G fault on the lateral
Superconducting Fault Current Limiters (SFCL). Finally, Part feeding L1 with varying DG ratings connected at L2.
6000
(4) presents the generalization of the proposed scheme against 5800

Current (A)
4229 4569 4222
the change in fault resistance and fault duration. 4000 Yg/Yg
1. Application of a Conventional Method to Mitigate the DG Yg/D
2000
Influences on Overcurrent Protection
- The conventional method is applied in this subsection to 0
maintain the protection coordination through two actions; the No DG DG No RD DG with RD
first is to restrict the DG connection points, while the second Fig. 6. Short circuit levels experienced by F1 for a 3p-G fault on the lateral
feeding L1, 8 MVA DG connected at L2. Two different interconnecting
is to restrict the penetration levels to the limit that will not transformer types: Yg/Yg and Yg/D.
disturb such a coordination. This method depicts the same
algorithm presented in [8] in order to determine both the 6000
selected candidate DG connection points and the loss of 5728
Current (A)

4141 4467 4137

coordination (LOC) limits for the system under study with the 4000 Yg/Yg
presence of DG sources. The results have shown that the
2000 Yg/D
candidate connection points during the investigations of this
paper are at loads L2, L3 and L5 with corresponding loss of 0
coordination (LOC) limits shown in Fig. 3. It can be No DG DG No RD DG with RD
concluded from this that LOC first occurs when a DG source Fig. 7. Short circuit levels experienced by F1 for a LL-G fault on the lateral
is connected at Bus2 and Bus3 during both three-phase-to- feeding L1, 8 MVA DG connected at L2. Two different interconnecting
ground and double-line-to-ground faults near L1 and L6. It can transformer types: Yg/Yg and Yg/D.
also be concluded that the maximum limit of DG penetration 2. Application of the Proposed Scheme to Mitigate the DG
for the system for three-phase-to-ground and double-line-to- Influences on Overcurrent Protection
ground faults are 4.2 and 2.6 MVA respectively. This subsection presents the application of the proposed
7
6 5.7 6 scheme to the problem under investigation. Case studies
4.8
DG Penetration

5 4.2 DG Bus 3 Fault Load 6 presented are chosen based on the following criteria: The first
4 3.3 is to show the capability of the proposed scheme, to maintain
(MVA)

2.6 DG Bus 5 Fault Load 1

3 the existing protection coordination, through its ability to
2 DG Bus 2 Fault Load 1
1 manage DG penetration levels beyond the LOC limits which
0 are connected at the same restricted connection points which
Phase Ground are determined by the conventional method in Part (1) and
Fig. 3. LOC limits for the candidate DG connection points - Yg/Yg presented in Fig. 3.
interconnection transformer.
7500 TABLE I: CASE STUDIES
5800 6745 1.6 MVA Case Study-1 Case Study-2
6000
Current (A)

4229
8 MVA Fault type 3ph-G LL-G
4500 4394 4222
16 MVA Fault location on the lateral feeding L1
3000 Fault inception 1 second of simulation time
1500 Fault duration Sustained fault
0 DG connection point at L2
No DG DG No RD DG with RD DG pre-fault load sharing 0.8 of 8 MVA SM-based DG, 0.9 pf
Fig. 4. Short circuit levels experienced by F1 for a 3ph-G fault on the lateral condition & PF
feeding L1 with varying DG ratings connected at L2. DG transformer configuration Yg/Yg

- Figs. 4 and 5 show the variation of the DG contribution to The second is to show the effectiveness of the proposed
the short circuit levels for the test system, during both types of scheme during different fault types. Two case studies are
selected for presentation in this subsection, namely Case

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Study-1 and Case Study-2. Details of these case studies are
given in Table I and are shown in Fig. 8. Case studies are
investigated for three different scenarios: without DG
penetration, with DG penetration only (no RD) and with both
the DG unit and RD in service. For the purpose of clear figure
presentation, a duration time from 0.9s to 1.6s is only shown
for the cases where the proposed scheme is not applied, while
a longer duration from 0.8s to 7.8s for the cases that include
the proposed scheme. It should be noted that for simplicity
reasons no local load is connected at the DG terminals, i.e.
Slocal equals zero. In addition, a fuse saving operational
concept is employed. All values of the currents stated are in
RMS and all of the voltages are stated in phase RMS values.
To upper RE2 2 km
stream
Communication F1
channel (5 millisecond
delay)
L1
Fault
Additionally, for these short circuit levels the corresponding
clearing times of both RE2 and F1 are 1.0762s and 1.424s
respectively.
 Fig. 10 shows the time domain responses while an 8 MVA
DG unit is connected to the lateral feeding L2 (RD is not
integrated at the DG terminals). Observations demonstrate
that the short circuit current experienced by RE2 is 4241 A
while the level experienced by F1 increases to 5800 A. This is
expected as the excess current experienced by F1 can be
attributed to the fault being fed independently by two sources
since it is located between the DG unit and the utility
substation. The corresponding clearing times of both RE2 and
F1 for these short circuit levels are 1.0762s and 1.0659s
To down respectively. The scenario depicted in Fig. 10 highlights the
stream existence of the coordination problem as F1 operated before
0.5 km the head-end recloser and violated the fuse-saving scheme
initially implemented in the network. It is worth highlighting
that due to the fault, the DG terminal voltage dropped to 0.993
kV.
1 km 8000

Current (A)
4000 RE2 current
PCC 0
CCB1
-4000
DG CCU -8000
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
CCB2 F2 Time (s)
10000
Current (A)

ZRE
5000 F1 current
ZRE selecting signal
0
L2
-5000
Shutdown signal in case of unsuccessful reclosing
-10000
Fig. 8. Fault applied on the lateral feeding load 1 with the DG unit at load 2. 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
Time (s)
Case Study-1: Figs. 9 to 12 illustrate the time domain 3000
simulation results for Case Study-1. According to these
Current (A)

1500 DG terminal current supplied to the system

results, the following observations are worth noting:
0
 In the case where there is no DG penetration (Fig. 9), the
-1500
operating sequence is such that RE2 operates twice in its fast
-3000
mode before F1 clears the fault. Through observations, it can 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
be seen that the short circuit current experienced by RE2 and Time (s)
F1 is 4244 A and 4229 A respectively.
Voltage (kVφ)

20.4
DG RMS terminal voltage
8000
Current (A)

RE2 10.4
4000
current
0
-4000 0.4
-8000 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
Time (s)
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
Time (s) 1
Recloser State
State

8000
Current (A)

4000 F1
Fuse State
current
0 0
-4000 0.9 1 1.1
1.2 1.3 1.4 1.5 1.6
-8000 Time (s)
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 Fig. 10. Case Study-1 with the DG source connected at L2 when RD is not
Time (s) applied: RE2 current, F1 current, DG terminal current, DG terminal voltage,
RE2 and F1 state signals.
Recloser State Fuse State  Fig. 11 shows the time domain responses while an 8 MVA
1
DG is connected to the lateral feeding L2 (RD is integrated at
State

the DG terminals). It can be seen that due to the presence of

0
the proposed scheme, the short circuit current experienced by
0.9 1 1.2 1.11.3 1.4 1.5 1.6
Time (s) RE2 remained relatively unchanged at 4242 A while the level
Fig. 9. Case Study-1 without the DG source: RE2 current, F1 current, RE2 and experienced by F1 decreased to 4226 A. Furthermore, it can
F1 state signals. be seen that RE2 detects the fault and sends a detection signal
to RD at 1.004 seconds. RD then switched the DG source from

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the system to ZRE at 1.013 seconds (less than one cycle from the DG unit from the system, switching the DG unit to ZRE and
fault occurrence). finally the reconnection of the DG unit to the system upon
8000 successful reclosing at 5.82 seconds. In other words, the
proposed scheme allowed the disconnection of DG, kept it
Current (A)

4000 RE2 current

0 operational until fault clearance and then it reconnected the
-4000 DG back to the system within 4.82 seconds time frame. This
-8000
0.8 1.8 2.8 3.8 4.8 5.8 6.8
highlights the faster reconnection of the DG due to the
Time (s) proposed scheme over the current utility practices.
8000  In terms of the reliability and system performance, it is
worth highlighting that with the presence of the proposed
Current (A)

4000 F1 current
0 scheme at the DG terminal, the voltage dropped to 11.274 kV
-4000 as opposed to 0.994 kV without RD. Additionally, the
-8000 overshoot in frequency when reconnecting the DG unit to the
0.8 1.8 2.8 3.8 4.8 5.8 6.8
Time (s)
system was 1.018 p.u (61.08 Hz) after which it decayed to the
nominal frequency. Moreover, Fig. 11 demonstrates that RE2
2 DG Frequency (per unit)
RD State
operated as normal (at 1.0761 seconds) and attempted to allow
for temporary fault clearing after which F1 cleared the fault (at
Freq/State

RE2 detection Signal

1 1.453 seconds). Finally, it can be observed from the time
domain responses presented in Fig. 12 (Feeder 2 power as
0 measured at RE2 and the system voltage at PCC on the system
0.8 1.8 2.8 3.8 4.8 5.8 6.8 side of the breaker) that the system regained a normal
Time (s)
operating state upon fault clearance and the reconnection of
2.2 DG Frequency (per unit)
1.8 the DG. This highlights the capacity of the proposed scheme
RD State
1.4 to restore coordination in the system.
Freq/State

RE2 detection Signal

1
0.6 80
Power (MW)

0.2 60 Feeder 2 Power

-0.2 40
0.95 1 Time (s) 1.05 1.1 20
4000 0
-20
Current (A)

2000 DG terminal current

0.8 1.8 2.8 3.8 4.8 5.8 6.8
0 Time (s)
-2000 30
Voltage (kVφ)

0.8 1.8 2.8 3.8 4.8 5.8 6.8 20 System PCC Voltage
Time (s)
10
15
0
Voltage (kVφ)

13 DG RMS terminal voltage -10

0.8 1.8 2.8
3.8 4.8 5.8 6.8
Time (s)
11
Fig. 12. Case Study-1 with the DG source at L2 when R D applied: Feeder 2
0.8 1.8 2.8 3.8 4.8 5.8 6.8
active power and System PCC voltage.
Time (s)
Case Study-2: Figs. 13 to 16 illustrate the time domain
1
simulation results for Case Study-2. According to these
Recloser State results, the following observations are worth noting:
State

Fuse State  In the case where there is no DG penetration (Fig. 13),

0 again, the operating sequence is such that RE2 operates twice
0.8 1.8 2.8 3.8 4.8 5.8 6.8 in its fast mode before F1 clears the fault. Through
Time (s) observations, it can be seen that the short circuit current
100 experienced by RE2 and F1 is 4162 A and 4141 A
respectively. Furthermore the corresponding clearing times of
Impedance (Ω)

50 R Calculated R Bank both RE2 and F1 are 1.0814s and 1.437s respectively.
X Calculated X Bank  Fig. 14 shows the scenario where an 8 MVA DG is
0 connected to the lateral feeding L2 (RD is not integrated at the
0.45 0.6
0.75 0.9 1.05 DG terminals). Through observations it can be seen that the
Time (s) short circuit current experienced by RE2 is 4160 A while the
Fig. 11. Case Study-1 with the DG source at L2 when RD applied: RE2 level experienced by F1 increases to 5728 A. Again, this is
current, F1 current, RE2, RD communication & DG frequency, Zoom on RE2,
RD signals, DG terminal current, DG voltage, DG frequency, State signals,
expected as the excess current experienced by F1 can be
load bank calculated and actual values. attributed to the fault being fed independently by two sources
 Fig. 11 also shows the DG terminal current, voltage and the since it is located between the DG unit and the utility
per unit frequency in the following sequence: disconnection of substation. The corresponding clearing times of both RE2 and
F1 are 1.0812s and 1.0632s respectively. This again highlights

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the existence of the coordination problem as F1 operated 8000

Current (A)
RE2 current
before the head-end recloser and violated the fuse-saving 4000
scheme initially implemented. It is worth highlighting that 0
due to the fault, the DG terminal voltage dropped to 1.016 kV. -4000
8000 -8000
RE2
Current (A)

4000 0.8 1.8 2.8 3.8 4.8 5.8 6.8

current
0
Time (s)
-4000
-8000 8000

Current (A)
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 4000 F1 current
Time (s) 0
8000
F1 -4000
Current (A)

4000
current -8000
0
0.8 1.8 2.8 3.8 4.8 5.8 6.8
-4000
-8000 Time (s)
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.5
Time (s)

Freq/State
1
1 DG Frequency (per unit)
0.5 RD State
State

Recloser State RE2 detection Signal

Fuse State 0
0 0.8 1.8 2.8 3.8 4.8 5.8 6.8
0 0.5 1 1.5 2 2.5 3 Time (s)
Time (s) 1.25
1
Fig. 13. Case Study-2 without the DG source: RE2 current, F1 current, RE2 Freq/State 0.75 DG Frequency (per unit)
and F1 state signals. 0.5 RD State
0.25 RE2 detection Signal
8000 0
4000 -0.25
Current (A)

RE2 current
0.95 1 1.05 1.1
0 Time (s)
-4000 2000
Current (A)

-8000 DG terminal current

0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1000
Time (s) 0
10000
F1 current -1000
Current (A)

5000
0.8 1.8 2.8 3.8 4.8 5.8 6.8
0
Time (s)
-5000
-10000
Voltage (kVφ)

0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 15.6

Time (s)
2000 13.4 DG RMS terminal voltage
DG terminal current supplied to the system
Current (A)

0
11.2
-2000 0.8 1.8 2.8 3.8 4.8 5.8 6.8
Time (s)
-4000
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
Time (s) 1
24.4 Recloser State
State
Voltage (kVφ)

18.4 DG RMS terminal voltage

Fuse State
12.4
0
6.4 0.8 1.8 2.8 3.8 4.8 5.8 6.8
0.4 Time (s)
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
Time (s) 100
Impedance (Ω)

1 R Calculated R Bank
Recloser State 50
State

X Calculated X Bank
Fuse State
0
0
0.45
0.6 0.75 Time (s) 0.9 1.05
0.9 1 1.21.1 1.3 1.4 1.5 1.6
Time (s) Fig. 15. Case Study-2 with the DG source at L2 when RD is applied: RE2
Fig. 14. Case Study-2 with the DG source connected at L2 when RD is not current, F1 current, RE2, RD communication & DG frequency, Zoom on RE2,
applied: RE2 current, F1 current, DG terminal current, DG terminal voltage. RD communication, DG terminal current, DG voltage, DG frequency, State
RE2 and F1 state signals. signals, load bank calculated and actual values.

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60
Power (MW)
40
Feeder 2 Power
20
0
-20
0.8 1.8 2.8 3.8 4.8
Time (s)
20
Voltage (kVφ)
15
10 System PCC Voltage
5 set to limit the fault current to a value greater than five times
0 the line nominal current, an excessive heating will occur
-5
0.8 1.8 2.8
3.8 4.8 5.8 6.8
Time (s)
Fig. 16. Case Study-2 with the DG source at L2 when RD is applied: Feeder 2
active power and System PCC voltage.
 Fig. 15 shows the time domain responses while an 8 MVA
DG is connected to the lateral feeding L2 (RD is integrated at
the DG terminals). It can be seen that due to the presence of
the proposed scheme the short circuit current experienced by
RE2 remained relatively unchanged at 4157 A while the level
experienced by F1 decreased to 4137 A. Furthermore, it can be
seen that RE2 detects the fault and sends a detection signal to
RD at 1.004 seconds. RD then switched the DG source from the
system to ZRE at 1.013 seconds (less than one cycle from fault
occurrence).
 Fig. 15 also demonstrates the DG terminal current and
voltage transitions as well as the per unit frequency in the
following sequence: disconnection of the DG unit from the
system, switching the DG unit to ZRE and finally the
reconnection of the DG unit to the system upon successful
reclosing at 6.579 seconds. In other words, the proposed
scheme allowed the disconnection of DG and kept it
operational until fault clearance then it reconnected the DG
back to the system within 5.579 seconds time frame. Here
again, this highlights the faster reconnection of the DG due to
the proposed scheme over the current utility practices.
 In terms of the reliability and system performance, it is
worth highlighting that with the presence of the proposed
scheme at the DG terminal, the voltage dropped to 11.938 kV
as opposed to 1.016 kV without RD. Additionally, the
overshoot in frequency when reconnecting the DG unit to the
system was 1.022 p.u (61.35 Hz) after which it decayed to the
nominal frequency. Moreover, Fig. 15 demonstrates that RE2
operated as normal (at 1.0812 seconds) and attempted to allow
for temporary fault clearing after which F1 cleared the fault (at
1.499 seconds). Finally, it can be observed from the time
domain responses presented in Fig. 16 (Feeder 2 power as
measured at RE2 and the system voltage at PCC on the system
side of the breaker) that the system regained a normal
operating state upon fault clearance and the reconnection of
the DG. This highlights the capacity of the proposed scheme
to restore coordination in the system.
3. Comparison between the Proposed Scheme and an SFCL to
Mitigate the DG Influences on Overcurrent Protection
In this section one of the schemes that are presented in the
current literature, namely Superconducting Fault Current
Limiters (SFCL), is applied to the problem under investigation
as a comparative study to highlight the effectiveness of the
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8
proposed scheme (RD) presented in Part (2). Case Study-1 is
selected for presentation in this section where a 30 ohm
resistive SFCL model presented in [20] is connected at the DG
terminal. Time domain simulation responses are presented in
Fig. 17. Practically, an SFCL is required to limit the fault
current between three and five times the line nominal current.
5.8 6.8
This is due to the fact that if the FCL limits the fault current to
a value lower than three times the line nominal current, then
the protection will not be able to differentiate a fault from
overload current (e.g., a large load switching). While if SFCL
within the SFCL [20]. It can be seen in Fig. 17 that the peak
steady state current experienced by the DG unit is 206 A.
When the SFCL is applied following fault inception, the DG
peak current is limited to 659 A in the second cycle after fault
inception (fault current almost equal to 3.68 times the steady
state value). This demonstrates that the SFCL is working as
expected. It can also be observed that even with the presence
of the SFCL, the short circuit current experienced by RE2
remained relatively unchanged at 4242 A while the level
experienced by F1 decreased to 4555 A. In addition, after RE2
tripped the utility source, the fuse continued to receive a
current of 460 A. Finally, the fuse melted at 1.2213 seconds
before RE2 could trip a second time. Therefore, it can be
concluded that for Case Study-1 the SFCL failed to maintain
the original coordination of the system for the DG size of 8
MVA. Comparing the results obtained in this sub-section to
the results obtained in sub-section (B) it can be clearly
observed that the proposed scheme is more flexible and more
robust at restoring fuse-recloser coordination of DG penetrated
feeders than the SFCL solution.
4. Generalization of the Proposed Scheme
4.1 Impact of changing the fault resistance
The impact of changing the fault resistance on the
performance of the proposed scheme has also been
investigated during Case Study-1. The zoom on the RE2 and
RD signals are presented in Fig. 18 for a 3 Ω fault resistance.
The results have shown that RD is still able to restore the
original system coordination with the RE2 detection and RD
signal being produced 50 microseconds and 2.6 milliseconds
slower than the bolted fault case.
4.2 Impact of changing the fault duration
The impact of changing the fault duration on the
performance of the proposed scheme has also been
investigated during Case Study-1 and is shown in Fig. 19. In
this figure a fault duration of 0.12 seconds is selected to
highlight the effectiveness of the proposed method on
reconnection of DG to the system and performance of the
system after fault clearance. The comparison between Fig. 19
and Fig. 11 (Case Study-1 with a permanent fault), shows that
the fault levels of RE2 and F1 and the tripping time of RE2 are
similar to the case of the permanent fault. In addition, it can be
seen in Fig. 19 that the fault is cleared after RE2 trips once
before reconnecting the utility to the system and F1 does not
melt. Furthermore, it can also be seen in Fig. 19 that the DG
unit reconnects with the system at the same time as that
expressed in Fig. 11. This highlights the capability of the
proposed scheme to successfully restore the original
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9

coordination of the network, by allowing for the temporary

10000
fault to self-clear without causing a fuse to melt prematurely. RE2 current
5000

Current (A)
10000 0
RE2 current
Current (A)

5000
-5000
0
-10000
-5000 0.8 1.8 2.8 3.8 4.8 5.8 6.8
Time (s)
-10000
0.8 1.8 2.8 3.8 4.8 10000
Time (s) Fuse current
5000

Current (A)
10000 0
Fuse current -5000
5000
Current (A)

-10000
0 0.8 1.8 2.8 3.8 4.8 5.8 6.8
Time (s)
-5000
-10000 2
DG Frequency (per unit)
0.8 1.8 2.8 3.8 4.8 RD State

Freq/State
Time (s) RE2 detection signal
1
2
DG Frequency (per unit) 0
Freq/State

0.8 1.8 2.8 3.8 4.8 5.8 6.8

1 Time (s)

0 2 DG Frequency (per unit)

RD State
Freq/State
0.8 1.8 2.8 3.8 4.8 RE2 detection signal
Time (s) 1

4000 0
2000 DG terminal current 0.95 1 Time (s) 1.05 1.1
Current (A)

0 3000
-2000 2000
Current (A)

DG terminal current
-4000 1000
0.8 1.8 2.8 3.8 4.8 0
Time (s)
-1000
20 0.8 1.8 2.8 3.8 4.8 5.8 6.8
DG Voltage Time (s)
Voltage (kVφ)

15
10 15
5 DG RMS terminal Voltage
Voltage (kVφ)

0 13
0.8 1.8 2.8 3.8 4.8
Time (s)
11
0.8 1.8 2.8 3.8(s)
Time 4.8 5.8 6.8
1
1
Recloser State
State

Fuse State Recloser State

State

0 Fuse State
0.8 1.8 2.8 3.8 4.8 0
Time (s) 0.8 1.8 2.8 3.8 4.8 5.8 6.8
Fig. 17. Case Study-1 with the DG source at L2 with a 30Ω resistive SFCL Time (s)
applied at the PCC: RE2 current, F1 current, RE2, DG frequency, DG 100
terminal current, DG voltage, State signals.
Impedance (Ω)

1 R Calculated R Bank
50
RD State X Calculated X Bank
State

RE2 detection Signal 0

0 0.45 0.60.75 0.9 1.05
0.95 1 1.05 1.1 Time (s)
Time (s) Fig. 19. Case Study-1 with the DG source at L2 when RD applied for a fault
Fig. 18. Case Study-1 with the DG source at L2 when RD is applied and the duration of 0.12 seconds: RE2 current, F1 current, RE2, R D communication &
fault impedance is 3 Ω: Zoom on RE2, RD communication. DG frequency, Zoom on DG frequency, RE2, R D signals, DG terminal
current, DG voltage, State signals, load bank calculated and actual values.

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V. CONCLUSION 53≤X 46≤X<53 X<46

Phase pickup current, A 555
This paper proposes a novel reclosing scheme for mitigation Ground pickup current, A 370
of DG effects on overcurrent protection infrastructure in
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